Methods for debugging the gate driving timing of display panel array substrates, and related systems, terminals, storage media, and software products.

Abstract

This application provides a method, system, terminal, storage medium, and program product for debugging the gate driving timing of an array substrate. The method includes: acquiring basic timing parameters, including the total number of horizontal pixels, the total number of vertical rows, and the refresh rate; and acquiring the pixel period and row period based on the basic timing parameters; acquiring configuration parameters of the control signals for the array substrate gate drive; acquiring the edge positions of multiple gate drive clock signals in pixel position representation based on the position parameters of the gate clock source signal group; acquiring the timing waveform of the control signals for the array substrate gate drive based on the edge positions and the position parameters of the frame start signal and latch pulse signal; acquiring the key phase difference in the timing waveform; and comparing the key phase difference with a preset timing specification range for debugging. This improves the debugging efficiency of the array substrate gate drive timing debugging method.

Description

Technical Field

[0001] This application relates to the field of display panel driving technology, specifically to a method, system, terminal, storage medium, and program product for debugging the gate driving timing of an array substrate. Background Technology

[0002] Liquid crystal display (LCD) panels typically consist of an array substrate and a color filter substrate. Multiple gate lines and data lines are formed on the array substrate, with each intersection of two adjacent gate lines and two adjacent data lines defining a pixel unit. To achieve progressive image display, gate-on pulses are sequentially supplied to the gate lines to turn on the thin-film transistors (TFTs) line by line, allowing the grayscale voltage on the data lines to be written to the corresponding pixel units. Array substrate gate driving technology integrates the gate driving circuit directly into the peripheral area of ​​the array substrate, using TFTs to form shift register units. Gate-on pulses are generated sequentially by externally provided timing control signals, thereby reducing the number of external driving chips and facilitating narrow bezel and low-cost designs.

[0003] In a display driving system, the timing controller receives image data and synchronization signals from the main control chip, generating various control timing signals, including a frame start signal, a gate clock source signal, and a latch pulse signal. These low-voltage timing signals are level-shifted by a level converter, outputting multiple gate drive clock signals with high voltage swings to drive the gate drive circuits on the array substrate. The gate drive circuits initiate a frame scan based on the frame start signal and sequentially generate enable pulses for each row of gate lines according to the phase relationship of the multiple gate drive clock signals. The latch pulse signal controls the source drive circuit to latch the image data and output it to the data lines.

[0004] Currently, the debugging efficiency of the gate drive timing of the array substrate still needs to be improved. Summary of the Invention

[0005] In view of this, embodiments of this application provide a method for debugging the gate driving timing of an array substrate, as well as a system, terminal, storage medium, and program product thereof, which improves the debugging efficiency of the debugging method for the gate driving timing of an array substrate, reduces the dependence on hardware devices such as oscilloscopes, and realizes the visualization of the debugging method for the gate driving timing of an array substrate.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0007] In a first aspect, embodiments of this application provide a method for debugging the gate driving timing of a display panel array substrate, comprising: acquiring basic timing parameters of the display panel, the basic timing parameters including the total number of horizontal pixels, the total number of vertical rows, and the refresh rate, and acquiring the pixel period and row period of the display panel based on the basic timing parameters; acquiring configuration parameters of the control signals for the gate driving of the array substrate, the configuration parameters including the position parameters of a frame start signal, a gate clock source signal group, and a latch pulse signal; acquiring the edge positions of multiple gate driving clock signals in pixel position representation based on the position parameters of the gate clock source signal group, wherein each gate driving clock signal is sequentially delayed by one row period; acquiring the timing waveform of the control signals for the gate driving of the array substrate based on the edge positions and the position parameters of the frame start signal and the latch pulse signal; acquiring a key phase difference in the timing waveform, wherein the step of acquiring the key phase difference includes: determining a pixel position difference based on the timing waveform, multiplying the pixel position difference by the pixel period to obtain the key phase difference; and comparing the key phase difference with a preset timing specification range for debugging.

[0008] Optionally, the gate clock source signal group includes a first gate clock source signal and a second gate clock source signal; the step of obtaining the edge position of the multiple gate drive clock signals includes: obtaining the edge position based on the level converter operating mode and the position parameters of the gate clock source signal group; wherein, the level converter operating mode includes a two-input multiple-output mode, with the position parameters of the first gate clock source signal and the second gate clock source signal as inputs, and the edge position of the gate drive clock signal as the output; or, the gate clock source signal group includes a first gate clock source signal; the step of obtaining the edge position of the multiple gate drive clock signals includes: obtaining the edge position based on the level converter operating mode and the position parameters of the gate clock source signal group; wherein, the level converter operating mode includes a one-input multiple-output mode, with the position parameters of the first gate clock source signal as inputs, and the edge position of the gate drive clock signal as the output.

[0009] Optionally, the step of obtaining the edge position of the control signal for the array substrate gate drive includes: when the level converter is in a two-input multiple-output mode, the high-level width of each output gate drive clock signal starts at the rising edge of the first gate clock source signal and ends at the falling edge of the second gate clock source signal, and the low-level width starts at the falling edge of the second gate clock source signal and ends at the rising edge of the next first gate clock source signal, and each gate drive clock signal is delayed by one row cycle; or, the step of obtaining the edge position of the control signal for the array substrate gate drive includes: when the level converter is in a one-input multiple-output mode, the high-level width of each output gate drive clock signal is equal to the preset number of cycles multiplied by the row cycle, the low-level width is equal to the row cycle minus the high-level width, and each gate drive clock signal is delayed by one row cycle.

[0010] Optionally, the step of obtaining the timing waveform of the control signal for the array substrate gate drive includes: determining the level state of the multiple gate drive clock signals in each pixel period based on the edge position of the multiple gate drive clock signals; determining the level state of the frame start signal and latch pulse signal in each pixel period based on the position parameters of the frame start signal and latch pulse signal; and plotting the timing waveform on the same coordinate axis based on the determined level state of the frame start signal, the level state of the latch pulse signal, and the level state of the multiple gate drive clock signals, wherein the horizontal axis of the coordinate axis is in units of pixel position, the value range of the pixel position is from zero to the total number of horizontal pixels minus one, and the vertical axis of the coordinate axis represents a high level state or a low level state.

[0011] Optionally, the step of obtaining the timing waveform of the control signal for the array substrate gate drive further includes: determining the level state of each gate clock source signal in each pixel period based on the position parameters of each gate clock source signal in the gate clock source signal group; and the step of drawing the timing waveform further includes drawing the timing waveform of each gate clock source signal on the same coordinate axis based on the determined level state of each gate clock source signal.

[0012] Optionally, the key phase difference includes the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal; the step of obtaining the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal includes: the key phase difference includes the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal, and the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals.

[0013] Optionally, the key phase difference includes the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals; the step of obtaining the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals includes: calculating the pixel position difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals; multiplying the pixel position difference by the pixel period to obtain the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals.

[0014] Optionally, when the level converter operates in a two-input multiple-output mode, the high-level width is formed by the following steps: multiplying the difference between the starting row of the second gate clock source signal and the starting row of the first gate clock source signal by the total number of horizontal pixels to obtain the row-level offset; taking the difference between the rising edge pixel position of the second gate clock source signal and the rising edge pixel position of the first gate clock source signal as the pixel-level offset; and adding the row-level offset to the pixel-level offset to obtain the high-level width.

[0015] Optionally, the level converter operating mode includes a two-input multiple-output mode or a one-input multiple-output mode. When the level converter operating mode includes a two-input multiple-output mode, the gate clock source signal group includes a first gate clock source signal and a second gate clock source signal. The steps for adjusting the configuration parameters include: first, adjusting the position parameters of the latch pulse signal until the high level of the latch pulse signal covers the row range from the first row to the total number of vertical rows; then, adjusting the position parameters of the second gate clock source signal until the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is within the timing specification range; finally, adjusting the position parameters of the frame start signal until the falling edge of the frame start signal and the first gate clock source signal are within the timing specification range. The phase difference of the first rising edge of the gate drive clock signal is within the timing specification range; or, when the level converter operating mode includes a one-input multiple-output mode, the gate clock source signal group is the first gate clock source signal, and the steps for adjusting the configuration parameters include: first, adjusting the position parameter of the latch pulse signal until the high level of the latch pulse signal covers the row range from the first row to the total number of vertical rows; then adjusting the preset number of cycles until the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is within the timing specification range; finally, adjusting the position parameter of the frame start signal until the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal is within the timing specification range.

[0016] Optionally, after obtaining the configuration parameters of the control signal for the array substrate gate drive, and before obtaining the edge position of the multiple gate drive clock signals, the debugging method further includes: setting a common propagation delay value between each gate clock source signal and the gate drive clock signal in the gate clock source signal group; and in the step of obtaining the edge position of the multiple gate drive clock signals, the method further includes: superimposing the common propagation delay value onto the edge position.

[0017] Optionally, in the step of debugging and comparing the key phase difference with a preset timing specification range, the timing specification range refers to the minimum and maximum values ​​allowed for the key phase difference; the step of debugging and comparing the key phase difference with the preset timing specification range includes: if the key phase difference does not meet the timing specification range, then adjust the configuration parameters and return to the step of obtaining the edge positions of multiple gate drive clock signals; if the key phase difference meets the timing specification range, then end the debugging.

[0018] Secondly, embodiments of this application provide a debugging system for the gate driving timing of a display panel array substrate, comprising: a first acquisition module, configured to acquire basic timing parameters of the display panel, the basic timing parameters including the total number of horizontal pixels, the total number of vertical rows, and the refresh rate, and to acquire the pixel period and row period of the display panel based on the basic timing parameters; a second acquisition module, configured to acquire configuration parameters of control signals for the gate driving of the array substrate, the configuration parameters including position parameters of a frame start signal, a gate clock source signal group, and a latch pulse signal, the position parameters of the gate clock source signal group including position parameters of one or more gate clock source signals; and a third acquisition module, configured to acquire the pixel period and row period of the display panel based on the gate clock source signal group. The signal group position parameters are used to obtain the edge positions of multiple gate drive clock signals in pixel position representation, and each gate drive clock signal is delayed by one row period; the fourth acquisition module is used to acquire the timing waveform of the control signal for the array substrate gate drive based on the edge positions and the position parameters of the frame start signal and latch pulse signal; the calculation module is used to acquire the key phase difference in the timing waveform, wherein the step of acquiring the key phase difference includes: determining the pixel position difference based on the timing waveform, and multiplying the pixel position difference by the pixel period to obtain the key phase difference; the debugging comparison module is used to debug and compare the key phase difference with a preset timing specification range.

[0019] Thirdly, embodiments of this application provide a terminal, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor runs the computer program, it executes the debugging method provided in the first aspect.

[0020] The fourth method, according to embodiments of this application, is a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is run by a processor, the debugging method provided in the first aspect is executed.

[0021] Fifthly, embodiments of this application provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the debugging method provided in the first aspect.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In this embodiment of the invention, the total number of horizontal pixels, the total number of vertical rows, and the refresh rate are obtained, and the pixel period and the row period are calculated accordingly. This establishes a unified time reference with the pixel period as the smallest time unit and the row period as the row-level time unit, so that the subsequent conversion between edge position and time value can be automatically completed based on this reference, eliminating the tedious conversion from microseconds to pixel units by manual calculation and the risk of calculation errors. Secondly, by acquiring the position parameters of the frame start signal, the gate clock source signal group, and the latch pulse signal, and then directly calculating the pixel-level edge positions of the multiple gate drive clock signals (i.e., multiple outputs such as CK_LS) based on the position parameters of the gate clock source signal group, this calculation process relies entirely on the acquired configuration parameters. Subsequently, the calculated edge positions of the multiple gate drive clock signals are combined with the acquired position parameters of the frame start signal and the latch pulse signal to acquire the complete timing waveforms containing the frame start signal, latch pulse signal, gate clock source signal group, and multiple gate drive clock signals in real time on the same coordinate axis. Since the edge positions of all signals are derived from internal software calculations or parameter inputs, rather than from hardware pin measurements using probes, the above can be previewed intuitively in a pure software environment without the need for an oscilloscope. The method utilizes the phase relationship of relevant signals to overcome the shortcomings of traditional debugging methods, which require repeated burning, multiple waveform captures with an oscilloscope, and the inability to simultaneously observe multiple signals. Furthermore, by determining the pixel position difference based on the timing waveform, the pixel position difference is multiplied by the pixel period to obtain the critical phase difference, which is then compared with a preset timing specification range. Only when the critical phase difference does not meet the specification are the configuration parameters adjusted and the edge position recalculated; otherwise, the debugging ends. This debugging comparison step completely replaces manual cursor measurement and timing specification verification, eliminating reading errors and reducing the number of debugging iterations from dozens in the traditional method to just a few. In summary, this significantly improves the debugging efficiency of the array substrate gate drive timing debugging method, reduces the dependence on hardware devices such as oscilloscopes, and enables visualization of the array substrate gate drive timing debugging method. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0024] Figure 1 This is a flowchart of the steps corresponding to the debugging method of the gate driving timing of the display panel array substrate in the embodiment of the present invention; Figure 2 This is the timing waveform of the control signal for driving the gate of the array substrate in an embodiment of the present invention; Figure 3 This is a system functional block diagram of the debugging system for the gate driving timing of the display panel array substrate in an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of a terminal in an embodiment of the present invention. Detailed Implementation

[0025] In the existing process of debugging the gate drive timing of the display panel array substrate, the debugging personnel usually first determine the timing parameter requirements of each signal, such as the frame start signal, gate clock source signal, and latch pulse signal, according to the panel specification. They then convert these parameters into configuration values ​​of the internal registers of the timing controller, and then burn the configuration values ​​into the timing controller chip. They measure the actual waveform of the multi-channel gate drive clock signals output by the level converter using an oscilloscope, manually measure the time difference between key edges, and compare it with the requirements of the specification. If the requirements are not met, they recalculate the register values ​​and repeat the above burning, measurement, and comparison process until all timing parameters meet the specification range.

[0026] Research has revealed that the above-mentioned debugging methods suffer from low debugging efficiency, strong dependence on hardware devices such as oscilloscopes, cumbersome parameter unit conversion, difficulty in intuitively grasping the phase relationship between multiple signals, and easy errors in manual measurement and calculation. As a result, debugging a single timing parameter often requires dozens of iterations and takes several hours, and the repeatability and reliability of the debugging results are low.

[0027] The reasons for the above technical problems are as follows: the internal register values ​​of the timing controller are usually in units of pixel clock cycles or line cycles, while the timing parameters in the specification are in units of microseconds or nanoseconds. The two require manual multiplication and division conversion, and the conversion factor is different at different resolutions, which is very easy to cause calculation errors. After each parameter modification, it is necessary to go through the physical process of burning chips and measuring with an oscilloscope, and it is impossible to preview the waveform effect after adjustment in real time. An oscilloscope can only observe a limited number of signal channels at a time, while the array substrate gate drive involves more than ten signals, such as frame start signal, multiple gate clock source signals, latch pulse signals, and multiple gate drive clock signals, making it difficult to fully analyze their phase relationship on the same time axis. In addition, the time difference between critical edges depends on manual measurement and recording using a cursor, which poses a risk of reading error and recording error. Moreover, specification comparison depends on manual memory or consulting paper documents, which is easy to overlook or misjudge.

[0028] To address the aforementioned technical problems, this disclosure provides a method for debugging the gate driving timing of a display panel array substrate. Specifically, Figure 1 This is a flowchart of the steps corresponding to the debugging method of the gate driving timing of the display panel array substrate in the embodiments of this disclosure.

[0029] Step S1: Obtain the timing parameters of the display panel, including the total number of horizontal pixels, the total number of vertical rows, and the refresh rate, and obtain the pixel period and row period based on the timing parameters; Step S2: Obtain the configuration parameters of the control signal for the array substrate gate drive. The configuration parameters include the position parameters of the frame start signal, the gate clock source signal group, and the latch pulse signal. Step S3: Based on the position parameters of the gate clock source signal group, obtain the edge positions of multiple gate drive clock signals in terms of pixel positions, and each of the gate drive clock signals is delayed by one row period. Step S4: Based on the edge position and the position parameters of the frame start signal and latch pulse signal, obtain the timing waveform of the control signal for the array substrate gate drive; Step S5: Obtain the key phase difference in the timing waveform, wherein the step of obtaining the key phase difference includes: determining the pixel position difference based on the timing waveform, and multiplying the pixel position difference by the pixel period to obtain the key phase difference; Step S6: Compare and adjust the key phase difference with the preset timing specification range.

[0030] In this embodiment of the invention, the total number of horizontal pixels, the total number of vertical rows, and the refresh rate are obtained, and the pixel period and the row period are calculated accordingly. This establishes a unified time reference with the pixel period as the smallest time unit and the row period as the row-level time unit, so that the subsequent conversion between edge position and time value can be automatically completed based on this reference, eliminating the tedious conversion from microseconds to pixel units by manual calculation and the risk of calculation errors. Secondly, by acquiring the position parameters of the frame start signal, the gate clock source signal group, and the latch pulse signal, and then directly calculating the pixel-level edge positions of the multiple gate drive clock signals (i.e., multiple outputs such as CK_LS) based on the position parameters of the gate clock source signal group, this calculation process relies entirely on the acquired configuration parameters. Subsequently, the calculated edge positions of the multiple gate drive clock signals are combined with the acquired position parameters of the frame start signal and the latch pulse signal to acquire the complete timing waveforms containing the frame start signal, latch pulse signal, gate clock source signal group, and multiple gate drive clock signals in real time on the same coordinate axis. Since the edge positions of all signals are derived from internal software calculations or parameter inputs, rather than from hardware pin measurements using probes, the above can be previewed intuitively in a pure software environment without the need for an oscilloscope. The method utilizes the phase relationship of relevant signals to overcome the shortcomings of traditional debugging methods, which require repeated burning, multiple waveform captures with an oscilloscope, and the inability to simultaneously observe multiple signals. Furthermore, by determining the pixel position difference based on the timing waveform, the pixel position difference is multiplied by the pixel period to obtain the critical phase difference, which is then compared with a preset timing specification range. Only when the critical phase difference does not meet the specification are the configuration parameters adjusted and the edge position recalculated; otherwise, the debugging ends. This debugging comparison step completely replaces manual cursor measurement and timing specification verification, eliminating reading errors and reducing the number of debugging iterations from dozens in the traditional method to just a few. In summary, this significantly improves the debugging efficiency of the array substrate gate drive timing debugging method, reduces the dependence on hardware devices such as oscilloscopes, and enables visualization of the array substrate gate drive timing debugging method.

[0031] To make the above-mentioned objectives, features and beneficial effects of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0032] in, Figure 1 This is a flowchart of the steps corresponding to the debugging method of the gate driving timing of the display panel array substrate in the embodiments of this disclosure. Figure 1 The method shown can be applied to an apparatus or device that has a method for debugging the gate driving timing of a display panel array substrate.

[0033] Step S1: Obtain the basic timing parameters of the display panel, including the total number of horizontal pixels, the total number of vertical rows, and the refresh rate, and obtain the pixel period and line period of the display panel based on the basic timing parameters.

[0034] Specifically, the total horizontal pixel count, total vertical row count, and refresh rate are obtained, and the pixel period and row period are calculated accordingly. This establishes a unified time base with the pixel period as the smallest time unit and the row period as the row-level time unit. The pixel period defines the absolute time length corresponding to a single pixel position, thus establishing a definite conversion relationship between pixel position and time value. Based on this conversion relationship, after acquiring the timing waveform, the pixel position difference between any two edge positions in the timing waveform can be automatically converted into the corresponding time difference by multiplying by the pixel period. This allows the unit conversion required for subsequent debugging and comparison to be automatically completed by the software, replacing the tedious process of manually converting the microsecond value in the specification to the register pixel value (or vice versa) in traditional debugging, eliminating the risk of manual conversion and calculation errors.

[0035] It should be noted that the total horizontal pixel count represents the total number of pixel cycles in each row of the display panel, and the total vertical row count represents the total number of line cycles in each frame of the display panel. The refresh rate represents the number of frames displayed per second. A pixel cycle refers to the absolute time required to display a single pixel. A line cycle refers to the absolute time required to scan a single line.

[0036] In practice, the display panel can be displayed in a line-by-line scanning manner or other gate scanning methods, and this debugging method can be adapted to both.

[0037] Based on the three fundamental parameters mentioned above, the length of a single pixel period can be calculated using the formula: Pixel Period = 1 / (Total Horizontal Pixels × Total Vertical Lines × Refresh Rate). The pixel period refers to the absolute duration (in seconds) required to display a single pixel. The absolute time occupied by a line can be calculated using the formula: Line Period = Total Horizontal Pixels × Pixel Period. Thus, the pixel period serves as a conversion factor between the pixel domain and the time domain, allowing the distance between edge positions represented by pixel position differences in the subsequently obtained timing waveform to be directly converted into a time value in microseconds or nanoseconds by multiplying by the pixel period. This fully automates the conversion from pixel value to time value during specification comparison without manual intervention.

[0038] It should be noted that the above calculation methods for pixel period and row period are not limited to a specific pixel architecture or gate scanning method. As long as the corresponding basic parameters are provided according to the pixel architecture and gate scanning method used, the subsequent timing debugging can be completed automatically.

[0039] For different pixel architectures, the values ​​of the total horizontal pixel count and / or the total vertical row count may differ. Regardless of the pixel architecture used, this debugging method only requires the total horizontal pixel count and the total vertical row count under the corresponding architecture as input parameters, while the calculation logic of the pixel period and the row period remains unchanged, to automatically adapt to different pixel architectures.

[0040] For different gate scanning methods, the values ​​of the total number of vertical rows and / or the refresh rate may differ. Regardless of the gate scanning method used, this debugging method only requires the total number of vertical rows and the refresh rate under the corresponding scanning method as the basic parameter inputs, while the calculation logic of the pixel period and the row period remains unchanged, to automatically adapt to different gate scanning methods. For example, the gate scanning method may include progressive scan, high-speed response scan, and dual-gate-line scan. In progressive scan, each row is scanned sequentially in each frame, and the row period is equal to the total number of horizontal pixels multiplied by the pixel period; in high-speed response scan, the same row is refreshed and scanned multiple times within the same frame, and the row period is shortened accordingly; in dual-gate-line scan, two adjacent gate lines are simultaneously activated, effectively halving the total number of vertical rows, and the row period is adjusted accordingly. Regardless of the gate scanning method used, this debugging method only requires the total number of vertical rows and the refresh rate under the corresponding scanning method as the basic parameter inputs, while the calculation logic of the pixel period and the row period remains unchanged, to automatically adapt to different gate scanning methods.

[0041] Step S2: Obtain the configuration parameters of the control signals for the array substrate gate drive. The configuration parameters include the position parameters of the frame start signal, the gate clock source signal group, and the latch pulse signal.

[0042] Specifically, the position parameters of the gate clock source signal group include the position parameters of one or more gate clock source signals.

[0043] It should be noted that the configuration parameters for obtaining the control signals of the array substrate gate drive are used to define the initial edge position of each control signal in the time domain. These configuration parameters directly correspond to the set values ​​of the internal registers of the timing controller. Therefore, without actual programming, the starting line, number of effective lines, rising edge pixel position, and falling edge pixel position of the frame start signal, gate clock source signal group, and latch pulse signal can be accurately described in the software.

[0044] It should also be noted that the configuration parameters include the frame start signal, the gate clock source signal group, and the latch pulse signal. These three signals constitute the core control sequence for driving the gate circuit of the array substrate.

[0045] Specifically, the frame start signal determines the starting timing position of a frame scan, the gate clock source signal group provides the reference clock required to generate multiple gate drive clocks, and the latch pulse signal controls the timing of data latching and output.

[0046] It should be noted that the position parameters of the gate clock source signal group include the position parameters of one or more gate clock source signals. This is to ensure compatibility with the two different operating modes of the subsequent level converter. In the two-input multiple-output mode, two inputs are required: the first gate clock source signal and the second gate clock source signal. In the one-input multiple-output mode, only the first gate clock source signal is required. In other words, by including one or more gate clock source signals in the gate clock source signal group, the debugging method of this embodiment can be flexibly adapted to different hardware requirements.

[0047] In this embodiment, the position parameters include: the start line, end line, rising edge pixel position, and falling edge pixel position of the frame start signal; the start line, number of valid lines, rising edge pixel position, and falling edge pixel position of the latch pulse signal; and the start line, number of valid lines, rising edge pixel position, and falling edge pixel position of each gate clock source signal in the gate clock source signal group.

[0048] The start line of the frame start signal indicates the line number where the signal begins to output; the end line indicates the line number where the signal ends to output; the rising edge pixel position indicates the pixel coordinates where the signal transitions from low to high within a line; and the falling edge pixel position indicates the pixel coordinates where the signal transitions from high to low.

[0049] The starting line, number of valid lines, rising edge pixel position, and falling edge pixel position of the latch pulse signal are defined in the same way as the frame start signal above. The number of valid lines indicates the range of lines in which the signal remains valid.

[0050] The starting row, number of valid rows, rising edge pixel position, and falling edge pixel position of each gate clock source signal in the gate clock source signal group are defined in the same way as the frame start signal above, and are used to precisely control the edge position of each gate clock source signal at the row level and pixel level.

[0051] In this embodiment, the gate clock source signal group includes a first gate clock source signal and a second gate clock source signal.

[0052] It should be noted that the gate clock source signal group includes a first gate clock source signal and a second gate clock source signal, enabling it to support the subsequent two-input multiple-output mode. In the two-input multiple-output mode, the first gate clock source signal is used to define the start edge position of the high level of the gate drive clock signal, and the second gate clock source signal is used to define the end edge position of the high level. Together, they determine the high level width of the gate drive clock signal. By providing two input signals simultaneously, the high level width of the gate drive clock signal can be precisely adjusted, improving the flexibility of timing debugging.

[0053] In other embodiments, the gate clock source signal group includes a first gate clock source signal.

[0054] Specifically, the gate clock source signal group includes a first gate clock source signal, enabling it to support a subsequent one-input multiple-output mode. In the one-input multiple-output mode, the high-level width of the gate drive clock signal is no longer determined by the edge position difference between the two signals, but by a preset number of cycles multiplied by the row period.

[0055] Step S21: Set the common propagation delay value between each gate clock source signal and the gate drive clock signal in the gate clock source signal group.

[0056] It should be noted that by setting a common propagation delay value, the inherent hardware delay from input to output of a real level converter chip can be simulated. In real hardware, after the gate clock source signal is input to the level converter, the change in the gate drive clock signal at its output is not instantaneous, but rather has a fixed time offset. In other words, by pre-setting this common propagation delay value in the software simulation and then superimposing it onto the subsequently acquired edge positions when calculating the edge positions of multiple gate drive clock signals, the generated timing waveform can be made closer to the actual hardware output waveform, thereby improving the simulation accuracy during debugging and reducing deviations during final programming and verification.

[0057] Step S3: Based on the position parameters of the gate clock source signal group, obtain the edge positions of the multiple gate drive clock signals in pixel position, and each of the gate drive clock signals is delayed by one row period.

[0058] Specifically, obtaining the edge positions of multiple gate drive clock signals can convert the gate clock source signals in the configuration parameters into multi-phase clock signals that are actually used to drive the gate circuits of the array substrate.

[0059] It should be noted that the edge positions of the multiple gate drive clock signals are obtained, including the row number and pixel position of the rising and falling edges of each gate drive clock signal.

[0060] The edge position is obtained based on the position parameters of the gate clock source signal group. This means that the calculation process relies entirely on the parameters and preset rules inside the software and does not depend on any hardware output. That is, accurate edge data can be obtained without connecting an oscilloscope. At the same time, the calculation can respond to the adjustment of configuration parameters in real time, realize the waveform refresh at the millisecond level, avoid the long iteration of repeated burning, measurement and calculation in traditional debugging, and improve the efficiency of timing debugging.

[0061] In this embodiment, the step of obtaining the edge position of the multiple gate drive clock signals includes: obtaining the edge position based on the level converter operating mode and the position parameters of the gate clock source signal group; wherein, the level converter operating mode includes a two-input multiple-output mode, wherein the position parameters of the first gate clock source signal and the second gate clock source signal are used as inputs, and the edge position of the gate drive clock signal is used as the output.

[0062] It should be noted that by controlling the start and end of the high level of the gate drive clock signal through two independent gate clock source signals, the high level width can be continuously adjusted in both row and pixel dimensions, thereby meeting the stringent requirements of different display panels for the gate opening window.

[0063] In this embodiment, the step of obtaining the edge position of the control signal for the gate drive of the array substrate includes: when the level converter is in the two-input multiple-output mode, the high-level width of each output gate drive clock signal starts at the rising edge of the first gate clock source signal and ends at the falling edge of the second gate clock source signal, the low-level width starts at the falling edge of the second gate clock source signal and ends at the rising edge of the next first gate clock source signal, and each gate drive clock signal is delayed by one row cycle.

[0064] In the aforementioned steps, the high-level width begins at the rising edge of the first gate clock source signal and ends at the falling edge of the second gate clock source signal. This rule ensures that the high-level width is entirely determined by the edge position difference between the first and second gate clock source signals, allowing for precise control of the gate-on duration by adjusting the position parameter of the second gate clock source signal. The low-level width begins at the falling edge of the second gate clock source signal and ends at the rising edge of the next first gate clock source signal. This rule guarantees the continuous alternation of high and low levels within each cycle, forming a complete clock waveform.

[0065] It should be noted that each gate drive clock signal is delayed by one row cycle, which enables progressive scanning of the gate drive. In other words, the first signal is used to enable the first row, the second signal is delayed by one row cycle and then used to enable the second row, and so on, forming a sequentially shifted scan pulse train.

[0066] In this embodiment, when the level converter operates in a two-input multiple-output mode, the high-level width is formed through the following steps: multiplying the difference between the starting row of the second gate clock source signal and the starting row of the first gate clock source signal by the total number of horizontal pixels to obtain the row-level offset; taking the difference between the rising edge pixel position of the second gate clock source signal and the rising edge pixel position of the first gate clock source signal as the pixel-level offset; and adding the row-level offset to the pixel-level offset to obtain the high-level width.

[0067] Specifically, obtaining the row offset allows the initial row difference between the two gate clock source signals in the vertical direction to be converted into a coarse adjustment amount in pixels. Since each row contains a number of pixel cycles of the total horizontal pixels, multiplying the initial row difference by the total horizontal pixels yields the total pixel offset across the row, thereby enabling a wide range of high-level width adjustments.

[0068] It should be noted that obtaining pixel-level offsets allows for fine-tuning of the rising edge pixel position within the same row, achieving high-precision adjustment at the pixel level.

[0069] Specifically, adding the row-level offset and the pixel-level offset yields the total number of pixel cycles between the rising edge of the first gate clock signal and the falling edge of the second gate clock signal. The row-level offset equals the difference in the number of rows between the starting row of the second gate clock signal and the starting row of the first gate clock signal multiplied by the total horizontal pixel count; each row difference corresponds to the total number of pixel cycles in the horizontal direction. The pixel-level offset equals the difference between the pixel position at the rising edge of the second gate clock signal and the pixel position at the rising edge of the first gate clock signal, representing the pixel position offset within the same row. Adding the row-level offset and the pixel-level offset gives the total number of pixel cycles corresponding to the total high-level width.

[0070] In other embodiments, the step of obtaining the edge position of the multiple gate drive clock signals includes: obtaining the edge position based on the level converter operating mode and the position parameters of the gate clock source signal group; wherein, the level converter operating mode includes a one-input multiple-output mode, wherein the position parameters of the first gate clock source signal are used as inputs and the edge position of the gate drive clock signal is used as outputs.

[0071] Specifically, the step of obtaining the edge position of the control signal for the gate drive of the array substrate includes: when the level converter is in one-input multiple-output mode, the high-level width of each output gate drive clock signal is equal to the preset number of cycles multiplied by the row cycle, the low-level width is equal to the row cycle minus the high-level width, and each gate drive clock signal is delayed by one row cycle.

[0072] It should be noted that in the one-input multiple-output mode, the high-level width is equal to the preset number of cycles multiplied by the row cycle, and the low-level width is equal to the row cycle minus the high-level width. This makes the high-level width no longer dependent on the second gate clock source signal, but controlled by the preset number of cycles.

[0073] Specifically, the preset number of cycles is a positive number greater than 0, for example, 2.5, which means the high level lasts for 2.5 line cycles. This design simplifies parameter adjustment; only the preset number of cycles needs to be modified to change the high-level width of all gate drive clock signals. Delaying each gate drive clock signal by one line cycle has the same effect as the two-channel mode, ensuring the continuity of line-by-line scanning.

[0074] In this embodiment, the step of obtaining the edge position of the multi-gate drive clock signal further includes: superimposing the common propagation delay value onto the edge position.

[0075] By superimposing the common propagation delay value onto the edge position when obtaining the edge position of the multi-channel gate drive clock signal, all rising and falling edges of the calculated gate drive clock signals are uniformly shifted backward by this delay amount, so that the timing waveform generated subsequently based on the edge position can reflect the time offset between the actual hardware output and the ideal calculated value.

[0076] Step S4: Based on the edge position and the position parameters of the frame start signal and latch pulse signal, obtain the timing waveform of the control signal for the array substrate gate drive.

[0077] It should be noted that by combining the calculated edge positions of the multiple gate drive clock signals with the position parameters of the acquired frame start signal and latch pulse signal, a complete timing waveform containing the frame start signal, latch pulse signal, gate clock source signal group, and multiple gate drive clock signals can be acquired in real time on the same coordinate axis. Since the edge positions of all signals are calculated or input by the software, rather than measured by the probe on the hardware pins, the phase relationship of all the above-mentioned related signals can be previewed intuitively in a pure software environment without the need to connect an oscilloscope. This overcomes the shortcomings of traditional debugging, which requires repeated burning, multiple waveform captures with an oscilloscope, and the inability to observe multiple signals simultaneously.

[0078] It should also be noted that the phase relationship of all relevant signals refers to: the time interval between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal; the time interval between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal; and the sequential delay between each gate drive clock signal. By displaying these signals simultaneously on the same time axis, it is possible to visually determine whether the timing relationship between the signals meets the timing specifications.

[0079] In this embodiment, the step of obtaining the timing waveform of the control signal for the array substrate gate drive includes: determining the level state of the multi-gate drive clock signal in each pixel period based on the edge position of the multi-gate drive clock signal; determining the level state of the frame start signal and latch pulse signal in each pixel period based on the position parameters of the frame start signal and latch pulse signal; and drawing the timing waveform on the same coordinate axis based on the determined level state of the frame start signal, the level state of the latch pulse signal, and the level state of the multi-gate drive clock signal, wherein the horizontal axis of the coordinate axis is in units of pixel position, the value range of the pixel position is from zero to the total number of horizontal pixels minus one, and the vertical axis of the coordinate axis represents the high level state or the low level state.

[0080] Specifically, based on the edge positions of the multiple gate drive clock signals, the corresponding level states of the multiple gate drive clock signals in each pixel cycle can be determined. This is because the edge positions define the specific pixel coordinates where the signal transitions, and the signal level remains constant across all pixel cycles between two adjacent edges. Similarly, based on the position parameters of the frame start signal and latch pulse signal, the corresponding level states of the frame start signal and latch pulse signal in each pixel cycle can also be determined.

[0081] It should be noted that plotting the level states of all signals on the same coordinate axis can form a complete timing waveform diagram. The horizontal axis is in units of pixel positions and the value ranges from zero to the total number of pixels in the horizontal direction minus one. The vertical axis represents the high level state or the low level state, which clearly distinguishes the logic level of the signal and makes it easy to observe the edge position.

[0082] In this embodiment, the step of obtaining the timing waveform of the control signal for the array substrate gate drive further includes: determining the level state of each gate clock source signal in each pixel period based on the position parameters of each gate clock source signal in the gate clock source signal group; the step of drawing the timing waveform further includes, specifically, drawing the timing waveform of each gate clock source signal on the same coordinate axis based on the determined level state of each gate clock source signal.

[0083] The position parameters of each gate clock source signal in the group determine the level state of each gate clock source signal in each pixel cycle. The waveforms of the first gate clock source signal and the second gate clock source signal can be displayed simultaneously in the timing waveform, allowing the debugging personnel to intuitively observe the phase relationship between each gate clock source signal in the input gate clock source signal group and the output gate drive clock signal, thereby more accurately determining whether the level converter is working properly.

[0084] In this embodiment, the timing waveform of the control signal for the array substrate gate drive includes the frame start signal, latch pulse signal, each gate clock source signal in the gate clock source signal group, and all waveforms of the multiple gate drive clock signals.

[0085] like Figure 2 As shown, the timing waveform of the control signal for the array substrate gate drive is illustrated.

[0086] Figure 2 The diagram shows five gate drive clock signals. In other embodiments, the number of gate drive clock signals can be any other integer greater than zero.

[0087] Step S5: Obtain the key phase difference in the timing waveform, wherein the step of obtaining the key phase difference includes: determining the pixel position difference based on the timing waveform, and multiplying the pixel position difference by the pixel period to obtain the key phase difference.

[0088] It should be noted that obtaining the key phase difference in the timing waveform can explicitly extract the time interval information hidden in the waveform in numerical form, providing a quantitative basis for subsequent specification comparison.

[0089] Specifically, the pixel position difference is determined based on the time-series waveform, and the phase difference is obtained by calculating the pixel position difference and multiplying it by the pixel period. This achieves accurate automatic conversion from the pixel domain to the time domain without manual intervention and avoids unit conversion errors.

[0090] In this embodiment, the key phase differences include the phase difference D1 from the falling edge of the latch pulse signal to the falling edge of the gate drive clock signal, and the phase difference D2 from the falling edge of the frame start signal to the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals.

[0091] Specifically, the phase difference D1 between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is taken as the critical phase difference, because this phase difference determines the time margin between the data latch operation and the gate shutdown. If the phase difference is too small, the data may be shut off before it is completely written to the gate; if it is too large, unnecessary waiting time may be introduced.

[0092] It should be noted that the phase difference D2 between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal is used as the critical phase difference because this phase difference determines the synchronization relationship between the frame start pulse and the first row scan clock. If this phase difference deviates from the design range, it may cause the first row to fail to start normally or result in abnormal display. At the same time, the first rising edge of the first gate drive clock signal is chosen instead of the second rising edge because the array substrate gate drive circuit usually requires the falling edge of the frame start signal to be strictly aligned with the first valid edge of the first gate drive clock signal. This is the initial condition for starting progressive scanning.

[0093] In this embodiment, the step of obtaining the phase difference D1 between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal includes: calculating the pixel position difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal in the timing waveform; multiplying the pixel position difference by the pixel period to obtain the phase difference D1 between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal.

[0094] The phase difference is obtained by calculating the pixel position difference and then multiplying it by the pixel period. The pixel period reference established in step S1 is directly used to achieve accurate automatic conversion from the pixel domain to the time domain without manual intervention, thus avoiding unit conversion errors.

[0095] In this embodiment, the step of obtaining the phase difference D2 between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal in the multiple gate drive clock signals includes: calculating the pixel position difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal in the multiple gate drive clock signals; multiplying the pixel position difference by the pixel period to obtain the phase difference D2 between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal in the multiple gate drive clock signals.

[0096] Step S6: Compare and adjust the key phase difference with the preset timing specification range.

[0097] Specifically, in the step of debugging and comparing the key phase difference with a preset timing specification range, the timing specification range refers to the minimum and maximum values ​​allowed for the key phase difference. The step of debugging and comparing the key phase difference with the preset timing specification range includes: if the key phase difference does not meet the timing specification range, adjusting the configuration parameters and returning to the step of obtaining the edge position of the multi-channel gate drive clock signal; if the key phase difference meets the timing specification range, ending the debugging.

[0098] It should be noted that by acquiring the key phase difference in the timing waveform and comparing it with the preset timing specification range, the configuration parameters are adjusted and the edge position is recalculated only when the phase difference does not meet the specification; otherwise, the debugging ends. This closed-loop comparison step completely replaces manual cursor measurement and timing specification verification, which not only eliminates reading errors but also reduces the number of debugging iterations from dozens in the traditional method to a few, significantly improving the debugging efficiency of the array substrate gate drive timing debugging method.

[0099] It should also be noted that the timing specification range refers to the range of values ​​that can be allowed for each critical phase difference. For example, the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal can be between 2 microseconds and 5 microseconds, and the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal can be between 20 microseconds and 50 microseconds.

[0100] Specifically, the preset timing specification range serves as the judgment criterion, ensuring the accuracy of the debugging results.

[0101] In this embodiment, when the level converter's operating mode includes a two-input multiple-output mode, the gate clock source signal group includes a first gate clock source signal and a second gate clock source signal. The steps for adjusting the configuration parameters include: first, adjusting the position parameters of the latch pulse signal until the high level of the latch pulse signal covers the row range from the first row to the total number of vertical rows; then, adjusting the position parameters of the second gate clock source signal until the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is within the timing specification range; finally, adjusting the position parameters of the frame start signal until the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal is within the timing specification range.

[0102] It should be noted that the position parameters of the latch pulse signal should be adjusted first. The high level of the latch pulse signal must cover the entire effective display area (from the first row to the total number of vertical rows); otherwise, some rows will fail to latch data correctly. This adjustment is independent of the phase of other signals and should therefore be performed first. After the latch pulse signal correctly covers the area, the position parameters of the second gate clock source signal should be adjusted. This is because the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is directly affected by the edge position of the second gate clock source signal, and this phase difference must be optimized only after the latch pulse signal has stabilized. Finally, the position parameters of the frame start signal should be adjusted. The frame start signal only affects the synchronization between the frame start time and the first gate drive clock signal. After the width and phase of the gate drive clock signal have been adjusted, fine-tuning the frame start signal can avoid interference with other signals. This step of adjusting configuration parameters reflects a debugging strategy from basic to fine-tuning, which can minimize the number of iterations and improve debugging efficiency.

[0103] It should also be noted that the choice to adjust the position parameters of the second gate clock source signal instead of the first gate clock source signal is based on the high-level width formation rule. The high level of each gate drive clock signal begins at the rising edge of the first gate clock source signal and ends at the falling edge of the second gate clock source signal. Therefore, the high-level width is equal to the falling edge position of the second gate clock source signal minus the rising edge position of the first gate clock source signal. If the rising edge of the first gate clock source signal is used as a fixed reference, then only the position parameters of the second gate clock source signal need to be adjusted to continuously change the high-level width, thereby achieving independent adjustment of the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal. This adjustment method uses the first gate clock source signal as a stable time reference point, simplifying the debugging process logic and requiring only one parameter to be modified in each iteration, which is beneficial for rapid convergence.

[0104] In other embodiments, the position parameters of the first gate clock source signal can be adjusted without adjusting the position parameters of the second gate clock source signal. Specifically, the falling edge of the second gate clock source signal is used as a fixed reference, and the high-level width is changed by adjusting the rising edge of the first gate clock source signal. In this case, the high-level width is equal to the falling edge position of the second gate clock source signal minus the rising edge position of the first gate clock source signal. Decreasing the rising edge position of the first gate clock source signal can also increase the high-level width. The technical effect of this adjustment method is essentially the same as adjusting the second gate clock source signal.

[0105] In other embodiments, when the level shifter operating mode includes a one-input multiple-output mode, the gate clock source signal group includes a first gate clock source signal, and the step of adjusting the configuration parameters includes: firstly, adjusting the position parameter of the latch pulse signal until the high level of the latch pulse signal covers the row range from the first row to the total number of vertical rows; then adjusting the preset number of cycles until the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is within the timing specification range; finally, adjusting the position parameter of the frame start signal until the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal is within the timing specification range.

[0106] Specifically, in the one-input multiple-output mode, the order of adjusting the latch pulse signal and the frame start signal is the same as in the two-input multiple-output mode. The difference is that when adjusting the high-level width of the gate drive clock signal, the second gate clock source signal is no longer adjusted (because the one-input multiple-output mode only inputs the first gate clock source signal), but the preset number of cycles is adjusted instead.

[0107] The preset number of cycles is a configuration item independent of the gate clock source signal position parameter. It directly determines that the high-level width is equal to the preset number of cycles multiplied by the row period. By adjusting the preset number of cycles, the high-level width of the gate drive clock signal can be continuously changed, thereby affecting the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal. After the latch pulse signal has been adjusted, the preset number of cycles is adjusted again to bring the phase difference into the specified range. Finally, the frame start signal is adjusted, following the same debugging sequence from basic to fine, ensuring efficient debugging.

[0108] It should be noted that the preset number of cycles can be an integer or a non-integer. For example, 2.5 means that the high level width is 2.5 times the line cycle. The specific value is set by the user according to the specifications of the display panel.

[0109] Reference Figure 3 , Figure 3 This is a schematic diagram of the structure of a debugging system for the gate driving timing of a display panel array substrate according to an embodiment of the present invention.

[0110] The debugging system for the gate drive timing of the display panel array substrate includes: a first acquisition module 200, used to acquire the basic timing parameters of the display panel, including the total number of horizontal pixels, the total number of vertical rows, and the refresh rate, and to acquire the pixel period and row period of the display panel based on the basic timing parameters; a second acquisition module 201, used to acquire the configuration parameters of the control signals for the gate drive of the array substrate, including the position parameters of the frame start signal, the gate clock source signal group, and the latch pulse signal, and the position parameters of the gate clock source signal group including the position parameters of one or more gate clock source signals; and a third acquisition module 202, used to acquire the pixel period and row period of the display panel based on the level converter operating mode and the bit position of the gate clock source signal group. The system sets parameters to obtain the edge positions of multiple gate drive clock signals in pixel position representation, with each gate drive clock signal delayed by one row period; a fourth acquisition module 203 is used to acquire the timing waveform of the control signal for the array substrate gate drive based on the edge positions and the position parameters of the frame start signal and latch pulse signal; a calculation module 204 is used to acquire the key phase difference in the timing waveform, wherein the step of acquiring the key phase difference includes: determining the pixel position difference based on the timing waveform, and multiplying the pixel position difference by the pixel period to obtain the key phase difference; and a debugging comparison module 205 is used to debug and compare the key phase difference with a preset timing specification range.

[0111] It should be noted that, regarding Figure 3 For more details on the working principle, operation method, and beneficial effects of the image data processing device shown, please refer to the specific description above, which will not be repeated here.

[0112] Reference Figure 4 , Figure 4 This is a schematic diagram of the hardware structure of a terminal in an embodiment of the present invention.

[0113] Figure 4 The terminal shown includes a memory 301, a processor 302, and a transceiver 303. The processor 302 is coupled to the memory 301 and the transceiver 303. The memory 301 can be located inside or outside the terminal. The memory 301, processor 302, and transceiver 303 can be connected via a communication bus. The transceiver 303 is used to communicate with other devices or communication networks.

[0114] Optionally, the transceiver 303 can be a transmitter. The memory 301 stores a computer program that can run on the processor 302. When the processor 302 runs the computer program, the transceiver 303 executes the steps in the debugging method for the gate driving timing of the display panel array substrate provided in the above embodiments.

[0115] This application also provides a computer-readable storage medium storing a computer program. When the computer program is run by a computer, the aforementioned debugging method for the gate driving timing of the display panel array substrate is executed. The storage medium may include read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc. The storage medium may also include non-volatile memory or non-transitory memory, etc.

[0116] This application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the above-described debugging method for the gate driving timing of a display panel array substrate.

[0117] It should be understood that in the embodiments of this application, the processor can be a central processing unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0118] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0119] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions according to the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, a computer program can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means.

[0120] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for debugging the gate driving timing of a display panel array substrate, characterized in that, include: Obtain the timing parameters of the display panel, including the total number of horizontal pixels, the total number of vertical rows, and the refresh rate, and obtain the pixel period and row period of the display panel based on the timing parameters; The configuration parameters for the control signal of the array substrate gate drive are obtained, including the position parameters of the frame start signal, the gate clock source signal group and the latch pulse signal respectively; Based on the position parameters of the gate clock source signal group, the edge positions of multiple gate drive clock signals, represented by pixel positions, are obtained, and each of the gate drive clock signals is delayed by one row period. Based on the edge position and the position parameters of the frame start signal and latch pulse signal, the timing waveform of the control signal for the array substrate gate drive is obtained; The key phase difference in the timing waveform is obtained, wherein the step of obtaining the key phase difference includes: determining the pixel position difference based on the timing waveform, and multiplying the pixel position difference by the pixel period to obtain the key phase difference; The key phase difference is compared and adjusted with the preset timing specification range.

2. The debugging method as described in claim 1, characterized in that, The gate clock source signal group includes a first gate clock source signal and a second gate clock source signal; The step of obtaining the edge position of the multiple gate drive clock signals includes: obtaining the edge position based on the level converter operating mode and the position parameters of the gate clock source signal group; wherein, the level converter operating mode includes a two-input multiple-output mode, the position parameters of the first gate clock source signal and the second gate clock source signal are used as inputs, and the edge position of the gate drive clock signal is used as the output; or, The gate clock source signal group includes a first gate clock source signal; The step of obtaining the edge position of the multiple gate drive clock signals includes: obtaining the edge position based on the level converter operating mode and the position parameters of the gate clock source signal group; wherein, the level converter operating mode includes a one-input multiple-output mode, wherein the position parameters of the first gate clock source signal are used as inputs and the edge position of the gate drive clock signal is used as outputs.

3. The debugging method as described in claim 2, characterized in that, The step of obtaining the edge position of the control signal for the gate drive of the array substrate includes: When the level converter operates in a two-input multiple-output mode, the high-level width of each output gate drive clock signal starts at the rising edge of the first gate clock source signal and ends at the falling edge of the second gate clock source signal, and the low-level width starts at the falling edge of the second gate clock source signal and ends at the next rising edge of the first gate clock source signal, and each gate drive clock signal is delayed by one row cycle. or, The step of obtaining the edge position of the control signal for the gate drive of the array substrate includes: when the level converter is in one-input multiple-output mode, the high-level width of each output gate drive clock signal is equal to the preset number of cycles multiplied by the row cycle, the low-level width is equal to the row cycle minus the high-level width, and each gate drive clock signal is delayed by one row cycle.

4. The debugging method as described in claim 1, characterized in that, The step of obtaining the timing waveform of the control signal for the gate drive of the array substrate includes: Based on the edge positions of the multiple gate drive clock signals, the level state of the multiple gate drive clock signals in each pixel cycle is determined; Based on the position parameters of the frame start signal and the latch pulse signal, determine the level state of the frame start signal and the latch pulse signal in each pixel period; Based on the determined level states of the frame start signal, the latch pulse signal, and the multiple gate drive clock signal, timing waveforms are plotted on the same coordinate axis. The horizontal axis of the coordinate axis is in units of pixel positions, and the value range of the pixel position is from zero to the total number of horizontal pixels minus one. The vertical axis of the coordinate axis represents a high-level state or a low-level state.

5. The debugging method as described in claim 4, characterized in that, The step of acquiring the timing waveform of the control signal for the gate drive of the array substrate further includes: Based on the position parameters of each gate clock source signal in the gate clock source signal group, determine the level state of each gate clock source signal in each pixel cycle; The step of drawing the timing waveforms further includes drawing the timing waveforms of each gate clock source signal on the same coordinate axis based on the determined level state of each gate clock source signal.

6. The debugging method as described in claim 1, characterized in that, The critical phase difference includes the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal; The step of obtaining the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal includes: Calculate the pixel position difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal in the timing waveform; Multiply the pixel position difference by the pixel period to obtain the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal.

7. The debugging method as described in claim 1, characterized in that, The critical phase difference includes the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals; The step of obtaining the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals includes: Calculate the pixel position difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals; Multiply the pixel position difference by the pixel period to obtain the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal among the multiple gate drive clock signals.

8. The debugging method as described in claim 3, characterized in that, When the level converter operates in a two-input multiple-output mode, the high-level width is formed through the following steps: The row offset is obtained by multiplying the difference between the starting row of the second gate clock source signal and the starting row of the first gate clock source signal by the total number of horizontal pixels. The difference between the pixel position of the rising edge of the second gate clock source signal and the pixel position of the rising edge of the first gate clock source signal is used as the pixel-level offset. The row-level offset is added to the pixel-level offset to obtain the high-level width.

9. The debugging method as described in claim 3, characterized in that, The level converter operates in two modes: a two-input multiple-output mode or a one-input multiple-output mode. When the level converter's operating mode includes a two-input multiple-output mode, the gate clock source signal group includes a first gate clock source signal and a second gate clock source signal. The steps for adjusting the configuration parameters include: First, adjust the position parameters of the latch pulse signal until the high level of the latch pulse signal covers the row range from the first row to the total number of vertical rows; Then adjust the position parameters of the second gate clock source signal until the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is within the timing specification range; Finally, adjust the position parameters of the frame start signal until the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal is within the timing specification range. or, When the level converter's operating mode includes a one-input multiple-output mode, and the gate clock source signal group is the first gate clock source signal, the steps for adjusting the configuration parameters include: First, adjust the position parameters of the latch pulse signal until the high level of the latch pulse signal covers the row range from the first row to the total number of vertical rows; Then adjust the preset number of cycles until the phase difference between the falling edge of the latch pulse signal and the falling edge of the gate drive clock signal is within the timing specification range; Finally, adjust the position parameters of the frame start signal until the phase difference between the falling edge of the frame start signal and the first rising edge of the first gate drive clock signal is within the timing specification range.

10. The debugging method as described in claim 1, characterized in that, After obtaining the configuration parameters of the control signals for the gate drive of the array substrate, and before obtaining the edge positions of the multiple gate drive clock signals, the debugging method further includes: Set the common propagation delay value between each gate clock source signal and the gate drive clock signal in the gate clock source signal group; The step of obtaining the edge position of the multi-gate drive clock signal further includes: superimposing the common propagation delay value onto the edge position.

11. The debugging method as described in claim 1, characterized in that, In the step of comparing the critical phase difference with a preset timing specification range, the timing specification range refers to the minimum and maximum values ​​allowed for the critical phase difference. The step of debugging and comparing the key phase difference with the preset timing specification range includes: if the key phase difference does not meet the timing specification range, then adjust the configuration parameters and return to the step of obtaining the edge positions of multiple gate drive clock signals; if the key phase difference meets the timing specification range, then end the debugging.

12. A system for debugging the gate driving timing of a display panel array substrate, characterized in that, include: The first acquisition module is used to acquire the timing basic parameters of the display panel, including the total number of horizontal pixels, the total number of vertical rows and the refresh rate, and to acquire the pixel period and row period of the display panel based on the timing basic parameters. The second acquisition module is used to acquire configuration parameters of the control signal for the array substrate gate drive. The configuration parameters include the position parameters of the frame start signal, the gate clock source signal group and the latch pulse signal, and the position parameters of the gate clock source signal group include the position parameters of one or more gate clock source signals. The third acquisition module is used to acquire the edge positions of multiple gate drive clock signals in pixel position based on the position parameters of the gate clock source signal group, and each of the gate drive clock signals is delayed by one row period. The fourth acquisition module is used to acquire the timing waveform of the control signal for the array substrate gate drive based on the edge position and the position parameters of the frame start signal and the latch pulse signal. A calculation module is used to obtain a key phase difference in the time-series waveform, wherein the step of obtaining the key phase difference includes: determining a pixel position difference based on the time-series waveform, and multiplying the pixel position difference by the pixel period to obtain the key phase difference; The debugging and comparison module is used to debug and compare the key phase difference with a preset timing specification range.

13. A terminal comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the debugging method according to any one of claims 1 to 11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is run by the processor, the debugging method according to any one of claims 1 to 11 is executed.

15. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, the debugging method described in any one of claims 1 to 11 is executed.

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