Color separation compensation method, compensation system and display device

Abstract

This application discloses a color separation compensation method, compensation system, and display device. The color separation compensation method includes: parsing input display frame image data to generate motion vector data; calculating the pre-offset of the spatial coordinates of the display sub-frame based on the effective motion vector data to generate offset address mapping data; and performing sub-pixel level grayscale weight calculation and grayscale reconstruction based on the address mapping data, outputting compensated display data. This application can adjust the processing speed of each step according to the current refresh rate of the display panel to ensure that the compensation process is consistent with the display timing, transmitting the compensated display data to the display panel according to the display timing requirements, completing color separation compensation, and ensuring stable output of the compensated image at different refresh rates. Each step can be implemented using hardware logic.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a color separation compensation method, compensation system and display device. Background Technology

[0002] Field Sequential Color (FSC) technology synthesizes colors by rapidly switching red, green, and blue (R / G / B) background light sources over time. This technology eliminates the need for color filters and has significant advantages in improving the transmittance of display panels and reducing system power consumption. It has become an important development direction in the field of high refresh rate and high resolution displays.

[0003] However, field-sequence display technology has inherent technical defects: when there are moving objects or the human eye is performing smooth pursuit in the display screen, due to the time difference in the display of different color subframes, their projection positions on the human eye's retina cannot coincide, resulting in a severe color breakup (CBU), or visual "rainbow edge". This phenomenon seriously reduces the visual effect of field-sequence display and is the core problem restricting its industrial application.

[0004] Existing compensation schemes for color separation mostly rely on software algorithms on the main control SoC to achieve motion compensation and subframe correction. When dealing with ultra-high refresh rates (such as above 180Hz) and high-resolution images, these schemes expose many unsolvable problems: First, the computational load of software operations is huge, with obvious computational delays, which cannot meet the requirements of real-time display; second, high computing power will significantly increase the power consumption of the main control SoC, which violates the technical intention of low power consumption in field-sequence display; third, the execution of software algorithms is limited by the processing power of the SoC, resulting in insufficient real-time performance in ultra-high-resolution display scenarios and a significant reduction in compensation effect.

[0005] The existing technology lacks a solution that can achieve color separation compensation at the driving hardware level (such as the TCON timing control module), and cannot achieve zero-latency, low-power motion compensation at the hardware level. Therefore, there is an urgent need to develop a field sequence display color separation compensation method and system based on hardware links. Summary of the Invention

[0006] The purpose of this application is to provide a color separation compensation method, compensation system, and display device that can achieve color separation compensation at the hardware level.

[0007] This application discloses a color separation compensation method for a color separation compensation system, the color separation compensation method comprising: Step S1: Parse the input display frame image data to generate motion vector data; Step S2: Based on the valid motion vector data, perform pre-offset calculation on the spatial coordinates of the display subframe to generate offset address mapping data; Step S3: Based on the address mapping data, complete the sub-pixel level grayscale weight calculation and grayscale reconstruction, and output the compensated display data; and Step S4: Based on the processing timing of each step, match the refresh rate of the display panel, and output the compensated display data to the display panel according to the display timing to achieve color separation compensation of the display panel at different refresh rates; The display frame is the input complete image frame, and the display subframe is a set of time-division display units obtained by splitting a display frame in the time dimension.

[0008] Optionally, the hardware compensation system includes a motion vector analysis module, which includes hardware gate-level circuitry and a motion gating unit. The step of analyzing the input display frame image data to generate motion vector data includes: The motion vector parsing module parses the input display frame image data through hardware gate circuits to generate motion vector data. After the motion gating unit filters out noise vectors, it outputs valid motion vector data. Based on the statistical results of motion intensity in the scene, when the motion intensity is lower than the preset intensity threshold, the power consumption of compensation processing in static scenes is reduced, and only the core motion vector parsing logic is retained. In the process of filtering noise, a preset noise threshold is set, motion vectors with amplitudes smaller than the noise threshold are removed, and only valid motion vector data are retained for subsequent spatial coordinate offset calculations.

[0009] Optionally, the step of pre-offsetting the spatial coordinates of the display subframe based on the valid motion vector data to generate offset address mapping data includes: Based on the amplitude value of the motion vector and the resolution parameters of the display panel, the coordinate offset is calculated. The spatial coordinates of the original display subframe are added to the offset to generate an offset address. When the offset address exceeds the physical boundary of the display panel, the offset is automatically truncated to avoid address out-of-bounds errors.

[0010] Optionally, the step of calculating sub-pixel level grayscale weights and reconstructing grayscale based on address mapping data, and outputting the compensated display data includes: Based on the fractional component of the motion vector, a corresponding grayscale weight control signal is generated. By replacing the division operation with a shift operation, grayscale sub-data with different weights are generated. The grayscale sub-data are accumulated to obtain grayscale data after subpixel level compensation.

[0011] Optionally, the step of matching the refresh rate of the display panel with the processing timing of each step, and outputting the compensated display data to the display panel according to the display timing to achieve color separation compensation of the display panel at different refresh rates includes: Generate a processing clock adapted to the display refresh rate, and synchronize the processing clocks of each step, such as motion vector analysis, coordinate pre-offset, and grayscale reconstruction, with the display timing clock to avoid data transmission conflicts and ensure real-time output of compensation data.

[0012] Optionally, the step of reducing the power consumption of compensation processing in static scenes and retaining only the core motion vector parsing logic when the motion intensity is lower than a preset intensity threshold, based on the statistical results of the image motion intensity, includes: The horizontal and vertical components of the original motion vector are input into the motion gating unit to eliminate interference from the motion direction, and the magnitude data of the motion vector is output, retaining only the motion intensity information; The summation of the horizontal and vertical modulus data yields the overall motion intensity of the current display area, quantifying the intensity of the motion. The comprehensive motion intensity data is compared with the preset motion judgment threshold in the hardware threshold register in real time. If the motion intensity is less than or equal to the preset threshold, the clock signal of the subsequent compensation circuit is physically turned off by the AND gate circuit, and the motion vector data is no longer passed down. If the motion intensity exceeds the preset threshold, the comparator outputs an enable signal and releases the motion vector data to the next compensation module.

[0013] Optionally, the color separation compensation method further includes a multi-refresh-rate adaptation step: based on the refresh rate signal of the display panel, the corresponding timing parameters are automatically switched from the multi-refresh-rate adaptation register, and the clock synchronization submodule synchronizes the processing clock of each module with the display timing clock to achieve real-time compensation output under different refresh rates.

[0014] This application also discloses a color separation compensation system, which generates compensated display data and outputs it to the display panel using any of the color separation compensation methods described above. The hardware compensation system includes a motion vector analysis module, an asynchronous address mapping engine, a zero division subpixel interpolation unit, and a timing control module. The motion vector analysis module is used to perform motion vector analysis on the input display frame image data, generating analytical data containing the direction and amplitude of the motion vectors. The asynchronous address mapping engine is connected to the motion vector analysis module and adopts an asynchronous dual-port storage architecture. It uses a hardware adder to perform pre-offset calculation of the spatial coordinates of the display subframes, generating offset address mapping data. The zero-division subpixel interpolation unit is connected to the asynchronous address mapping engine. It uses a barrel shift register to replace the divider and performs subpixel-level grayscale weight calculation and grayscale reconstruction based on the address mapping data, outputting compensated display data. The timing control module is electrically connected to the motion vector analysis module, the asynchronous address mapping engine, and the zero-division subpixel interpolation unit, respectively, to synchronize the clock signals of each module and match the refresh rate of the display panel.

[0015] Optionally, the motion vector parsing module includes a hardware gate circuit and a motion gating unit. The hardware gate circuit parses the input display frame image data to generate motion vector data. After the motion gating unit filters out noise vectors, it outputs valid motion vector data. The asynchronous address mapping engine includes a first asynchronous dual-port, a hardware adder, and an address offset register. The asynchronous dual-port caches the spatial coordinate data and motion vector parsing data of the original display frame image, and supports asynchronous parallel execution of read and write operations. The hardware adder calculates the coordinate offset in real time based on the amplitude value in the motion vector parsing data, and accumulates the spatial coordinates and offset of the original display frame image to generate the offset address mapping data. The zero-division subpixel interpolation unit includes a barrel shift register group, a grayscale weight lookup table unit, and an accumulator. The barrel shift register group is used to shift the spatial coordinates of the input original display frame image by a preset number of bits to generate grayscale sub-data with different weights. The preset number of bits matches the bit width of the fractional component of the motion vector. The grayscale weight lookup table unit is used to store the grayscale weight parameters corresponding to the fractional component of the motion vector, and outputs the corresponding weight control signal according to the address mapping data to complete the shift operation with the driving barrel shift register group. The accumulator is connected to the barrel shift register group and performs an accumulation operation on the shifted grayscale sub-data to generate subpixel-level compensated grayscale data. The timing control module includes a phase-locked loop unit, a multi-refresh-rate adaptation register, and a clock synchronization submodule. The phase-locked loop unit is used to amplify the input reference clock signal in phase lock. The clock synchronization submodule is connected to the motion vector analysis module, the asynchronous address mapping engine, and the zero-division subpixel interpolation unit, respectively, and realizes signal timing synchronization between the modules through clock domain cross-processing.

[0016] This application also discloses a display device, which includes a display panel and a color separation compensation system as described above. The color separation compensation system generates display data as described above using the color separation compensation method to achieve color separation compensation of the display panel at different refresh rates.

[0017] Compared to solutions that rely on software algorithms on the main control SoC to achieve motion compensation and subframe correction, this application can adjust the processing speed of each step according to the current refresh rate of the display panel (e.g., 180Hz), so that the compensation process is consistent with the display timing. The compensated display data is transmitted to the display panel according to the display timing requirements to complete color separation compensation. This ensures that the compensated image can be stably output at different refresh rates. Each step can be implemented by hardware logic, with fast processing speed and no software calculation delay. It ensures that the compensation process is synchronized with the display timing, avoids secondary image distortion caused by compensation delay, does not require additional complex functions, and can be adapted to various basic display scenarios. Attached Figure Description

[0018] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic flowchart of the color separation compensation method according to the first embodiment of this application; Figure 2 This is a schematic diagram of the hardware compensation system structure according to the second embodiment of this application; Figure 3 This is a schematic flowchart of the color separation compensation method according to the second embodiment of this application; Figure 4 This is another signal output schematic diagram corresponding to the color separation compensation method of the second embodiment of this application; Figure 5 This is a schematic diagram of the signal output corresponding to the color separation compensation method of the second embodiment of this application; Figure 6 This is a schematic flowchart of the color separation compensation method according to the third embodiment of this application; Figure 7 This is a schematic flowchart of the color separation compensation method according to the fourth embodiment of this application; Figure 8 This is a schematic diagram of the signal output corresponding to the color separation compensation method of the fourth embodiment of this application; Figure 9 This is a schematic flowchart of the color separation compensation method according to the fifth embodiment of this application; Figure 10 This is a schematic diagram of the hardware compensation system structure according to the sixth embodiment of this application; Figure 11 This is a schematic diagram of the structure of the display device according to the seventh embodiment of this application.

[0019] Among them, 100 is the hardware compensation system; 110 is the motion vector analysis module; 111 is the hardware gate-level circuit; 112 is the motion gating unit; 120 is the asynchronous address mapping engine; 121 is the first asynchronous dual-port; 122 is the hardware adder; 123 is the address offset register; 130 is the zero division subpixel interpolation unit; 131 is the barrel shift register group; 132 is the grayscale weight lookup table unit; 133 is the accumulator; 140 is the TCON timing control module; 141 is the PLL phase-locked loop unit; 142 is the multi-refresh-rate adaptation register; 143 is the clock synchronization submodule; 200 is the display panel; and 300 is the display device. Detailed Implementation

[0020] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0021] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0022] refer to Figure 1 As shown, as a first embodiment of this application, a color separation compensation method is disclosed. This color separation compensation method is used in a color separation compensation system, and the color separation compensation method includes: Step S1: Parse the input display frame image data to generate motion vector data; Step S2: Based on the valid motion vector data, perform pre-offset calculation on the spatial coordinates of the display subframe to generate offset address mapping data; Step S3: Based on the address mapping data, complete the sub-pixel level grayscale weight calculation and grayscale reconstruction, and output the compensated display data; and Step S4: Based on the processing timing of each step, match the refresh rate of the display panel, and output the compensated display data to the display panel according to the display timing to achieve color separation compensation of the display panel at different refresh rates; The display frame is the input complete image frame, and the display subframe is a set of time-division display units obtained by splitting a display frame in the time dimension.

[0023] In this embodiment, continuous frame image data transmitted from the display panel is received, the pixel displacement information of each frame image is analyzed, the motion trajectory of each pixel in the image is captured, and motion vector data containing the direction (horizontal / vertical direction) and amplitude (pixel displacement distance) of the motion vector is generated. This analysis process is completed by hardware logic to ensure analysis efficiency and provide accurate motion reference for subsequent compensation. Valid motion vector data is filtered out (invalid interference data is removed), and the spatial coordinate offset of each field sequence subframe is calculated based on the amplitude value of the motion vector. The spatial coordinates of the original subframe are calculated with the offset to generate offset address mapping data, realizing the initial calibration of the subframe spatial position and ensuring that the subframe position matches the motion trajectory.

[0024] Furthermore, based on the address mapping data, the sub-pixel level grayscale weight of each pixel is determined. The grayscale weight is calculated through corresponding operations, and then the grayscale data is reconstructed to correct the grayscale deviation caused by color separation. Finally, the compensated display data is output to ensure that the compensated data can correct the color separation defect. The processing timing of steps S1 to S3 is synchronized. According to the current refresh rate of the display panel (e.g., 180Hz), the processing speed of each step is adjusted to keep the compensation process consistent with the display timing. The compensated display data is transmitted to the display panel according to the display timing requirements to complete the color separation compensation and ensure that the compensated image can be stably output at different refresh rates.

[0025] Correspondingly, the hardware compensation system 100 includes a motion vector parsing module 110, an asynchronous address mapping engine 120, a zero-division subpixel interpolation unit 130, and a TCON timing control module 140. The motion vector analysis module 110 is used to perform motion vector analysis on the input display frame image data, generating analysis data containing the direction and amplitude of the motion vectors. The analysis process of the motion vector analysis module 110 is implemented entirely in hardware gate-level circuits without software involvement. The asynchronous address mapping engine 120 is connected to the motion vector analysis module 110 and adopts an asynchronous dual-port storage architecture. It uses a hardware adder to perform pre-offset calculation of the subframe spatial coordinates and generates offset address mapping data. The zero-division subpixel interpolation unit 130 is connected to the asynchronous address mapping engine. It uses a barrel shift register to replace the divider and performs subpixel-level grayscale weight calculation and grayscale reconstruction based on the address mapping data, outputting the compensated display data. The TCON timing control module 140 is electrically connected to the motion vector analysis module 110, the asynchronous address mapping engine 120, and the zero-division subpixel interpolation unit 130, respectively, and is used to synchronize the clock signals of each module to match the display refresh rate.

[0026] As can be seen from the above, the motion vector analysis module is connected to the asynchronous address mapping engine, the asynchronous address mapping engine is connected to the zero division subpixel interpolation unit, and the timing control module is electrically connected to the above three modules respectively to synchronize the clock signals of each module, ensuring a smooth compensation process. This improves the situation where traditional compensation methods rely heavily on software calculations, have processing delays, cannot adapt to the real-time requirements of display, and are difficult to balance the compensation stability at different refresh rates, resulting in a decrease in display quality and affecting the user's viewing experience.

[0027] refer to Figure 3 As shown, as a second embodiment of this application, it is a further refinement and improvement of the first embodiment described above. The hardware compensation system includes a motion vector analysis module, which includes a hardware gate-level circuit and a motion gating unit. Step S1 includes: Step S11: The motion vector parsing module parses the input display frame image data through hardware gate circuits to generate motion vector data. After the noise vectors are filtered by the motion gating unit, the valid motion vector data is output. Step S12: Based on the statistical results of motion intensity in the scene, when the motion intensity is lower than the preset intensity threshold, reduce the power consumption of compensation processing in static scenes and retain only the core motion vector parsing logic; In the process of filtering noise, a preset noise threshold is set, motion vectors with amplitudes smaller than the noise threshold are removed, and only valid motion vector data are retained for subsequent spatial coordinate offset calculations.

[0028] The step of reducing the power consumption of compensation processing in static scenes and retaining only the core motion vector parsing logic when the motion intensity is lower than a preset intensity threshold, based on the statistical results of the motion intensity of the scene, includes: The horizontal and vertical components of the original motion vector are input into the motion gating unit to eliminate interference from the motion direction, and the magnitude data of the motion vector is output, retaining only the motion intensity information; The summation of the horizontal and vertical modulus data yields the overall motion intensity of the current display area, quantifying the intensity of the motion. The comprehensive motion intensity data is compared with the preset motion judgment threshold in the hardware threshold register in real time. If the motion intensity is too low, the clock signal of the subsequent compensation circuit is physically turned off by the AND gate circuit, and the motion vector data is no longer passed down. If the motion intensity exceeds the preset threshold, the comparator outputs an enable signal and releases the motion vector data to the next compensation module.

[0029] Correspondingly, the motion vector parsing module includes a hardware gate circuit and a motion gating unit. The hardware gate circuit parses the input display frame image data to generate motion vector data. After the motion gating unit filters out noise vectors, it outputs valid motion vector data. The asynchronous address mapping engine includes a first asynchronous dual-port, a hardware adder, and an address offset register. The asynchronous dual-port caches the spatial coordinate data and motion vector parsing data of the original display frame image, and supports asynchronous parallel execution of read and write operations. The hardware adder calculates the coordinate offset in real time based on the amplitude value in the motion vector parsing data, and accumulates the original coordinates and the offset to generate the offset address mapping data. The zero-division subpixel interpolation unit includes a barrel shift register group, a grayscale weight lookup table unit, and an accumulator. The barrel shift register group is used to shift the spatial coordinates of the input original display frame image by a preset number of bits to generate grayscale sub-data with different weights. The preset number of bits matches the bit width of the fractional component of the motion vector. The grayscale weight lookup table unit is used to store the grayscale weight parameters corresponding to the fractional component of the motion vector and outputs the corresponding weight control signal according to the address mapping data to drive the barrel shift register group to complete the shift operation. The accumulator is connected to the barrel shift register group and performs an accumulation operation on the shifted grayscale sub-data to generate subpixel-level compensated grayscale data. The timing control module includes a phase-locked loop (PLL) unit, a multi-refresh-rate adaptation register, and a clock synchronization submodule. The PLL unit amplifies the input reference clock signal to generate a hardware processing clock of 300MHz or higher, matching the high-speed computing requirements of each module. The multi-refresh-rate adaptation register stores timing parameters for different refresh rates such as 180Hz, 240Hz, and 360Hz, automatically switching parameters based on the refresh rate signal from the display panel to achieve multi-refresh-rate adaptation. The clock synchronization submodule is connected to the motion vector analysis module, the asynchronous address mapping engine, and the zero-division subpixel interpolation unit, respectively, and achieves signal timing synchronization between modules through clock domain cross-processing.

[0030] In this embodiment, the main focus is on noise filtering of motion vectors and functional optimization of static scenes. The motion vector parsing module parses the input display frame image data through hardware gate-level circuits to generate motion vector data. The motion gating unit performs noise filtering: it sets a preset noise threshold (e.g., 0.5 pixels), discards motion vectors with amplitudes smaller than this threshold, and retains only valid motion vector data for subsequent spatial coordinate offset calculations; it also filters static backgrounds through hardware logic to prevent noise from causing image jitter. For details, please refer to... Figure 4 As shown, the absolute value operation units 1 & 2 convert MV_x and MV_y into non-negative magnitudes to eliminate the interference of directionality on intensity. The adder calculates |MV_x| + |MV_y| to obtain the estimated synthetic motion intensity of the current pixel block. A 16-bit threshold register is set to store the preset motion compensation start threshold (which can be adjusted through firmware).

[0031] Threshold setting and quantization standard: Quantization range: The MV modulus is stored in a 16-bit register, corresponding to the screen pixel displacement.

[0032] Judgment criteria: The noise threshold is set to 0.5 pixels. If the intensity is lower than this value, it is considered background noise or hand shaking, and the subsequent compensation clock is turned off to save circuit power consumption.

[0033] The high-speed judgment threshold is set to 4 pixels. If this value is exceeded, sub-pixel level full-precision interpolation will be activated.

[0034] Firmware adjustment criteria: dynamically written based on the monitor refresh rate (e.g., 180Hz or 240Hz) and liquid crystal response time (Tr / Tf). The higher the refresh rate, the smaller the allowable displacement threshold.

[0035] Furthermore, the numerical comparator compares the synthesized motion intensity with a threshold. If the intensity is greater than the threshold, it outputs a logic "1". (By combining the "comparison result" and the "global enable signal" through an AND gate, a trigger pulse is output only when both conditions are met simultaneously, activating the subsequent offset and interpolation modules, thereby reducing system power consumption in static scenes.) The power consumption optimization steps for static scenes are as follows: The horizontal and vertical components of the original motion vector are input into the motion gating unit to eliminate interference from the motion direction, and the magnitude data of the motion vector is output, retaining only the motion intensity information; The summation of the horizontal and vertical modulus data yields the overall motion intensity of the current display area, quantifying the intensity of the motion. The comprehensive motion intensity data is compared in real time with the preset motion judgment threshold in the hardware threshold register. If the motion intensity is too low (below the preset intensity threshold), the clock signal of the subsequent compensation circuit is physically turned off by the AND gate circuit, and the motion vector data is no longer passed down; if the motion intensity exceeds the preset threshold, the comparator outputs an enable signal, releasing the motion vector data to the asynchronous address mapping engine, realizing noise filtering, reducing power consumption in static scenes, and improving compensation accuracy and system energy efficiency.

[0036] Preset motion detection threshold logic: Low-speed motion (no interpolation required): 0.5 pixel ≤ |MV| < 2 pixel. In this case, only the offset engine module is activated for integer pixel displacement, and the interpolation unit is turned off to save power.

[0037] High-speed motion (full-precision compensation): |MV|≥2 pixels. At this point, the rainbow effect is severe, and the entire image is activated.

[0038] Static / very slight motion: |MV| < 0.5 pixels. The system classifies this as noise, performs no compensation, and maintains the original display timing.

[0039] Beneficial effects: Enables hardware-based analysis and effective determination of motion vectors, filters noise signals, avoids invalid compensation operations, provides accurate input signals for subsequent hardware compensation, and reduces meaningless circuit power consumption.

[0040] Coordinate offset based on asynchronous address mapping engine (offset engine module) such as Figure 5 Functional modules: This module implements "spatial remapping" in a physical sense, converting time deviation into spatial displacement.

[0041] Offset Latch: When the parsing hardware issues a trigger pulse, it latches the current MV Data and outputs compensation data [9:0]. Compensation Data Generation: From MV to address offset, data latching and retrieval: After receiving the trigger pulse from the parsing hardware, the offset latch latches the current MV signal. It extracts the integer bits to form the compensation data [9:0]. Hardware Addition Mapping: The 10-bit CLA (Carry-Look-Ahead Adder) receives this compensation data. Execution Logic: The adder adds the "base address" (the address currently being scanned normally) to the "compensation data". Calculation Result: The resulting Sum address is the compensated physical read position; Example: If the integer part of MV is +5, the compensation data is 5. The adder causes the read pointer to jump 5 pixels to the right, thus achieving spatial pre-offset of the subframe at the physical layer.

[0042] 10-bit CLA adder (carry-lookahead adder): Performs high-speed summation between the original base address and the compensation data. Its function is to calculate the asynchronous read address (Sum address) of the current subframe after retinal alignment.

[0043] Threshold comparator (boundary detection): Real-time monitoring of whether the Sum address exceeds the physical boundary of the screen row pixels.

[0044] Boundary security assessment: To prevent compensation data from causing the system to access illegal addresses, strict hardware boundaries are set: Physical boundary setting: The threshold comparator monitors in real time whether the Sum address exceeds the physical boundary of the screen row pixels (such as 3840 for a 4K screen).

[0045] MUX switching logic: If the compensation shift caused by MV causes address overflow, the 2:1 MUX forcibly cuts off the adder output and instead outputs a preset safe address (such as a black background pixel) through the address constant register.

[0046] Function: This ensures that no matter how drastically the MV changes, the physical address generated by the compensation data is always within the legal range, avoiding screen flickering and other abnormalities.

[0047] Address constant register / address constant unit: Provides a preset "safe address" (such as a black background or edge-padded address).

[0048] 2:1 MUX (Multiplexer): Based on the boundary detection results, it determines whether to output a sum address or a constant address. Its function is to prevent display distortion (display abnormalities) caused by out-of-bounds access.

[0049] Final output: Generates the physical read address [9:0] and sends it to the frame buffer (8T-SRAM). This value is not fixed and changes according to the information displayed on the screen. FHD (1080P) resolution: physical boundary value is 1920. Address range is 0 ~ 1919.

[0050] QHD (2K) resolution: Physical boundary value is 2560. Address range is 0 ~ 2559.

[0051] UHD (4K) resolution: Physical boundary value is 3840. Address range is 0 ~ 3839.

[0052] It's also important to note that in the hardware logic, the motion vector (MV Data) is not a single numerical value, but rather a set of parallel bit signals carrying physical meaning. To achieve hardware-based compensation, the system deconstructs it into two parts: an integer part, used to drive the "pixel offset engine," which determines the physical address jump amount of a pixel in the row / column direction.

[0053] The fractional part: used to drive the "parallel subpixel interpolation unit," determining the grayscale weighting ratio between adjacent pixels. Physical meaning: 1 unit of MV integer data strictly corresponds to 1 pixel storage unit in display memory.

[0054] like Figure 6 As shown, the third embodiment of this application is a further refinement and improvement of any of the above embodiments. Step S2 includes: S21: Calculate the coordinate offset based on the amplitude value of the motion vector and the resolution parameters of the display panel. Add the original subframe spatial coordinates to the offset to generate an offset address. When the offset address exceeds the physical boundary of the display panel, the offset is automatically truncated to avoid address out-of-bounds errors.

[0055] This example primarily demonstrates the specific process of coordinate pre-offset calculation in step S2 and the working mechanism of the asynchronous address mapping engine. In the corresponding hardware compensation system, the asynchronous address mapping engine includes a first asynchronous dual-port, a hardware adder, and an address offset register. The asynchronous dual-port caches the spatial coordinate data and motion vector analysis data of the original frame image, supporting asynchronous parallel execution of read and write operations. The hardware adder calculates the coordinate offset in real time based on the amplitude value in the motion vector analysis data and the resolution parameters of the display panel (e.g., FHD resolution). It accumulates the original subframe spatial coordinates with the calculated offset to generate an offset address. The offset address is monitored in real time; when it exceeds the physical boundary of the display panel, the offset is automatically truncated and adjusted to the maximum value of the panel's physical boundary to avoid display anomalies caused by address overflow. The address offset register stores preset basic offset parameters, which can be flexibly adjusted according to the display panel's resolution to ensure the accuracy of coordinate pre-offset calculation in different resolution scenarios. The remaining steps S1 and S3-S4 are consistent with any of the above embodiments.

[0056] Furthermore, the color separation compensation method also includes a multi-refresh-rate adaptation step: based on the refresh rate signal of the display panel, the corresponding timing parameters are automatically switched from the multi-refresh-rate adaptation register, and the clock synchronization submodule synchronizes the processing clock of each module with the display timing clock to achieve real-time compensation output under different refresh rates.

[0057] In the hardware compensation system, the TCON timing control module's multi-refresh-rate adaptation register stores timing parameters for three different refresh rates: 180Hz, 240Hz, and 360Hz, supporting automatic parameter switching. Specifically, the hardware compensation system receives the refresh rate signal from the display panel in real time (e.g., switching to 240Hz). Based on this refresh rate signal, the TCON timing control module automatically switches the corresponding 240Hz timing parameters from the multi-refresh-rate adaptation register. The PLL phase-locked loop unit adjusts the hardware processing clock to 350MHz to match the high-speed computing requirements of the 240Hz refresh rate. The clock synchronization submodule synchronizes the processing clocks of each module with the 240Hz display timing clock, achieving real-time compensation output at the 240Hz refresh rate. When the refresh rate switches to 360Hz, the above steps are repeated. The PLL phase-locked loop unit adjusts the hardware processing clock to 400MHz, automatically switching the timing parameters corresponding to 360Hz without requiring manual adjustment of the compensation logic. The remaining steps S1-S4 are consistent with Embodiment 1 or 2, achieving flexible multi-refresh-rate adaptation.

[0058] This embodiment designs an asynchronous address mapping engine, adopts an asynchronous dual-port storage architecture, changes the pixel reading order in real time through a hardware address adder, realizes spatial pre-offset of subframes at the physical layer, completes spatial transformation of motion vectors from the address reading level, and adapts to the display characteristics of the subframes.

[0059] Based on the asynchronous address mapping engine, spatial coordinate mapping of the integer part of the motion vector is implemented, and spatial pre-offset of subframes is completed at the physical layer. Further detailed steps are as follows: ① Data latching: The enable signal output by the parsing hardware module triggers the offset latch, which formally stores the motion vector data into the timing domain driven by TCON, thus completing the synchronous latching of the motion vector signal; ② Address calculation: An asynchronous dual-port storage architecture is adopted, and the integer part of the motion vector is received through a 10-bit CLA carry-lookahead adder. _ As a bias, it is related to the pixel reference address. _ Perform hardware addition to obtain the corrected pixel readout address. _ The hardware implementation formula is: _ = _ + ( _ ); Formula Explanation: Offset Function ( _ It is defined as a linear address mapping operator, whose core function is to map displacements in pixels. _ This is converted into a linear address bias in the frame buffer.

[0060] The specific hardware conversion logic of this function is as follows: .

[0061] Integer components of the horizontal and vertical motion vectors separated by the analytical hardware module; (Row span): The number of physical storage units occupied by each row of the display (e.g., 3840 for 4K resolution). The direction coefficient is determined by the sign bit of MV. It is 1 for forward movement and the address is decremented by two's complement arithmetic for reverse movement.

[0062] Conversion process: Unit correspondence: The hardware circuit will convert 1 unit _ It is directly mapped to the address of a 1-pixel memory cell on the memory address bus.

[0063] Bias stacking: 10-bit CLA carry-lookahead adder receives this ( _ As a result, this is used as an offset and accumulated in real time to the pixel reference address. _ superior.

[0064] Asynchronous mapping: This conversion process is performed during the reading phase, directly changing the read pointer position of the 8T-SRAM, thereby achieving spatial pre-offset of subframes at the physical reading level without changing the data storage order.

[0065] ③ Boundary protection: The threshold comparator and the multiplexer MUX work together to perform boundary detection on the corrected read address; if the calculated address overflows due to excessive displacement, the MUX will force a switch to the safe pixel value provided by the address constant register to avoid display abnormalities caused by address out of bounds; The reference value for determining whether the displacement is too large is determined by the effective display resolution of the display panel: For FHD (1080P) specifications: the maximum physical boundary value is 1919.

[0066] For UHD (4K) specifications: the maximum physical boundary value is 3839.

[0067] Address start boundary: The minimum physical boundary value for all specifications is 0.

[0068] The hardware determines that the address overflow is caused by "excessive displacement" when the calculated corrected address meets any of the following conditions: Positive overflow (right boundary out of bounds): (For example, in 4K mode,) (≥3840). This typically occurs when the motion vector MV is large and the current pixel is at the right edge of the screen.

[0069] Negative overflow (left boundary out of bounds): <0, which typically occurs when MV is negative (moving to the left) and the current pixel is at the left edge of the screen.

[0070] ④ Address Output: The corrected valid read address is output to the storage module to change the pixel readout order in real time and realize the spatial pre-offset of the display subframe at the physical layer.

[0071] The corrected valid read address Subsequently, the hardware implements real-time realignment of the pixel readout order through the following logic: Traditional readout order (sequential addressing): In the absence of motion compensation, the read counter inside the TCON generates an incrementing address 0, 1, 2, … N, and the frame buffer (8T-SRAM) outputs pixels sequentially according to the physical storage order.

[0072] Corrected read order (jump / offset addressing): Pre-read (moving to the right): If the motion vector MV determines that the object has moved K pixels to the right, then = _ + K. At this point, at time T0 of the current scan sequence, the address decoder skips the intermediate pixels and directly selects the N+Kth memory unit. Delayed read (moving left): If moving K pixels to the left, then = _ - K. At this point, the memory outputs the historical pixel data to the left of this scan point.

[0073] The asynchronous address mapping engine enables hardware-based coordinate offset of motion vectors, eliminating software computation delays. Subframe space compensation is completed at the pixel reading level, adapting to the high-speed subframe switching characteristics of the display. At the same time, boundary protection prevents address out-of-bounds access, ensuring display stability.

[0074] refer to Figure 7 As shown, this fourth embodiment of the present application is a further refinement and improvement of any of the above embodiments. Step S3 includes: S31: Based on the fractional component of the motion vector, generate the corresponding grayscale weight control signal, replace the division operation with a shift operation to generate grayscale sub-data with different weights, and perform an accumulation operation on the grayscale sub-data to obtain grayscale data after subpixel level compensation.

[0075] This embodiment focuses on the specific process of subpixel-level grayscale weight calculation and grayscale reconstruction in step S3, as well as the working mechanism of the zero-division subpixel interpolation unit. In the corresponding hardware compensation system, the zero-division subpixel interpolation unit includes a barrel shift register group, a grayscale weight lookup table unit, and an accumulator. These units work together to complete subpixel-level compensation. The bit width of the fractional component of the motion vector is extended to 6 bits, and the grayscale weight lookup table unit stores the 10-bit grayscale weight parameters corresponding to the 6-bit fractional component. Based on the fractional component of the motion vector, a corresponding grayscale weight control signal is generated. The grayscale weight lookup table unit outputs the weight control signal according to the address mapping data, which drives the barrel shift register group to complete the 0-5 bit shifting process. By replacing the division operation with the shift operation, grayscale sub-data with different weights are generated. The accumulator performs a 16-bit accumulation operation on the four shifted grayscale sub-data to obtain the sub-pixel level compensated grayscale data, completes the grayscale reconstruction, and outputs the compensated display data.

[0076] The preset shift number of the barrel shift register group matches the bit width (6 bits) of the fractional component of the motion vector to ensure the accuracy of grayscale weight calculation. The remaining steps S1-S2 and S4 can be consistent with any of the above embodiments to achieve sub-pixel level high-precision compensation.

[0077] Further reference Figure 8 As shown, the zero-division subpixel grayscale reconstruction (interpolation unit module) and various functional modules complete subpixel precision grayscale synthesis within an extremely short subframe time.

[0078] 8T-SRAM frame buffer: Adopts a read-write separation architecture, outputting data from two adjacent pixels simultaneously based on the "asynchronous physical read address" provided by the upper-level engine. and .

[0079] The system analyzes the motion vector components output by the hardware module. and The absolute value of the value determines the selected dimension. Horizontal selection logic: ≥ Currently, the movement is primarily horizontal. At this time, the address decoder is reading... (Right now At the same time, it automatically selects the next pixel with the logical address adjacent in the same row. (Right now ).

[0080] Vertical selection logic: < | Primarily vertical movement. At this time, The selection rules become + (in (Total pixels in a single row), which means extracting the adjacent pixels directly below the current pixel.

[0081] Subpixel weight lookup table (lookup table): Receives the fractional component of MV and outputs two shift control instructions. Its function is to define the contribution ratio of two pixels to the final color.

[0082] Bit width setting: This scheme uses a 4-bit bit width to represent the fractional component of MV; The lookup table outputs "Shift Instruction 1" and "Shift Instruction 2," which control two barrel shift registers respectively. Their core logic is to simulate grayscale weighting (1...). ) and ; Encoding rule: Instructions are directly mapped to the number of bits to shift right in a shift register. Shift instruction 1 (control) ): Corresponding weight 1 .when When increasing, the number of bits shifted to the right increases; when decreasing... . brightness contribution.

[0083] Shift instruction 2 (control) +1): Corresponding weight .when When the value increases, the number of bits shifted to the right decreases, and the value increases. +1 brightness contribution.

[0084] Barrel shift registers 1 & 2: Perform hardware shift operations. Their function is to replace the high-power "divider" and achieve fast weighted calculations.

[0085] For example, shifting right by 0 bits represents 100% weight, full weight output, and no brightness loss; Shifting right by 1 bit represents 50% weighting, and the weights are combined in half. Shifting right by 2 bits represents a 25% weight, and a quarter weight is used for composition. Shifting right by 3 bits represents a 12.5% ​​weight, which is the weight of an eighth of the total weight.

[0086] Binary accumulator: Summes the processed weighted data Pn and weighted data Pn+1 to synthesize the final grayscale value.

[0087] Pipeline latch: Latches calculation results under clock (CLK) drive. Its function is to implement pipelined operation and ensure that the data output is strictly synchronized with the clock cycle of the source driver; Source driver interface: Receives synchronous output signals and drives the display panel to form an image.

[0088] This embodiment uses a zero-division subpixel processing method to achieve subpixel-level grayscale compensation for the fractional part of the motion vector. The specific execution steps are as follows: Controlled generation: fractional components of motion vectors The input interpolation unit module drives the subpixel weight lookup table, and the lookup table outputs the corresponding hardware control instructions. Shift control: The "Shift Instruction 1" and "Shift Instruction 2" output from the lookup table are sent to two barrel shift registers respectively. The number of shift bits in the barrel shift registers is used to simulate the grayscale weighting (1... )and It replaces the traditional divider to achieve hardware implementation of weights; Grayscale blending: merging the grayscale values ​​of adjacent pixels. _ and _( +1) Input the data into two barrel shift registers respectively. After shift scaling, hardware summation is performed in the binary accumulator to obtain the final output grayscale. _ Hardware implementation of grayscale weighted interpolation formula: _ = _ ×(1 )+ +1× ; Input bit width: raw pixels and The grayscale bit width of +1 is set to 10-bit (quantization range is 0 ~ 1023) to adapt to the high dynamic range display requirements; Internal operation bit width: In order to ensure that multiplication (shift) operations do not lose precision, the internal hardware accumulator uses a 14-bit width for intermediate result processing.

[0089] Since this scheme uses a barrel shift register to simulate multiplication weights, the following rules are implemented to address the potential issue of discarding low-order bits after shifting: Truncation rule: When When driving the barrel shifter to perform a right shift operation, the hardware directly discards the least significant bit (LSB) that exceeds the bit width definition. Compensation rounding: To compensate for the loss of average brightness caused by truncation, the hardware performs "add 1 and round" logic on the discard bits in the middle position before summing in the binary accumulator. Specific logic: If the highest bit being shifted out is 1, then add 1 to the result of the remaining valid bits, similar to rounding, thereby controlling the calculation error within ±0.5 LSB. Furthermore, an HDR / SDR switching switch is added to the interpolation unit module. The main control logic automatically adjusts the shift precision of the barrel shift register and the bit width of the accumulator according to the dynamic range signal (HDR enable signal) of the input image (the accumulator bit width is expanded to 16-bit in HDR mode and remains at 14-bit in SDR mode) to adapt to the grayscale requirements of different display scenarios.

[0090] refer to Figure 9 As shown, the fifth embodiment of this application is a further improvement and refinement of any of the above embodiments. Step S4 includes: S41: Generates a processing clock adapted to the display refresh rate, synchronizing the processing clocks for each step of motion vector analysis, coordinate pre-offset, and grayscale reconstruction with the display timing clock to avoid data transmission conflicts and ensure real-time output of compensation data.

[0091] This embodiment focuses on the specific process of timing synchronization in step S4, and the working mechanism of the TCON timing control module, as follows: In the hardware compensation system corresponding to step S4, the TCON timing control module includes a PLL phase-locked loop unit, a multi-refresh-rate adaptation register, and a clock synchronization submodule, used to realize timing synchronization and refresh rate adaptation of each module; specifically, the PLL phase-locked loop unit amplifies the input reference clock signal to generate a 300MHz hardware processing clock to match the high-speed computing requirements of each module; and generates a processing clock adapted to the display refresh rate (e.g., 180Hz). The clock synchronization submodule synchronizes the processing clocks of motion vector analysis, coordinate pre-offset, and grayscale reconstruction with the display timing clock through clock domain cross-processing to avoid data transmission conflicts. The compensated display data is output to the display panel according to the display timing sequence to ensure real-time output of the compensated data and realize color separation compensation of the display panel at a refresh rate of 180Hz. The multi-refresh-rate adaptation register pre-stores the timing parameters of 180Hz to support timing synchronization. The remaining steps S1-S3 can be consistent with any of the above embodiments to ensure the real-time performance and stability of the compensation process.

[0092] refer to Figure 10 As shown, as the sixth embodiment of this application, a color separation compensation system 100 is disclosed, which is a further improvement and refinement of the first embodiment described above. The motion vector analysis module 110 includes a hardware gate circuit 111 and a motion gating unit 112. The hardware gate circuit 111 analyzes the input display frame image data to generate motion vector data. After the motion gating unit 112 filters out noise vectors, it outputs valid motion vector data. The asynchronous address mapping engine 120 includes a first asynchronous dual-port 121, a hardware adder 122, and an address offset register 123. It uses the asynchronous dual-port to cache the spatial coordinate data and motion vector analysis data of the original display frame image, and supports asynchronous parallel execution of read and write operations. The hardware adder 122 calculates the coordinate offset in real time based on the amplitude value in the motion vector analysis data, and accumulates the original coordinates and the offset to generate the offset address mapping data. The zero-division subpixel interpolation unit 130 includes a barrel shift register group 131, a grayscale weight lookup table unit 132, and an accumulator 133. The barrel shift register group 131 is used to shift the input raw grayscale data by a preset number of bits to generate grayscale sub-data with different weights. The preset number of bits matches the bit width of the fractional component of the motion vector. The grayscale weight lookup table unit 132 is used to store the grayscale weight parameters corresponding to the fractional component of the motion vector and output the corresponding weight control signal according to the address mapping data to drive the barrel shift register group to complete the shift operation. The accumulator 133 is connected to the barrel shift register group and performs an accumulation operation on the shifted grayscale sub-data to generate subpixel-level compensated grayscale data. The TCON timing control module 140 includes a PLL phase-locked loop unit 141, a multi-refresh-rate adaptation register 142, and a clock synchronization submodule 143. The PLL unit 141 is used to amplify the input reference clock signal to generate a hardware processing clock of 300MHz or higher to match the high-speed computing requirements of each module. The multi-refresh-rate adaptation register is used to store timing parameters for different refresh rates such as 180Hz, 240Hz, and 360Hz, and automatically switches parameters according to the refresh rate signal of the display panel to achieve multi-refresh-rate adaptation. The clock synchronization submodule is connected to the motion vector analysis module 110, the asynchronous address mapping engine 120, and the zero-division subpixel interpolation unit 130, respectively, and achieves signal timing synchronization between modules through clock domain cross-processing.

[0093] Referring to Figure 11, as the seventh embodiment of this application, a display device 300 is disclosed, which integrates the above-mentioned hardware compensation system to realize color separation compensation at different refresh rates. The display device includes a display panel (such as an OLED display panel) and a color separation compensation system. The hardware compensation system adopts the hardware compensation system structure described in any one of the first to sixth embodiments, including a motion vector analysis module 110, an asynchronous address mapping engine 120, a zero division subpixel interpolation unit 130, and a TCON timing control module 140.

[0094] The display panel inputs display frame image data to the hardware compensation system and outputs its own refresh rate signal (such as 180Hz, 240Hz, or 360Hz). Based on the color separation compensation method described in any of the above embodiments, the hardware compensation system performs motion vector analysis, coordinate pre-offset calculation, sub-pixel grayscale reconstruction, timing synchronization, and multi-refresh-rate adaptation steps to generate compensated display data. The hardware compensation system outputs the compensated display data to the display panel according to the display timing sequence. After receiving the data, the display panel presents a picture without color separation and without ghosting. When the display panel switches refresh rates, the hardware compensation system automatically switches timing parameters and processing clocks without manual intervention, ensuring accurate color separation compensation at different refresh rates.

[0095] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0096] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A color separation compensation method for a color separation compensation system, characterized in that, The color separation compensation method includes: The input display frame image data is parsed to generate motion vector data; Based on the valid motion vector data, the spatial coordinates of the display subframe are pre-offset calculated to generate offset address mapping data. Based on the address mapping data, perform sub-pixel level grayscale weight calculation and grayscale reconstruction, and output the compensated display data; and Based on the processing timing of each step, the refresh rate of the display panel is matched, and the compensated display data is output to the display panel according to the display timing to achieve color separation compensation of the display panel at different refresh rates. The display frame is the input complete image frame, and the display subframe is a set of time-division display units obtained by splitting a display frame in the time dimension.

2. The color separation compensation method as described in claim 1, characterized in that, The color separation compensation system includes a motion vector analysis module, which comprises a hardware gate-level circuit and a motion gating unit. The step of analyzing the input display frame image data to generate motion vector data includes: The motion vector parsing module parses the input display frame image data through hardware gate circuits to generate motion vector data. After the motion gating unit filters out noise vectors, it outputs valid motion vector data. Based on the statistical results of motion intensity in the scene, when the motion intensity is lower than the preset intensity threshold, the power consumption of compensation processing in static scenes is reduced, and only the core motion vector parsing logic is retained. In the process of filtering noise, a preset noise threshold is set, motion vectors with amplitudes smaller than the noise threshold are removed, and only valid motion vector data are retained for subsequent spatial coordinate offset calculations.

3. The color separation compensation method as described in claim 1, characterized in that, The step of pre-offsetting the spatial coordinates of the display subframe based on the effective motion vector data to generate the offset address mapping data includes: Based on the amplitude value of the motion vector and the resolution parameters of the display panel, the coordinate offset is calculated. The spatial coordinates of the original display subframe are added to the offset to generate an offset address. When the offset address exceeds the physical boundary of the display panel, the offset is automatically truncated to prevent the offset address from going out of bounds.

4. The color separation compensation method as described in claim 1, characterized in that, The steps of calculating sub-pixel grayscale weights and reconstructing grayscale based on address mapping data, and outputting compensated display data include: Based on the fractional component of the motion vector, a corresponding grayscale weight control signal is generated. By replacing the division operation with a shift operation, grayscale sub-data with different weights are generated. The grayscale sub-data are accumulated to obtain grayscale data after subpixel level compensation.

5. The color separation compensation method as described in claim 1, characterized in that, The steps of matching the refresh rate of the display panel with the processing timing of each step, and outputting the compensated display data to the display panel according to the display timing to achieve color separation compensation of the display panel at different refresh rates include: Generate a processing clock adapted to the display refresh rate, and synchronize the processing clocks for each step of motion vector analysis, coordinate pre-offset, and grayscale reconstruction with the display timing clock to avoid data transmission conflicts and ensure real-time output of compensation data.

6. The color separation compensation method as described in claim 2, characterized in that, The step of reducing the power consumption of compensation processing in static scenes and retaining only the core motion vector parsing logic when the motion intensity is lower than a preset intensity threshold, based on the statistical results of the motion intensity of the image, includes: The horizontal and vertical components of the original motion vector are input into the motion gating unit to eliminate interference from the motion direction, output the magnitude data of the motion vector, and retain only the motion intensity information. The summation of the horizontal and vertical modulus data yields the overall motion intensity of the current display area, quantifying the intensity of the motion. The comprehensive motion intensity data is compared with the preset motion judgment threshold in the hardware threshold register in real time. If the motion intensity is less than or equal to the preset threshold, the clock signal of the subsequent compensation circuit is physically turned off by the AND gate circuit, and the motion vector data is no longer passed down. If the motion intensity exceeds the preset threshold, the comparator outputs an enable signal and releases the motion vector data to the next compensation module.

7. The color separation compensation method as described in claim 1, characterized in that, The color separation compensation method also includes a multi-refresh-rate adaptation step: based on the refresh rate signal of the display panel, the corresponding timing parameters are automatically switched from the multi-refresh-rate adaptation register, and the clock synchronization submodule synchronizes the processing clock of each module with the display timing clock to achieve real-time compensation output under different refresh rates.

8. A color separation compensation system, characterized in that, The color separation compensation method described in any one of claims 1-7 is used to generate compensated display data and output it to the display panel. The hardware compensation system includes a motion vector analysis module, an asynchronous address mapping engine, a zero division subpixel interpolation unit, and a timing control module. The motion vector analysis module is used to perform motion vector analysis on the input display frame image data, generating analytical data containing the direction and amplitude of the motion vectors. The asynchronous address mapping engine is connected to the motion vector analysis module and adopts an asynchronous dual-port storage architecture. It uses a hardware adder to perform pre-offset calculation of the spatial coordinates of the display subframes, generating offset address mapping data. The zero-division subpixel interpolation unit is connected to the asynchronous address mapping engine. It uses a barrel shift register to replace the divider and performs subpixel-level grayscale weight calculation and grayscale reconstruction based on the address mapping data, outputting compensated display data. The timing control module is electrically connected to the motion vector analysis module, the asynchronous address mapping engine, and the zero-division subpixel interpolation unit, respectively, to synchronize the clock signals of each module and match the refresh rate of the display panel.

9. The hardware compensation system as described in claim 8, characterized in that, The motion vector parsing module includes a hardware gate circuit and a motion gating unit. The hardware gate circuit parses the input display frame image data to generate motion vector data. After the motion gating unit filters out noise vectors, it outputs valid motion vector data. The asynchronous address mapping engine includes a first asynchronous dual-port, a hardware adder, and an address offset register. The asynchronous dual-port caches the spatial coordinate data and motion vector parsing data of the original display frame image, and supports asynchronous parallel execution of read and write operations. The hardware adder calculates the coordinate offset in real time based on the amplitude value in the motion vector parsing data, and accumulates the spatial coordinates and offset of the original display frame image to generate the offset address mapping data. The zero-division subpixel interpolation unit includes a barrel shift register group, a grayscale weight lookup table unit, and an accumulator. The barrel shift register group is used to shift the spatial coordinates of the input original display frame image by a preset number of bits to generate grayscale sub-data with different weights. The preset number of bits matches the bit width of the fractional component of the motion vector. The grayscale weight lookup table unit is used to store the grayscale weight parameters corresponding to the fractional component of the motion vector, and outputs the corresponding weight control signal according to the address mapping data to complete the shift operation with the driving barrel shift register group. The accumulator is connected to the barrel shift register group and performs an accumulation operation on the shifted grayscale sub-data to generate subpixel-level compensated grayscale data. The timing control module includes a phase-locked loop unit, a multi-refresh-rate adaptation register, and a clock synchronization submodule. The phase-locked loop unit is used to amplify the input reference clock signal in a phase-locked manner; The multi-refresh-rate adaptation register is used to automatically switch timing parameters for different refresh rates according to the refresh rate signal of the display panel; the clock synchronization submodule is connected to the motion vector analysis module, the asynchronous address mapping engine, and the zero-division subpixel interpolation unit respectively, and realizes signal timing synchronization between modules through clock domain cross-processing.

10. A display device, characterized in that, The display device includes a display panel and a color separation compensation system as described in claims 8-9. The color separation compensation system generates display data based on the color separation compensation method as described in any one of claims 1-7, and is used to realize color separation compensation of the display panel at different refresh rates.

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