voltage driver

Abstract

This disclosure discloses a voltage driver comprising a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The first P-type transistor has a first terminal and a second terminal for receiving a pump voltage, and a control terminal for receiving a first control signal. The second P-type transistor has a first terminal coupled to a second terminal of the first P-type transistor, a second terminal for outputting a drive signal, and a control terminal for receiving a power supply voltage. The first N-type transistor has a first terminal and a second terminal coupled to a second terminal of the second P-type transistor, and a control terminal for receiving a power supply voltage. The second N-type transistor has a first terminal coupled to a second terminal of the first N-type transistor, a second terminal for receiving a reference voltage, and a control terminal for receiving a second control signal.

Description

Technical Field

[0001] This invention relates to a voltage driver, and more specifically, to a voltage driver suitable for high-voltage operation. Background Technology

[0002] In response to the demand for low power consumption in electronic devices, integrated circuits (ICs) have been redesigned to operate in low-voltage environments. While lower voltages are beneficial for reducing power consumption, there are still situations where higher voltages are required. For example, non-volatile memory may require high voltages to perform write operations, and these high voltages are typically provided by level shifters and voltage drivers.

[0003] However, designing level shifters and voltage drivers that can operate in low-voltage environments can be quite challenging. For example, special care must be taken to ensure that the transistors used in the circuit operate within their safe operating area (SOA). Therefore, designing high-efficiency, high-voltage output circuits that can operate in low-voltage environments becomes a problem to be solved.

[0004] This "Background Art" section provides background information only. The statements in this "Background Art" section are not an admission that the subject matter disclosed in this section constitutes prior art to this invention, and nothing in this "Background Art" section should be used as an admission that any part of this application (including this "Background Art" section) constitutes prior art to this invention. Summary of the Invention

[0005] One embodiment of this disclosure provides a voltage driver. The voltage driver includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The first P-type transistor has a first terminal and a second terminal for receiving a pump voltage, and a control terminal for receiving a first control signal. The second P-type transistor has a first terminal coupled to a second terminal of the first P-type transistor, a second terminal for outputting a drive signal, and a control terminal for receiving a power supply voltage. The first N-type transistor has a first terminal and a second terminal coupled to a second terminal of the second P-type transistor, and a control terminal for receiving the power supply voltage. The second N-type transistor has a first terminal coupled to a second terminal of the first N-type transistor, a second terminal for receiving a reference voltage, and a control terminal for receiving a second control signal. The pump voltage is higher than the power supply voltage, and the power supply voltage is higher than the reference voltage. The first control signal and the second control signal are in phase, the first control signal switching between a first high voltage and a first low voltage, and the second control signal switching between a second high voltage and a second low voltage, both the first high voltage and the first low voltage being higher than or equal to the power supply voltage, and both the second high voltage and the second low voltage being lower than or equal to the power supply voltage.

[0006] Another embodiment of this disclosure provides a memory peripheral circuit for providing a drive voltage to write non-volatile memory cells. The memory peripheral circuit includes a level shifter and a voltage driver. The level shifter generates a first control signal and a second control signal based on an input signal. The voltage driver includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The first P-type transistor has a first terminal and a second terminal for receiving a pump voltage, and a control terminal for receiving the first control signal. The second P-type transistor has a first terminal coupled to a second terminal of the first P-type transistor, a second terminal for outputting a drive signal, and a control terminal for receiving a power supply voltage. The first N-type transistor has a first terminal and a second terminal coupled to a second terminal of the second P-type transistor, and a control terminal for receiving the power supply voltage. The second N-type transistor has a first terminal coupled to a second terminal of the first N-type transistor, a second terminal for receiving a reference voltage, and a control terminal for receiving the second control signal. The pump voltage is higher than the power supply voltage, and the power supply voltage is higher than the reference voltage. The first control signal and the second control signal are in phase. The first control signal switches between a first high voltage and a first low voltage, and the second control signal switches between a second high voltage and a second low voltage. Both the first high voltage and the first low voltage are higher than or equal to the power supply voltage, and both the second high voltage and the second low voltage are lower than or equal to the power supply voltage. Attached Figure Description

[0007] A more complete understanding of the invention can be obtained by referring to the detailed description and the claims, as well as by considering the drawings, in which similar reference numerals in all the drawings represent similar elements.

[0008] Figure 1 This shows a memory peripheral circuit according to a comparative embodiment of the present disclosure; Figure 2 This shows a memory peripheral circuit according to an embodiment of the present disclosure; Figure 3 This illustrates an embodiment of the present disclosure where, when the input signal is at the system voltage... Figure 2 One application scenario for the peripheral circuitry of this memory; Figure 4 This illustrates an embodiment of the present disclosure where, when the input signal is at the power supply voltage... Figure 2 Another application scenario for the peripheral circuitry of this memory; Figure 5 This shows the well layout of P-type transistors and N-type transistors according to one embodiment of the present disclosure; Figure 6 This shows a memory peripheral circuit according to another embodiment of the present disclosure; Figure 7 This illustrates an embodiment of the present disclosure where, when the input signal is at the system voltage... Figure 6 One application scenario for the peripheral circuitry of this memory; Figure 8 This illustrates an embodiment of the present disclosure where, when the input signal is at the power supply voltage... Figure 6 Another application scenario for the peripheral circuitry of this memory. Detailed Implementation

[0009] Figure 1 This illustration shows a memory peripheral circuit 100 according to a comparative embodiment of the present disclosure. The memory peripheral circuit 100 includes a level shifter 110 and a voltage driver 120. The memory peripheral circuit 100 can provide a drive voltage VD for writing operations to a non-volatile memory cell MC1.

[0010] In this embodiment, the non-volatile memory cell MC1 includes an antifuse transistor T1, a follower transistor T2, and a select transistor T3. The antifuse transistor T1 includes a first terminal, a second terminal, and a gate terminal. The gate terminal includes an oxide layer with a breakdown voltage greater than 5V (e.g., 5.25V) and is coupled to the antifuse control line AF1. The follower transistor T2 has a first terminal coupled to the second terminal of the antifuse transistor T1, a second terminal coupled to the follower gate line FL1, and a control terminal coupled to the follower gate line FL1. The select transistor T3 has a first terminal coupled to the second terminal of the follower transistor T2, a second terminal coupled to the bit line BL1, and a control terminal coupled to the word line WL1.

[0011] When a non-volatile memory cell MC1 is selected for a write operation in write mode, the voltage on bit line BL1 is low, while the voltage on word line WL1 and follower gate line FL1 rises to high to turn on selection transistor T3 and follower transistor T2. Furthermore, during the write operation of non-volatile memory cell MC1, memory peripheral circuitry 100 can provide a high-level drive voltage VD1 to the antifuse control line AF1, causing the antifuse transistor T1 to withstand a large voltage between its second terminal and its gate terminal. Therefore, the gate oxide layer at the gate terminal of the antifuse transistor T1 may crack, thereby forming a low-resistance path between its gate terminal and its second terminal. Thus, non-volatile memory cell MC1 can be written.

[0012] In some embodiments, during the write operation, the voltage on the follower gate line FL1 may be higher than the voltage on the word line WL1. Therefore, the follower transistor T2 helps reduce the cross voltage applied to the select transistor T3, thereby reducing gate-induced drain-leakage (GIDL) and preventing punch-through current. However, in some embodiments, depending on system requirements, the follower transistor T2 may be omitted, and the first terminal of the select transistor T3 may be directly coupled to the second terminal of the antifuse transistor T1.

[0013] exist Figure 1In the illustrated embodiment, to provide a drive voltage VD capable of breaking down the antifuse transistor T1 during write operations, the memory peripheral circuitry 100 employs a level shifter 110 to generate a control signal SC1A based on the input signal SIN. In some embodiments, the input signal SIN switches within a first voltage domain, for example, between the system voltage VSS and the power supply voltage VDD, and the control signal SC1A can switch within a second voltage domain, for example, between the system voltage VSS and the pump voltage VPP. In other words, when the input signal SIN is at the power supply voltage VDD, the level shifter 110 can generate the control signal SC1A by changing the level of the input signal SIN. In some embodiments, the pump voltage VPP can be higher than the power supply voltage VDD, and the power supply voltage VDD can be higher than the system voltage VSS. For example, the system voltage VSS can be ground, the power supply voltage VDD can be 1.8V, and the pump voltage VPP can be 5.25V. However, this disclosure is not limited thereto.

[0014] The memory peripheral circuitry 100 further utilizes the voltage driver 120 as a buffer to output the drive voltage VD according to the control signal SC1A, thereby ensuring the driving capability of the drive voltage VD.

[0015] The voltage driver 120 includes a P-type transistor (e.g., PMOS) P1A and an N-type transistor (e.g., NMOS) N1A. The P-type transistor P1A has a first terminal and a second terminal for receiving the pump voltage VPP, and a control terminal for receiving the control signal SC1A. The N-type transistor N1A has a first terminal coupled to the second terminal of the P-type transistor P1A, a second terminal for receiving the system voltage VSS, and a control terminal coupled to the control terminal of the P-type transistor P1A.

[0016] In some embodiments, the P-type transistor P1A and N-type transistor N1A may be implemented using low-voltage or medium-voltage devices with breakdown voltages lower than the pump voltage VPP (e.g., the pump voltage VPP may be 5.25V, while the breakdown voltages of the P-type transistor P1A and N-type transistor N1A may be 5V). In this case, when the control signal SC1A is at the pump voltage VPP, the N-type transistor N1A is turned on and the P-type transistor P1A is turned off, thereby pulling the drive voltage VD down to the system voltage VSS. Therefore, the drain-to-source voltage of the P-type transistor P1A is approximately equal to the pump voltage VPP, which may cause the P-type transistor P1A to break down. Alternatively, when the control signal SC1A is at the system voltage VSS, the P-type transistor P1A is turned on and the N-type transistor N1A is turned off, thus pulling the drive voltage VD up to the pump voltage VPP. In this case, the drain-to-source voltage of the N-type transistor N1A is approximately equal to the pump voltage VPP, which may cause the N-type transistor N1A to break down.

[0017] To prevent the transistors in the voltage driver 120 from being damaged, a cascode structure can be used. Figure 2 This shows a memory peripheral circuit 200 according to an embodiment of the present disclosure.

[0018] The memory peripheral circuitry 200 includes a level shifter 210 and a voltage driver 220. The level shifter 210 generates control signals SC1B and SC2B based on the input signal SIN. In some embodiments, control signals SC1B and SC2B are in phase. Control signal SC1B switches between a first high voltage VH1 and a first low voltage VL1, and control signal SC2B switches between a second high voltage VH2 and a second low voltage VL2, wherein the first high voltage VH1 and the first low voltage VL1 are higher than or equal to the supply voltage VDD, and both the second high voltage VH2 and the second low voltage VL2 are lower than or equal to the supply voltage VDD. For example, the pump voltage VPP may be 5.25V, the supply voltage VDD may be 1.8V, and the system voltage VSS may be ground. In this case, the high voltage VH1 may be the same as the pump voltage VPP, and the low voltage VL1 may be higher than or equal to the supply voltage VDD. For example, the low voltage VL1 may be 2V. Furthermore, the high voltage VH2 can be the same as the power supply voltage VDD, and the low voltage VL2 can be the same as the system voltage VSS.

[0019] The voltage driver 220 includes P-type transistors P1B and P2B and N-type transistors N1B and N2B. P-type transistor P1B has a first terminal and a second terminal for receiving the pump voltage VPP, and a control terminal for receiving the control signal SC1B. P-type transistor P2B has a first terminal coupled to the second terminal of P-type transistor P1B, a second terminal for outputting a drive voltage VD, and a control terminal for receiving a power supply voltage VDD. N-type transistor N1B has a first terminal and a second terminal coupled to the second terminal of P-type transistor P2B, and a control terminal for receiving the power supply voltage VDD. N-type transistor N2B has a first terminal coupled to the second terminal of N-type transistor N1B, a second terminal for receiving a reference voltage VR, and a control terminal for receiving the control signal SC2B. In this embodiment, the reference voltage VR may be the same as the system voltage VSS.

[0020] Furthermore, the base of the P-type transistor P1B receives the pump voltage VPP, and the base of the second P-type transistor P2B is coupled to the first terminal of the P-type transistor P2B. In addition, the base of the N-type transistor N1B is coupled to the second terminal of the N-type transistor N1B, and the base of the N-type transistor N2B receives the reference voltage VR.

[0021] In this case, P-type transistors P1B and P2B and N-type transistors N1B and N2B can be protected from breakdown due to excessive inter-terminal voltage. Figure 3 This illustrates an application scenario of the memory peripheral circuitry 200 according to one embodiment of this disclosure, when the input signal SIN is at the system voltage VSS. In this case, control signals SC1B and SC2B are at low voltages VL1 (e.g., 2V) and VL2 (e.g., system voltage VSS), therefore P-type transistors P1B and P2B are turned on, while N-type transistors N1B and N2B are turned off. Therefore, the pump voltage VPP (e.g., 5.25V) is output as the drive voltage VD. Figure 3 As shown, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of P-type transistors P1B and P2B can all be kept below the breakdown voltage of P-type transistors P1B and P2B (for example, the breakdown voltage of P-type transistors P1B and P2B can be 5V). Therefore, P-type transistors P1B and P2B can be protected from breakdown.

[0022] Furthermore, in Figure 3 In this configuration, due to the use of a stacked structure, the voltage at the second terminal of the N-type transistor N1B can be reduced, thereby protecting N-type transistors N1B and N2B from breakdown. In some embodiments, the voltage at the second terminal of the N-type transistor N1B can be an intermediate voltage VIT1 (e.g., 1.58V) between the power supply voltage VDD and the system voltage VSS. In this case, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of the N-type transistors N1B and N2B can also be kept lower than the breakdown voltage of the N-type transistors N1B and N2B (e.g., the breakdown voltage of the N-type transistors N1B and N2B can be the same as the breakdown voltage of the P-type transistors P1B and P2B, which is 5V), thus protecting the N-type transistors N1B and N2B from breakdown.

[0023] Figure 4 This illustrates another application scenario of the memory peripheral circuitry 200 when the input signal SIN is at the power supply voltage VDD, according to one embodiment of this disclosure. In this case, control signals SC1B and SC2B are at high voltages VH1 (e.g., pump voltage VPP) and VH2 (e.g., power supply voltage VDD), respectively. Therefore, P-type transistors P1B and P2B are turned off, while N-type transistors N1B and N2B are turned on, and the reference voltage VR (in this case, the reference voltage VR is the same as the system voltage VSS) is output as the drive voltage VD. Figure 4 As shown, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of N-type transistors N1B and N2B can be kept below the breakdown voltage. Therefore, N-type transistors N1B and N2B can be protected from breakdown.

[0024] Furthermore, in Figure 4 In this configuration, due to the use of a stacked structure, the voltage at the second terminal of the P-type transistor P1B can be reduced, thereby protecting P-type transistors P1B and P2B from breakdown. In some embodiments, the voltage at the second terminal of the P-type transistor P1B can be approximately the intermediate voltage VIT2 (e.g., 2V) between the pump voltage VPP and the power supply voltage VDD. In this case, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of the P-type transistors P1B and P2B can also remain below the breakdown voltage, thus protecting P-type transistors P1B and P2B from breakdown.

[0025] In this embodiment, the base terminals of P-type transistors P1B and P2B and the base terminals of N-type transistors N1B and N2B are coupled to different voltages, so that the drain-to-base voltage and base-to-source voltage received by P-type transistors P1B and P2B and N-type transistors N1B and N2B can be controlled within their breakdown voltage range. However, this configuration also requires that P-type transistors P1B and P2B and N-type transistors N1B and N2B be formed in different wells, and may increase the area of ​​voltage driver 220.

[0026] Figure 5 This diagram shows the layout of the wells of P-type transistors P1B, P2B and N-type transistors N1B, N2B according to one embodiment of this disclosure. As... Figure 5 As shown, the voltage driver 220 includes deep N-type wells DNW1 and DNW2. In this case, a P-type transistor P1B can be formed in an N-type well NW1 within the deep N-type well DNW1, and a P-type transistor P2B can be formed in an N-type well NW2 within the deep N-type well DNW2. Additionally, an N-type transistor N1B can be formed in a P-type well PW1 within the deep N-type well DNW1, and an N-type transistor N2B can be formed in a P-type well PW2 within the deep N-type well DNW1. Since the P-type transistors P1B and P2B, and the N-type transistors N1B and N2B need to be formed in different wells, the voltage driver 220 may require a larger area to implement.

[0027] Figure 6This illustrates a memory peripheral circuit 300 according to another embodiment of the present disclosure. The memory peripheral circuit 300 differs from the memory peripheral circuit 200 in that the base terminals of P-type transistors P1C and P2C can receive a pump voltage VPP, while the base terminals of N-type transistors N1C and N2C can receive a reference voltage VR' higher than the system voltage VSS but lower than the power supply voltage VDD. Furthermore, the difference between the pump voltage VPP and the reference voltage VR' is less than the breakdown voltage of the N-type transistor N1C and the P-type transistor P2C. In this case, the P-type transistors P1C and P2C and the N-type transistors N1C and N2C can be protected from breakdown due to excessive inter-terminal voltage. In some embodiments, the system voltage VSS can be 0V, and the reference voltage VR' can be 0.5V. In other words, the voltage driver 320 can employ a reference voltage VR' slightly higher than the system voltage VSS to protect the P-type transistor P2C and the N-type transistor N2C.

[0028] Figure 7 This illustrates an application scenario of the memory peripheral circuitry 300 according to one embodiment of this disclosure, when the input signal SIN is at the system voltage VSS. In this case, control signals SC1B and SC2B are at low voltages VL1 (e.g., 2V) and VL2 (e.g., system voltage VSS), therefore P-type transistors P1C and P2C are turned on, while N-type transistors N1C and N2C are turned off. Therefore, the pump voltage VPP (e.g., 5.25V) is output as the drive voltage VD. Figure 7 As shown, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of P-type transistors P1C and P2C can be maintained below the breakdown voltage of P-type transistors P1C and P2C (for example, the breakdown voltage of P-type transistors P1C and P2C can be 5V). Therefore, P-type transistors P1C and P2C can be protected from breakdown.

[0029] Furthermore, in Figure 7 In this design, due to the use of a stacked structure, the voltage at the second terminal of the N-type transistor N1C can be reduced, thereby protecting N-type transistors N1C and N2C from breakdown. In some embodiments, the voltage at the second terminal of the N-type transistor N1C can be an intermediate voltage VIT3 (e.g., 1.58V) between the power supply voltage VDD and the system voltage VSS. Furthermore, since the difference between the reference voltage VR' and the pump voltage VPP can be less than the breakdown voltage of the N-type transistor N1C, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of the N-type transistors N1C and N2C can all be kept below the breakdown voltage of the N-type transistors N1C and N2C, thereby protecting the N-type transistors N1C and N2C from breakdown.

[0030] Figure 8 This illustrates another application scenario of the memory peripheral circuitry 300 when the input signal SIN is at the power supply voltage VDD, according to one embodiment of this disclosure. In this case, control signals SC1B and SC2B are at high voltages VH1 (e.g., pump voltage VPP) and VH2 (e.g., power supply voltage VDD), respectively. Therefore, P-type transistors P1C and P2C are turned off, while N-type transistors N1C and N2C are turned on, and the reference voltage VR' (in this case, the reference voltage VR' is higher than the system voltage VSS) is output as the drive voltage VD. Figure 8 As shown, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of N-type transistors N1C and N2C can all be kept below the breakdown voltage, thus protecting N-type transistors N1C and N2C from breakdown.

[0031] Furthermore, in Figure 8 In this design, due to the use of a stacked structure, the voltage at the second terminal of the P-type transistor P1C can be reduced, thereby protecting P-type transistors P1C and P2C from breakdown. In some embodiments, the voltage at the second terminal of the P-type transistor P1C can be the intermediate voltage VIT4 (e.g., 2V) between the pump voltage VPP and the power supply voltage VDD. Furthermore, since the difference between the reference voltage VR' and the pump voltage VPP can be less than the breakdown voltage of the P-type transistor P2C, the gate-to-drain voltage, gate-to-source voltage, drain-to-source voltage, drain-to-base voltage, and base-to-source voltage of the P-type transistors P1C and P2C can all remain below the breakdown voltage, thus protecting P-type transistors P1C and P2C from breakdown.

[0032] By configuring the voltage driver 320, P-type transistors P1C and P2C can be formed in the same N-type well, and N-type transistors N1C and N2C can be formed in the same P-type well. Furthermore, the N-type well and the P-type well are set in the same depth of N-type well, thus reducing the area required for the voltage driver 320.

[0033] In this embodiment, the voltage driver 320 may further include a reference voltage generator 322 for generating a reference voltage VR'. Figure 8As shown, the reference voltage generator 322 includes P-type transistors P3C and P4C, and N-type transistors N3C and N4C. P-type transistor P3C has a first terminal and a second terminal for receiving the power supply voltage VDD, and a control terminal for receiving an enable signal SEN. P-type transistor P4C has a first terminal and a second terminal coupled to the second terminal of P-type transistor P3C, and a control terminal for receiving the enable signal SEN. N-type transistor N3C includes a first terminal coupled to the second terminal of P-type transistor P4C, a second terminal for receiving the system voltage VSS, and a control terminal coupled to the first terminal of N-type transistor N3C. N-type transistor N4C has a first terminal coupled to the second terminal of P-type transistor P4C, a second terminal for receiving the system voltage VSS, and a control terminal for receiving the enable signal SEN.

[0034] In some embodiments, when the non-volatile memory cell MC1 is not in write mode, the enable signal SEN can be high (e.g., power supply voltage VDD), and the N-type transistor N4C can be turned on to pull the reference voltage VR' down to the system voltage VSS. Conversely, when the non-volatile memory cell MC1 enters write mode, the enable signal SEN can be low (e.g., system voltage VSS). In this case, when the enable signal SEN changes to low, the P-type transistors P3C and P4C can be turned on, thereby establishing a current path from the first terminal of the P-type transistor P3C to the second terminal of the P-type transistor P4C. Since the N-type transistor N3C is connected as a diode, it can act as a voltage clamp. Specifically, because the N-type transistor N3C is connected as a diode, once the reference voltage VR' reaches the critical voltage of the N-type transistor N3C, it begins to conduct current to the system voltage (VSS). This mechanism effectively adjusts the reference voltage VR', preventing it from rising significantly. Therefore, the final reference voltage VR' stabilizes near the critical voltage of the N-type transistor N3C. In some embodiments, the supply voltage VDD may be 1.8V, the critical voltage of the N-type transistor N3C may be 0.5V, and the reference voltage VR' may be 0.5V. However, this disclosure is not limited thereto. In some embodiments, the reference voltage generator 322 may include a different number of P-type transistors for generating the reference voltage VR' required by the system.

[0035] In summary, the voltage driver and memory peripheral circuitry provided in the embodiments of this disclosure can employ a stacked structure to protect the transistors therein from breakdown caused by excessive voltage between their terminals. Furthermore, the voltage driver and memory peripheral circuitry provided in the embodiments of this disclosure can further adjust the connection of the transistor base terminals, or adjust the reference voltage supplied to the N-type transistor, thereby further ensuring that the transistor can operate within its safe operating area (SOA).

[0036] Symbol Explanation 100, 200, 300: Memory peripheral circuitry 110, 210: Level shifters 120, 220, 320: Voltage driver 322: Reference Voltage Generator AF1: Anti-fuse control line BL1: Bitline DNW1, DNW2: Deep N-type wells FL1: Follow gate line MC1: Non-volatile memory cell N1A, N1B, N2B, N1C, N2C, N3C, N4C: N-type transistors NW1, NW2: N-type wells P1A, P1B, P2B, P1C, P2C, P3C, P4C: P-type transistors PW1, PW2: P-type wells SC1A, SC1B, SC2B: Control signals SIN: Input signal SEN: Enable signal T1: Antifuse transistor T2: Follower transistor T3: Select transistor VD: Drive voltage VD1: Drive voltage VDD: Power supply voltage VH1, VH2: High voltage VIT1, VIT2, VIT3, VIT4: Intermediate voltage VL1, VL2: Low voltage VPP: Pump voltage VR: Reference Voltage VR': Reference voltage VSS: System Voltage WL1: Wordline

Claims

1. A voltage driver, comprising: The first P-type transistor has a first terminal and a second terminal for receiving a pump voltage, and a control terminal for receiving a first control signal. The second P-type transistor has a first terminal coupled to the second terminal of the first P-type transistor, a second terminal for outputting a drive signal, and a control terminal for receiving a power supply voltage. The first N-type transistor has a first terminal and a second terminal coupled to the second terminal of the second P-type transistor, and a control terminal for receiving the power supply voltage. as well as The second N-type transistor has a first terminal coupled to the second terminal of the first N-type transistor, a second terminal for receiving a reference voltage, and a control terminal for receiving a second control signal. in: The pump voltage is higher than the power supply voltage, and the power supply voltage is higher than the reference voltage; and The first control signal and the second control signal are in phase. The first control signal switches between a first high voltage and a first low voltage, and the second control signal switches between a second high voltage and a second low voltage. Both the first high voltage and the first low voltage are higher than or equal to the power supply voltage, and both the second high voltage and the second low voltage are lower than or equal to the power supply voltage.

2. The voltage driver of claim 1, wherein: The base of the first P-type transistor is used to receive the pump voltage; and The base terminal of the second N-type transistor is used to receive the reference voltage.

3. The voltage driver of claim 2, wherein: The base terminal of the second P-type transistor is used to receive the pump voltage; The base terminal of the first N-type transistor is used to receive the reference voltage; as well as The reference voltage is higher than the system voltage, and the difference between the pump voltage and the reference voltage is less than the breakdown voltage of the first N-type transistor.

4. The voltage driver of claim 3, further comprising a reference voltage generator for generating the reference voltage, and the reference voltage generator comprising: The third P-type transistor has a first terminal and a second terminal for receiving the power supply voltage, and a control terminal for receiving an enable signal. The fourth P-type transistor has a first terminal coupled to the second terminal of the third P-type transistor, a second terminal for outputting the reference voltage when the enable signal is at a low level, and a control terminal for receiving the enable signal. The third N-type transistor has a first terminal coupled to the second terminal of the fourth P-type transistor, a second terminal for receiving system voltage, and a control terminal coupled to the first terminal of the third N-type transistor. as well as The fourth N-type transistor has a first terminal coupled to the second terminal of the fourth P-type transistor, a second terminal for receiving the system voltage, and a control terminal for receiving the enable signal.

5. The voltage driver of claim 3, wherein: The first high voltage is equal to the pump voltage, and the first low voltage is higher than or equal to the power supply voltage, but lower than the first high voltage; and The second high voltage is equal to the power supply voltage, and the second low voltage is equal to the system voltage.

6. The voltage driver of claim 2, wherein: The base terminal of the second P-type transistor is coupled to the first terminal of the second P-type transistor; and The base terminal of the first N-type transistor is coupled to the second terminal of the first N-type transistor.

7. The voltage driver of claim 6, further comprising a first deep N-well and a second deep N-well, wherein: The first P-type transistor is formed in the first N-type well in the first deep N-type well; The second P-type transistor is formed in the second N-type well within the second deep N-type well; The first N-type transistor is formed in a first P-type well within the first deep N-type well; and The second N-type transistor is formed in the second P-type well within the first deep N-type well.

8. The voltage driver of claim 6, wherein: The first high voltage is equal to the pump voltage, and the first low voltage is higher than or equal to the power supply voltage, but lower than the first high voltage; The second highest voltage is equal to the power supply voltage, and the second lowest voltage is equal to the system voltage; as well as The reference voltage is equal to the system voltage.

9. A memory peripheral circuit for providing a drive voltage to write non-volatile memory cells, the memory peripheral circuit comprising: A level shifter, used to generate a first control signal and a second control signal based on an input signal; as well as Voltage driver, including: The first P-type transistor has a first terminal and a second terminal for receiving the pump voltage, and a control terminal for receiving the first control signal. The second P-type transistor has a first terminal coupled to the second terminal of the first P-type transistor, a second terminal for outputting a drive signal, and a control terminal for receiving a power supply voltage. A first N-type transistor has a first terminal and a second terminal coupled to the second terminal of the second P-type transistor, and a control terminal for receiving the power supply voltage; and The second N-type transistor has a first terminal coupled to the second terminal of the first N-type transistor, a second terminal for receiving a reference voltage, and a control terminal for receiving the second control signal. in: The pump voltage is higher than the power supply voltage, and the power supply voltage is higher than the reference voltage; and The first control signal and the second control signal are in phase. The first control signal switches between a first high voltage and a first low voltage, and the second control signal switches between a second high voltage and a second low voltage. Both the first high voltage and the first low voltage are higher than or equal to the power supply voltage, and both the second high voltage and the second low voltage are lower than or equal to the power supply voltage.

10. The memory peripheral circuitry of claim 9, wherein: The base of the first P-type transistor is used to receive the pump voltage; and The base terminal of the second N-type transistor is used to receive the reference voltage.

11. The memory peripheral circuitry of claim 10, wherein: The base terminal of the second P-type transistor is used to receive the pump voltage; The base terminal of the first N-type transistor is used to receive the reference voltage; as well as The reference voltage is higher than the system voltage, and the difference between the pump voltage and the reference voltage is less than the breakdown voltage of the first N-type transistor.

12. The memory peripheral circuitry of claim 11, wherein the voltage driver further includes a reference voltage generator for generating the reference voltage, and the reference voltage generator includes: The third P-type transistor has a first terminal and a second terminal for receiving the power supply voltage, and a control terminal for receiving an enable signal. The fourth P-type transistor has a first terminal coupled to the second terminal of the third P-type transistor, a second terminal for outputting the reference voltage when the enable signal is at a low level, and a control terminal for receiving the enable signal. The third N-type transistor has a first terminal coupled to the second terminal of the fourth P-type transistor, a second terminal for receiving system voltage, and a control terminal coupled to the first terminal of the third N-type transistor. as well as The fourth N-type transistor has a first terminal coupled to the second terminal of the fourth P-type transistor, a second terminal for receiving the system voltage, and a control terminal for receiving the enable signal. When the non-volatile memory cell is in write mode, the enable signal is at a low level, and when the non-volatile memory cell is not in write mode, the enable signal is at a high level.

13. The memory peripheral circuitry of claim 11, wherein: The first high voltage is equal to the pump voltage, and the first low voltage is higher than or equal to the power supply voltage, but lower than the first high voltage; and The second high voltage is equal to the power supply voltage, and the second low voltage is equal to the system voltage.

14. The memory peripheral circuitry of claim 9, wherein: The base terminal of the second P-type transistor is coupled to the first terminal of the second P-type transistor; and The base terminal of the first N-type transistor is coupled to the second terminal of the first N-type transistor.

15. The memory peripheral circuitry of claim 14, wherein the voltage driver further comprises a first deep N-well and a second deep N-well, wherein: The first P-type transistor is formed in the first N-type well in the first deep N-type well; The second P-type transistor is formed in the second N-type well within the second deep N-type well; The first N-type transistor is formed in a first P-type well within the first deep N-type well; and The second N-type transistor is formed in a second P-type well formed in the first deep N-type well.

16. The memory peripheral circuitry of claim 15, wherein: The first high voltage is equal to the pump voltage, and the first low voltage is higher than or equal to the power supply voltage, but lower than the first high voltage; The second highest voltage is equal to the power supply voltage, and the second lowest voltage is equal to the system voltage; as well as The reference voltage is equal to the system voltage.

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