Inductive amplifiers and their data access methods, memory, electronic devices

Abstract

This application provides an inductive amplifier and its data access method, memory, and electronic device, relating to the field of storage technology. The inductive amplifier includes an inductive amplification unit and an initialization unit. During the initialization phase, the voltage of the bit line is a pre-charge voltage, a first voltage is applied to the second terminal of a ferroelectric capacitor, and the initialization unit outputs a reference voltage to a reference bit line. During a first data writing phase, the second terminal of the ferroelectric capacitor maintains the first voltage applied; if the voltage of the bit line corresponds to first data, the first data is written to the storage unit; if the voltage of the bit line corresponds to second data, the inductive amplification unit stores the second data. During a second data writing phase, in response to a pre-charge command, a second voltage is applied to the second terminal of the ferroelectric capacitor, and the second data is written to the storage unit. This application can change the voltage at the second terminal of the ferroelectric capacitor upon receiving a pre-charge command, ensuring data read / write speed and saving power consumption.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more specifically, to an inductive amplifier and its data access method, a memory, and an electronic device. Background Technology

[0002] Currently, reading and writing data in memory cells based on ferroelectric capacitors is relatively complex. This is because the stored data is not the charge on the capacitor, but rather the polarity of the ferroelectric domains. Applying a voltage in the same direction does not change the polarity of the ferroelectric capacitor, resulting in a small change in charge; however, applying a voltage in the opposite direction can change the polarity and cause the ferroelectric capacitor to release a large amount of charge. By detecting the amount of charge released by the ferroelectric capacitor, it can be determined whether the original data was 0 or 1. In related technologies, applying a voltage to one end of the ferroelectric capacitor in the memory for data reading and writing results in slow overall circuit data reading and writing speeds, leading to increased power consumption. Summary of the Invention

[0003] This application proposes an inductive amplifier and its data access method, memory, and electronic device to solve the technical problem of increased power consumption caused by slow memory data read / write.

[0004] In a first aspect, embodiments of this application provide an induction amplifier, including: an induction amplification unit for being electrically connected to a bit line and a reference bit line, and an initialization unit for being electrically connected to the reference bit line; the bit line is used to be electrically connected to a first end of a ferroelectric capacitor of a memory cell; The inductive amplifier is configured such that, during the initialization phase, the voltage of the bit line is the pre-charge voltage, a first voltage is applied to the second terminal of the ferroelectric capacitor, and the initialization unit outputs a reference voltage to the reference bit line; during the first data writing phase, the second terminal of the ferroelectric capacitor maintains the application of the first voltage, and if the voltage of the bit line corresponds to the first data, the first data is written to the storage unit; if the voltage of the bit line corresponds to the second data, the inductive amplifier unit stores the second data; during the second data writing phase, in response to the pre-charge command, the first voltage applied to the second terminal of the ferroelectric capacitor is switched to the second voltage, and the second data is written to the storage unit. The precharge command is used to instruct the voltage of the bit line and the reference bit line to be reset to the precharge voltage. The first voltage is high, the precharge voltage is low, and the second voltage is low.

[0005] In one possible implementation, the inductive amplifier further includes: The pre-charge unit, which is electrically connected to both the bit line and the reference bit line, is configured to output a pre-charge voltage to the bit line and the reference bit line during the pre-charge phase, and to disconnect from the bit line and the reference bit line during the initialization phase; the pre-charge phase is located before the initialization phase.

[0006] In one possible implementation, the control terminal, first terminal, second terminal, and third terminal of the pre-charge unit are respectively used to be electrically connected to the pre-charge signal line, the pre-charge voltage terminal, the bit line, and the reference bit line; the voltage of the pre-charge voltage terminal is the pre-charge voltage. The pre-charge unit is specifically configured as follows: During the pre-charging phase, the control terminal of the pre-charging unit receives the first pre-charging signal output from the pre-charging signal line, and the second and third terminals of the pre-charging unit are both connected to the first terminal of the pre-charging unit; during the initialization phase, the control terminal of the pre-charging unit receives the second pre-charging signal output from the pre-charging signal line, and the second and third terminals of the pre-charging unit are both disconnected from the first terminal of the pre-charging unit.

[0007] In one possible implementation, the first terminal of the pre-charge unit is grounded during the pre-charge phase, and the pre-charge voltage is 0.

[0008] In one possible implementation, the pre-charging unit includes a first switching device and a second switching device; The control terminals of the first and second switching devices together serve as the control terminals of the pre-charging unit. The first terminal of the first switching device and the first terminal of the second switching device together serve as the first terminal of the pre-charging unit. The second terminal of the first switching device and the second terminal of the second switching device serve as the second and third terminals of the pre-charging unit, respectively.

[0009] In one possible implementation, the pre-charging unit includes a first switching device and a second switching device; The control terminals of the first and second switching devices together serve as the control terminals of the pre-charging unit. The first terminal of the first switching device serves as the first terminal of the pre-charging unit. The second terminal of the first switching device and the first terminal of the second switching device together serve as the second terminal of the pre-charging unit. The second terminal of the second switching device serves as the third terminal of the pre-charging unit.

[0010] In one possible implementation, the pre-charging unit includes a first switching device and a second switching device; The control terminals of the first and second switching devices together serve as the control terminals of the pre-charging unit. The first terminal of the second switching device serves as the first terminal of the pre-charging unit. The second terminal of the first switching device serves as the second terminal of the pre-charging unit; The first terminal of the first switching device and the second terminal of the second switching device together serve as the third terminal of the pre-charging unit.

[0011] In one possible implementation, the first control terminal, the first terminal, and the second terminal of the initialization unit are respectively used to electrically connect to the first initialization signal line, the reference voltage terminal, and the reference bit line; the voltage of the reference voltage terminal is a reference voltage, which is located between the voltage corresponding to the first data and the voltage corresponding to the second data. The initialization unit is specifically configured such that, during the initialization phase, the first control terminal of the initialization unit receives the first initialization signal output from the first initialization signal line, and the first and second terminals of the initialization unit are turned on.

[0012] In one possible implementation, the second control terminal and the third terminal of the initialization unit are respectively used to be electrically connected to the second initialization control line and the bit line; The initialization unit is also configured such that during the initialization phase, the second control terminal of the initialization unit receives the second initialization signal output from the second initialization signal line, and the first and third terminals of the initialization unit are disconnected.

[0013] In one possible implementation, the initialization unit includes a third switching device and a fourth switching device; The first terminal of the third switching device and the first terminal of the fourth switching device together serve as the first terminal of the initialization unit. The control terminals of the third and fourth switching devices serve as the first and second control terminals of the initialization unit, respectively. The second terminal of the third switching device and the second terminal of the fourth switching device serve as the second and third terminals of the initialization unit, respectively.

[0014] In one possible implementation, the first, second, third, and fourth terminals of the sensing amplification unit are respectively used to electrically connect to the first control voltage terminal, the second control voltage terminal, the bit line, and the reference bit line. The inductive amplification unit is also configured to apply a first control voltage to the first control voltage terminal and a second control voltage to the second control voltage terminal during the sensing and write-back phases, so that the inductive amplification unit is powered on and started, converting the voltage of the bit line into a voltage corresponding to the first data or the second data, and converting the voltage of the reference bit line into a voltage corresponding to the second data or the first data. The induction and write-back phases occur before the first data writing phase, and the second end of the ferroelectric capacitor maintains the first voltage during the induction and write-back phases.

[0015] In one possible implementation, the inductive amplification unit includes a fifth switching device, a sixth switching device, a seventh switching device, and an eighth switching device; The first terminal of the fifth switching device and the first terminal of the sixth switching device together serve as the first terminal of the inductive amplification unit; The first terminal of the seventh switching device and the first terminal of the eighth switching device together serve as the second terminal of the inductive amplification unit; The second terminal of the fifth switching device, the control terminal of the sixth switching device, the second terminal of the seventh switching device, and the control terminal of the eighth switching device together serve as the third terminal of the inductive amplification unit. The control terminal of the fifth switching device, the second terminal of the sixth switching device, the control terminal of the seventh switching device, and the second terminal of the eighth switching device together serve as the fourth terminal of the inductive amplification unit. If the fifth and sixth switching devices are PMOS transistors, then the seventh and eighth switching devices are NMOS transistors. If the fifth and sixth switching devices are NMOS transistors, then the seventh and eighth switching devices are PMOS transistors.

[0016] In one possible implementation, the inductive amplifier further includes: The port control unit, including its control terminal, first terminal, second terminal, third terminal, and fourth terminal, is used to electrically connect to the read / write control signal line, bit line, reference bit line, first port, and second port, respectively. The port control unit is configured such that during the first data writing phase, the control terminal of the port control unit receives the first control signal output by the read / write control signal line, the first and third terminals of the port control unit are turned on, and the second and fourth terminals are turned on, and the first port and the second port transmit data with the bit line and the reference bit line, respectively.

[0017] In one possible implementation, the port control unit includes a ninth switching device and a tenth switching device; The control terminals of the ninth and tenth switching devices together serve as the control terminals of the port control unit. The first and second terminals of the ninth switching device serve as the first and third terminals of the port control unit, respectively. The first and second terminals of the tenth switching device serve as the second and fourth terminals of the port control unit, respectively.

[0018] Secondly, embodiments of this application provide a memory, including: multiple bit lines, multiple word lines, multiple arrayed memory cells, and multiple sensing amplifiers as described in the first aspect; One bit line corresponds to one column of memory cells; One word line corresponds to one row of memory cells; Each inductive amplifier is electrically connected to a bit line and a reference bit line.

[0019] Thirdly, embodiments of this application provide an electronic device, including: a memory as described in the second aspect or an inductive amplifier as described in the first aspect.

[0020] Fourthly, embodiments of this application provide a data access method applied to the inductive amplifier of the first aspect, comprising: During the initialization phase, the voltage of the control bit line is the pre-charge voltage, the first voltage is applied to the second terminal of the ferroelectric capacitor, and the reference voltage is output to the reference bit line through the initialization unit; In the first data writing stage, the second end of the ferroelectric capacitor is kept under a first voltage. If the voltage of the bit line corresponds to the first data, the first data is written to the storage unit; if the voltage of the bit line corresponds to the second data, the second data is stored through the inductive amplification unit. In the second data writing stage, in response to the pre-charge command, the first voltage applied to the second terminal of the ferroelectric capacitor is switched to the second voltage, so that the second data is written to the storage cell.

[0021] In one possible implementation, before the initialization phase, a pre-charge phase is also included, in which the pre-charge unit is electrically connected to both the bit line and the reference bit line, and the pre-charge voltage is output to the bit line and the reference bit line through the pre-charge unit. The initialization phase also includes: disconnecting the pre-charge unit from the bit line and the reference bit line; A pre-charge phase is also included after the second data writing phase.

[0022] In one possible implementation, the process between the initialization phase and the first data writing phase also includes: During the charge sharing phase, the first terminal of the ferroelectric capacitor shares charge with the potential line. During the sensing and write-back phase, the control sensing amplification unit is powered on and started, converting the voltage of the bit line into a voltage corresponding to the first data or the second data, and converting the voltage of the reference bit line into a voltage corresponding to the second data or the first data.

[0023] In one possible implementation, the first data writing phase also includes: The port control unit controls the first port and the second port to transmit data with the bit line and the reference bit line, respectively.

[0024] The beneficial technical effects of the technical solutions provided in this application include: In the initialization phase of this embodiment, the bit line voltage is the pre-charge voltage, and a first voltage is applied to the second end of the ferroelectric capacitor. The initialization unit outputs a reference voltage to the reference bit line. Since the bit line is electrically connected to the first end of the ferroelectric capacitor, the first voltage is high and the pre-charge voltage is low, creating a voltage difference across the ferroelectric capacitor and completing the initialization of the inductive amplifier. Simultaneously, in the first data writing phase of this embodiment, one end of the ferroelectric capacitor maintains the first voltage applied. When the bit line voltage corresponds to the first data, the first data can be written to the storage unit. When the bit line voltage corresponds to the second data, since the second end of the ferroelectric capacitor maintains the first voltage applied, the second data cannot be written to the storage unit. The second data can be temporarily stored in the inductive amplifier unit until a pre-charge command is received, i.e., before the voltages of the bit line and reference bit line are reset to the pre-charge voltage, the first voltage applied to the second end of the ferroelectric capacitor switches to the second voltage, allowing the second data to be written to the storage unit.

[0025] Since this embodiment does not immediately write the second data into the storage unit, but instead temporarily stores the second data in the sensing amplification unit, it only writes the second data into the storage unit when the pre-charge command arrives. Therefore, this embodiment changes the voltage at the second terminal of the ferroelectric capacitor only before resetting the circuit, eliminating the need to change the voltage at the second terminal of the ferroelectric capacitor in other stages (e.g., the charge sharing stage, the sensing and write-back stages). This avoids the need to change the voltage at the second terminal of the ferroelectric capacitor every time data is written, as is required in related technologies, thus ensuring data read / write speed and saving power consumption.

[0026] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0027] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram of the frame for the electrical connection of the first type of inductive amplifier and storage unit provided in the embodiments of this application; Figure 2 A schematic diagram of the frame for the electrical connection of the second type of inductive amplifier and storage unit provided in the embodiments of this application; Figure 3 A schematic diagram of the frame for the electrical connection of the third inductive amplifier and the storage unit provided in the embodiments of this application; Figure 4 A schematic diagram of the frame for the electrical connection of the fourth inductive amplifier and the storage unit provided in the embodiments of this application; Figure 5This is a schematic diagram of the fifth type of electrical connection between the induction amplifier and the storage unit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the electrical connection between the sixth type of inductive amplifier and the storage unit provided in the embodiments of this application; Figure 7 This is a schematic diagram of the electrical connection between the seventh type of inductive amplifier and the memory unit provided in the embodiments of this application; Figure 8 A flowchart illustrating a data access method provided in an embodiment of this application; Figure 9 This is a timing control diagram provided for an embodiment of this application. Figure label: 10-Induction amplifier; 110 - Induction Amplification Unit, 120 - Initialization Unit, 130 - Pre-charge Unit, 140 - Port Control Unit; 20 - Storage unit. Detailed Implementation

[0028] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0029] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] In related technologies, applying a voltage in the same direction to a ferroelectric capacitor does not change the polarity of the ferroelectric capacitor memory, resulting in a small change in charge; however, applying a voltage in the opposite direction can change the polarity. When a voltage in the opposite direction is applied, the change in capacitor polarity causes the original data to be lost, therefore reading from a ferroelectric capacitor is destructive. Similarly, when writing, a positive voltage (e.g., corresponding to the second data D1) or a reverse voltage (e.g., corresponding to the first data D0) must be applied to the ferroelectric capacitor.

[0032] Ferroelectric capacitor reading falls into two categories. One type maintains a fixed voltage PL at a certain value V0 at the second terminal of the ferroelectric capacitor during reading and writing. The other type allows the voltage PL at the second terminal of the ferroelectric capacitor to vary during reading and writing. The former requires pulling the BL voltage to 2V0 when writing the second data D1, placing very high demands on the voltage withstand capability and control voltage of the read / write transistor. The latter, however, uses PL=V0 and BL=0 to write the first data D0, and PL=0 and BL=V0 to write the second data D1. This keeps the maximum voltage of BL at V0, reducing the requirements on the read / write transistor. The disadvantage of this approach is that during random writing, the first data D0 and the second data D1 cannot be written simultaneously; they must be written sequentially. Each time data is written, a corresponding judgment is needed to adjust the voltage at one end of the ferroelectric capacitor, resulting in a slower overall read / write speed.

[0033] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0034] See Figure 1 As shown, this application embodiment provides a schematic diagram of the frame connecting a first type of induction amplifier 10 and a storage unit 20 electrically. (As shown...) Figure 1 As shown, the inductive amplifier 10 includes: an inductive amplification unit 110 for being electrically connected to the bit line BL and the reference bit line BLB, and an initialization unit 120 for being electrically connected to the reference bit line BLB.

[0035] Bit line BL is used to electrically connect to the first terminal of the ferroelectric capacitor in memory cell 20.

[0036] The inductive amplifier 10 is configured such that, during the initialization phase, the voltage of the bit line BL is a pre-charge voltage, a first voltage is applied to the second terminal of the ferroelectric capacitor, and the initialization unit 120 outputs a reference voltage to the reference bit line BLB; during the first data writing phase, the second terminal of the ferroelectric capacitor is kept at the first voltage, and if the voltage of the bit line BL corresponds to the first data, the first data is written to the storage unit 20; if the voltage of the bit line BL corresponds to the second data, the inductive amplifier unit 110 stores the second data; during the second data writing phase, in response to the pre-charge command, the first voltage applied to the second terminal of the ferroelectric capacitor is switched to the second voltage, and the second data is written to the storage unit 20. The precharge instruction is used to instruct the voltages of bit line BL and reference bit line BLB to be reset to the precharge voltage. The first voltage is high, the precharge voltage is low, and the second voltage is low.

[0037] Optionally, in this embodiment, a voltage PL is applied to the second terminal of the ferroelectric capacitor. During the entire data read and write process, the voltage PL is initially a first voltage, and then switches to a second voltage when a pre-charge command is received.

[0038] In the initialization phase of this embodiment, the voltage of bit line BL is the pre-charge voltage. A first voltage is applied to the second end of the ferroelectric capacitor. The initialization unit 120 outputs a reference voltage to the reference bit line BLB. Since bit line BL is electrically connected to the first end of the ferroelectric capacitor, the first voltage is high and the pre-charge voltage is low, creating a voltage difference across the ferroelectric capacitor and completing the initialization of the inductive amplifier. Simultaneously, in the first data writing phase of this embodiment, one end of the ferroelectric capacitor maintains the first voltage. When the voltage of bit line BL corresponds to the first data, the first data can be written to storage unit 20. When the voltage of bit line BL corresponds to the second data, since the second end of the ferroelectric capacitor maintains the first voltage, the second data cannot be written to storage unit 20. The second data can be temporarily stored in the inductive amplifier unit 110 until a pre-charge command is received, i.e., before the voltages of bit line BL and reference bit line BLB are reset to the pre-charge voltage, the first voltage applied to the second end of the ferroelectric capacitor switches to the second voltage, allowing the second data to be written to storage unit 20.

[0039] Since this embodiment does not immediately write the second data into the storage unit 20, but instead temporarily stores the second data in the sensing amplification unit 110, it only writes the second data into the storage unit 20 when the pre-charge command arrives. Therefore, this embodiment changes the voltage at the second end of the ferroelectric capacitor only before resetting the circuit, eliminating the need to change the voltage at the second end of the ferroelectric capacitor in other stages (e.g., the charge sharing stage, the sensing and write-back stage). This avoids the need to change the voltage at the second end of the ferroelectric capacitor every time data is written, as is required in related technologies, thus ensuring data read / write speed and saving power consumption.

[0040] Meanwhile, this embodiment of the application uses a method of pulling up or down the voltage PL during read and write operations. Compared with keeping the voltage PL constant, the BL operating voltage in this method is only half, which reduces the voltage withstand requirement of the sensing amplifier 10 and also reduces the requirements of the read / write transistor.

[0041] See Figure 2 As shown in the figure, this application embodiment provides a schematic diagram of the frame connecting a second type of inductive amplifier 10 and a storage unit 20 electrically. The inductive amplifier 10 also includes a pre-charging unit 130.

[0042] The pre-charge unit 130 is electrically connected to both the bit line BL and the reference bit line BLB. The pre-charge unit 130 is configured to output a pre-charge voltage to the bit line BL and the reference bit line BLB during the pre-charge phase, and to disconnect from the bit line BL and the reference bit line BLB during the initialization phase. The pre-charge phase is located before the initialization phase.

[0043] In some embodiments, the control terminal, first terminal, second terminal, and third terminal of the pre-charge unit 130 are respectively used to electrically connect to the pre-charge signal line, the pre-charge voltage terminal, the bit line BL, and the reference bit line BLB; the voltage of the pre-charge voltage terminal is the pre-charge voltage.

[0044] The pre-charging unit 130 is specifically configured such that: during the pre-charging phase, the control terminal of the pre-charging unit 130 receives a first pre-charging signal output from the pre-charging signal line, and the second and third terminals of the pre-charging unit 130 are both connected to the first terminal of the pre-charging unit 130; during the initialization phase, the control terminal of the pre-charging unit 130 receives a second pre-charging signal output from the pre-charging signal line, and the second and third terminals of the pre-charging unit 130 are both disconnected from the first terminal of the pre-charging unit 130.

[0045] In this embodiment of the application, the pre-charge unit 130 is turned on and off by the pre-charge signal (i.e., the first pre-charge signal and the second pre-charge signal) output by the pre-charge signal line, thereby outputting the pre-charge voltage to bit line BL and reference bit line BLB, and then making the pre-charge voltage of bit line BL and reference bit line BLB floating.

[0046] See Figure 3 As shown, this application embodiment provides a schematic diagram of the framework for the electrical connection between a third type of induction amplifier 10 and a storage unit 20. (As...) Figure 3 As shown, the initialization unit 120 can also be electrically connected to the bit line BL.

[0047] In some embodiments, the first control terminal, the first terminal, and the second terminal of the initialization unit 120 are respectively used to electrically connect to the first initialization signal line, the reference voltage terminal, and the reference bit line BLB; the voltage of the reference voltage terminal is a reference voltage, which is located between the voltage corresponding to the first data and the voltage corresponding to the second data.

[0048] The initialization unit 120 is specifically configured such that, during the initialization phase, the first control terminal of the initialization unit 120 receives the first initialization signal output from the first initialization signal line, and the first and second terminals of the initialization unit 120 are turned on.

[0049] In this embodiment, the initialization unit 120 is turned on by a first initialization signal output from the first initialization signal line, thereby outputting a reference voltage to the reference bit line BLB. Simultaneously, the initialization unit 120 can be turned off at other stages by a second initialization signal output from the first initialization signal line. Both the first and second initialization signals are initialization signals.

[0050] In some embodiments, the second control terminal and the third terminal of the initialization unit 120 are respectively used to electrically connect with the second initialization control line and the bit line BL.

[0051] The initialization unit 120 is also configured such that during the initialization phase, the second control terminal of the initialization unit 120 receives the second initialization signal output by the second initialization signal line, and the first and third terminals of the initialization unit 120 are disconnected.

[0052] The initialization unit 120 in this embodiment can also be electrically connected to the bit line BL. The first and third terminals of the initialization unit 120 can be disconnected through the second initialization signal output by the second initialization signal line. During the data read and write process, the initialization unit 120 can remain electrically disconnected from the bit line BL. See Figure 4 As shown, this application embodiment provides a schematic diagram of the framework for the electrical connection between a fourth type of induction amplifier 10 and a storage unit 20. See also... Figure 4 As shown, the induction amplifier 10 also includes a port control unit 140.

[0053] In some embodiments, the control terminal, first terminal, second terminal, third terminal, and fourth terminal of the port control unit 140 are respectively used to electrically connect to the read / write control signal line, bit line BL, reference bit line BLB, first port, and second port.

[0054] The port control unit 140 is configured to receive a first control signal output from the read / write control signal line during the first data writing phase. The first and third terminals of the port control unit 140 are turned on, and the second and fourth terminals are turned on. The first port and the second port transmit data with the bit line BL and the reference bit line BLB, respectively.

[0055] In this embodiment, the port control unit 140 is turned on by a first control signal output from the read / write control signal line, thereby enabling data transmission with the bit line BL and the reference bit line BLB. Data can be read and written. Simultaneously, the port control unit 140 is turned off by a second control signal output from the read / write control signal line. Both the first and second control signals are control signals.

[0056] In some embodiments, the first, second, third, and fourth terminals of the sensing amplification unit 110 are respectively used to electrically connect to the first control voltage terminal, the second control voltage terminal, the bit line BL, and the reference bit line BLB.

[0057] The sensing amplification unit 110 is also configured to apply a first control voltage to the first control voltage terminal and a second control voltage to the second control voltage terminal during the sensing and write-back phase, so that the sensing amplification unit 110 is powered on and starts up, converting the voltage of the bit line BL into a voltage corresponding to the first data or the second data, and converting the voltage of the reference bit line BLB into a voltage corresponding to the second data or the first data. The induction and write-back phases occur before the first data writing phase, and the second end of the ferroelectric capacitor maintains the first voltage during the induction and write-back phases.

[0058] The inductive amplification unit 110 of this application embodiment can convert the voltage of the bit line BL to obtain a voltage corresponding to the first data or the second data, and at the same time convert the voltage of the reference bit line BLB to a voltage corresponding to the second data or the first data.

[0059] See Figure 5 As shown in the diagram, this application embodiment provides a schematic diagram of the electrical connection between a fifth type of induction amplifier 10 and a storage unit 20. (As shown...) Figure 5 As shown, Cs represents the ferroelectric capacitor, PL represents the voltage applied to the second terminal of the ferroelectric capacitor, WL represents the word line, RST represents the precharge signal, INITB represents the initialization signal output from the first initialization signal line, INITA represents the initialization signal output from the second initialization signal line, CSL represents the control signal output from the read / write control signal line, VSS represents the precharge voltage, VREF represents the reference voltage, the voltage at the first control voltage terminal can be SAP, the voltage at the second control voltage terminal can be VSS, LIO is the data at the first port, and LIOB is the data at the second port.

[0060] See Figure 5 As shown, the ferroelectric capacitor Cs and the switching device M0 constitute the memory cell 20. The switching device M0 is controlled to be turned on and off via the word line WL. During the charge sharing phase, the first terminal of the ferroelectric capacitor Cs is powered on via the word line WL, controlling the charge sharing between the first terminal of the ferroelectric capacitor Cs and the bit line BL. The charge sharing phase is located between the initialization phase and the sensing and write-back phases.

[0061] In some embodiments, the pre-charging unit 130 includes a first switching device and a second switching device.

[0062] The control terminals of the first and second switching devices together serve as the control terminals of the pre-charging unit 130; the first terminal of the first and second switching devices together serve as the first terminal of the pre-charging unit 130; the second terminal of the first and second switching devices respectively serve as the second and third terminals of the pre-charging unit 130.

[0063] In some embodiments, the initialization unit 120 includes a third switching device and a fourth switching device.

[0064] The first terminal of the third switching device and the first terminal of the fourth switching device together serve as the first terminal of the initialization unit 120; the control terminal of the third switching device and the control terminal of the fourth switching device serve as the first control terminal and the second control terminal of the initialization unit 120, respectively; the second terminal of the third switching device and the second terminal of the fourth switching device serve as the second terminal and the third terminal of the initialization unit 120, respectively.

[0065] In some embodiments, the inductive amplification unit 110 includes a fifth switching device, a sixth switching device, a seventh switching device, and an eighth switching device.

[0066] The first terminals of the fifth and sixth switching devices together serve as the first terminal of the induction amplification unit 110; the first terminals of the seventh and eighth switching devices together serve as the second terminal of the induction amplification unit 110; the second terminals of the fifth, sixth, seventh, and eighth switching devices together serve as the third terminal of the induction amplification unit 110; and the control terminals of the fifth, sixth, seventh, and eighth switching devices together serve as the fourth terminal of the induction amplification unit 110.

[0067] If the fifth and sixth switching devices are PMOS transistors, then the seventh and eighth switching devices are NMOS transistors; if the fifth and sixth switching devices are NMOS transistors, then the seventh and eighth switching devices are PMOS transistors.

[0068] See Figure 5 As shown, as an example, the fifth switching device M5 and the sixth switching device M6 in this embodiment are PMOS transistors, the seventh switching device T7 and the eighth switching device T8 are NMOS transistors, and the remaining transistors can be NMOS transistors.

[0069] In this embodiment of the application, the control terminal of the switching device is the gate of a transistor. In the first and second terminals of the switching device, one is the source of the transistor and the other is the drain of the transistor, which can be adjusted accordingly according to the specific circuit structure.

[0070] In some embodiments, the port control unit 140 includes a ninth switching device and a tenth switching device. The control terminals of the ninth and tenth switching devices together serve as the control terminals of the port control unit 140; the first and second terminals of the ninth switching device serve as the first and third terminals of the port control unit 140, respectively; and the first and second terminals of the tenth switching device serve as the second and fourth terminals of the port control unit 140, respectively.

[0071] See Figure 5 As shown, M1 represents the first switching device, M2 represents the second switching device, M3 represents the third switching device, M4 represents the fourth switching device, M5 represents the fifth switching device, M6 represents the sixth switching device, M7 represents the seventh switching device, M8 represents the eighth switching device, M9 represents the ninth switching device, and M10 represents the tenth switching device.

[0072] See Figure 5 As shown, the first terminal of the pre-charge unit 130 is grounded during the pre-charge phase, and the pre-charge voltage VSS is 0.

[0073] In this embodiment, the bit line BL can be precharged to 0V, and the precharge unit 130 can be directly grounded without the need for additional precharge circuits. This reduces the number of transistors and control signals in the induction amplifier 10, saves the number of transistors in the induction amplifier, ensures the read and write speed of the memory, and saves power consumption.

[0074] See Figure 6 As shown in the diagram, this application embodiment provides a schematic diagram of the electrical connection between a sixth type of induction amplifier 10 and a storage unit 20. (As shown...) Figure 6 The sixth type of inductive amplifier 10 shown is... Figure 5 The difference of the fifth type of inductive amplifier 10 shown is that the pre-charge unit 130 includes a first switching device and a second switching device; the control terminal of the first switching device and the control terminal of the second switching device together serve as the control terminal of the pre-charge unit 130; the first terminal of the first switching device serves as the first terminal of the pre-charge unit 130; the second terminal of the first switching device and the first terminal of the second switching device together serve as the second terminal of the pre-charge unit 130; and the second terminal of the second switching device serves as the third terminal of the pre-charge unit 130.

[0075] See Figure 6 As shown, the first end of the second switching device M2 is electrically connected to the bit line BL. Since the second end of the pre-charging unit 130 is electrically connected to the bit line BL, the first end of the second switching device M2 can be used together with the second end of the first switching device as the second end of the pre-charging unit 130.

[0076] See Figure 7As shown in the diagram, this application embodiment provides a schematic diagram of the electrical connection between a seventh type of induction amplifier 10 and a storage unit 20. (As shown...) Figure 7 The seventh type of inductive amplifier 10 shown is... Figure 5 The difference of the fifth type of inductive amplifier 10 shown is that the pre-charge unit 130 includes a first switching device and a second switching device; the control terminal of the first switching device and the control terminal of the second switching device together serve as the control terminal of the pre-charge unit 130; the first terminal of the second switching device serves as the first terminal of the pre-charge unit 130; the second terminal of the first switching device serves as the second terminal of the pre-charge unit 130; and the first terminal of the first switching device and the second terminal of the second switching device together serve as the third terminal of the pre-charge unit 130.

[0077] Specifically, see Figure 7 As shown, the first terminal of the first switching device M1 is electrically connected to the reference bit line BLB. Since the third terminal of the pre-charging unit 130 is electrically connected to the reference bit line BLB, the first terminal of the first switching device M1 and the second terminal of the second switching device can be used together as the third terminal of the pre-charging unit 130.

[0078] Based on the three electrical connection relationships of the pre-charge unit 130 given in this application, this application embodiment can connect the second switching device M2 to the reference bit line BLB and the bit line BL instead of the reference bit line BLB and the pre-charge voltage terminal, or connect the first switching device M1 to the bit line BL and the reference bit line BLB instead of the bit line BL and the pre-charge voltage terminal. This application embodiment can pre-charge the bit line BL and the reference bit line BLB to 0V during the pre-charge stage, and the number of transistors can remain unchanged.

[0079] In this embodiment of the application, during the first data writing stage, or during the sensing and write-back stage, the second data is not immediately written into the storage unit 20. Instead, the second data is temporarily stored on the sensing amplifier 10. When the precharge command PRE arrives, the second data is written into the storage unit 20 before the word line WL is turned off. This avoids changing the PL level every time data is written, which would affect the speed and thus save power consumption.

[0080] It should be noted that the circuit connection method described in this application is only an example of the induction amplifier 10 provided in the embodiment of this application. Each switching device can be selected as a different transistor such as PMOS or NMOS as needed, and the electrical connection method of each component in the induction amplifier provided in the embodiment of this application can be adapted. The adapted electrical connection method is still within the protection scope of the embodiment of this application.

[0081] Based on the same inventive concept, this application provides a memory including: multiple bit lines BL, multiple word lines, multiple array-arranged memory cells 20, and multiple inductive amplifiers 10 according to this application embodiment; One bit line BL is electrically connected to one column of memory cells 20; One word line corresponds to an electrical connection to one row of memory cell 20; Each inductive amplifier 10 is electrically connected to a bit line BL and a reference bit line BLB.

[0082] This application provides a novel inductive amplifier 10 for reading and writing memory that uses ferroelectric capacitors as data storage elements. Based on the inductive amplifier 10, a corresponding timing data access method is adopted, which simplifies the circuit, integrates reading and writing, simplifies the control signals, reduces the requirement for the number of transistors, and saves power consumption.

[0083] Based on the same inventive concept, this application provides an electronic device, including: a memory or an inductive amplifier 10 according to this application.

[0084] Alternatively, the electronic device can be a mobile terminal such as a smartphone, laptop, digital radio receiver, PDA (personal digital assistant), PAD (tablet computer), PMP (portable multimedia player), in-vehicle terminal (e.g., in-vehicle navigation terminal), or a fixed terminal such as a smart TV or desktop computer.

[0085] See Figure 8 As shown, this application provides a flowchart of a data access method. Figure 8 As shown, the data access method of this application embodiment is applied to the inductive amplifier 10 of this application embodiment. The data access method includes steps S801 to S803.

[0086] S801. During the initialization phase, the voltage of the control bit line BL is the pre-charge voltage. The first voltage is applied to the second terminal of the ferroelectric capacitor, and the reference voltage is output to the reference bit line BLB through the initialization unit 120.

[0087] S802. In the first data writing stage, the second end of the ferroelectric capacitor is controlled to maintain the application of the first voltage. If the voltage of the bit line BL corresponds to the first data, the first data is written into the storage unit 20; if the voltage of the bit line BL corresponds to the second data, the second data is stored through the induction amplification unit 110.

[0088] S803, in the second data writing stage, in response to the pre-charge command, the first voltage applied to the second terminal of the ferroelectric capacitor is switched to the second voltage, so that the second data is written to the storage unit 20.

[0089] In this embodiment of the application, in response to a precharge command, the second data writing stage is entered. That is, before resetting the circuit, the first voltage applied to the second terminal of the ferroelectric capacitor is switched to the second voltage, so that the second data is written to the storage unit 20.

[0090] In some embodiments, before the initialization phase, a pre-charging phase is further included, in which the pre-charging unit 130 is electrically connected to both the bit line BL and the reference bit line BLB, and the pre-charging unit 130 outputs the pre-charging voltage to the bit line BL and the reference bit line BLB. The initialization phase also includes: disconnecting the precharge unit 130 from the bit line BL and the reference bit line BLB; the precharge phase is also included after the second data writing phase.

[0091] In some embodiments, between the initialization phase and the first data writing phase, a charge sharing phase is further included, in which the first terminal of the ferroelectric capacitor shares charge with the bit line BL. During the sensing and write-back phase, the control sensing amplification unit 110 is powered on and started, converting the voltage of bit line BL into a voltage corresponding to the first data or the second data, and converting the voltage of reference bit line BLB into a voltage corresponding to the second data or the first data.

[0092] In some embodiments, the first data writing stage further includes: controlling the first port and the second port to transmit data with the bit line BL and the reference bit line BLB respectively through the port control unit 140.

[0093] See Figure 9 As shown, a timing control diagram is illustrated. Figure 9 As shown, the data access method of this application embodiment includes stages T1 to T7, which are, in sequence, a pre-charging stage T1, an initialization stage T2, a charge sharing stage T3, a sensing and write-back stage T4, a first data writing stage T5, a second data writing stage T6, and a pre-charging stage T7. Combined with... Figure 5 The circuit structure shown illustrates the specific steps of this data access method, which include: Pre-charge phase T1: RST remains high, the first switching device M1 and the second switching device M2 are turned on, the bit line BL and the reference bit line BLB are pre-charged to 0V, SAP is pulled down to 0V, and the inductive amplifier unit 110 composed of the fifth switching device M5, the sixth switching device M6, the seventh switching device M7 and the eighth switching device M8 are all in a power-off state.

[0094] Initialization phase T2: Voltage PL is pulled up to the VCORE voltage (high level). Simultaneously, RST is pulled low, the first switching device M1 and the second switching device M2 are turned off, and bit line BL and reference bit line BLB float at 0V. INITB is pulled high, the third switching device M3 is turned on, and the reference bit line BLB is charged to the reference voltage VREF, completing the initialization. This phase is absent in traditional memory data access processes; it is a new phase added in this embodiment.

[0095] Charge sharing phase T3: The word line WL voltage goes high, and the switching device M0 turns on. If the ferroelectric capacitor is negative, it outputs a small amount of charge (ferroelectric polarity does not reverse) under the influence of the bit line BL voltage; if the ferroelectric capacitor is positive, it outputs a larger amount of charge (ferroelectric polarity reverses) under the influence of the bit line BL voltage, thus generating two different voltages, one low and one high, on the bit line BL, corresponding to the first data D0 and the second data D1, respectively. During the initialization phase, the reference voltage VREF of the reference bit line BLB is between the two voltages.

[0096] In the sensing and write-back phase T4: The SAP voltage is pulled high to VCORE, and the sensing amplifier unit 110, composed of the fifth switching device M5, the sixth switching device M6, the seventh switching device M7, and the eighth switching device M8, is simultaneously powered on, converting the voltage on the bit line BL into an electrical signal corresponding to data 0 or 1. Simultaneously, the reference BLB voltage is pulled to the corresponding electrical signal. Since the voltage PL is still high (VCORE) at this time, only the first data D0 is written to the storage unit 20; the second data D1 cannot actually be written to the storage unit 20, but is only stored in the sensing amplifier 10.

[0097] In the first data writing stage T5: CSL is pulled high, the ninth switch M9 and the tenth switch M10 are turned on, and data is written to the sensing amplifier 10. At the same time, the voltages of the bit line BL and the reference bit line BLB are also changed accordingly. However, since the voltage PL is still at a high voltage (VCORE) at this time, only the first data D0 is written to the storage cell 20, and the second data D1 cannot actually be written to the storage cell 20, but is only stored in the sensing amplifier 10.

[0098] Second data writing stage T6: When the memory receives the precharge command PRE, it pulls the voltage PL low and writes the second data D1, temporarily stored in the sensing amplifier 10, into the corresponding memory cell 20. At this point, both the first data D0 and the second data D1 have been written into the memory array. This stage is not present in the data access process of conventional memory; it is a new stage added in this embodiment.

[0099] Pre-charge phase T7: The voltage of word line WL is pulled low to turn off switching device M0, and the inductive amplifier unit 110 composed of the fifth switching device M5, the sixth switching device M6, the seventh switching device M7, and the eighth switching device M8 is de-energized. Finally, RST is pulled high, and the first switching device M1 and the second switching device M2 are turned on, re-pre-charging bit line BL and reference bit line BLB to 0V.

[0100] See Figure 9 As shown, in this embodiment of the application, the voltage of the bit line BL in the first data writing stage T5 corresponds to the first data D0 as an example. In the first data writing stage T5, the first data D0 has been written into the storage unit 20.

[0101] Furthermore, the data access method in this application embodiment may also include a random read phase. Figure 9 This stage is not included in the timing diagram shown. During the random read stage, CSL is pulled high, the ninth switch M9 and the tenth switch M10 are turned on, and data is read from the inductive amplifier 10 through the first and second ports. The storage cell 20 is unaffected, and the read speed during this stage is the same as that of a conventional memory.

[0102] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0103] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0104] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0105] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0106] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0107] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. An inductive amplifier, characterized in that, include: An induction amplification unit for electrical connection to the bit line and the reference bit line, and an initialization unit for electrical connection to the reference bit line; The bit line is used to electrically connect to the first terminal of the ferroelectric capacitor of the memory cell; The inductive amplifier is configured such that, during the initialization phase, the voltage of the bit line is a pre-charge voltage, a first voltage is applied to the second terminal of the ferroelectric capacitor, and the initialization unit outputs a reference voltage to the reference bit line. During the first data writing phase, the second terminal of the ferroelectric capacitor is maintained with the first voltage applied. If the voltage of the bit line corresponds to the first data, the first data is written to the storage unit. If the voltage of the bit line corresponds to the second data, the sensing amplification unit stores the second data. During the second data writing phase, in response to the pre-charge command, the first voltage applied to the second terminal of the ferroelectric capacitor is switched to the second voltage, and the second data is written to the storage unit. The precharge command is used to instruct the voltage of the bit line and the reference bit line to be reset to the precharge voltage, wherein the first voltage is high, the precharge voltage is low, and the second voltage is low.

2. The inductive amplifier according to claim 1, characterized in that, Also includes: A pre-charge unit, electrically connected to both the bit line and the reference bit line, is configured to output the pre-charge voltage to the bit line and the reference bit line during the pre-charge phase, and to disconnect from the bit line and the reference bit line during the initialization phase. The pre-charging phase occurs before the initialization phase.

3. The inductive amplifier according to claim 2, characterized in that, The control terminal, first terminal, second terminal, and third terminal of the pre-charge unit are respectively used to electrically connect to the pre-charge signal line, the pre-charge voltage terminal, the bit line, and the reference bit line; the voltage of the pre-charge voltage terminal is the pre-charge voltage; The pre-charging unit is specifically configured as follows: During the pre-charging phase, the control terminal of the pre-charging unit receives the first pre-charging signal output by the pre-charging signal line, and the second and third terminals of the pre-charging unit are both connected to the first terminal of the pre-charging unit; during the initialization phase, the control terminal of the pre-charging unit receives the second pre-charging signal output by the pre-charging signal line, and the second and third terminals of the pre-charging unit are both disconnected from the first terminal of the pre-charging unit.

4. The inductive amplifier according to claim 3, characterized in that, The first terminal of the pre-charging unit is grounded during the pre-charging phase, and the pre-charging voltage is 0.

5. The inductive amplifier according to claim 3, characterized in that, The pre-charging unit includes a first switching device and a second switching device; The control terminals of the first and second switching devices together serve as the control terminals of the pre-charging unit. The first end of the first switching device and the first end of the second switching device together serve as the first end of the pre-charging unit; The second end of the first switching device and the second end of the second switching device serve as the second and third ends of the pre-charging unit, respectively.

6. The inductive amplifier according to claim 3, characterized in that, The pre-charging unit includes a first switching device and a second switching device; The control terminals of the first and second switching devices together serve as the control terminals of the pre-charging unit. The first terminal of the first switching device serves as the first terminal of the pre-charging unit. The second end of the first switching device and the first end of the second switching device together serve as the second end of the pre-charging unit. The second terminal of the second switching device serves as the third terminal of the pre-charging unit.

7. The inductive amplifier according to claim 3, characterized in that, The pre-charging unit includes a first switching device and a second switching device; The control terminals of the first and second switching devices together serve as the control terminals of the pre-charging unit. The first terminal of the second switching device serves as the first terminal of the pre-charging unit; The second terminal of the first switching device serves as the second terminal of the pre-charging unit. The first end of the first switching device and the second end of the second switching device together serve as the third end of the pre-charging unit.

8. The inductive amplifier according to claim 1, characterized in that, The first control terminal, the first terminal, and the second terminal of the initialization unit are respectively used to electrically connect to the first initialization signal line, the reference voltage terminal, and the reference bit line; the voltage of the reference voltage terminal is the reference voltage, which is located between the voltage corresponding to the first data and the voltage corresponding to the second data; The initialization unit is specifically configured such that, during the initialization phase, the first control terminal of the initialization unit receives the first initialization signal output from the first initialization signal line, and the first and second terminals of the initialization unit are turned on.

9. The inductive amplifier according to claim 8, characterized in that, The second control terminal and the third terminal of the initialization unit are respectively used to be electrically connected to the second initialization control line and the bit line; The initialization unit is further configured such that, during the initialization phase, the second control terminal of the initialization unit receives the second initialization signal output by the second initialization signal line, and the first and third terminals of the initialization unit are disconnected.

10. The inductive amplifier according to claim 9, characterized in that, The initialization unit includes a third switching device and a fourth switching device; The first terminal of the third switching device and the first terminal of the fourth switching device together serve as the first terminal of the initialization unit. The control terminals of the third and fourth switching devices serve as the first and second control terminals of the initialization unit, respectively. The second terminal of the third switching device and the second terminal of the fourth switching device serve as the second and third terminals of the initialization unit, respectively.

11. The inductive amplifier according to claim 1, characterized in that, The first, second, third, and fourth terminals of the inductive amplification unit are respectively used to electrically connect to the first control voltage terminal, the second control voltage terminal, the bit line, and the reference bit line; The inductive amplification unit is further configured to apply a first control voltage to the first control voltage terminal and a second control voltage to the second control voltage terminal during the sensing and write-back phase, so that the inductive amplification unit is powered on and starts up, converting the voltage of the bit line into a voltage corresponding to the first data or the second data, and converting the voltage of the reference bit line into a voltage corresponding to the second data or the first data. The induction and write-back phase is located before the first data writing phase, and the second end of the ferroelectric capacitor maintains the first voltage during the induction and write-back phase.

12. The inductive amplifier according to claim 11, characterized in that, The inductive amplification unit includes a fifth switching device, a sixth switching device, a seventh switching device, and an eighth switching device; The first terminal of the fifth switching device and the first terminal of the sixth switching device together serve as the first terminal of the inductive amplification unit; The first terminal of the seventh switching device and the first terminal of the eighth switching device together serve as the second terminal of the inductive amplification unit; The second terminal of the fifth switching device, the control terminal of the sixth switching device, the second terminal of the seventh switching device, and the control terminal of the eighth switching device together serve as the third terminal of the inductive amplification unit. The control terminal of the fifth switching device, the second terminal of the sixth switching device, the control terminal of the seventh switching device, and the second terminal of the eighth switching device together serve as the fourth terminal of the inductive amplification unit. If the fifth and sixth switching devices are PMOS transistors, then the seventh and eighth switching devices are NMOS transistors; If the fifth and sixth switching devices are NMOS transistors, then the seventh and eighth switching devices are PMOS transistors.

13. The inductive amplifier according to claim 1, characterized in that, Also includes: The port control unit, wherein the control terminal, first terminal, second terminal, third terminal, and fourth terminal are respectively used to electrically connect to the read / write control signal line, bit line, reference bit line, first port, and second port; The port control unit is configured such that, during the first data writing phase, the control terminal of the port control unit receives the first control signal output by the read / write control signal line, the first and third terminals of the port control unit are turned on, and the second and fourth terminals are turned on, and the first port and the second port respectively transmit data with the bit line and the reference bit line.

14. The inductive amplifier according to claim 13, characterized in that, The port control unit includes a ninth switching device and a tenth switching device; The control terminals of the ninth and tenth switching devices together serve as the control terminals of the port control unit. The first and second terminals of the ninth switching device serve as the first and third terminals of the port control unit, respectively. The first and second terminals of the tenth switching device serve as the second and fourth terminals of the port control unit, respectively.

15. A memory, characterized in that, include: Multiple bit lines, multiple word lines, multiple array-arranged memory cells, and multiple sensing amplifiers as described in any one of claims 1-14; One of the bit lines is electrically connected to a column of the memory cells; One of the word lines is electrically connected to one row of the memory cells; Each inductive amplifier is electrically connected to a bit line and a reference bit line.

16. An electronic device, characterized in that, include: The memory as claimed in claim 15 or the inductive amplifier as claimed in any one of claims 1-14.

17. A data access method, characterized in that, The inductive amplifier used in any one of claims 1-14 comprises: During the initialization phase, the voltage of the control bit line is the pre-charge voltage, the first voltage is applied to the second terminal of the ferroelectric capacitor, and the reference voltage is output to the reference bit line through the initialization unit; During the first data writing stage, the second terminal of the ferroelectric capacitor is controlled to maintain the first voltage applied. If the voltage of the bit line corresponds to the first data, the first data is written to the storage unit; if the voltage of the bit line corresponds to the second data, the second data is stored through the inductive amplification unit. In the second data writing phase, in response to the pre-charge command, the first voltage applied to the second terminal of the ferroelectric capacitor is switched to the second voltage, so that the second data is written to the storage cell.

18. The data access method according to claim 17, characterized in that, Before the initialization phase, a pre-charging phase is also included, in which the pre-charging unit is electrically connected to both the bit line and the reference bit line, and the pre-charging unit outputs a pre-charging voltage to the bit line and the reference bit line. The initialization phase further includes: disconnecting the pre-charge unit from the bit line and the reference bit line; The pre-charge phase is included after the second data writing phase.

19. The data access method according to claim 17, characterized in that, Between the initialization phase and the first data writing phase, the following is also included: During the charge sharing phase, the first terminal of the ferroelectric capacitor is controlled to share the charge with the bit line. During the sensing and write-back phase, the sensing amplification unit is powered on and started, converting the voltage of the bit line into a voltage corresponding to the first data or the second data, and converting the voltage of the reference bit line into a voltage corresponding to the second data or the first data.

20. The data access method according to claim 17, characterized in that, The first data writing stage also includes: The port control unit controls the first port and the second port to transmit data with the bit line and the reference bit line, respectively.

Images