MRAM-compatible sensitive amplifiers, amplifier circuits, and modules

Abstract

This invention relates to the field of non-volatile magnetic random access memory (MRAM) circuit design technology, and discloses a sensitive amplifier, amplification circuit, and module adapted to MRAM. The sensitive amplifier adapted to MRAM of this invention includes: 5 PMOS transistors P0~P4, 5 NMOS transistors N0~N4, and 10 switching switches AMP1~AMP1. 10 Two capacitors C1 and C2 are used. This invention uses circuit design to record the offset of the two NMOS transistors N1 and N2, which act as transmission transistors, on capacitors C1 and C2 during bit line pre-charge. In conjunction with switches AMP3 and AMP6, the overdrive voltage of N1 and N2 is compensated, so that they are not affected by the offset of N1 and N2. This not only eliminates the offset, but also saves the time sacrifice of the traditional method.

Description

Technical Field

[0001] This invention relates to the field of non-volatile magnetic random access memory (MRAM) circuit design technology, and more specifically, to: 1. a sensitive amplifier adapted to MRAM; 2. an amplifier circuit adapted to MRAM constructed based on the sensitive amplifier; 3. an amplifier module using the layout of the sensitive amplifier or amplifier circuit. Background Technology

[0002] Unlike traditional semiconductor random access memory (RAM), MRAM uses magnetic tunnel junctions (MTJs) as storage devices, recording binary data by changing the magnetization direction. Currently, common MRAM memory cells generally adopt a 2T-2MTJ (i.e., containing 2 transistors and 2 magnetic tunnel junctions) structure design, using the complementary resistance states of the two MTJs to represent 0 or 1.

[0003] Existing sensitive amplifiers use the voltage difference between two bit lines BL and BLB, generated by their different discharge rates, to determine the stored data when reading from an MRAM memory array. However, this method relies on a relatively small voltage difference, making it highly susceptible to offset voltage fluctuations and prone to reading errors. While extending the sensing time can improve the amplifier's performance, or sacrificing additional cycles for offset sampling and compensation, this excessively lengthens the overall recognition cycle, failing to meet the requirements for rapid recognition. Summary of the Invention

[0004] Therefore, it is necessary to provide sensitive amplifiers, amplification circuits, and modules adapted to MRAM to address the problem that the sensitive amplifiers used in existing MRAMs are susceptible to read errors due to offset voltage and cannot achieve fast identification.

[0005] This invention is achieved using the following technical solution: In a first aspect, the present invention provides a sensitive amplifier adapted to MRAM, comprising: 5 PMOS transistors P0~P4, 5 NMOS transistors N0~N4, and 10 switching switches AMP1~AMP1. 10 Two capacitors, C1 and C2.

[0006] The sources of P0~P4 are connected to the power supply VDD; the gates of P1, P4, and N0 are connected to the enable signal SAE1; the gate of P0 is connected to the enable signal SAE; the drains of P1~P2, the gate of P3, the drain of N3, and the gate of N4 are connected together to form node V1; the drains of P3~P4, the gate of P2, the drain of N4, and the gate of N3 are connected together to form node V2; the source of N3 is connected to bit line BL through AMP9 and AMP1 in sequence; the source of N3 is connected to the drain of N1 through AMP9; the gate of N1 is connected to VDD through AMP2; the gate of N1 is connected to bit line BLB through AMP3; the source of N4 is connected to AMP9 through AMP2 and AMP3 through AMP4 ... 10 AMP4 is connected to BLB; the source of N4 is connected to AMP. 10 Connect the drain of N2; connect the gate of N2 to VDD via AMP5; connect the source of N1 to the source of N2; connect the source of N1 to the drain of N0 via AMP7; connect the source of N2 to the drain of P0 via AMP8; connect the gate of N2 to BL via AMP6; connect BL to ground via C1; connect BLB to ground via C2.

[0007] C1 and C2 work with AMP3 and AMP6 to record the offset of N1 and N2, and to ensure that the overdrive voltage of N1 and N2 is not affected by the offset of N1 and N2; V1 and V2 are used to characterize the result of reading the stored value.

[0008] This type of sensitive amplifier adapted to MRAM is implemented according to the method or process of embodiments of the present disclosure.

[0009] In a second aspect, the present invention discloses an amplifier circuit adapted to MRAM, comprising: an MRAM memory cell and a sensitive amplifier adapted to MRAM as disclosed in the first aspect.

[0010] MRAM memory cells are used to store 0 or 1. The sensitive amplifier adapted to MRAM is connected to the MRAM memory cell via BL and BLB, and is used to read the value stored in the MRAM memory cell and reflect it on V1 and V2.

[0011] This type of amplifier circuit is implemented according to the method or process of an embodiment of this disclosure.

[0012] Thirdly, the present invention discloses an amplification module that adopts the layout of the sensitive amplifier adapted to MRAM disclosed in the first aspect, or the layout of the amplification circuit adapted to MRAM disclosed in the second aspect.

[0013] This amplification module is implemented according to the method or process of an embodiment of this disclosure.

[0014] Compared with the prior art, the present invention has the following beneficial effects: This invention uses circuit design to record the offset of the two NMOS transistors N1 and N2, which act as transmission transistors, on capacitors C1 and C2 during bit line pre-charge. In conjunction with switches AMP3 and AMP6, it compensates for the overdrive voltage of N1 and N2, so that they are not affected by the offset of N1 and N2. This not only eliminates the offset, but also saves the time sacrifice of the traditional method. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A circuit diagram of an amplifier circuit adapted for MRAM provided in an embodiment of the present invention; Figure 2 for Figure 1 Timing diagram of the amplifier circuit adapted to MRAM. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0020] Example First, see Figure 1The circuit diagram provided in this embodiment is an amplifier circuit adapted to MRAM, which can be divided into the following functional areas: a sensitive amplifier adapted to MRAM and an MRAM memory cell.

[0021] In general, MRAM memory cells are used to store 0 or 1; the sensitive amplifiers adapted to MRAM are connected to the MRAM memory cells through bit lines BL and BLB, and are used to read the values ​​stored in the MRAM memory cells and reflect them on nodes V1 and V2.

[0022] I. The MRAM memory cell adopts the common 2T-2MTJ structure, which includes: 2 NMOS transistors NM1~NM2 and 2 magnetic tunnel junctions MTJ1~MTJ2.

[0023] The gates of NM1 and NM2 are connected to the word line WL; the source of NM1 is connected to the source line SL, and the drain is connected to one end of MTJ1; the other end of MTJ1 is connected to BL; the source of NM2 is connected to the source line SLB, and the drain is connected to one end of MTJ2; the other end of MTJ2 is connected to BLB.

[0024] As described in the background section, the resistance states of MTJ1 and MTJ2 are complementary. Therefore, it can be configured such that: MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, corresponding to storing 1 in the MRAM memory cell; or MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, corresponding to storing 0 in the MRAM memory cell. Alternatively, it can be configured such that: MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, corresponding to storing 0 in the MRAM memory cell; or MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, corresponding to storing 1 in the MRAM memory cell.

[0025] In addition, MRAM memory cells can also use other compatible sensitive amplifier designs, such as replacing the NMOS transistors with PMOS transistors (the corresponding WL control logic needs to be reversed).

[0026] II. The sensitive amplifier adapted to MRAM is designed to include: 5 PMOS transistors P0~P4, 5 NMOS transistors N0~N4, and 10 switching switches AMP1~AMP 10 Two capacitors, C1 and C2.

[0027] The specific link is as follows: The sources of P0~P4 are connected to the power supply VDD; the gates of P1, P4, and N0 are connected to the enable signal SAE1; the gate of P0 is connected to the enable signal SAE; the drains of P1~P2, the gate of P3, the drain of N3, and the gate of N4 are connected together to form node V1; the drains of P3~P4, the gate of P2, the drain of N4, and the gate of N3 are connected together to form node V2; the source of N3 is connected to bit line BL through AMP9 and AMP1 in sequence; the source of N3 is connected to the drain of N1 through AMP9; the gate of N1 is connected to VDD through AMP2; the gate of N1 is connected to bit line BLB through AMP3; the source of N4 is connected to AMP9 through AMP2 and AMP3 through AMP4 ... 10 AMP4 is connected to BLB; the source of N4 is connected to AMP. 10 Connect the drain of N2; connect the gate of N2 to VDD via AMP5; connect the source of N1 to the source of N2; connect the source of N1 to the drain of N0 via AMP7; connect the source of N2 to the drain of P0 via AMP8; connect the gate of N2 to BL via AMP6; connect BL to ground via C1; connect BLB to ground via C2.

[0028] Among them, AMP1, AMP4, and AMP8 are in the same state; AMP2 and AMP5 are in the same state; AMP3, AMP6, and AMP7 are in the same state; AMP9 and AMP... 10 Same status.

[0029] For ease of control, it can be configured as follows: AMP1, AMP4, and AMP8 are all controlled by control signal S0; AMP2 and AMP5 are all controlled by control signal S1; AMP3, AMP6, and AMP7 are all controlled by control signal S2; AMP9 and AMP4 are all controlled by control signal S2. 10 It is uniformly controlled by the control signal S3.

[0030] Therefore, when S0~S3 are high, AMP1~AMP 10 On; when S0~S3 are low, AMP1~AMP 10 disconnect.

[0031] It should be noted that N1 and N2, as transmission transistors, can cause the entire sensitive amplifier to exhibit the problems mentioned in the background section. In this embodiment, C1 and C2, together with AMP3 and AMP6, record the offset of N1 and N2 and ensure that the overdrive voltage of N1 and N2 is not affected by the offset of N1 and N2; V1 and V2 are used to characterize the stored value reading result.

[0032] The amplifier circuit adapted to MRAM based on the above design has the following operating timing sequence: bit line precharge and offset recording stage, node precharge stage, bit line discharge stage, offset cancellation and sensing amplification stage.

[0033] See Figure 2 The following provides a detailed explanation of the timing of each of the above stages: 1. In the bit line precharge and offset recording stage: WL is set to low level (NM1~NM2 are off), SAE is set to low level (P0 is on), SAE1 is set to high level (N0 is on, P1 and P4 are off), AMP1, AMP4, and AMP8 are turned on (i.e., S0 is set to high level), AMP2 and AMP5 are turned on (i.e., S1 is set to high level), AMP3, AMP6, and AMP7 are turned off (i.e., S2 is set to low level), AMP9, AMP... 10 Disconnect (i.e., S3 is set to low level).

[0034] P0, AMP8, N1, and AMP1 form a path from VDD to BL, meaning VDD charges BL through P0, AMP8, N1, and AMP1. It should be noted that the signal can be considered lossless when passing through P0, AMP8, and AMP1, but when passing through N1, its threshold voltage must be overcome. Therefore, the voltage at the connection point of C1 and BL (i.e., the BL voltage) is set to VDD-Vth1; Vth1 represents the threshold voltage of N1.

[0035] P0, AMP8, N2, and AMP4 form a path from VDD to BLB, meaning VDD charges BLB through P0, AMP8, N2, and AMP4. It should be noted that the signal can be considered lossless when passing through P0, AMP8, and AMP4, but when passing through N2, its threshold voltage must be overcome. Therefore, the voltage at the connection point between C2 and BLB (i.e., the BLB voltage) is set to VDD - Vth2; Vth2 represents the threshold voltage of N2.

[0036] Through the above processing, in the bit line pre-charge and offset recording stage, not only are BL and BLB pre-charged, but the offset is also recorded on C1 and C2.

[0037] 2. During the node precharge phase: WL remains low (NM1~NM2 are off), SAE switches to high (P0 is off), SAE1 switches to low (N0 is off, P1 and P4 are on), AMP1, AMP4, and AMP8 are off (i.e., S0 is low), AMP2 and AMP5 are on (i.e., S1 is high), AMP3, AMP6, and AMP7 are off (i.e., S2 is low), AMP9, AMP... 10 Turn on (i.e., S3 is set to high level).

[0038] P1 forms a path from VDD to V1, that is, VDD charges V1 through P1 and turns on N4. P4 forms a path from VDD to V2, meaning that VDD charges V2 through P4 and turns on N3.

[0039] Since AMP1 and AMP4 are disconnected, V1 and V2 have no discharge path, so they are pre-charged and kept at a high level.

[0040] 3. During the in-line discharge stage: WL switches to high level (NM1~NM2 are turned on), BL discharges to SL through MTJ1 and NM1, and BLB discharges to SLB through MTJ2 and NM2.

[0041] SAE remains high (P0 off), SAE1 remains low (N0 off, P1 and P4 on), AMP1, AMP4, and AMP8 are off (i.e., S0 is low), AMP2 and AMP5 are on (i.e., S1 is high), AMP3, AMP6, and AMP7 are off (i.e., S2 is low), AMP9, AMP... 10 Turn on (i.e., S3 is set to high level).

[0042] It should be noted that when the resistance state of an MTJ is determined, it is equivalent to a resistor with a fixed resistance value, and therefore the current flowing through it is also fixed.

[0043] In other words, the discharge current from BL to SL (denoted as I1) and the discharge current from BLB to SLB (denoted as I2) are fixed values, and I1 and I2 satisfy: If MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, then I1 < I2; If MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, then I1 > I2.

[0044] 4. During the offset cancellation and sensing amplification stage, WL remains high (NM1~NM2 are on), SAE remains high (P0 is off), SAE1 switches to high (N0 is on, P1 and P4 are off), AMP1, AMP4, and AMP8 are off (i.e., S0 is low), AMP2 and AMP5 are off (i.e., S1 is low), AMP3, AMP6, and AMP7 are on (i.e., S2 is high), and AMP9 and AMP... 10 Turn on (i.e., S3 is set to high level).

[0045] AMP6 forms a path from BL to the gate of N2. Then, BL passes through AMP6 to connect the gate of N2, and the gate voltage of N2 is set at VDD-Vth1-I1Δt, thereby setting the overdrive voltage of N2 at VDD-Vth1-Vth2-I1Δt; Δt represents the discharge duration.

[0046] AMP3 forms a path from BLB to the gate of N1. Then, BLB passes through AMP3 to connect the gate of N1. The gate voltage of N1 is then set to VDD-Vth2-I2Δt, thereby setting the overdrive voltage of N1 to VDD-Vth2-Vth1-I2Δt.

[0047] Comparing the overdrive voltage expressions for N1 and N2, we can see that VDD-Vth1-Vth2 are the same, only I1Δt and I2Δt are different. In other words, the overdrive voltages of N1 and N2 are no longer affected by the offset of N1 and N2 (it can be regarded as the offset of N1 and N2 being completely eliminated), so there is no need to excessively prolong the discharge time, thus effectively controlling the overall identification cycle.

[0048] N3, AMP9, N1, AMP7, and N0 form a path from V1 to ground, so V1 discharges to ground through N3, AMP9, N1, AMP7, and N0. N3, AMP9, N1, AMP7, and N0 form a path from V2 to ground, so V2 discharges to ground through N3, AMP9, N1, AMP7, and N0.

[0049] If MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, the discharge rate of V1 is less than the discharge rate of V2 (i.e., I1 < I2), the remaining voltage of V2 is less than the remaining voltage of V1, and the conduction amplitude of N3 is less than that of N4. The discharge rate of V1 further decreases, and P2 gradually conducts and causes VDD to charge V1, thereby widening the potential difference between V1 and V2, so that V1 is placed at a high level and V2 is placed at a low level.

[0050] If MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, the discharge rate of V1 is greater than that of V2 (i.e., I1 > I2), the remaining voltage of V2 is greater than that of V1, and the conduction amplitude of N3 is greater than that of N4. The discharge rate of V2 further decreases, and P3 gradually conducts and charges VDD to V2, thereby widening the potential difference between V1 and V2, so that V1 is placed at a low level and V2 is placed at a high level.

[0051] In other words, when MTJ1 and MTJ2 are in different resistive states, V1 and V2 can eventually be smoothly and quickly pulled to opposite potentials. As mentioned above, V1 and V2 are used to characterize the result of the stored value read. At the end of the offset cancellation and sensing amplification stage, V1 and V2 will be placed at opposite potentials, which correspond to the resistive states of MTJ1 and MTJ2. Therefore, the value stored in the MRAM memory cell can be further deduced.

[0052] This embodiment also discloses an amplification module, which adopts the layout of the MRAM-adapted sensitive amplifier or MRAM-adapted amplification circuit disclosed above. The modular packaging facilitates the promotion and application of the aforementioned circuit. Of course, the circuit can also be designed as a chip—in this case, the corresponding terminals can be designed as pins.

[0053] Furthermore, to quantify the effectiveness of the aforementioned MRAM-adapted sensitive amplifier, Monte Carlo simulations were performed under the same conditions as a conventional sensitive amplifier to examine their read accuracy. The results show that, sensing at 0.05 ns after WL is opened, the accuracy of reading MRAM memory cells using the conventional sensitive amplifier is only 46%, while the accuracy using the aforementioned MRAM-adapted sensitive amplifier is improved to 98.5%, demonstrating the effectiveness and superiority of the MRAM-adapted sensitive amplifier.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A sensitive amplifier adapted to MRAM, characterized in that, include: 5 PMOS transistors P0~P4, 5 NMOS transistors N0~N4, and 10 switching switches AMP1~AMP 10 Two capacitors, C1 and C2; The sources of P0~P4 are connected to the power supply VDD; the gates of P1, P4, and N0 are connected to the enable signal SAE1; the gate of P0 is connected to the enable signal SAE; the drains of P1~P2, the gate of P3, the drain of N3, and the gate of N4 are connected together to form node V1; the drains of P3~P4, the gate of P2, the drain of N4, and the gate of N3 are connected together to form node V2; the source of N3 is connected to bit line BL through AMP9 and AMP1 in sequence; the source of N3 is connected to the drain of N1 through AMP9; the gate of N1 is connected to VDD through AMP2; the gate of N1 is connected to bit line BLB through AMP3; the source of N4 is connected to AMP9 through AMP2 and AMP3 through AMP4 ... 10 AMP4 is connected to BLB; the source of N4 is connected to AMP. 10 Connect the drain of N2; connect the gate of N2 to VDD via AMP5; connect the source of N1 to the source of N2; connect the source of N1 to the drain of N0 via AMP7; connect the source of N2 to the drain of P0 via AMP8; connect the gate of N2 to BL via AMP6; connect BL to ground via C1; connect BLB to ground via C2. C1 and C2 work with AMP3 and AMP6 to record the offset of N1 and N2, and to ensure that the overdrive voltage of N1 and N2 is not affected by the offset of N1 and N2; V1 and V2 are used to characterize the result of reading the stored value.

2. The sensitive amplifier adapted to MRAM according to claim 1, characterized in that, AMP1, AMP4, and AMP8 are in the same state; AMP2 and AMP5 are in the same state; AMP3, AMP6, and AMP7 are in the same state; AMP9 and AMP8 are in the same state. 10 Same status.

3. An amplifier circuit adapted to MRAM, characterized in that, include: MRAM memory cells are used to store 0 or 1; as well as The sensitive amplifier adapted to MRAM as described in claim 1 or 2 is connected to the MRAM storage cell via BL and BLB, and is used to read the value stored in the MRAM storage cell and reflect it on V1 and V2.

4. The MRAM-compatible amplifier circuit according to claim 3, characterized in that, The MRAM memory cell includes: 2 NMOS transistors NM1~NM2 and 2 magnetic tunnel junctions MTJ1~MTJ2; The gates of NM1 and NM2 are connected to the word line WL; the source of NM1 is connected to the source line SL, and the drain is connected to one end of MTJ1; the other end of MTJ1 is connected to BL; the source of NM2 is connected to the source line SLB, and the drain is connected to one end of MTJ2; the other end of MTJ2 is connected to BLB. In this context, MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, corresponding to the storage of 1 in the MRAM memory cell; MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, corresponding to the storage of 0 in the MRAM memory cell. Alternatively, MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, corresponding to the storage of 0 in the MRAM memory cell; MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, corresponding to the storage of 1 in the MRAM memory cell.

5. The MRAM-compatible amplifier circuit according to claim 4, characterized in that, The working sequence includes: bit line precharge and offset recording stage, node precharge stage, bit line discharge stage, offset elimination and sensing amplification stage.

6. The MRAM-compatible amplifier circuit according to claim 5, characterized in that, During the bit line precharge and offset recording phase, WL is set to low level, SAE is set to low level, SAE1 is set to high level, AMP1, AMP4, and AMP8 are turned on, AMP2 and AMP5 are turned on, AMP3, AMP6, and AMP7 are turned off, and AMP9 and AMP8 are turned off. 10 disconnect; VDD charges BL through P0, AMP8, N1, and AMP1, so that the voltage at the connection point between C1 and BL is set at VDD-Vth1; VDD charges BLB through P0, AMP8, N2, and AMP4, so that the voltage at the connection point between C2 and BLB is set at VDD-Vth2; Vth1 represents the threshold voltage of N1, and Vth2 represents the threshold voltage of N2.

7. The MRAM-compatible amplifier circuit according to claim 6, characterized in that, During the node pre-charge phase, WL remains low, SAE switches to high, SAE1 switches to low, AMP1, AMP4, and AMP8 are disconnected, AMP2 and AMP5 are turned on, AMP3, AMP6, and AMP7 are disconnected, and AMP9 and AMP8 are turned on. 10 Conduction; VDD charges V1 through P1 and turns on N4; VDD charges V2 through P4 and turns on N3.

8. The amplifier circuit adapted for MRAM according to claim 7, characterized in that, During the bit line discharge phase, WL switches to a high level, BL discharges to SL through MTJ1 and NM1, and BLB discharges to SLB through MTJ2 and NM2. SAE remains high, SAE1 remains low, AMP1, AMP4, and AMP8 are off, AMP2 and AMP5 are on, AMP3, AMP6, and AMP7 are off, and AMP9 and AMP8 are off. 10 Conduction.

9. The MRAM-compatible amplifier circuit according to claim 8, characterized in that, During the offset cancellation and sensing amplification phase, WL remains high, SAE remains high, SAE1 switches to high, AMP1, AMP4, and AMP8 are disconnected, AMP2 and AMP5 are disconnected, AMP3, AMP6, and AMP7 are turned on, and AMP9 and AMP... 10 Conduction; BL connects to the gate of N2 via AMP6, setting the overdrive voltage of N2 to VDD-Vth1-Vth2-I1Δt; BLB connects to the gate of N1 via AMP3, setting the overdrive voltage of N1 to VDD-Vth2-Vth1-I2Δt; where I1 represents the discharge current from BL to SL; I2 represents the discharge current from BLB to SLB; Δt represents the discharge duration; I1 and I2 satisfy the following conditions: if MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, I1 < I2; if MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, I1 > I2; V1 discharges to ground via N3, AMP9, N1, AMP7, and N0; V2 discharges to ground via N3, AMP9, N1, AMP7, and N0. If MTJ1 is in a high-resistance state and MTJ2 is in a low-resistance state, the discharge rate of V1 is less than the discharge rate of V2, the remaining voltage of V2 is less than the remaining voltage of V1, and the conduction amplitude of N3 is less than that of N4. The discharge rate of V1 further decreases, and P2 gradually conducts and VDD charges V1, thereby widening the potential difference between V1 and V2, so that V1 is placed at a high level and V2 is placed at a low level. If MTJ1 is in a low-resistance state and MTJ2 is in a high-resistance state, the discharge rate of V1 is greater than that of V2, the remaining voltage of V2 is greater than that of V1, and the conduction amplitude of N3 is greater than that of N4. The discharge rate of V2 further decreases, and P3 gradually conducts and charges VDD to V2, thereby widening the potential difference between V1 and V2, so that V1 is placed at a low level and V2 is placed at a high level.

10. An amplification module, characterized in that, It adopts the layout of the sensitive amplifier adapted to MRAM as described in any one of claims 1-2, or the layout of the amplifier circuit adapted to MRAM as described in any one of claims 3-9.

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