Receiving circuit, semiconductor memory device, and control method for semiconductor memory device

Abstract

This invention provides a receiving circuit, a semiconductor memory device, and a control method for the semiconductor memory device, enabling high-speed operation even when the amplitude of the input signal is large. The solution is a receiving circuit 1, comprising: amplifiers 10a and 10b, which amplify an input signal CK_t and operate by configuring bias voltages PBIAS and NBIAS based on the voltage of the input signal CK_t; and controllers 13a and 13b, which suppress the bias voltages PBIAS and NBIAS from becoming floating when an input signal CK_t with an amplitude greater than a given value is input to amplifiers 10a and 10b.

Description

Technical Field

[0001] This invention relates to a receiving circuit, a semiconductor memory device, and a control method for the semiconductor memory device. Background Technology

[0002] In the prior art (e.g., Japanese Patent Application Publication No. 2001-103098), semiconductor memory devices (e.g., Dynamic Random Access Memory (DRAM)) have a receiving circuit that includes an amplifying section that amplifies a signal input from an external source.

[0003] Existing receiver circuits use a transistor to control the bias voltage in order for the amplifier to operate. This bias voltage is generated based on the input signal voltage. However, when an input signal with an amplitude exceeding a given value is input to the amplifier, the amplifier, composed of transistors, becomes OFF, and the bias voltage may become floating. In this case, it is difficult to properly pull up / pull down the amplifier's output signal, making it impossible to suppress the output signal amplitude to the desired range. Consequently, the time required to invert the logic state of the output signal increases. Therefore, achieving high-speed operation on a semiconductor device can become difficult. Summary of the Invention

[0004] The present invention provides a receiving circuit comprising: an amplifier that amplifies an input signal and operates by biasing a voltage based on the voltage of the input signal; and a controller that suppresses the bias voltage from becoming floating when an input signal of an amplitude greater than a given value is input to the amplifier.

[0005] According to the present invention, when an input signal with an amplitude greater than a given value is input to the amplifier, since the bias voltage can be suppressed from becoming floating, the output signal of the amplifier can be appropriately pulled up / pull down, thereby suppressing the amplitude of the output signal to a desired range. Therefore, the time required to invert the logic state of the output signal is shortened, enabling high-speed operation on the semiconductor device even when the amplitude of the input signal is large.

[0006] Furthermore, the present invention provides a semiconductor storage device having the receiving circuit described above.

[0007] The present invention also provides a control method for a semiconductor memory device, wherein the receiving circuit of the semiconductor memory device includes: an amplifier for amplifying an input signal and configured to operate as a bias voltage based on the voltage of the input signal; and a controller; wherein the control method of the semiconductor memory device executed by the controller includes the step of suppressing the bias voltage from becoming a floating state when the input signal of an amplitude greater than a given value is input to the amplifier.

[0008] According to the receiving circuit, semiconductor memory device, and control method of the semiconductor memory device of the present invention, high-speed operation can be achieved even when the amplitude of the input signal is large. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a receiving circuit according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a voltage generator.

[0011] Figure 3 This is a schematic diagram illustrating the structure of the receiving circuit when the input clock signal and the complementary clock signal are sent to it.

[0012] Figure 4 (a) is a schematic time table showing the time shift of the amplifier output signal associated with the comparative example and the amplifier output signal associated with one embodiment when the input complementary clock signal is used. Figure 4 (b) is a schematic time table showing the time shift of the bias voltage associated with the comparative example and the bias voltage associated with an embodiment when the complementary clock signal is input.

[0013] Symbol explanation: 1: Receiving circuit; 10a, 10b, 10c, 10d: Amplifiers; 11a, 11b, 14a, 14b: Current mirrors; 12a, 12b: Bias transistors; 13a, 13b: Controller; 14: Voltage generator; 15a~15h: Inverter circuit; 16: Adjustment circuit; 16a~16b: Transmission transistors; CK_t: Clock signal; CKOUT_t: Output clock signal; CK_c: Complementary clock signal; CKOUT_c: Outputs complementary clock signals; COM_N, COM_P: Voltage; MN1~MN12: N-type transistors; MP1~MP12: P-type transistors; NBIASA, NBIAS, PBIASA, PBIAS: Bias voltage; NBIASB, PBIASB, VDDQ, VSSQ: Voltage; Vth: Critical voltage; R1~R6: Resistors; V1: Output signal. Detailed Implementation

[0014] Figure 1 This is a schematic block diagram of a receiving circuit structure example related to an embodiment of the present invention. The receiving circuit 1, according to an embodiment of the present invention, is disposed in a semiconductor memory device (e.g., dynamic random access memory) and can receive signals input to the semiconductor memory device from an external device. In this embodiment, the receiving circuit 1 includes amplifiers 10a and 10b; current mirrors 11a and 11b serving as loads for amplifiers 10a and 10b; bias transistors 12a and 12b; controllers 13a and 13b; a voltage generator 14; and multiple inverter circuits 15a to 15h (e.g., ...). Figure 3 (as shown); and adjustment circuit 16 (as shown) Figure 3 (As shown). Furthermore, as... Figure 1 As shown, amplifiers 10a and 10b, current mirrors 11a and 11b, bias transistors 12a and 12b, and controllers 13a and 13b are each constructed using any one of multiple P-type transistors MP1 to MP7 and multiple N-type transistors MN1 to MN7. Furthermore, for the sake of simplicity, other existing configurations of semiconductor memory devices (such as memory cell arrays, power supply circuits, and clock generators) will not be shown here.

[0015] In this embodiment, amplifiers 10a and 10b are differential amplifiers, wherein the input clock signal CK_t is connected to an input terminal, and the complementary clock signal CK_c of the input clock signal CK_t is connected to another input terminal. Therefore, in amplifiers 10a and 10b, common-mode noise can be easily removed by amplifying the difference between the voltage of the clock signal CK_t and the voltage of the complementary clock signal CK_c. Furthermore, amplifiers 10a and 10b amplify the difference between the voltage of the clock signal CK_t and the voltage of the complementary clock signal CK_c, and output this amplified signal as the output signal V1. In other embodiments, amplifiers 10a and 10b may be other types of amplifiers.

[0016] Here, amplifier 10a includes a pair of P-type transistors MP1 and MP2. A complementary clock signal CK_c is input to the gate of P-type transistor MP1, and a clock signal CK_t is input to the gate of P-type transistor MP2. The sources of P-type transistors MP1 and MP2 are connected together. Furthermore, amplifier 10a is an example of the "first differential amplifier" of the present invention.

[0017] Furthermore, amplifier 10b is connected in parallel with amplifier 10a and includes a pair of N-type transistors MN3 and MN4. A complementary clock signal CK_c is input to the gate of N-type transistor MN3, and a clock signal CK_t is input to the gate of N-type transistor MN4. The sources of N-type transistors MN3 and MN4 are connected together. Amplifier 10b is an example of the "second differential amplifier" of this invention.

[0018] The current mirror section 11a includes a pair of N-type transistors MN1 and MN2. The drain of N-type transistor MN1 is connected to the drain of P-type transistor MP1 of amplifier 10a, and the gate of N-type transistor MN1 is connected to the bias voltage PBIAS. Furthermore, the gate of N-type transistor MN1 is connected (diode connected) to the drain of N-type transistor MN1. The drain of N-type transistor MN2 is connected to the drain of P-type transistor MP2 of amplifier 10a and the output signal V1 of amplifiers 10a and 10b, and the gate of N-type transistor MN2 is connected to the bias voltage PBIAS. Furthermore, the sources of N-type transistors MN1 and MN2 are connected together.

[0019] The current mirror section 11b includes a pair of P-type transistors MP3 and MP4. The drain of P-type transistor MP3 is connected to the drain of N-type transistor MN3 of amplifier 10b, and the gate of P-type transistor MP3 is connected to the bias voltage NBIAS. Furthermore, the gate of P-type transistor MP3 is connected (diode connected) to the drain of P-type transistor MP3. The drain of P-type transistor MP4 is connected to the drain of N-type transistor MN4 of amplifier 10b and the output signal V1 of amplifiers 10a and 10b, and the gate of P-type transistor MP4 is connected to the bias voltage NBIAS. Additionally, the sources of P-type transistors MP3 and MP4 are connected together.

[0020] The bias transistor 12a includes a P-type transistor MP5 and is configured to control the bias voltage PBIAS. The source of the P-type transistor MP5 is connected to a high power supply voltage (e.g., input / output voltage VDDQ), and the drain of the P-type transistor MP5 is connected to the source of the P-type transistors MP1 and MP2 of the amplifier 10a. Furthermore, the gate of the P-type transistor MP5 is connected to the bias voltage PBIAS.

[0021] The bias transistor 12b includes an N-type transistor MN5 and is configured to control the bias voltage NBIAS. The source of the N-type transistor MN5 is connected to a low supply voltage (e.g., ground voltage VSSQ), and the drain of the N-type transistor MN5 is connected to the source of the N-type transistors MN3 and MN4 of the amplifier 10b. Furthermore, the gate of the N-type transistor MN5 is connected to the bias voltage NBIAS.

[0022] When an input signal with an amplitude above a given value (in this case, clock signal CK_t and complementary clock signal CK_c) is input to amplifiers 10a and 10b, controllers 13a and 13b suppress the bias voltages PBIAS and NBIAS to float.

[0023] Furthermore, controllers 13a and 13b are configured to operate based on power supply voltages (hereinafter referred to as voltages PBIASB and NBIASB) that are different from the voltages of the input signals (clock signal CK_t and complementary clock signal CK_c). Accordingly, controllers 13a and 13b can operate independently of the input signals, and therefore, using controllers 13a and 13b can appropriately suppress the bias voltages PBIAS and NBIAS from becoming floating.

[0024] Furthermore, the operating current of controllers 13a and 13b can be greater than the minimum operating current of the portions controlled by bias voltages PBIAS and NBIAS (in this embodiment, amplifiers 10a and 10b, current mirrors 11a and 11b, and bias transistors 12a and 12b), and less than the maximum operating current of the portions controlled by bias voltages PBIAS and NBIAS. Accordingly, for example, while suppressing the influence on the operation of amplifiers 10a and 10b, it is possible to suppress bias voltages PBIAS and NBIAS from becoming floating.

[0025] The controller 13a includes P-type transistors MP6 and MP7. The source of P-type transistor MP6 is connected to a high power supply voltage (VDDQ), and the drain of P-type transistor MP6 is connected to the diode connection side of the current mirror 11a and the gate of the bias transistor 12a (i.e., connected to the bias voltage PBIAS). Furthermore, the gate of P-type transistor MP6 is connected to the voltage PBIASB generated by the voltage generator 14. Additionally, P-type transistor MP6 is an example of the "first transistor" of this invention.

[0026] The source of the P-type transistor MP7 is connected to voltage VDDQ, and the drain of the P-type transistor MP7 is connected to the output signal V1 of amplifiers 10a and 10b. Furthermore, the gate of the P-type transistor MP7 is connected to voltage PBIASB generated by voltage generator 14. Additionally, the P-type transistor MP7 is an example of the "second transistor" of this invention.

[0027] The controller 13b includes N-type transistors MN6 and MN7. The source of N-type transistor MN6 is connected to a low power supply voltage (voltage VSSQ), and the drain of N-type transistor MN6 is connected to the diode connection side of the current mirror 11b and the gate of the bias transistor 12b (i.e., connected to the bias voltage NBIAS). Furthermore, the gate of N-type transistor MN6 is connected to the voltage NBIASb generated by the voltage generator 14. Additionally, N-type transistor MN6 is an example of the "first transistor" of this invention.

[0028] The source of N-type transistor MN7 is connected to a low supply voltage (voltage VSSQ), and the drain of N-type transistor MN7 is connected to the output signal V1 of amplifiers 10a and 10b. Furthermore, the gate of N-type transistor MN7 is connected to the voltage NBIASB generated by voltage generator 14. Additionally, N-type transistor MN7 is an example of the "second transistor" of this invention.

[0029] Reference Figure 2 The configuration of voltage generator 14 in this embodiment is explained. Voltage generator 14 is configured to generate power supply voltages (PBIASB, NBIASB) that are different from the voltages of the input signals (clock signal CK_t and complementary clock signal CK_c). For example... Figure 2 As shown, the voltage generator 14 includes multiple (e.g., four) resistors R1 to R4, multiple P-type transistors MP8 to MP12, and multiple N-type transistors MN8 to MN12.

[0030] Here, the voltage generator 14 may also include at least one current mirror 14a, 14b. Therefore, the output current of the voltage generator 14 can be kept constant.

[0031] Multiple resistors R1 to R4 are connected in series between the high power supply voltage (VDDQ) and the low power supply voltage (VSSQ).

[0032] The gate of P-type transistor MP8 is connected to the node between resistors R1 and R2, and the drain of P-type transistor MP8 is connected to the current mirror 14a. Furthermore, the source of P-type transistor MP9 is connected to a high supply voltage (VDDQ), and the drain of P-type transistor MP9 is connected to the source of P-type transistor MP8. Even further, the gate of P-type transistor MP9 is connected to a bias voltage PBIASA.

[0033] The current mirror section 14a includes a pair of N-type transistors MN8 and MN9. The drain of N-type transistor MN8 is connected to the drain of P-type transistor MP8. Furthermore, the gate of N-type transistor MN8 is connected to the bias voltage PBIASA and is connected (diode-connected) to the drain of N-type transistor MN8. The drain of N-type transistor MN9 is connected to the drain of P-type transistor MP10, and the gate of N-type transistor MN9 is connected to the bias voltage PBIASA. Additionally, the sources of N-type transistors MN8 and MN9 are connected to a low power supply voltage (VSSQ).

[0034] The source of the P-type transistor MP10 is connected to a high supply voltage (VDDQ), and the gate of the P-type transistor MP10 is connected to the output voltage (PBIASB) of the voltage generator 14. Furthermore, the gate of the P-type transistor MP10 is connected (diode connected) to the drain of the P-type transistor MP10.

[0035] The gate of N-type transistor MN10 is connected to the node between resistors R3 and R4, and the drain of N-type transistor MN10 is connected to the current mirror 14b. Furthermore, the source of N-type transistor MN11 is connected to a low supply voltage (voltage VSSQ), and the drain of N-type transistor MN11 is connected to the source of N-type transistor MN10. Further still, the gate of N-type transistor MN11 is connected to the bias voltage NBIASA.

[0036] The current mirror section 14b includes a pair of P-type transistors MP11 and MP12. The drain of P-type transistor MP11 is connected to the drain of N-type transistor MN10. Furthermore, the gate of P-type transistor MP11 is connected to the bias voltage NBIASA and is connected (diode-connected) to the drain of P-type transistor MP11. The drain of P-type transistor MP12 is connected to the drain of N-type transistor MN12, and the gate of P-type transistor MP12 is connected to the bias voltage NBIASA. Additionally, the sources of P-type transistors MP11 and MP12 are connected to a high power supply voltage (VDDQ).

[0037] The source of N-type transistor MN12 is connected to a low supply voltage (VSSQ), and the gate of N-type transistor MN12 is connected to the output voltage (NBIASB) of voltage generator 14. Furthermore, the gate of N-type transistor MN12 is connected (diode connected) to the drain of N-type transistor MN12.

[0038] The voltage generator 14, as described above, generates a bias voltage PBIASA based on the voltage at the node between resistors R1 and R2. The bias voltage PBIASA is then converted to voltage PBIASB by the current mirror 14a. Here, as will be described later, when the voltage of the complementary clock signal CK_c reaches voltage VDDQ, since the P-type transistor MP1 of amplifier 10a is in the Off state, in order to suppress the bias voltage PBIAS from becoming floating, the voltage at the node between resistors R1 and R2 used to generate the bias voltage PBIASA can also be set to a given value (e.g., a value higher than VDDQ / 2, such as 0.51×VDDQ).

[0039] Similarly, when the voltage of the complementary clock signal CK_c reaches the voltage VSSQ, since the N-type transistor MN3 of amplifier 10b is in the Off state, in order to suppress the bias voltage NBIAS from becoming floating, the voltage at the node between resistors R3 and R4 used to generate the bias voltage NBIASA can also be set to a given value (e.g., a value lower than VDDQ / 2, such as 0.49×VDDQ).

[0040] Furthermore, to ensure the normal operation of amplifiers 10a and 10b, the output current of current mirrors 14a and 14b (i.e., the operating current of controllers 13a and 13b) can be set to be less than the maximum value of the operating current of the portion controlled by bias voltages PBIAS and NBIAS (in this embodiment, amplifiers 10a and 10b, current mirrors 11a and 11b, and bias transistors 12a and 12b) (e.g., the output current value of amplifiers 10a and 10b). Additionally, as described later, to suppress the saturation of bias voltage PBIAS to voltage COM_N and bias voltage NBIAS to voltage COM_P due to leakage current, the output current of current mirrors 14a and 14b (i.e., the operating current of controllers 13a and 13b) can also be set to be greater than the minimum value of the operating current of the portion controlled by bias voltages PBIAS and NBIAS (e.g., the leakage current value of current mirrors 11a and 11b). Alternatively, the output current of the current mirrors 14a and 14b can be set by arbitrarily setting the current mirror ratio of the current mirrors 14a and 14b.

[0041] Furthermore, voltage generator 14 can also be configured to generate voltages PBIASB and NBIASB within a given period. Therefore, compared to the case where voltages PBIASB and NBIASB are generated frequently, the power consumption of receiving circuit 1 can be reduced. For example, voltage generator 14 can also generate voltages PBIASB and NBIASB within a given period after the power-on sequence of the semiconductor memory device is completed. Furthermore, voltage generator 14 can also generate voltages PBIASB and NBIASB during a given period when a generation indicator signal (not shown) is valid (assert). Additionally, the generation indicator signal can also be generated by circuits other than receiving circuit 1. Taking DRAM as an example, generating voltages PBIASB and NBIASB during the period when the clock enable (CKE) terminal is valid reduces power consumption during power-down. Furthermore, by setting the aforementioned given period as the recovery time from power-down, since the desired PBIASB and NBIASB are generated after the power-down period ends, more accurate input can be received.

[0042] Figure 3 This is an example of the configuration when the input clock signal CK_t and the complementary clock signal CK_c are sent to receiver circuit 1. Here, Figure 3 Only amplifiers 10c and 10d are shown in a simplified form, and amplifiers 10c and 10d each have the same configuration as amplifiers 10a and 10b. Furthermore, for simplicity... Figure 3 The middle part is omitted Figure 1 Other components connected to amplifiers 10c and 10d include current mirrors 11a and 11b, bias transistors 12a and 12b, controllers 13a and 13b, and voltage generator 14.

[0043] A clock signal CK_t is input to one input terminal (+) of amplifier 10c, and a complementary clock signal CK_c is input to the other input terminal (-). Additionally, a complementary clock signal CK_c is input to one input terminal (+) of amplifier 10d, and a clock signal CK_t is input to the other input terminal (-). Amplifier 10c is an example of the "third differential amplifier" of this invention, and amplifier 10d is an example of the "fourth differential amplifier" of this invention.

[0044] Multiple (four in this example) inverter circuits 15a-15d are connected in series to the output terminals of amplifier 10c. Inverter circuit 15a receives the output signal V1 from amplifier 10c. Furthermore, receiving circuit 1 includes a resistor R5 connected in parallel with inverter circuit 15a, with one end of resistor R5 connected to the output of inverter circuit 15a and the other end connected to the input of inverter circuit 15a. Therefore, the output signal of inverter circuit 15a can be added as a feedback signal to the output signal V1 of amplifier 10c. Additionally, by configuring inverter circuits 15b-15d, the amplitude of the output waveform can be shaped to a given level (e.g., VDDQ / VSSQ). Here, inverter circuit 15a is one example of the "logic inversion circuit" of the present invention, while the other inverter circuits 15b, 15c, and 15d are examples of "one or more other logic inversion circuits" of the present invention.

[0045] Furthermore, multiple (four in this example) inverter circuits 15e-15h are connected in series to the output terminal of amplifier 10d. Inverter circuit 15e receives the output signal V1 of amplifier 10d. Additionally, receiving circuit 1 includes a resistor R6 connected in parallel with inverter circuit 15e, one end of which is connected to the output of inverter circuit 15e, and the other end to the input of inverter circuit 15e. Therefore, the output signal of inverter circuit 15e can be added as a feedback signal to the output signal V1 of amplifier 10d. Furthermore, by setting inverter circuits 15f-15h, the amplitude of the output waveform can be shaped to a given level (e.g., VDDQ / VSSQ, etc.). Here, inverter circuit 15e is one example of the "logic inversion circuit" of the present invention, while the other inverter circuits 15f, 15g, and 15h are examples of "one or more other logic inversion circuits" of the present invention.

[0046] The adjustment circuit 16 is configured to suppress the error at each output time point of the output signal V1 of amplifiers 10c and 10d. Therefore, the output time points of the output clock signal CKOUT_t and the output complementary clock signal CKOUT_c from the receiving circuit 1 can be made consistent.

[0047] The regulating circuit 16 includes multiple (two in this example) transfer transistors 16a and 16b. Transfer transistor 16a is connected between the node between inverter circuits 15b and 15c, and between inverter circuits 15g and 15h. Furthermore, transfer transistor 16b is connected between the node between inverter circuits 15c and 15d, and between inverter circuits 15f and 15g.

[0048] Because of the adjustment circuit 16 configured as described above, the output timing of the output clock signal CKOUT_t and the output complementary clock signal CKOUT_c from the receiving circuit 1 can be made to be consistent.

[0049] Reference Figure 4 This section explains the operation of the receiving circuit 1 in this embodiment. Figure 4 (a) is a schematic time table showing the time shift of the output signals V1 of amplifiers 10a and 10b in the comparative example and the output signals V1 of amplifiers 10a and 10b in this embodiment when the complementary clock signal CK_c is input. Figure 4 Table (b) shows a schematic time-shifting time table of the bias voltages PBIAS and NBIAS related to the comparative example and the bias voltages PBIAS and NBIAS related to this embodiment when the complementary clock signal CK_c is input. Furthermore, it will be assumed here that... Figure 1 The receiving circuit shown in the example does not include the controllers 13a and 13b and the voltage generator 14. The receiving circuit is described as a comparative example.

[0050] In the comparative example receiving circuit, when the amplitude of the complementary clock signal CK_c is small (specifically, when the amplitude is between voltage VSSQ+Vth and voltage VDDQ-Vth, where Vth represents the threshold voltage of each transistor MP1, MP2, MN3, MN4 of each amplifier 10a, 10b), since each transistor MP1, MP2, MP3, MN4 of each amplifier 10a, 10b that receives the complementary clock signal CK_c and its inverted clock signal CK_t is not fully turned on or off, bias voltages PBIAS and NBIAS can be stably generated, and each amplifier 10a, 10b can generate an output signal V1 with a small amplitude.

[0051] Here, when the amplitude of the complementary clock signal CK_c increases (for example, when the voltage of the complementary clock signal CK_c reaches a certain value), the amplitude of the complementary clock signal CK_c increases. Figure 4 In the voltage VSSQ shown on the right side of (a), the N-type transistor MN3 of amplifier 10b, which receives the complementary clock signal CK_c, is turned off. In this case, the bias voltage NBIAS becomes floating and is difficult to control the bias voltage NBIAS by the voltage COM_P on the source side of each P-type transistor MP3, MP4 from the current mirror 11b through the voltage drop of P-type transistor MP3. Therefore, as Figure 4As shown on the right side of (b), it can be assumed that due to the leakage current of the P-type transistor MP4, the bias voltage NBIAS gradually rises towards the voltage COM_P. Furthermore, in this case, since the clock signal CK_t has reached the voltage VDDQ, it can be assumed that the pull-down function of the output signal V1 in the N-type transistor MN4 of amplifier 10b will operate more strongly than assumed.

[0052] Furthermore, when the clock signal CK_t reaches voltage VDDQ, the P-type transistor MP2 of amplifier 10a turns off, and the pull-up function of the output signal V1 stops. Because the pull-down function of the output signal V1 in amplifier 10b operates more strongly, the amplitude of the output signal V1 increases. Furthermore, as... Figure 4 As shown on the left side of (a), when the voltage of the complementary clock signal CK_c reaches the voltage VDDQ, the pull-down function of the output signal V1 in amplifier 10a stops, and the pull-up function of the output signal V1 in amplifier 10b operates more strongly, thus increasing the amplitude of the output signal V1. Therefore, since the time required to invert the logic state of the output signal V1 increases, the operating speed of the semiconductor memory device may be reduced.

[0053] On the other hand, in the receiving circuit 1 related to this embodiment, the problems in the comparative example described above can be solved by including controllers 13a and 13b and voltage generator 14. For example, when the voltage of the complementary clock signal CK_c reaches voltage VSSQ, the N-type transistor MN3 of the amplifier 10b receiving the complementary clock signal CK_c is turned off, but since the N-type transistor MN6 of the controller 13b provides current to lower the bias voltage NBIAS, the rise of the bias voltage NBIAS to voltage COM_P can be suppressed. Furthermore, in this case, when the clock signal CK_t reaches voltage VDDQ, the P-type transistor MP2 of the amplifier 10a is turned off, but since the P-type transistor MP6 of the controller 13a provides current to raise the bias voltage PBIAS, the fall of the bias voltage PBIAS to voltage COM_N can be suppressed.

[0054] Therefore, as Figure 4 As shown in (b), the receiving circuit 1 of this embodiment can suppress variations in bias voltages PBIAS and NBIAS compared to the receiving circuit of the comparative example. Furthermore, as Figure 4 As shown in (a), fluctuations in the output signal V1 can be suppressed. Therefore, the receiving circuit 1 of this embodiment can shorten the time required for the logic state of the inverted output signal V1, thus enabling high-speed operation of the semiconductor memory device even when the amplitude of the input signals (clock signal CK_t, complementary clock signal CK_c) is large.

[0055] As described above, according to the receiving circuit 1, semiconductor memory device, and control method of this embodiment, when an input signal (clock signal CK_t, complementary clock signal CK_c) with an amplitude greater than a given value is input to amplifiers 10a and 10b, since the suppression bias voltages PBIAS and NBIAS become floating, the pull-up / pull-down processing of the output signal V1 of amplifiers 10a and 10b can be appropriately executed, suppressing the amplitude of the output signal V1 within the desired range. Therefore, since the time required to invert the logic state of the output signal V1 can be shortened, high-speed operation of the semiconductor memory device can be achieved even when the amplitude of the input signal (clock signal CK_t, complementary clock signal CK_c) is large.

[0056] Furthermore, the above embodiments are provided for ease of understanding of the invention and are not intended to limit the invention. Therefore, each element disclosed in each of the above embodiments is intended to encompass all design variations or equivalents falling within the technical field of this invention.

[0057] For example, in the above embodiment, the case where the input clock signal CK_t and the complementary clock signal CK_c are input to amplifiers 10a and 10b is illustrated as an example, but the present invention is not limited to this case. For example, the input signal may also be a command signal, an address signal, etc. Furthermore, when the command signal, address signal, etc., are input to one input terminal of amplifiers 10a and 10b, a given reference signal may also be input to the other input terminal of amplifiers 10a and 10b. Here, taking the case where the semiconductor memory device conforms to the DDR4 SDRAM specification as an example, the voltage (e.g., VREF) of the given reference signal may also be half of the voltage VDDQ (i.e., VDDQ / 2). In this case, similar to the above embodiment, even when the amplitude of the input signal (command signal, address signal, etc.) is large, high-speed operation of the semiconductor memory device can be achieved.

[0058] Furthermore, in the above embodiments, the case of the semiconductor memory device being DRAM is described as an example, but the present invention is not limited to this case. For example, the semiconductor memory device may be static random access memory, virtual static random access memory, flash memory, or other semiconductor memory devices.

[0059] also, Figure 1 The amplifiers 10a and 10b, the current mirrors 11a and 11b, the bias transistors 12a and 12b, and the controllers 13a and 13b are shown. Figure 2 The voltage generator 14 shown; and Figure 3 Each of the adjustment circuits 16 shown is an example, but can be modified as appropriate, and can also adopt known configurations or other various structures.

Claims

1. A receiving circuit, characterized in that, include: An amplifier that amplifies an input signal and is configured to operate as a bias voltage based on the voltage of the input signal; as well as A controller that suppresses the bias voltage from becoming floating when the input signal of an amplitude greater than a given value is input to the amplifier.

2. The receiving circuit according to claim 1, characterized in that, The controller operates based on a power supply voltage that is different from the voltage of the input signal.

3. The receiving circuit according to claim 2, characterized in that, The operating current of the controller is greater than the minimum operating current of the portion controlled by the bias voltage, and less than the maximum operating current of the portion controlled by the bias voltage.

4. The receiving circuit according to claim 2, characterized in that, Also includes: A current mirror, wherein the current mirror is the load of the amplifier; as well as A bias transistor that controls the bias voltage; The controller includes: A first transistor having a gate connected to the power supply voltage, wherein the first transistor is connected to the diode connection side of the current mirror and a gate of the bias transistor.

5. The receiving circuit according to claim 4, characterized in that, The controller includes a second transistor having a gate connected to the power supply voltage, wherein the second transistor is connected to the output voltage of the amplifier.

6. The receiving circuit according to claim 2, characterized in that, It also includes a voltage generator for generating the power supply voltage.

7. The receiving circuit according to claim 6, characterized in that, The voltage generator also includes at least one current mirror.

8. The receiving circuit according to claim 6, characterized in that, The voltage generator is used to generate the power supply voltage within a given period.

9. The receiving circuit according to claim 1, characterized in that, Also includes: A logic inverting circuit, wherein the input of the logic inverting circuit comes from an output signal of the amplifier; as well as A resistor is connected in parallel with the logic inversion circuit.

10. The receiving circuit according to claim 9, characterized in that, It also includes at least one other logic inversion circuit connected in series with the output of the logic inversion circuit.

11. The receiving circuit according to claim 1, characterized in that, The amplifier includes at least one differential amplifier.

12. The receiving circuit according to claim 11, characterized in that, The amplifier includes: A first differential amplifier, the first differential amplifier including a pair of first type transistors; and A second differential amplifier, the second differential amplifier including a pair of second type transistors, the second type transistors being different from the first type transistors; The first differential amplifier and the second differential amplifier are connected in parallel.

13. The receiving circuit according to claim 11, characterized in that, The input of the differential amplifier comes from the input signal and the complementary signal of the input signal.

14. The receiving circuit according to claim 13, characterized in that, The amplifier includes: A third differential amplifier, wherein the input signal is input to one input terminal of the third differential amplifier, and a complementary signal of the input signal is input to another input terminal of the third differential amplifier; and A fourth differential amplifier, wherein the complementary signal of the input signal is input to one input terminal of the fourth differential amplifier, and the input signal is input to the other input terminal of the fourth differential amplifier.

15. The receiving circuit according to claim 14, characterized in that, It also includes an adjustment circuit for controlling the error of each output signal from the third differential amplifier and the fourth differential amplifier at the output time point.

16. A semiconductor memory device, characterized in that, Includes the receiving circuit as described in any one of claims 1 to 15.

17. The semiconductor memory device according to claim 16, characterized in that, The input signal is any one of a command signal, an address signal, and a clock signal input to the semiconductor memory device.

18. A control method for a semiconductor memory device, characterized in that, The receiving circuit of the semiconductor memory device includes: An amplifier for amplifying an input signal and configured to operate based on a bias voltage based on the voltage of the input signal; as well as One controller; The control method for the semiconductor memory device executed by the controller includes: The step of suppressing the bias voltage from becoming floating when the input signal of an amplitude greater than a given value is input to the amplifier.

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