Memory and electronic device

Abstract

The present disclosure relates to the technical field of memory, and provides a memory and an electronic device. The memory comprises: a memory cell array, a timing control circuit, and a data transmission line electrically connected to the memory cell array; the timing control circuit is configured to monitor a working environment parameter of the memory cell array in real time, and output a column selection signal with a pulse width corresponding to the working environment parameter, so that a voltage of the data transmission line is offset to different target voltages in time periods corresponding to different pulse widths; wherein the column selection signal is configured to turn on a column selection transistor connected to the data transmission line.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more particularly to a memory and electronic device. Background Technology

[0002] In memory, the voltage of the global data line (such as the segmented voltage of the global data line, or the control voltage that offsets the voltage of the data transmission line to the target voltage) is typically used to pre-bias the data transmission lines to make data transmission between the memory cell array and the external read / write path more stable and efficient. Because the conduction capability and timing characteristics of memory devices change under different process corners, temperatures, and voltage conditions, the appropriate target voltage required for the data transmission lines will also change accordingly. Improperly setting the voltage of the global data line can easily lead to a decrease in read / write margin, deterioration of access performance, or reduction in data integrity. Summary of the Invention

[0003] This disclosure provides a memory and an electronic device.

[0004] In a first aspect, embodiments of this disclosure provide a memory, including: a memory cell array, a timing control circuit, and a data transmission line electrically connected to the memory cell array; The timing control circuit is used to monitor the operating environment parameters of the memory cell array in real time and output a column selection signal with a pulse width corresponding to the operating environment parameters, so that the voltage of the data transmission line shifts to different target voltages in different time periods corresponding to the pulse width; wherein, the column selection signal is used to turn on the column selection transistor connected to the data transmission line.

[0005] In some embodiments, the memory includes at least two states during the operating phase. In a first state, the memory cell array is under a first operating environment parameter, and the timing control circuit outputs the column selection signal with a first pulse width. In a second state, the memory cell array is under a second operating environment parameter, and the timing control circuit outputs the column selection signal with a second pulse width. The first pulse width is different from the second pulse width, and the operating environment parameter includes at least: process angle, temperature, and voltage.

[0006] In some embodiments, the timing control circuit includes: A real-time monitoring circuit is configured to monitor the operating environment parameters of the storage cell array in real time during the working phase and output the current operating environment parameters. The encoding selection circuit, connected to the real-time monitoring circuit, is configured to logically encode the received current working environment parameters, select the column selection signal corresponding to different pulse widths according to the logical encoding result, and output the selected column selection signal.

[0007] In some embodiments, the encoding selection circuit includes an encoder electrically connected to the output of the real-time monitoring circuit, the encoder being used to logically encode the current working environment parameters and output the logical encoding result; A configuration parameter generation circuit is electrically connected to the encoder and receives the logic encoding result as a selection signal. The configuration parameter generation circuit has a variety of preset configuration parameters stored in advance. Under the indication of the selection signal, a target configuration parameter is selected from the variety of preset configuration parameters. The preset configuration parameters are used to indicate the generation of column selection signals with different pulse widths.

[0008] In some embodiments, the real-time monitoring circuit includes: a signal generation circuit and a detection circuit; The signal generating circuit is used to generate an oscillating signal that characterizes the offset of the operating environment parameters of the memory cell array; The detection circuit is electrically connected to the signal generation circuit. The detection circuit is used to receive the oscillation signal, count the number of oscillations of the oscillation signal within a preset time period, generate a count code, and generate the corresponding working environment parameters according to the numerical range of the count code.

[0009] In some embodiments, the detection circuit includes a counter and a comparison circuit; The counter is electrically connected to the signal generating circuit and is used to count the number of oscillations of the oscillation signal to obtain the count code; The comparison circuit is connected to the counter and is used to determine the numerical range of the counter code and generate the operating environment parameters corresponding to the numerical range.

[0010] In some embodiments, the comparison circuit includes: a plurality of first comparators connected in parallel, each of the first comparators being configured with a set numerical threshold. The plurality of first comparators are connected to the counter, and each first comparator is used to compare the counter code with the set numerical threshold and output a first comparison result; the first comparison result is used to characterize the current working environment parameters.

[0011] In some embodiments, the number of preset configuration parameters is greater than or equal to the number of the first comparators.

[0012] In some embodiments, the comparison circuit includes: a linearization conversion circuit and a plurality of second comparators connected in parallel, each of the second comparators being configured with a set slope threshold. The linearization conversion circuit is connected to the counter. The linearization conversion circuit is used to calculate the difference between the counter code and the preset reference counter code, and convert the difference, which represents the frequency domain deviation, into a target slope, which represents the time domain deviation. The second comparator is used to compare the target slope with the set slope threshold to obtain a second comparison result, so as to determine the slope interval in which the target slope is located, and generate the working environment parameters corresponding to the slope interval.

[0013] In some embodiments, the linearization conversion circuit includes a subtractor and a divider connected in sequence; The subtractor is used to calculate the difference between the counter code and the reference counter code; The divider is used to calculate the ratio between the preset working environment parameter difference constant and the difference value to obtain the target slope.

[0014] In some embodiments, the signal generating circuit includes: a ring oscillator and a frequency divider; The ring oscillator is used to generate the oscillation signal; The frequency divider is connected to the ring oscillator and is used to perform frequency division processing on the received oscillation signal and output a down-frequency oscillation signal.

[0015] In some embodiments, the encoding selection circuit further includes: a column selection signal generation circuit; The column selection signal generation circuit is connected to the configuration parameter generation circuit and is used to perform digital-to-analog conversion on the target configuration parameters to obtain the column selection signal with a pulse width corresponding to the working environment parameters.

[0016] In some embodiments, the column selection signal generation circuit includes a delay circuit for determining the pulse width of the column selection signal based on the effective number of bits in the target configuration parameters, and generating the column selection signal having the pulse width.

[0017] In some embodiments, the configuration parameter generation circuit includes: a multiple input selector; Each input terminal of the multi-input selector is used to receive corresponding preset configuration parameters; The selection terminal of the multi-input selector receives the selection signal; The output of the multi-input selector outputs the preset configuration parameters corresponding to the working environment parameters as the target configuration parameters.

[0018] In some embodiments, the timing control circuit includes: A real-time monitoring circuit is configured to monitor the operating environment parameters of the storage cell array in real time during the working phase and output the current operating environment parameters. A pulse width adjustment circuit is provided; the pulse width adjustment circuit is connected to the real-time monitoring circuit, and the pulse width adjustment circuit is used to receive the working environment parameters, and select the column selection signal with a pulse width corresponding to the working environment parameters from column selection signals with different pulse widths according to the working environment parameters, so as to output the column selection signal with a pulse width corresponding to the working environment parameters.

[0019] In a second aspect, embodiments of this disclosure provide an electronic device that includes a memory as described in the first aspect.

[0020] This disclosure provides a memory and electronic device capable of real-time monitoring of operating environment parameters and outputting a column select signal with a pulse width corresponding to the operating environment parameters. This allows the column select transistor connected to the data transmission line to have different conduction durations under different operating environments, thereby enabling the voltage of the data transmission line to shift to different target voltages within corresponding time periods. Therefore, this disclosure can dynamically adjust the target low voltage of the data transmission line according to changes in process angle, temperature, voltage, etc., improving the timing accuracy of adjusting to the target voltage. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the memory provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the circuit structure of a timing control circuit provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the circuit structure of the encoding selection circuit provided in the embodiments of this disclosure; Figure 4 This is a schematic diagram of the circuit structure of the real-time monitoring circuit provided in the embodiments of this disclosure; Figure 5 This is a graph provided in this disclosure that shows the relationship between working environment parameters and optimal configuration parameters; Figure 6 This is a schematic diagram of the circuit structure of another timing control circuit provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the circuit structure of another comparison circuit provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the circuit structure of the signal generation circuit provided in the embodiments of this disclosure. Detailed Implementation

[0022] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0024] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0026] In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments, and therefore the illustrations are not necessarily drawn to scale.

[0027] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, the technical terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0028] In this disclosure, "electrical connection" or "electrical connection" refers to the ability of corresponding modules to transmit information via electrical signals. In specific implementations, "electrical connection" can be a direct connection between corresponding modules via wires, or an indirect connection between corresponding modules via other circuit structures.

[0029] To ensure the speed, stability, and data integrity of data read / write processes in memory, it is typically necessary to control the segmented voltages of global data lines. Taking Dynamic Random Access Memory (DRAM) as an example, when data in the memory cell array is transmitted to the inductive amplifier and input / output paths via the column select path, the voltage state of the relevant data transmission lines directly affects the charge sharing effect, signal establishment speed, and subsequent read / write decision margin. Therefore, it is usually necessary to pre-adjust the nodes or data transmission lines of the global data lines to a suitable target voltage, i.e., to control the voltage of the data transmission lines through segmented global data line voltage. Since the global data line path is long and the load is large, there may be voltage drops or noise differences between different segments of the global data line. By dividing the global data line into multiple segments and setting an independent reference voltage for each segment, the voltage loss of each segment can be compensated, ensuring the accuracy of signal decision. In this case, the conduction time of the column select transistor connected to the data transmission line is usually controlled by controlling the pulse width of the column select signal (CSL Pulse), thereby changing the charging and discharging process of the data transmission line and shifting it to the expected target voltage. Specifically, during the chip testing or calibration phase, a set of configuration parameters for voltage control, such as trim code, is first determined based on the test results or process information. Then, these configuration parameters are fixed through fuse programming, register configuration, or other static methods. Subsequently, when the memory is working normally, it outputs column selection signals with corresponding pulse widths according to the fixed configuration to control the voltage of the global data lines.

[0030] However, the aforementioned control method is a static configuration. Once the pulse width of the column select signal is pre-programmed through tuning codes or similar parameters, it remains essentially unchanged during actual operation. It is difficult to dynamically adjust it according to the real-time operating environment of the memory cell array. Furthermore, the device characteristics and timing behavior of the memory drift with changes in process corners, temperature, and supply voltage. This directly leads to inconsistent data transmission line voltage offsets for the same fixed pulse width under different environments. In other words, a fixed pulse width control scheme for the global data line voltage can cause a mismatch between the target voltage and the actual operating environment. For example, the data transmission line may not be sufficiently offset to the required voltage, resulting in reduced read / write margins, slower signal establishment, and poorer transmission stability. Alternatively, a conservative pulse width setting may cause excessive voltage offset, leading to unnecessary power consumption increases. To ensure chip availability under worst-case conditions, chip calibration typically only allows for a large control margin under the most unfavorable environment, increasing power consumption waste under typical operating conditions and limiting the voltage control accuracy of the global data lines and the overall performance improvement of the memory.

[0031] See Figure 1This illustrates a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Figure 1 As shown, the memory includes a memory cell array 100, a timing control circuit 200, and a data transmission line 300 electrically connected to the memory cell array 100.

[0032] In this embodiment, the memory cell array 100 refers to an array structure formed by arranging multiple memory cells in rows and columns. It can be a DRAM memory cell array 100, a Static Random-Access Memory (SRAM) memory cell array, a NAND (Non-Volatile Flash Memory) memory cell array, or other memory array structures that require column selection control and data transmission line 300 voltage regulation. The memory cell array 100 is affected by factors such as process technology, temperature, and voltage during operation.

[0033] In this embodiment of the disclosure, the data transmission line 300 is used to carry data signal transmission during read operations, write operations, or other data interactions of the storage cell array 100. It should be noted that... Figure 1 The data transmission line 300 shown is schematically drawn in the form of a functional module to illustrate its connection relationship with the timing control circuit 200 and the memory cell array 100. In the actual circuit, the data transmission line 300 can be a single transmission line or a transmission path composed of multiple transmission lines.

[0034] In this embodiment of the disclosure, the column select signal is a control signal used to control the column select transistor to be turned on or off. It is usually a pulse signal, and the duration of its effective level corresponds to its pulse width.

[0035] It should be noted that the column selection transistor is in Figure 1 As not shown in the diagram, when the column select transistor is turned on under the action of the column select signal, the voltage of the data transmission line 300 will shift during the on-time corresponding to the column select signal.

[0036] In some embodiments, the timing control circuit 200 is used to monitor the operating environment parameters of the memory cell array 100 in real time and output a column selection signal with a pulse width corresponding to the operating environment parameters, so that the voltage of the data transmission line 300 is shifted to different target voltages in the time periods corresponding to different pulse widths; wherein, the column selection signal is used to turn on the column selection transistor connected to the data transmission line 300.

[0037] In this embodiment, the timing control circuit 200 can monitor the operating environment parameters of the memory cell array 100 in real time during the memory's operation. Real-time monitoring, unlike the one-time static configuration at the factory, involves continuous monitoring, periodic monitoring, or monitoring updated at preset times during memory operation. After obtaining the current operating environment parameters, the timing control circuit 200 determines the column selection signal corresponding to the current operating environment parameters from a variety of preset pulse widths and outputs this column selection signal to the column selection transistor connected to the data transmission line 300, causing the column selection transistor to conduct for the corresponding duration. Because the pulse widths of the column selection signals differ, the duration of the column selection transistor's effect on the data transmission line 300 also differs, resulting in different degrees of voltage offset on the data transmission line 300 during the time periods corresponding to different pulse widths, ultimately achieving different target voltages. Here, the target voltage is the voltage level more suitable for data transmission, read / write operations, or voltage pre-bias control under the current operating environment, such as the target voltage required by the column selection transistor.

[0038] In some embodiments, during the operating phase, the memory includes at least two states. In a first state, the memory cell array 100 is under a first operating environment parameter, and the timing control circuit 200 outputs a column selection signal with a first pulse width. In a second state, the memory cell array 100 is under a second operating environment parameter, and the timing control circuit 200 outputs a column selection signal with a second pulse width. The first pulse width and the second pulse width are different, and the operating environment parameter includes at least one of the following: process angle, temperature, or voltage. The process angle is a classification method used to characterize the impact of chip manufacturing process variations on the electrical performance of devices. Different process angles reflect the speed characteristics of transistors under variations in process parameters such as threshold voltage, carrier mobility, and gate length deviation. Common process corners include: TT (Typical-Typical), indicating that both NMOS and PMOS devices are at a typical process level; FF (Fast-Fast), indicating that both NMOS and PMOS devices are relatively fast, with strong conduction capability and high speed; SS (Slow-Slow), indicating that both NMOS and PMOS devices are relatively slow, with weak conduction capability and low speed; FS (Fast-Slow) and SF (Slow-Fast), representing mismatches between NMOS and PMOS devices, one fast and one slow. The delay, power consumption, and timing characteristics of circuits differ under different process corners; therefore, the impact of process corners on voltage control and timing adjustment must usually be considered in memory design.

[0039] In this embodiment, the first state and the second state represent the operating states of the memory under different operating environment parameters. For example, in the first state, the memory cell array 100 is under the first operating environment parameters, which can be: process angle TT, operating temperature 25°C, and supply voltage 1.2V; at this time, the timing control circuit 200 outputs a column select signal with a first pulse width. As another example, in the second state, the memory cell array 100 is under the second operating environment parameters, which can be: process angle SS, operating temperature 85°C, and supply voltage 1.0V; at this time, the timing control circuit 200 outputs a column select signal with a second pulse width. Since the device conduction capability decreases relatively under the SS process angle, high temperature, and low voltage conditions, and the voltage establishment speed of the data transmission line 300 slows down, the conduction time of the column select transistor connected to the data transmission line 300 can be extended by increasing the pulse width of the column select signal, so that the voltage of the data transmission line 300 can still be shifted to the target voltage required under the current operating environment. Therefore, the second pulse width can be greater than the first pulse width.

[0040] It should be noted that the working environment parameters of the first state and the second state may differ in only one parameter. For example, the first working environment parameter in the first state may be the process angle TT, and the second working environment parameter in the second state may be the process angle FF, while other parameters may not be considered; or two parameters may be different, or three or more parameters may be different, without specific restrictions here.

[0041] Furthermore, the first and second states can occur in both the read and write phases. For example, during the read phase, when the memory is operating at FF process corner, 0°C, and 1.3V, it is considered to be in another first state. In this state, the device has strong conduction capability, the voltage of the data transmission line 300 is established quickly, and the timing control circuit 200 can output a column selection signal with a relatively short pulse width to reduce power consumption during the voltage offset process of the data transmission line 300 and avoid excessive offset. As another example, during the write phase, when the memory is operating at SS process corner, 85°C, and 1.0V, it is considered to be in another second state. In this state, the device's driving capability decreases, and the timing control circuit 200 can output a column selection signal with a relatively long pulse width to compensate for the decrease in driving capability caused by high temperature and low voltage. It should be noted that the aforementioned TT, FF, and SS process corners and the corresponding temperature and voltage values ​​are only examples to illustrate that the first and second states correspond to different process, temperature, and voltage operating environments. As long as the current operating environment parameters are different, the output column selection signal pulse width will be adjusted accordingly.

[0042] In some embodiments, the timing control circuit 200 includes: The real-time monitoring circuit 210 is configured to monitor the operating environment parameters of the memory cell array 100 in real time during the working phase and output the current operating environment parameters. The encoding selection circuit 220, connected to the real-time monitoring circuit 210, is configured to perform logical encoding on the received current working environment parameters. Different logical encoding results correspond to different pulse widths, and the corresponding column selection signal is selected and output according to the logical encoding result.

[0043] See Figure 2 The diagram shows a schematic of the timing control circuit 200. The real-time monitoring circuit 210 distinguishes different actual operating conditions by detecting operating environment parameters and outputs these parameters to the encoding selection circuit 220. The encoding selection circuit 220 then selects a column selection signal that matches the operating environment parameters from a set of preset column selection signals.

[0044] In some embodiments, the operating environment parameters output by the real-time monitoring circuit 210 may be multi-bit data (usually represented as a counter code) such as the original detection results, frequency information, and voltage information. By logically encoding the current operating environment parameters, continuously changing, wide-ranging, or inconsistent detection results (i.e., the aforementioned multi-bit data) can be converted into encoded results that are easy for subsequent circuits to identify and call, so that different operating environments are classified into a finite number of environmental states and a clear correspondence is established with preset width or configuration parameters.

[0045] In some embodiments, logical encoding can be performed using interval encoding. Specifically, the parameter range of the current working environment parameter can be determined first based on one or more preset thresholds, and then different parameter ranges can be mapped to encoding results such as a first encoded value, a second encoded value, and a third encoded value. In other embodiments, logical encoding can also be performed using lookup table mapping or combined logical mapping. This embodiment does not limit the specific logical encoding method.

[0046] In some embodiments, the encoding selection circuit 220 includes: Encoder 401 is electrically connected to the output terminal of real-time monitoring circuit 210. Encoder 401 is used to logically encode the current working environment parameters and output the logical encoding result. The configuration parameter generation circuit 402 is electrically connected to the encoder 401 and receives the logic encoding result as a selection signal. The configuration parameter generation circuit 402 has a variety of preset configuration parameters stored in it. Under the indication of the selection signal, the target configuration parameter is selected from the variety of preset configuration parameters. The preset configuration parameters are used to indicate the generation of column selection signals with different pulse widths.

[0047] In some embodiments, see Figure 3 The diagram illustrates the structure of the encoding selection circuit 220. The encoder 401 can logically encode operating environment parameters based on preset mapping rules. These preset mapping rules can be established in advance during simulation or test calibration to reflect the differences in control strength required for the data transmission line 300 to reach the target voltage under different operating environments. For example, when the operating environment corresponds to a device with strong driving capability, such as an FF process corner, lower temperature, or higher supply voltage, the encoder 401 can output a first logical encoding result corresponding to a shorter pulse width; when the operating environment corresponds to a device with moderate driving capability, the encoder 401 can output a second logical encoding result corresponding to a medium pulse width; and when the process environment corresponds to a device with weak driving capability, such as an SS process corner, higher temperature, or lower supply voltage, the encoder 401 can output a third logical encoding result corresponding to a longer pulse width. The encoder 401 can convert operating environment parameters into encoding results that can be recognized by the configuration parameter generation circuit, thus providing a basis for subsequent dynamic adjustment of the column selection signal. Different encoding results can represent different operating environment types.

[0048] In some embodiments, see Figure 3 The configuration parameter generation circuit 402 can be a multi-input selector. Various preset configuration parameters can be pre-stored in the configuration parameter generation circuit 402 during the design, testing, or initialization phases. These preset configuration parameters can be pre-stored in register groups, lookup tables, latch units, or programmed into non-volatile memory units. Figure 3 The first configuration parameter, such as TT_Trim_Code0, is shown. <m:0>The second configuration parameter TS_Trim_Code1 <m:0>The third configuration parameter FF_Trim_Code7 <m:0>And the fourth configuration parameter TT_Trim_Code8 <m:0>(The image shows nine configuration parameters set as an example, omitting Trim_Code2) <m:0>Up to Trim_Code6 <m:0>(Not shown), these configuration parameters correspond to different column selection signal pulse width control requirements. After receiving the selection signal output by the encoder 401, the configuration parameter generation circuit 402 can select and output the target configuration parameter that matches the current working environment from the first configuration parameter, the second configuration parameter, and the third configuration parameter according to a one-to-one or many-to-one correspondence.

[0049] In some embodiments, the configuration parameter generation circuit 402 includes: a multiple input selector; Each input of the multi-input selector is used to receive the corresponding preset configuration parameters; The selection terminal of a multi-input selector receives the selection signal; The output of the multi-input selector outputs the preset configuration parameters corresponding to the working environment parameters as the target configuration parameters.

[0050] In some embodiments, taking four types of operating environment parameters as examples, when the real-time monitoring circuit determines that the current storage cell array 100 is in the first type of environment, the encoder 401 outputs a first logical encoding result as a selection signal, and the configuration parameter generation circuit 402 selects the first configuration parameter as the target configuration parameter accordingly. When the real-time monitoring circuit determines that the current storage cell array 100 is in the second type of environment, the encoder 401 outputs a second logical encoding result as a selection signal, and the configuration parameter generation circuit 402 selects the second configuration parameter as the target configuration parameter accordingly. When the real-time monitoring circuit determines that the current storage cell array 100 is in the third type of environment, the encoder 401 outputs a third logical encoding result as a selection signal, and the configuration parameter generation circuit 402 selects the third configuration parameter as the target configuration parameter accordingly. When the real-time monitoring circuit determines that the current storage cell array 100 is in the fourth type of environment, the encoder 401 outputs a fourth logical encoding result as a selection signal, and the configuration parameter generation circuit 402 selects the fourth configuration parameter as the target configuration parameter accordingly.

[0051] It should be noted that, Figure 3 The four preset configuration parameters shown do not constitute a limitation of this disclosure. In other embodiments, the number of preset configuration parameters can be set to two, three, or more. Correspondingly, the logical encoding result output by encoder 401 can also be 1 bit, 2 bits, 3 bits, or more bits. By logically encoding the current working environment parameters and having the configuration parameter generation circuit 402 select the target configuration parameter from a variety of preset configuration parameters based on the encoding result, the embodiments of this disclosure can achieve dynamic selection of the column selection signal pulse width, thereby enabling the voltage of the data transmission line 300 to be more accurately offset to the target voltage under different working environments.

[0052] In some embodiments, the encoding selection circuit 220 further includes: a column selection signal generation circuit 403; The column selection signal generation circuit 403 is electrically connected to the configuration parameter generation circuit 402, and is used to convert the target configuration parameters into a digital-to-analog conversion to obtain a column selection signal with a pulse width corresponding to the working environment parameters.

[0053] In some embodiments, the column selection signal generation circuit 403 can generate a column selection signal with a corresponding pulse width based on the target configuration parameters. The control signal of the column selection transistor typically needs to have a clear start time, end time, effective level duration, and time-domain characteristics matching the memory read / write access timing. However, the target configuration parameters themselves only characterize the pulse width level and lack the attributes required to directly drive the column selection path. Therefore, the target configuration parameters can be converted into an actual column selection signal by the column selection signal generation circuit 403. For example, the target configuration parameters can correspond to different pulse width levels such as the first pulse width, the second pulse width, and the third pulse width. After receiving the target configuration parameters, the column selection signal generation circuit 403 outputs a column selection signal corresponding to the target configuration parameters according to a pre-set mapping relationship, causing the column selection transistor to conduct within the corresponding duration. The column selection signal output from the subsequent stage then acts on the column selection path via the read / write conversion circuit 230 to control the voltage of the data transmission line 300 to shift to the desired target voltage within a set time period (so that the voltage of the data transmission line follows the specified path). Figure 3 (The first voltage, second voltage, or third voltage in the process is varied). The read / write conversion circuit 230 refers to the circuit at one end of the global data line, which is connected to the data transmission line. This embodiment of the present disclosure, by setting an independent generation stage between the target configuration parameters and the column selection signal, not only ensures that the column selection signal is aligned with the read / write access timing, but also shapes, buffers, and adjusts the width of the output waveform, thereby improving the stability and flexibility of the column selection voltage control.

[0054] In some embodiments, the column select signal generation circuit 403 includes a delay circuit for determining the pulse width of the column select signal based on the number of effective bits in the target configuration parameters, and generating a column select signal with the pulse width.

[0055] In some embodiments, the delay circuit can be a numerically controlled delay circuit. For example, the column selection signal generation circuit 403 can determine the time interval between the start and end edges of the pulse based on the effective number of bits, the code value, or the gear number in the target configuration parameters, thereby generating a column selection signal with a corresponding pulse width. Such as the target configuration signal Trim_Code. <m:0>The signal is m+1 bits, where the high level is bit a and the low level is bit b, where a≤m+1, b≤m+1, a+b=m+1, and a, b, and m are all positive integers. The column selection signal generation circuit 403 can generate a column selection signal with a corresponding pulse width based on the number of bits of the high level.

[0056] In some embodiments, the real-time monitoring circuit 210 includes: a signal generation circuit 211 and a detection circuit; Signal generation circuit 211 is used to generate an oscillating signal characterizing the offset of the operating environment parameters of the memory cell array 100; The detection circuit is electrically connected to the signal generation circuit 211. The detection circuit is used to receive the oscillation signal, count the number of oscillations of the oscillation signal within a preset time period, generate a count code, and generate corresponding working environment parameters according to the numerical range of the count code.

[0057] In some embodiments, the offset of operating environment parameters characterizes the shift in circuit speed, delay characteristics, or conduction capability exhibited after changes in the process corner, temperature, and / or supply voltage of the current memory cell array 100 relative to reference operating conditions. Since the oscillation frequency or oscillation period of the oscillation signal typically varies with device process, temperature, and supply voltage, this oscillation signal can be used to characterize the current operating environment. That is, the oscillation signal generated by the signal generation circuit 211 is not only used to provide a clock but also serves as a detection signal reflecting the changing trend of the current operating environment of the memory cell array 100. For example, under FF process corner, lower temperature, or higher supply voltage conditions, the device switching speed is faster, and the oscillation frequency is typically relatively high; while under SS process corner, higher temperature, or lower supply voltage conditions, the device switching speed is slower, and the oscillation frequency is typically relatively low. Therefore, the state of the current operating environment parameters can be concisely reflected by detecting the number of oscillations of the oscillation signal within a preset time.

[0058] Furthermore, the signal generation circuit 211 can operate under the control of a start signal and an end signal. That is, the start signal is used to indicate the start of a detection process, and the end signal is used to indicate the end of the current detection process. During a preset time between the start signal and the end signal, the signal generation circuit 211 continuously outputs an oscillation signal for the detection circuit to count.

[0059] In some embodiments, see Figure 4 The diagram illustrates the structure of the real-time monitoring circuit 210. The input of the detection circuit is connected to the output of the signal generation circuit 211. Here, the counting code can be a multi-bit binary code representing the number of oscillations, a hexadecimal code, or other digital signals capable of representing the magnitude of the number of oscillations. Specifically, when the start signal arrives, the detection circuit begins counting the effective edges of the oscillation signal; when the end signal arrives, it stops counting and latches the counting result as the current counting code. Since the preset time period is pre-set, the more times counted within that preset time period, the higher the oscillation frequency, indicating that the current working environment is more inclined towards a faster device speed; conversely, fewer counts indicate that the current working environment is more inclined towards a slower device speed. Through the detection circuit, the analog frequency change can be converted into a digital counting code, facilitating subsequent circuitry for interval judgment, working environment classification, and logic control.

[0060] In some embodiments, the detection circuit includes a counter 214 and a comparator circuit 213; The counter 214 is electrically connected to the signal generation circuit 211 and is used to count the number of oscillations of the oscillation signal to obtain a counting code; The comparator circuit 213 is connected to the counter 214 to determine the numerical range of the counter code and generate the corresponding operating environment parameters for the numerical range.

[0061] In some embodiments, counter 214 can count the rising edge, falling edge, or a specified valid edge of the oscillation signal. Before the start of a detection cycle, counter 214 can be reset to its initial value, such as an all-zero state; at the end of the detection cycle, counter 214 can latch the currently accumulated count result for subsequent comparison circuit 213 to judge. In embodiments of this disclosure, the count code output by counter 214 can be a binary code, such as the count code Process_code. <n:0>, is a counting code of length n+1 bits.

[0062] In some embodiments, see Figure 4 The comparator is used to determine the environmental category of the current working environment parameters based on the counter code. Specifically, multiple numerical thresholds can be preset, and these thresholds are used to divide the range of counter code values ​​into multiple numerical intervals. The comparator circuit 213 generates the working environment parameters corresponding to the numerical interval by determining which numerical interval the current counter code falls into. For example, a first value, a second value, a third value, and a fourth value can be set to divide the counter code into five intervals: less than the first value, greater than or equal to the first value and less than the second value, greater than or equal to the second value and less than the third value, greater than or equal to the third value and less than the fourth value, and greater than or equal to the fourth value. After determining the interval in which the counter code is located (i.e., obtaining the number of times it is greater than the preset value), the comparator circuit 213 outputs the first working environment parameter, the second working environment parameter, the third working environment parameter, the fourth working environment parameter, or the fifth working environment parameter, respectively.

[0063] In some embodiments, the operating environment output by the comparator circuit 213 can correspond to multiple physical quantities, such as the classification result after considering the combined effects of process corner, temperature, and voltage. For example, when the count code is large, it can be considered that the device corresponding to the current memory cell array 100 is faster, possibly under one or more combinations of FF process corner, lower temperature, or higher voltage; in this case, the comparator circuit 213 can output operating environment parameters corresponding to the faster environment. When the count code is small, it can be considered that the device corresponding to the current memory cell array 100 is slower, possibly under one or more combinations of SS process corner, higher temperature, or lower voltage; in this case, the comparator circuit 213 can output operating environment parameters corresponding to the slower environment. This interval determination method avoids directly processing continuously changing raw detection results, facilitating rapid pulse width selection by subsequent circuits.

[0064] In some embodiments, the comparison circuit 213 includes: a plurality of first comparators 404 connected in parallel, each first comparator 404 being configured with a set numerical threshold. Multiple first comparators 404 are connected to counter 214. Each first comparator 404 is used to compare the counter code with a set numerical threshold and output a first comparison result. The first comparison result is used to characterize the current working environment parameters.

[0065] In some embodiments, see Figure 4 Each first comparator 404 has its input connected to the output of the counter 214 to jointly receive the count code output by the counter 214. Each first comparator 404 compares the count code with a corresponding set numerical threshold and outputs a corresponding first comparison result. The first comparison result can be a binary logic signal, for example, a high level indicates that the count code is greater than or equal to the corresponding set value, and a low level indicates that the count code is less than the corresponding set value. In other embodiments, the opposite level definition may also be used, which is not specifically limited in this disclosure. Since the count code is the result of counting the number of oscillations of the oscillation signal within a fixed time period, the first comparison results output by multiple first comparators 404 can jointly reflect the current oscillation frequency level, thereby characterizing the current working environment state of the memory cell array 100. For example, multiple incrementing first values ​​Reference_code0 can be set. <n:0>The second value, Reference_code1 <n:0>The third value, Reference_code7 <n:0>And the fourth value Reference_code8 <n:0>(The image shows an example with eight values ​​set, omitting Reference_code2) <n:0>Up to Reference_code6 <n:0>(Not shown), and satisfying the condition: first value < second value < third value < fourth value. Multiple first comparators 404 compare the counter code with each of the aforementioned value thresholds in parallel. When the outputs of the first first comparator 404a, the second first comparator 404b, the third first comparator 404c, and the fourth first comparator 404d are 0000, it indicates that the current environment belongs to the first type of working environment; when the outputs of multiple first comparators 404 are 1000, it indicates that the current environment belongs to the second type of working environment; and when the outputs of multiple first comparators 404 are 1100, it indicates that the current environment belongs to the third type of working environment. In this way, without complex conversions to the original counter code, the category of the current environment can be quickly determined based on the parallel comparison results.

[0066] It should be noted that the numerical threshold corresponding to each first comparator 404 can be preset based on simulation data, test data, or calibration results, so that each numerical threshold better conforms to the speed distribution characteristics of the memory under different process angles, temperatures, and voltage conditions. For example, different numerical thresholds can be set according to different process angles, or multiple numerical thresholds can be set as multiple environmental boundary points, so that adjacent thresholds correspond to different pulse width adjustment ranges. In this way, when the first comparison results output by multiple first comparators 404 change, the subsequent connected circuits can determine that the current working environment has changed, and further select a pulse width of the column selection signal that is more suitable for the current environment. Since multiple first comparators 404 adopt a parallel structure, each threshold judgment can be completed at the same time, meeting the real-time requirements of environmental detection and pulse width switching.

[0067] Furthermore, the number of multiple first comparators 404 can be flexibly set according to the required number of environmental classifications. When the number of first comparators 404 is small, the working environment can be divided into coarse-grained categories to simplify the circuit structure; when the number of first comparators 404 is large, the working environment can be divided into fine-grained categories, thereby improving the accuracy of subsequent column selection signal pulse width adjustment.

[0068] In some embodiments, the number of preset configuration parameters is greater than or equal to the number of first comparators 404.

[0069] In this embodiment, since the operating environment parameters can have multiple dimensions, such as process angle, temperature, and voltage, the column selection signal can be adjusted based on a single parameter (or a single comprehensive parameter), or it can be adjusted based on multiple parameters (e.g., obtaining the operating environment parameters of the process angle and the operating environment parameters of temperature separately, and then selecting the column selection signal based on the two different operating environment parameters). Multiple first comparators 404 can be used to perform graded comparisons of operating environment parameters in a certain dimension, or to perform interval judgments corresponding to operating environment parameters in different dimensions, thereby outputting different first comparison results. To ensure that different combinations of comparison results correspond to appropriate pulse width control schemes, the number of preset configuration parameters pre-stored in the configuration parameter generation circuit 402 can be set to be greater than or equal to the number of first comparators 404, and can even be further greater than the number of combined states formed by the output results of multiple first comparators 404. For example, if the column selection signal is simultaneously affected by process angle and temperature, two different first comparison results can be obtained through the process angle comparison branch and the temperature comparison branch, respectively. Then, based on the combined state of these two first comparison results, the target configuration parameter is selected from a larger number of preset configuration parameters.

[0070] It should be noted that the preset configuration parameters can be adjustment codes predetermined during the testing phase and can be written into the configuration generation circuit via fuse programming. The adjustment codes can be calibrated for a single environmental dimension or for combinations of multiple environmental dimensions. For example, to meet the pulse width requirements of column selection signals under different process angles, the corresponding configuration parameters can be tested and programmed first. For pulse width differences caused by variations in process angle and temperature combinations, more refined preset configuration parameters can be configured to select the target configuration parameters more suitable for the current environment based on real-time monitoring results during runtime.

[0071] In some other embodiments, the comparison circuit 213 includes: a linearization conversion circuit 215 and a plurality of second comparators 407 connected in parallel, each second comparator 407 being configured with a set slope threshold. The linearization conversion circuit 215 is connected to the counter 214. The linearization conversion circuit 215 is used to calculate the difference between the counting code and the preset reference counting code, and convert the difference, which represents the frequency domain deviation, into a target slope, which represents the time domain deviation. The second comparator 407 is used to compare the target slope with a set slope threshold to obtain a second comparison result, thereby determining the slope range in which the target slope is located and generating the working environment parameters corresponding to the slope range.

[0072] It should be noted that, see Figure 5 Since the operating environment parameters are numerical values ​​representing the frequency domain deviation, the optimal configuration parameters and the operating environment parameters are usually not directly proportional, but rather have a curvilinear relationship. For example, in the range of higher operating environment parameters, only a small change in the operating environment parameters is needed for the optimal configuration parameters to change. In the range of lower operating environment parameters, the optimal configuration parameters will remain stable even when the operating environment parameters fluctuate within a certain range.

[0073] To address the aforementioned issues, in some embodiments, another timing control circuit 200 is also provided, see [link to relevant documentation]. Figure 6 It shows a schematic diagram of the circuit structure of another timing control circuit 200. Figure 6 Will Figure 2 The comparator circuit 213 in the original text has been replaced with a different comparator circuit 213 structure. See [link / reference]. Figure 7 The diagram illustrates the circuit structure of another comparator circuit 213. This other comparator circuit 213 includes a linearization conversion circuit 215 and multiple second comparators 407 connected in parallel. Figure 6 and Figure 7 Only one second comparator 407 is shown, which can distinguish between two different working environment parameters. The number of second comparators 407 can be determined according to the types of working environment parameters that need to be distinguished, and there is no specific limitation.

[0074] In some embodiments, see Figure 5 When the boundaries of some working environment parameter types are too dense, the working environment parameters can be converted into target slopes that characterize the time-domain deviation for subsequent comparison. For example, different process parameters can be divided into nine intervals according to different process angles, corresponding to nine sets of curve slopes ATT, AFF, ASS, AFS, ASF, ATF, AFT, ATS and AST. The counting code is converted into the target slope through a linear conversion circuit, so as to determine the working environment parameters through the second comparator 407. Figure 5 The curve shown can be obtained by comparing the adjustment effect based on different working environment parameters obtained from the test and corresponding to different configuration parameters, or it can be obtained by linear fitting curves based on the configuration parameter table corresponding to different working environment parameters obtained from the test, so as to determine the configuration parameters according to the slope of the curve.

[0075] In some embodiments, the linearization conversion circuit 215 includes a subtractor 405 and a divider 406 connected in sequence; Subtractor 405 is used to calculate the difference between the counter code and the reference counter code; The divider 406 is used to calculate the ratio between the preset working environment parameter difference constant and the difference value to obtain the target slope.

[0076] Here, the reference count code represents the counting result corresponding to the oscillation signal generated by the signal generation circuit 211 within a preset time period under the reference working environment. Therefore, the difference obtained by the subtractor 405 can reflect the degree of deviation of the current working environment from the reference working environment.

[0077] Furthermore, the target slope is obtained by performing a ratio operation between the preset working environment parameter difference constant and the difference value. The working environment parameter difference constant can be a pre-set fixed constant used to characterize the parameter span between adjacent working environment levels, or it can be used to normalize the difference value. Through the conversion of the divider 406, the difference value, which originally reflects the oscillation frequency deviation, can be converted into a target slope that is more suitable for the subsequent comparator circuit 213, so that the target slope can characterize the time-domain deviation trend of the current working environment. The subsequent second comparator 407 can quickly determine the interval to which the current working environment parameter belongs based on the comparison results between the target slope and different slope thresholds, and output the working environment parameter corresponding to that interval.

[0078] In some embodiments, the signal generation circuit 211 includes: a ring oscillator 408 and a frequency divider 409; The ring oscillator 408 is used to generate an oscillation signal; Frequency divider 409 is connected to ring oscillator 408 and is used to divide the received oscillation signal and output a down-frequency oscillation signal.

[0079] In some embodiments, see Figure 8 The ring oscillator 408 here can be an oscillation structure composed of odd-numbered inverting cells connected end-to-end, or it can be other equivalent structures that can utilize circuit propagation delay to form self-excited oscillation. Since the oscillation frequency of the ring oscillator 408 is typically sensitive to process corner, temperature, and supply voltage, its output oscillation signal can effectively characterize changes in the current operating environment parameters of the memory cell array 100. For example, under FF process corner, low temperature, or high voltage conditions, the device propagation delay decreases, and the oscillation frequency output by the ring oscillator 408 is typically higher; while under SS process corner, high temperature, or low voltage conditions, the device propagation delay increases, and the oscillation frequency output by the ring oscillator 408 is typically lower. Therefore, the ring oscillator 408 can convert changes in operating environment parameters into changes in oscillation frequency, providing a basis for subsequent detection circuits to identify the operating environment parameters.

[0080] It should be noted that the original oscillation signal output by the ring oscillator 408 typically has a high frequency. If the detection circuit directly counts the original oscillation signal, it may result in a higher operating frequency requirement for the counter 214, an increased counting bit width, and increased circuit power consumption. Furthermore, the counting range may become too large within the preset statistical period, which is detrimental to the interval judgment by the subsequent comparison circuit 213. By down-dividing the oscillation signal using the frequency divider 409, the implementation difficulty of the subsequent detection circuit can be reduced while preserving the original oscillation frequency variation trend, improving counting stability, and helping to control hardware area and power consumption.

[0081] It should be noted that the frequency divider 409 can employ multi-stage triggers, counting divider units, configurable divider chains, or other circuit structures capable of achieving integer frequency division. The division ratio can be preset based on the output frequency range of the ring oscillator 408, the counting capability of the detection circuit, and the required environmental resolution.

[0082] In another embodiment, a further timing control circuit 200 is proposed, comprising: The real-time monitoring circuit 210 is configured to monitor the operating environment parameters of the memory cell array 100 in real time during the working phase and output the current operating environment parameters. Pulse width adjustment circuit; The pulse width adjustment circuit is connected to the real-time monitoring circuit 210. The pulse width adjustment circuit is used to receive the working environment parameters, and select the column selection signal with the pulse width corresponding to the working environment parameters from the column selection signals with different pulse widths according to the working environment parameters, so as to output the column selection signal with the pulse width corresponding to the working environment parameters.

[0083] In this embodiment, the pulse width adjustment circuit can pre-store or pre-generate various column selection signals with different pulse widths, such as a first pulse width column selection signal, a second pulse width column selection signal, a third pulse width column selection signal, etc. The current operating environment parameters output by the real-time monitoring circuit 210 can be directly used as the selection basis for the pulse width adjustment circuit, so that it automatically switches to the corresponding pulse width column selection signal when different environmental conditions are detected. For example, when the memory cell array 100 is under FF process corner, low temperature or high voltage conditions, the pulse width adjustment circuit can select a shorter pulse width column selection signal to avoid excessive voltage offset of the data transmission line 300 and reduce unnecessary power consumption; when the memory cell array 100 is under SS process corner, high temperature or low voltage conditions, the pulse width adjustment circuit can select a longer pulse width column selection signal to extend the conduction time of the column selection transistor and compensate for the slow voltage build-up caused by the decrease in device drive capability. In this way, the column selection signal can change in real time with the current operating environment parameters, so that the voltage of the data transmission line 300 is more accurately offset to the target voltage that matches the current environment.

[0084] In another embodiment of this disclosure, an electronic device is provided that includes the memory described in the foregoing embodiments.

[0085] In summary, the embodiments of this disclosure provide a memory and an electronic device. By setting a timing control circuit 200, the operating environment parameters of the memory cell array can be monitored in real time during the operation phase. Based on the current operating environment parameters, a column select signal with a corresponding pulse width is dynamically output to control the conduction duration of the column select transistor connected to the data transmission line 300, thereby shifting the voltage of the data transmission line 300 to a target voltage that better matches the current environment. Compared to the prior art scheme that controls the global data line voltage by burning a fixed trim code onto a fuse and statically setting the column select signal pulse width, this disclosure has at least the following significant advantages: (1) By acquiring operating environment parameters such as process corner, temperature, and voltage in real time during the operation of the memory, the pulse width of the column selection signal is dynamically adjusted accordingly. Since the conduction capability of the column selection transistor, the voltage setup speed of the data transmission line, and the bias requirements of the global data line may differ in different operating environments, the solution of this disclosure can offset the data transmission line to a more suitable target voltage in different environments, thereby improving read / write margin and access stability.

[0086] (2) By monitoring the working environment parameters in real time and dynamically selecting the column selection signal with the corresponding pulse width during operation, the chip does not need to be finely calibrated for all processes, voltages, and temperatures during the factory testing phase; usually, only basic calibration, reference parameter acquisition, and confirmation of a small number of preset configuration parameters are required. This can reduce the number of test modes, shorten the finished product testing time, reduce the number of repeated tests and repeated programming, and thus reduce the occupation of test equipment and production costs.

[0087] (3) By changing the effective conduction time of the column selection transistor, the voltage offset of the data transmission line is adjusted, realizing on-chip closed loop. The entire process of monitoring, encoding and control is completed autonomously inside the chip. No external voltage generation structure is introduced. Dynamic control of the target voltage can be realized on the existing column selection control circuit. The circuit complexity is low, the system reliability is improved, and it is suitable for high frequency and high integration DRAM application scenarios.

[0088] (4) An oscillating signal that characterizes the deviation of working environment parameters is generated by using the signal generation circuit inside the memory. The detection circuit then counts the number of oscillations within a preset time period to obtain a count code. Based on the interval to which the count code belongs, the corresponding working environment parameters are generated. Through an encoder, a configuration parameter generation circuit, and a multi-input selector, the target configuration parameter corresponding to the current environment is quickly selected from a variety of preset configuration parameters, and a column selection signal with a corresponding pulse width is generated. This realizes the conversion of continuously changing and complex environmental detection results into discrete control results that are easy to process in subsequent stages, shortens the control link, improves the timing control response speed, and reduces the complexity of subsequent logic implementation.

[0089] (5) Compared with the fixed setting based on a single static tuning code, this embodiment can configure the column selection signal more finely, so that the pulse width selection is closer to the actual working environment requirements, avoiding the use of conservative settings for a long time to meet the worst working conditions, thereby ensuring functional reliability while taking into account performance and power consumption optimization under typical working conditions.

[0090] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0091] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0092] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0093] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0094] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0095] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, comprising: include: The memory cell array, timing control circuitry, and data transmission lines electrically connected to the memory cell array; The timing control circuit has multiple preset configuration parameters stored in it. These preset configuration parameters are used to indicate the generation of column selection signals with different pulse widths. The timing control circuit is used to monitor the operating environment parameters of the memory cell array in real time, and select a target configuration parameter from the multiple preset configuration parameters according to the operating environment parameters. It then outputs the column selection signal with a pulse width corresponding to the target configuration parameter, so that the voltage of the data transmission line shifts to different target voltages within different time periods corresponding to the pulse widths. The column selection signal is used to turn on the column selection transistor connected to the data transmission line.

2. The memory according to claim 1, characterized in that, During the working phase, the memory includes at least two states. In the first state, the memory cell array is under a first working environment parameter, and the timing control circuit outputs the column selection signal with a first pulse width. In the second state, the memory cell array is under the second operating environment parameters, and the timing control circuit outputs the column selection signal with a second pulse width; the first pulse width is different from the second pulse width, and the operating environment parameters include at least one of the following: process angle, temperature or voltage.

3. The memory of claim 1, wherein, The timing control circuit includes: A real-time monitoring circuit is configured to monitor the operating environment parameters of the storage cell array in real time during the working phase and output the current operating environment parameters. The encoding selection circuit, connected to the real-time monitoring circuit, is configured to perform logical encoding on the received current working environment parameters, with different logical encoding results corresponding to different pulse widths, and to select and output the corresponding column selection signal according to the logical encoding result.

4. The memory of claim 3, wherein, The encoding selection circuit includes: An encoder is electrically connected to the output of the real-time monitoring circuit. The encoder is used to logically encode the current working environment parameters and output the logical encoding result. A configuration parameter generation circuit is electrically connected to the encoder, receives the logic encoding result as a selection signal, and selects a target configuration parameter from the various preset configuration parameters under the instruction of the selection signal.

5. The memory of claim 4, wherein, The real-time monitoring circuit includes: a signal generation circuit and a detection circuit; The signal generating circuit is used to generate an oscillation signal, which characterizes the offset of the operating environment parameters of the memory cell array; The detection circuit is electrically connected to the signal generation circuit. The detection circuit is used to receive the oscillation signal, count the number of oscillations of the oscillation signal within a preset time period, generate a count code, and generate the corresponding working environment parameters according to the numerical range of the count code.

6. The memory according to claim 5, characterized in that, The detection circuit includes: a counter and a comparison circuit; The counter is electrically connected to the signal generating circuit and is used to count the number of oscillations of the oscillation signal to obtain the count code; The comparison circuit is connected to the counter and is used to determine the numerical range of the counter code and generate the operating environment parameters corresponding to the numerical range.

7. The memory according to claim 6, characterized in that, The comparison circuit includes: a plurality of first comparators connected in parallel, each of which is configured with a set numerical threshold. The plurality of first comparators are electrically connected to the counter. Each first comparator is used to compare the counter code with the set numerical threshold and output a first comparison result. The first comparison result is used to characterize the current working environment parameters.

8. The memory according to claim 7, characterized in that, The number of preset configuration parameters is greater than or equal to the number of the first comparators.

9. The memory according to claim 6, characterized in that, The comparison circuit includes: a linearization conversion circuit and a plurality of second comparators connected in parallel, each of which is configured with a set slope threshold. The linearization conversion circuit is connected to the counter. The linearization conversion circuit is used to calculate the difference between the counter code and the preset reference counter code, and convert the difference, which represents the frequency domain deviation, into a target slope, which represents the time domain deviation. The second comparator is used to compare the target slope with the set slope threshold to obtain a second comparison result, so as to determine the slope interval in which the target slope is located, and generate the working environment parameters corresponding to the slope interval.

10. The memory according to claim 9, characterized in that, The linearization conversion circuit includes a subtractor and a divider connected in sequence; The subtractor is used to calculate the difference between the counter code and the reference counter code; The divider is used to calculate the ratio between the preset working environment parameter difference constant and the difference value to obtain the target slope.

11. The memory according to claim 5, characterized in that, The signal generation circuit includes: a ring oscillator and a frequency divider; The ring oscillator is used to generate the oscillation signal; The frequency divider is connected to the ring oscillator and is used to perform frequency division processing on the received oscillation signal and output a down-frequency oscillation signal.

12. The memory according to claim 4, characterized in that, The encoding selection circuit further includes: a column selection signal generation circuit; The column selection signal generation circuit is electrically connected to the configuration parameter generation circuit, and is used to perform digital-to-analog conversion on the target configuration parameters to obtain the column selection signal with a pulse width corresponding to the working environment parameters.

13. The memory according to claim 12, characterized in that, The column selection signal generation circuit includes a delay circuit for determining the pulse width of the column selection signal based on the effective number of bits in the target configuration parameters, and generating the column selection signal having the pulse width.

14. The memory according to claim 4, characterized in that, The configuration parameter generation circuit includes: a multi-input selector; Each input terminal of the multi-input selector is used to receive the corresponding preset configuration parameters; The selection terminal of the multi-input selector receives the selection signal; The output of the multi-input selector outputs the preset configuration parameters corresponding to the working environment parameters as the target configuration parameters.

15. The memory according to claim 1, characterized in that, The timing control circuit includes: A real-time monitoring circuit is configured to monitor the operating environment parameters of the storage cell array in real time during the working phase and output the current operating environment parameters. A pulse width adjustment circuit is provided; the pulse width adjustment circuit is connected to the real-time monitoring circuit, and the pulse width adjustment circuit is used to receive the working environment parameters, and select the column selection signal with a pulse width corresponding to the working environment parameters from column selection signals with different pulse widths according to the working environment parameters, so as to output the column selection signal with a pulse width corresponding to the working environment parameters.

16. An electronic device, characterized in that, include: The memory as described in any one of claims 1 to 15.

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