In-memory computing working method based on capacitorless single-gate 2T0C structure

Abstract

This invention discloses a memory-computing integrated operation method based on a capacitorless single-gate 2T0C structure, belonging to the field of semiconductor memory device technology. The structure includes a write transistor controlled by a write word line, a read transistor, and a memory node with parasitic capacitance, with the transistor channel using IGZO material. The operation method includes: during the charge storage phase, turning on the write transistor allows the input current to accumulate in the parasitic capacitance; during the charge holding phase, turning off the write transistor allows the node charge to slowly dissipate due to leakage, causing an exponential decay of the carrier concentration in the read transistor channel; during the read and computation phase, turning on the read transistor and acquiring the real-time read current. This invention directly maps this exponential decay characteristic to the dynamic state space of stored-value computation, eliminating the need for additional independent capacitors and computation units, thus achieving highly integrated memory-computing integration.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory device technology, specifically relating to an in-memory computing method based on a capacitorless single-gate 2T0C structure. Background Technology

[0002] Neuromorphic computing and in-memory computing architectures have become a core direction for breaking through the memory wall. Oxide-based 2TOC structures, due to their advantages of requiring no additional capacitors and high integration density, are widely used in dynamic random access memory and neuromorphic computing devices. These existing 2TOC devices typically use oxides such as IGZO as the channel material, utilize node parasitic capacitance to store charge, and complete data reading and writing by injecting charge through write transistors and acquiring read current through read transistors. They have significant application potential in low-power storage and time-series signal processing scenarios.

[0003] However, in neuromorphic computing, the Reservoir (storage node) increases the low-dimensional feature noise of the reservoir, slows down the training convergence speed of the lightweight CNN readout layer, and ultimately results in a lower accuracy than ideal. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an in-memory computing method based on a capacitorless single-gate 2T0C structure, thereby solving the problems in existing technologies.

[0005] The objective of this invention can be achieved through the following technical solutions: A memory-computing integrated operation method based on a capacitorless single-gate 2TOC structure, wherein the capacitorless single-gate 2TOC structure includes: a write transistor and a read transistor whose gates are controlled by write word lines, and a memory node connected between the source / drain of the write transistor and the gate of the read transistor, the memory node having parasitic capacitance, and the channels of both the write transistor and the read transistor being made of IGZO material; the operation method includes: Charge storage step: Apply a conduction voltage higher than the write transistor threshold to the write word line, and apply an input signal to the write bit line connected to the write transistor, so that the input current is injected through the write transistor and accumulated in the parasitic capacitance of the storage node; Charge retention step: Applying a turn-off voltage below a threshold to the write word line turns off the write transistor, and the accumulated charge in the memory node is lost over time through the leakage current of the write transistor, causing the carrier concentration in the read transistor channel to decay exponentially. Reading and mapping calculation steps: Apply a bias voltage to the read bit line, collect the real-time read current reflecting the exponential decay characteristic through the read bit line connected to the read transistor, use the real-time read current as the dynamic state space of neuromorphic computing and map it as a stored value state, and output it for subsequent computing network processing.

[0006] Furthermore, in the capacitor-free single-gate 2TOC structure, the gate dielectric layer of both the write transistor and the read transistor adopts... and The stacked structure; wherein the bottom gate dielectric layer includes a thickness of 20 nm. Film layer and 5nm thickness Membrane.

[0007] Furthermore, in the charge storage step: a set current pulse sequence is applied to the write bit line, and by increasing the amplitude of the injected current, the charge on the parasitic capacitance of the storage node is forced to accumulate continuously, thereby increasing the initial reference value of the real-time read current when entering the charge holding step.

[0008] Furthermore, the working method combines input data to perform a pattern recognition task, including: In the charge storage step, the image pixel input data to be identified is grouped and converted into a binary pulse sequence. According to the rule that 0 states correspond to low values ​​and 1 states correspond to high values, the binary pulse sequence is used as an input signal to the write bit line. In the readout and mapping calculation step, the dynamic response difference and exponential decay characteristics of the parasitic capacitance charge with the continuous pulse sequence are used to generate a stored value state with current difference corresponding to different pulse input sequences; a double pulse stimulus is applied to the capacitorless single-gate 2TOC structure to obtain the paired pulse facilitation effect feature, and the stored value state containing the feature is linearly transformed and then input to the readout network classifier to output the classification and recognition result.

[0009] A storage-based neuromorphic computing system, comprising: Storage and computing array: includes multiple capacitor-free single-gate 2T0C structural units. Each structural unit includes: a write transistor and a read transistor controlled by a write word line and a storage node connecting the two. The storage node has parasitic capacitance. The channels of the write transistor and the read transistor are both IGZO material layers. Controller: Electrically connected to the write word line, write bit line and read bit line of the storage and computing array, the controller is configured to execute charge timing control logic: controlling the write word line to conduct in order to inject input charge into the parasitic capacitance via the write bit line; State mapping module: acquires the real-time read current on the read line that decays exponentially over time, and maps it to the dynamic storage value state variable for reservoir calculation.

[0010] Furthermore, the gate dielectric layer in the capacitor-free single-gate 2T0C structural unit includes a thickness of 20 nm. With a thickness of 5nm It forms a double-layered stacked structure.

[0011] Furthermore, the controller integrates a charge accumulation enhancement circuit, which is connected to the write bit line and is used to output a gain current with a specific amplitude to the write bit line of the target cell, thereby driving the parasitic capacitance of the storage node to accumulate charge and improve the initial reference value of the real-time read current in the cell.

[0012] Furthermore, the aforementioned computing system also includes: Input encoding module: used to encode external image matrix data into binary pulse signals and drive the input timing of the controller; The readout network is connected to the output of the state mapping module. It is used to extract the current amplitude difference of the dynamic storage state variable calculated by the reservoir, and to perform multiplication and addition operations through a pre-trained linear weight matrix to output the final pattern recognition prediction label.

[0013] A computer device includes: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; The memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the in-memory computing method described above.

[0014] The beneficial effects of this invention are: 1. This invention employs a single-gate 2T0C structure and utilizes the parasitic capacitance of the IGZO transistor itself to achieve charge storage, successfully eliminating the bulky independent capacitor cells found in traditional DRAM devices. This structural subtraction not only simplifies the device configuration but also fundamentally breaks through the bottleneck of physical size, thereby significantly improving the integration density of semiconductor memory arrays.

[0015] 2. By selecting IGZO (indium gallium zinc oxide) material as the channel layer of the transistor, this invention makes full use of the extremely low turn-off current characteristics of IGZO transistors. During the charge holding stage, this material characteristic significantly reduces the leakage loss of node charge, thereby significantly extending the charge holding time and giving the device excellent low power consumption characteristics.

[0016] 3. By directly mapping the naturally occurring exponential decay of channel carrier concentration in the device's off-state to the dynamic state space required for stored-value computation, this invention achieves true integration of storage and computation at the physical level. This in-situ computation mode eliminates the need for additional computing units, completely eradicating the latency caused by frequent data interactions between storage and computing units in the traditional von Neumann architecture, and significantly improving computational efficiency and real-time performance.

[0017] 4. To address the shortcomings of existing neuromorphic computing, such as high noise in low-dimensional node features leading to slow convergence speed and limited accuracy in lightweight CNN readout layers, this invention introduces a mechanism for co-regulating the bias voltage at the WWL terminal and the injected current at the WBL terminal, thereby achieving control over the readout current (I... d Precise dynamic control of decay rate. This control method enables the device to perfectly match the relaxation characteristics required for reservoir calculation, thereby effectively improving the pattern recognition accuracy and overall operational reliability of the reservoir calculation system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the single-gate 2T0C structure of the present invention; Figure 2 This is a flowchart of the in-memory computing operation based on a capacitorless single-gate 2T0C structure of the present invention; Figure 3 This is the transfer characteristic curve of the DRAM device of the present invention; Figure 4 This is the relaxation characteristic curve of the 2T0C DRAM of the present invention; Figure 5 This describes the growth characteristics of the DRAM device of the present invention under four consecutive pulses; Figure 6 These are the convergence curves of different training schemes. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1 like Figure 1 As shown, the capacitor-free single-gate 2T0C structure includes: a write transistor (controlled by the write word line WWL), a read transistor (controlled by the read bit line RBL), and a storage node SN, and has no additional capacitor units.

[0022] The gate of the write transistor is electrically connected to the write word line (WWL), and its on / off state is controlled by the voltage applied to the WWL; the source is electrically connected to the write bit line (WBL), and the drain is electrically connected to the storage node (SN). The gate of the read transistor is electrically connected to the storage node (SN), and its channel conductance is directly controlled by the charge potential on the SN; the source is grounded or connected to a reference potential, and the drain is electrically connected to the read bit line (RBL). The read operation is achieved by applying a read bias to the RBL and detecting the current.

[0023] The transistor channel uses IGZO material, the gate dielectric layer uses an Al2O3 / SiO2 stacked structure, and the BG (bottom gate layer) uses 20nm Mo.

[0024] In this embodiment, the typical dimensions of the write transistor and read transistor are: channel length LCH = 13.9 nm, channel width W = 200 nm, corresponding to a width-to-length ratio W / L ≈ 14.4. This size design allows for precise control of the device's on-resistance and turn-off leakage current, adapting to the charge storage and relaxation characteristics requirements of the 2T0C structure. The parasitic capacitance of the storage node SN is determined by the overlap area of ​​the write transistor drain, read transistor gate, and interconnect metal layout, as well as the dielectric properties of the gate dielectric layer. Through theoretical calculations and experimental calibration, its typical value is on the order of fF (approximately 1~10 fF).

[0025] This parasitic capacitance level provides a self-consistent physical basis for microsecond-level applications: if the parasitic capacitance is too large (e.g., in the pF range), the charge-discharge time constant will be too long, failing to match the microsecond-level input pulse timing of reservoir calculations; if the parasitic capacitance is too small (e.g., in the aF range), the charge retention time will be too short, easily leading to instantaneous light leakage and preventing the formation of stable relaxation characteristics. The fF-level parasitic capacitance of this invention can achieve a controllable charge relaxation time of 20~100μs, perfectly adapting to the timing signal processing requirements of neuromorphic computing.

[0026] like Figure 2 As shown, the in-memory computing method based on a capacitorless single-gate 2T0C structure includes the following steps: S1, Charge Storage Stage Triggering condition: Applying a voltage higher than the write transistor threshold voltage V to the write word line (WWL). th,write positive bias voltage (V) WWL =V th,write +1V~2V) to put the write transistor into a deep saturation conduction state, forming a low-resistance path between the source and drain; at the same time, the read bit line (RBL) remains at 0V to ensure that the read transistor is turned off and to avoid charge leakage at the SN node.

[0027] Charge injection: A constant current IWBL (or a stepped voltage VWBL) is applied to the write bit line (WBL). The current flows through the write transistor to the SN node (the gate of the read transistor), affecting the node parasitic capacitance C. SN Charging, charge Q SN =C SN × V SN Accumulated over time.

[0028] Enhancement mechanism: A stepped current injection method is adopted, first pre-charging with a small current, then switching to a large current for enhanced charging, so that Q... SN Continuous accumulation modulates the effective threshold voltage V of the read transistor. th,eff Increase the initial on-current I of the read transistor read,0 This enhances computational sensitivity.

[0029] Charge lockout: After charging is complete, WWL is set to below V. th,write At low voltage, the write transistor is turned off, and the SN node is physically isolated from WBL; by utilizing the high off-state resistance of the write transistor, Q is... SN Stable locking enables the preservation of non-volatile charge, providing a stable weighting benchmark for subsequent calculations.

[0030] S2, charge retention phase: WWL remains low, and the write transistor remains off.

[0031] Attenuation characteristics: Charge at the SN node is slowly lost due to the write transistor being turned off, and the carrier concentration in the read transistor channel gradually decreases. read It exhibits an exponential decay.

[0032] Control logic: WWL is maintained below the write transistor threshold voltage V. th,write When the voltage level is low (such as 0V or −0.5V), the write transistor remains off, and a high-impedance isolation is formed between the source and drain. At the same time, RBL remains at 0V, the read transistor is off, and the charge at the SN node is prevented from leaking to the read / write bit line.

[0033] Attenuation characteristics: The charge at the SN node is slowly lost due to leakage induced by the write transistor gate, intrinsic leakage in the IGZO channel, and leakage from parasitic capacitance. The charge Q SN (t) decays exponentially over time: Where τ≈50μs∼100μs is the charge retention time constant.

[0034] Current response: SN node charge decay modulates the effective threshold voltage V of the read transistor. th,eff (t) gradually reduces the channel carrier concentration, and reads the transistor's on-current I. read (t) corresponds to an exponential decay: This feature provides the physical basis for time-dependent in-memory computation.

[0035] Maintaining constraints: The effective charge retention window is approximately 100μs to 200μs, during which subsequent operations and reads must be completed. Charge can be replenished by briefly turning on the write transistor to achieve a refresh operation and extend the retention time.

[0036] S3, Reading and Status Verification Phase A read bias voltage of 0.1V is applied to the read bit line (RBL), and the real-time current I of the read transistor is acquired. read Record the current value and its decay trend.

[0037] Current acquisition: The drain current I of the read transistor is acquired in real time through a current sensing circuit (such as a transimpedance amplifier TIA). read (t), sampling frequency ≥ 10MHz, record initial current I read,0 The real-time current value and exponential decay trend are used to fit and extract the decay time constant τ.

[0038] State verification: Compare I read,0 The charge injection accuracy is verified against the target value, and the device leakage characteristics are verified through τ stability; the τ deviation of the same array unit is <10%, ensuring the consistency of storage and computation; paired pulses can be applied to verify the PPF effect and evaluate synaptic plasticity.

[0039] Read and hold: After the read is completed, RBL is set back to low level, the read transistor is turned off, the charge of the SN node remains basically unchanged, and continues to maintain the exponential decay trend. It can enter the subsequent operation or reset stage within the effective hold window.

[0040] S4, Stored Value Calculation Application Stage Input layer processing: The input data, such as image pixels, is grouped into binary inputs, with 0 state corresponding to I. read Low value, state 1 corresponds to I read High value.

[0041] Stored value state mapping: After inputting a binary pulse sequence, I is used read The dynamic decay characteristics and pulse timing response differences generate a variety of stored value states based on current differences.

[0042] Synaptic property verification: Applying double-pulse stimulation, detecting the paired-pulse facilitation (PPF) effect, and evaluating I read Dynamic response plasticity with pulse timing.

[0043] Readout network classification: The stored value state (current difference) is linearly transformed and then input into the readout network to complete the pattern recognition task.

[0044] Input layer processing: Binarize the input data such as image pixels according to a threshold, with 0 corresponding to I. read Low value (single narrow pulse input), state 1 corresponds to I read High value (dual narrow pulse input), pulse interval matched with IGZO leakage time constant τ≈50μs, parallel input is achieved by scanning in row order.

[0045] The input mapping rule is as follows: The image pixel grayscale values ​​P (range 0–255) are mapped according to a threshold P. th Binarization: If P <P th The code is in state 0, corresponding to the read transistor I. read Low-level output; If P≥P th The code is set to state 1, corresponding to the read transistor I. read High-level output.

[0046] Encoding method selected: Time coding (pulse coding) State 0: Apply a single narrow pulse (pulse width tp = 10 μs, amplitude V) to the write bit line (WBL). low =0.5V). State 1: Apply a double pulse / continuous pulse (pulse width tp = 10 μs, amplitude V) to the write bit line (WBL). high =2V, pulse interval Δt=50μs).

[0047] Input method: Image pixels are input in line scanning order, with each row of pixels corresponding to a set of timing pulses, realizing parallel input line by line.

[0048] Pulse parameters (width and interval) are matched to IGZO leakage current, specifically including: Pulse width: tp = 10 μs, matched to the carrier response time of the IGZO device to ensure I read Fully responsive.

[0049] Pulse interval: Δt = 50 μs, matched with the IGZO parasitic capacitance leakage time constant τ ≈ 50 μs, so that I read It exhibits exponential decay characteristics: ; Ensure the I of adjacent pulses read The difference can be sensed by the circuit.

[0050] Stored value state mapping: After inputting a binary pulse sequence, I is used read The difference between the exponential decay characteristics and the pulse timing response generates a multi-level storage state (empty state S0, low storage S1, high storage S2, full storage S3), and the different states correspond to distinguishable current differences ΔI.

[0051] Synaptic property verification: Paired pulse stimulation was applied to the WBL, the paired pulse facilitation (PPF) effect was detected, and the facilitation rate PPF = (I2−I1) / I1×100% was calculated to evaluate I. read The dynamic response plasticity with pulse timing was used to verify the synaptic enhancement and fatigue characteristics of the device; where I1 is the peak value of the read current generated by the read transistor under the first pulse stimulation, and I2 is the peak value of the read current generated by the read transistor under the second pulse stimulation. These two are two key current characteristic values ​​under dual-pulse timing stimulation.

[0052] Readout network classification: The stored value state (current difference ΔI) is linearly transformed and then input into a single-layer fully connected readout network to complete the pattern recognition task (such as MNIST handwritten digit recognition). The test set accuracy reaches 98.72%, and the convergence speed is 50% faster than that of a lightweight CNN.

[0053] Example 2 In this embodiment, relevant experimental tests were conducted on the capacitorless single-gate 2T0C structure in Example 1 and its integration process. 1. Transfer characteristics test of IGZO thin film transistor in single-gate 2T0C structure In the test platform, a constant drain-source bias voltage V is applied to the source and drain of the transistor. DS (e.g. V) DS =0.1V or 1V), and a scanning voltage V is applied to the gate (G) of the transistor using a semiconductor parameter analyzer. G (The test range is approximately −2V to 6V). During the voltage scan, the drain current flowing through the transistor channel is recorded in real time. ).

[0054] Experimental test results are as follows Figure 3 As shown, it can be seen that: 1) When the gate voltage When the transistor is in the negative bias and low positive voltage range (approximately below 1.5V), it is in the off state. The drain current at this time... Minimal, stable at to The limiting noise level is extremely low.

[0055] 2) When Once the threshold for activation is exceeded, the current increases sharply and exponentially, eventually reaching the activation current. Level. Device switching ratio ( )Exceed .

[0056] Figure 3 The results show that the present invention uses IGZO material as the channel, Transistors that act as gate dielectrics possess excellent ultra-low turn-off current (low leakage loss) characteristics.

[0057] 2. Time-domain characteristics test of natural relaxation (leakage decay) of stored node charge in 2T0C cell The experimental procedure includes: 1) Injection excitation: First, apply a voltage higher than the threshold to the write word line (WWL) to turn on the write transistor, and inject current through the write bit line (WBL) to charge the parasitic capacitance of the storage node (SN).

[0058] 2) Shutdown and Monitoring: Subsequently, set WWL to low-voltage lockout charge; at this time, apply a bias voltage to the read line (RBL), and use an oscilloscope or high-precision ammeter to continuously acquire and record the real-time read current on the read line in microseconds (µs). The trajectory of change over time.

[0059] Experimental results are as follows Figure 4 As shown, at the initial moment immediately after charge injection is completed, The peak value is reached. After entering the hold phase, due to the weak leakage current in the write transistor even in the off state, the charge on the parasitic capacitance of the SN node gradually dissipates. This causes a decrease in the carrier concentration in the read transistor channel, macroscopically manifested as… Figure 4 middle It exhibits a smooth and extremely regular exponential decay curve over time.

[0060] This experiment verifies that the 2T0C device exhibits a stable physical decay process during the hold phase without external intervention. This relaxation characteristic demonstrates that the device possesses the "short-term memory / forgetting" mechanism required to support reservoir computing.

[0061] 3. Dynamic response plasticity (state mapping) test under binary continuous pulse sequence stimulation To simulate the input environment of a neural network, four electrical pulses of the same amplitude and width are continuously applied to the write end (WBL) of the device at specific time intervals (timing). Simultaneously, the output read current is continuously monitored at the read end. The response reflects the cumulative and changing situation over time; Experimental results are as follows Figure 5 As shown, the output curve exhibits a distinct sawtooth-shaped, step-like upward trend; specifically: After the first pulse injection, the current generates a peak and begins to follow... Figure 4 The current decays according to a certain pattern. Because the charge injected by the previous pulse has not yet completely decayed by the time subsequent pulses arrive, the newly injected charge will be superimposed on the remaining charge at the node, causing the peak current generated by the second pulse to be higher than that of the first. After stimulation by four consecutive pulses, the read current ( The trough baseline and peak absolute values ​​of the wave have both achieved a significant step-like increase.

[0062] Figure 5 The invention demonstrates that the device exhibits a memory accumulation effect on time-series signals, successfully verifying a "paired pulse facilitation (PPF) effect" similar to biological synapses and dynamic response plasticity. It proves that the invention can accurately utilize the dynamic decay characteristics of capacitance and the response differences of pulse timing to generate various stored-value states based on current differences, thereby providing rich, linearly classifiable, high-quality features for subsequent readout networks, ultimately achieving in-memory computing integrated pattern recognition.

[0063] Example 3 This embodiment uses a single-layer fully connected neural network (SLP) as the readout network, with the following structure: Input layer: The dimension N of the current difference feature output from the 2T0C storage pool is equal to the dimension N (matching the array size, such as N=784 corresponding to MNIST28×28 pixels). Output layer: The dimension is equal to the number of classification categories C (e.g., MNIST has 10 categories of numbers), the activation function is Softmax, and the output is the probability of each category; Compared to lightweight CNNs, it has a simpler structure, fewer parameters, faster training convergence, and is also compatible with the linear features of current-based in-memory computing outputs.

[0064] The method for training the weights of the readout network is as follows: Data preprocessing: The current difference ΔI output by the 2T0C storage pool is normalized to the [0,1] interval and used as the network input feature; Loss function: Cross-entropy loss is used. L= Among them, y i Let C be the true label of the i-th class, and C be the total number of categories.

[0065] Optimizer: The Adam optimizer is used, with an initial learning rate η=10. −3 Weight decay λ=10 −4 Batch size B=64; The training process is as follows: Forward propagation: The current characteristics are linearly transformed into W⋅x+b and then input into Softmax; Backpropagation: Update the weights W and bias b of the fully connected layer based on the loss gradient; Validation: Accuracy is evaluated on the validation set every 5 epochs, and early stopping is used to prevent overfitting.

[0066] The method of the present invention will be compared and verified by analogy with other methods in the prior art; wherein: This solution: 2T0C stored value pools + single-layer fully connected readout network; Existing technology: Lightweight CNN (2 convolutional layers + 2 fully connected layers); Ideal CNN: Standard LeNet-5 network.

[0067] Dataset: MNIST handwritten digit dataset, containing 60k training samples and 10k test samples, with a resolution of 28×28; Input mapping: Binarize pixel grayscale values ​​(threshold P) th =127), which is converted into a time-coded pulse sequence and input into the 2T0C storage pool; The comparative experiment procedure is as follows: Image pixels → binary pulses → 2T0C storage tank → current difference features; feature input to readout network, trained to convergence, convergence curves of different schemes are shown below. Figure 6 As shown in Table 1, the number of training epochs and the accuracy on the test set were recorded. Table 1 Comparison test results of the method of the present invention and existing solutions From Table 1 and Figure 6 It can be seen that the accuracy of this scheme stabilizes at over 98.5% after 15 epochs, while lightweight CNNs require 30 epochs to converge and ideal CNNs require 25 epochs, which verifies that this scheme converges faster. Final accuracy: The accuracy of this solution on the test set reached 98.72%, which is slightly higher than that of the ideal CNN (98.56%) and significantly higher than that of the lightweight CNN (97.85%), proving that this solution overcomes the defects of "low accuracy and slow convergence" in the background technology.

[0068] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0069] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A memory computing integrated working method based on a capacitorless single-gate 2T0C structure, characterized in that, The capacitor-free single-gate 2T0C structure includes: a write transistor and a read transistor whose gates are controlled by a write word line, and a memory node connected between the source / drain of the write transistor and the gate of the read transistor. The memory node has parasitic capacitance, and the channels of both the write transistor and the read transistor are made of IGZO material. The operating method includes: Charge storage step: Apply a conduction voltage higher than the write transistor threshold to the write word line, and apply an input signal to the write bit line connected to the write transistor, so that the input current is injected through the write transistor and accumulated in the parasitic capacitance of the storage node; Charge retention step: Applying a turn-off voltage below a threshold to the write word line turns off the write transistor, and the accumulated charge in the memory node is lost over time through the leakage current of the write transistor, causing the carrier concentration in the read transistor channel to decay exponentially. Reading and mapping calculation steps: Apply a bias voltage to the read bit line, collect the real-time read current reflecting the exponential decay characteristic through the read bit line connected to the read transistor, use the real-time read current as the dynamic state space of neuromorphic computing and map it as a stored value state, and output it for subsequent computing network processing.

2. The in-memory computing method based on a capacitorless single-gate 2TOC structure according to claim 1, characterized in that, In the capacitor-free single-gate 2T0C structure, the gate dielectric layers of both the write transistor and the read transistor are made of... and The stacked structure.

3. The in-memory computing method based on a capacitorless single-gate 2TOC structure according to claim 2, characterized in that, In the capacitor-free single-gate 2T0C structure, the bottom gate dielectric layer includes a thickness of 20nm. Film layer and 5nm thickness Membrane.

4. The in-memory computing method based on a capacitorless single-gate 2TOC structure according to claim 1, characterized in that, In the charge storage step: a set current pulse sequence is applied to the write bit line, and by increasing the amplitude of the injected current, the charge on the parasitic capacitance of the storage node is forced to accumulate continuously, thereby increasing the initial reference value of the real-time read current when entering the charge holding step.

5. The in-memory computing method based on a capacitorless single-gate 2TOC structure according to any one of claims 1-4, characterized in that, The working method combines input data to perform pattern recognition tasks, including: In the charge storage step, the image pixel input data to be identified is grouped and converted into a binary pulse sequence. According to the rule that 0 states correspond to low values ​​and 1 states correspond to high values, the binary pulse sequence is used as an input signal to the write bit line. In the readout and mapping calculation step, the dynamic response difference and exponential decay characteristics of the parasitic capacitance charge with the continuous pulse sequence are used to generate a stored value state with current difference corresponding to different pulse input sequences; a double pulse stimulus is applied to the capacitorless single-gate 2TOC structure to obtain the paired pulse facilitation effect feature, and the stored value state containing the feature is linearly transformed and then input to the readout network classifier to output the classification and recognition result.

6. A storage-based neuromorphic computing system, characterized in that, include: Storage and computing array: includes multiple capacitor-free single-gate 2T0C structural units. Each structural unit includes: a write transistor and a read transistor controlled by a write word line and a storage node connecting the two. The storage node has parasitic capacitance. The channels of the write transistor and the read transistor are both IGZO material layers. Controller: Electrically connected to the write word line, write bit line and read bit line of the storage and computing array, the controller is configured to execute charge timing control logic: controlling the write word line to conduct in order to inject input charge into the parasitic capacitance via the write bit line; State mapping module: acquires the real-time read current on the read line that decays exponentially over time, and maps it to the dynamic storage value state variable for reservoir calculation.

7. The computing system according to claim 6, characterized in that, The gate dielectric layer in the capacitor-free single-gate 2T0C structural unit has a thickness of 20 nm. With a thickness of 5nm It forms a double-layered stacked structure.

8. The computing system according to claim 6, characterized in that, The controller integrates a charge accumulation enhancement circuit, which is connected to the write bit line and is used to output a gain current with a specific amplitude to the write bit line of the target cell, thereby driving the parasitic capacitance of the storage node to accumulate charge and improve the initial reference value of the real-time read current in the cell.

9. The computing system according to any one of claims 6-8, characterized in that, Also includes: Input encoding module: used to encode external image matrix data into binary pulse signals and drive the input timing of the controller; The readout network is connected to the output of the state mapping module. It is used to extract the current amplitude difference of the dynamic storage state variable calculated by the reservoir, and to perform multiplication and addition operations through a pre-trained linear weight matrix to output the final pattern recognition prediction label.

10. A computer device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the in-memory computing method as described in any one of claims 1-4.

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