Semiconductor memory devices

Abstract

This invention relates to a semiconductor memory device. A memory is provided capable of performing an update operation during read or write operations. The memory includes a plurality of first data lines and a plurality of first control lines for writing, and a plurality of second data lines and a plurality of second control lines for reading. A memory cell includes: a first transistor, the gate of which is connected to a first control line and one end of which is connected to a first data line; a second transistor, the gate of which is connected to a second control line and one end of which is connected to a second data line; and a third transistor, the gate of which is connected to the other end of the first transistor and one end of which is connected to the other end of the second transistor. A third data line corresponds to a plurality of first data lines, and a fourth data line corresponds to a plurality of second data lines. An input portion of a detection circuit is connected to the fourth data line. A storage circuit is disposed between the output portion of the detection circuit and the third data line. A fourth transistor is disposed between the output portion of the detection circuit and the third data line.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Technology

[0002] The industry is developing a gain-cell memory as an alternative to DRAM (Dynamic Random Access Memory) storage cells. DRAM cannot perform update operations such as writing stored data back to the same storage cell during read or write operations. Summary of the Invention

[0003] The present invention provides a semiconductor memory device capable of performing update operations during read or write operations.

[0004] The semiconductor memory device of this embodiment includes a plurality of first data lines and a plurality of first control lines for writing data, and a plurality of second data lines and a plurality of second control lines for reading data.

[0005] Each of the multiple memory cells includes: a first transistor, whose gate is connected to any one of a plurality of first control lines and one end is connected to any one of a plurality of first data lines; a second transistor, whose gate is connected to any one of a plurality of second control lines and one end is connected to any one of a plurality of second data lines; and a third transistor, whose gate is connected to the other end of the first transistor and stores data from the first data line, and one end is connected to the other end of the second transistor and becomes on according to the data. The third data line is provided corresponding to the plurality of first data lines. The fourth data line is provided corresponding to the plurality of second data lines.

[0006] A detection circuit is provided corresponding to the 3rd or 4th data line, with its input section connected to the 4th data line to detect data. A storage circuit is provided corresponding to the 3rd or 4th data line, located between the output section of the detection circuit and the 3rd data line, to store the data detected by the detection circuit. A 4th transistor is provided corresponding to the 3rd or 4th data line, located between the output section of the detection circuit and the 3rd data line. Attached Figure Description

[0007] Figure 1 This is a circuit diagram illustrating a configuration example of a single memory cell in the first embodiment.

[0008] Figure 2A This is a perspective view showing a configuration example of the gain unit memory in the first embodiment.

[0009] Figure 2B This is a perspective view showing a configuration example of the gain unit memory in the first embodiment.

[0010] Figure 3This is a diagram illustrating a configuration example of the gain unit memory in the first embodiment.

[0011] Figure 4 This is a circuit diagram illustrating an example of the internal structure of a latching circuit.

[0012] Figure 5 This is a timing diagram illustrating an operational example of the gain unit memory in the first embodiment.

[0013] Figure 6 This is a timing diagram illustrating an operational example of the gain unit memory in the second embodiment.

[0014] Figure 7 This is a diagram illustrating a configuration example of the gain unit memory in the third embodiment.

[0015] Figure 8 This is a circuit diagram illustrating an example of the configuration of a sense amplifier. Detailed Implementation

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic diagrams or conceptual diagrams. In the specification and drawings, the same elements are labeled with the same reference numerals.

[0017] (First Embodiment)

[0018] Figure 1 This is a circuit diagram illustrating a configuration example of a single memory cell in the first embodiment. The memory cell MC of the gain unit memory includes three transistors MW1, MR1, and MR2. Transistors MW1, MR1, and MR2 are, for example, constructed from n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0019] The gate of transistor MW1, acting as the first transistor, is connected to the write word line WWL, which serves as the first control line. One electrode of transistor MW1 is connected to the write bit line WBL, which serves as the first data line. The other electrode of transistor MW1 is connected to the gate of transistor MR1. The one and other electrodes of transistor MW1 function as source or drain electrodes depending on the voltage supplied to transistor MW1. Transistor MW1, controlled by the write word line WWL, connects the write bit line WBL to the gate of transistor MR1 (hereinafter also referred to as the sense node SN), which functions as a sense node SN. When transistor MW1 is in the ON state, it transmits the voltage of the write bit line WBL to the sense node SN. When transistor MW1 is in the OFF state, it maintains the voltage of the sense node SN. In this way, transistor MW1 can write the voltage (data) from the write bit line WBL to the sense node SN, or maintain the written voltage (data) on the sense node SN.

[0020] The gate of transistor MR1, acting as the third transistor, is connected to the other electrode of transistor MW1, functioning as a sensing node SN. One electrode (e.g., the source) of transistor MR1 is connected to a low-voltage source VSS. The other electrode (e.g., the drain) of transistor MR1 is connected to one electrode of transistor MR2. Transistor MR1 becomes on based on the voltage (i.e., data) of the sensing node SN. For example, when the sensing node SN is held at a high voltage level (e.g., data "1"), transistor MR1 is on. When the sensing node SN is held at a low voltage level (e.g., data "0"), transistor MR1 is off.

[0021] The gate of transistor MR2, acting as the second transistor, is connected to the read word line RWL, which serves as the second control line. One electrode of transistor MR2 is connected to the drain of transistor MR1. The other electrode of transistor MR2 is connected to the read bit line RBL, which serves as the second data line. Depending on the voltage supplied to transistor MR2, one electrode and the other electrode of transistor MR2 can function as either source or drain electrodes. Transistor MR2, controlled by the read word line RWL, connects the read bit line RBL to the drain of transistor MR1. Transistor MR1 enters a state corresponding to the voltage (data) held by the sensing node SN (on or off). Regarding transistor MR2, if the read bit line RBL is connected to transistor MR1 when it is on, the charge from the read bit line RBL flows to the low-voltage source VSS depending on the state of transistor MR1. When transistor MR1 is on, the charge from the read bit line RBL flows to the low-voltage source VSS, and the voltage of the read bit line RBL decreases. When transistor MR1 is off, almost no charge flows from the read bit line RBL to the low voltage source VSS, and the voltage of the read bit line RBL remains high. Therefore, the voltage based on the data stored at the sensing node SN is transmitted to the read bit line RBL.

[0022] The sense amplifier SA, acting as the detection circuit, is connected to the read bit line RBL. The sense amplifier SA is not directly connected to the write bit line WBL. The sense amplifier SA detects the read data based on the voltage of the read bit line RBL. The read data latched in the sense amplifier SA is sent to the outside via the latch circuit LAT. The sense amplifier SA also pre-charges the read bit line RBL. Furthermore, during the update operation, the sense amplifier SA writes the read data directly back to the write bit line WBL without using the latch circuit LAT.

[0023] The latch circuit LAT is connected to the write bit line WBL and the sense amplifier SA. The latch circuit LAT latches write data from the external source and applies a voltage corresponding to the write data to the write bit line WBL. Additionally, the latch circuit LAT temporarily latches read data from the sense amplifier SA. The read data latched in the latch circuit LAT is sent to the external source at a specified time.

[0024] The controller CTL is connected to the write word line WWL and the read word line RWL, and controls the voltage of the write word line WWL and the read word line RWL.

[0025] The write word line (WWL) and write bit line (WBL) are wiring used for writing data. The read word line (RWL) and read bit line (RBL) are wiring used for reading data. In this way, gain-cell memory uses different word lines and bit lines for writing and reading data. Therefore, gain-cell memory can read data while maintaining the data at the sense node (SN) (non-destructive read). Furthermore, each memory cell (MC) contains three transistors (MW1, MR1, MR2) and does not have capacitors that are difficult to miniaturize like in DRAM. Therefore, gain-cell memory has advantages in miniaturization.

[0026] Figure 2A and Figure 2B This is a perspective view showing a configuration example of the gain cell memory according to the first embodiment. The gain cell memory of this embodiment includes a three-dimensional memory cell array in which a plurality of memory cells MC are arranged in three dimensions. The plurality of memory cells MC are arranged in a matrix consisting of multiple rows and columns. Rows represent the arrangement of the memory cells MC in the X direction. Columns represent the arrangement of the memory cells MC in the Z direction. Furthermore, the matrix of memory cells MC is arranged along the Y direction. Thus, the memory cell array MCA becomes a three-dimensional array obtained by arranging a plurality of memory cells MC in three dimensions. Furthermore, the number of rows, columns, and matrices of the memory cells MC are not particularly limited. Hereinafter, refer to... Figure 2A To illustrate the memory cell array (MCA).

[0027] Multiple write word lines (WWL) are configured to correspond to multiple rows of memory cells (MC). Multiple read word lines (RWL), which serve as multiple second control lines, are also configured to correspond to multiple rows of memory cells (MC). The write word lines (WWL) are used to write data and extend in the X direction. The read word lines (RWL) are used to read data and extend in the X direction.

[0028] Multiple write word lines (WWL) and multiple read word lines (RWL) arranged along the Y direction share a common drive line (WDRV). The drive line (WDRV) transmits the selection voltage for data writing. The multiple drive lines (WDRV) extend in the Y direction and are arranged along the Z direction.

[0029] Multiple transistors WT1 are connected between multiple write word lines WWL and drive lines WDRV, respectively. One electrode of each transistor WT1 is connected to one of the multiple write word lines WWL. The other electrodes of the multiple transistors WT1 arranged along the Y direction are all connected to one drive line WDRV. Furthermore, one electrode and the other electrode of each transistor WT1, RT1, WT2, WTbl, and RTbl can function as source or drain electrodes depending on the voltage supplied to the transistors WT1, RT1, WT2, WTbl, and RTbl.

[0030] Multiple transistors RT1 are connected between multiple read word lines RWL and drive line WDRV, respectively. One electrode of each transistor RT1 is connected to one of the read word lines RWL. The other electrodes of the transistors RT1, arranged along the Y direction, are all connected to one drive line WDRV. Multiple transistors WT1 and RT1, arranged along the Y direction, are all connected to one drive line WDRV.

[0031] The write main word line WMWL is commonly connected to the gate of multiple transistors WT1 arranged along the Z-direction. That is, the write main word line WMWL is a common setting for the multiple write word lines WWL arranged along the Z-direction. The multiple write main word lines WMWL extend in the Z-direction and are arranged along the Y-direction. The write main word line WMWL selectively turns on the multiple transistors WT1 connected to it, thereby connecting the drive line WDRV to the corresponding write word line WWL. The multiple write main word lines WMWL arranged along the Y-direction are each driven independently. Therefore, Figure 2A The transistor WT1 shown is individually controlled to be either on or off for each of the multiple rows arranged along the Z direction.

[0032] The read word line RMWL is commonly connected to the gate of a plurality of transistors RT1 arranged along the Z direction. That is, the read word line RMWL is a common configuration for the plurality of read word lines RWL arranged along the Z direction. The plurality of read word lines RMWL extend in the Z direction and are arranged along the Y direction. The read word line RMWL turns on the plurality of transistors RT1 connected to it, thereby connecting the drive line WDRV to the corresponding plurality of read word lines RWL. The plurality of read word lines RMWL arranged along the Y direction are each driven independently. Therefore, Figure 2A The transistor RT1 shown is individually controlled to be either on or off for each of the multiple rows arranged along the Z direction.

[0033] A common non-write voltage line VUW is provided for the multiple write word lines (WWL) arranged along the Y direction. The non-write voltage line VUW transmits a non-selection voltage that does not perform data writing. The multiple non-write voltage lines VUW extend in the Y direction and are arranged along the Z direction.

[0034] Multiple transistors WT2 are connected between multiple write word lines WWL and non-write voltage lines VUW, respectively. One electrode of each transistor WT2 is connected to one of the multiple write word lines WWL. The other electrodes of the multiple transistors WT2, arranged along the Y direction, are all connected to a single non-write voltage line VUW. On the other hand, multiple read word lines RWL are electrically isolated from the multiple non-write voltage lines VUW. Furthermore, when the non-selection voltage is fixed, the multiple non-write voltage lines VUW can be shorted together as a single drive line.

[0035] The non-select main word line bWMWL is commonly connected to the gate of multiple transistors WT2 arranged along the Z direction. These multiple non-select main word lines bWMWL extend in the Z direction and are arranged along the Y direction. The non-select main word line bWMWL turns on the multiple transistors WT2 connected to the write word line WWL corresponding to the memory cell MC that has not been written to, connecting the non-write voltage line VUW to the corresponding write word line WWL.

[0036] Multiple write bit lines (WBL) are configured corresponding to multiple columns of the memory cell (MC). Multiple read bit lines (RBL), which serve as multiple second data lines, are also configured corresponding to multiple columns of the memory cell (MC). Furthermore, Figure 2A The diagram only shows one column each of the write bit lines WBL and read bit lines RBL arranged along the Y direction. The write bit line WBL is used to write data and extends in the Z direction. The read bit line RBL is used to read data and extends in the Z direction. The read bit line RBL, write bit line WBL, write main word line WMWL, read main word line RMWL, and non-select main word line bWMWL extend in the Z direction.

[0037] The write global bit line WGBL is a common setting for multiple write bit lines WBL arranged along the Y direction. The multiple write global bit lines WGBL extend in the Y direction and are arranged along the X direction. Furthermore, Figure 2A In the diagram, only one write global bit line WGBL is shown. The write global bit line WGBL is connected to a write bit line WBL selected from the corresponding plurality of write bit lines WBL, and data from the latch circuit LAT or the sense amplifier SA is transmitted to the selected write bit line WBL.

[0038] The read global bit line RGBL is a common setting for multiple read global bit lines RBL arranged along the Y direction. These multiple read global bit lines RGBL extend in the Y direction and are arranged along the X direction. Furthermore, Figure 2A In the diagram, only one global readout bit line RGBL is shown. The global readout bit line RGBL is connected to a readout bit line RBL selected from the corresponding plurality of readout bit lines RBL, and transmits data from the selected readout bit line RBL to the sense amplifier SA.

[0039] It can simultaneously write or read data with the same number of bits as the logarithm of the bits written to the global bit line WGBL and read from the global bit line RGBL. This data that can be written or read simultaneously is called a "page".

[0040] In addition, by using global bit lines WGBL, RGBL and bit lines WBL, RBL to hierarchically construct the bit lines, the capacitance of bit lines WBL and RBL can be reduced.

[0041] Multiple transistors WTbl are connected between multiple write bit lines WBL and write global bit line WGBL, respectively. One electrode of each WTbl transistor is connected to one of the write bit lines WBL. The other electrodes of the WTbl transistors arranged along the Y direction are all connected to a single write global bit line WGBL. The gates of the WTbl transistors arranged along the X direction are all connected to a write select line WSEL. The write select lines WSEL extend along the X direction and are arranged along the Y direction. A transistor WTbl connects one of the write bit lines WBL to the single write global bit line WGBL.

[0042] During the write operation, one of the multiple write select lines WSEL is selectively driven. Multiple transistors WTbl connected to the selected write select line WSEL are turned on, electrically connecting their respective write bit lines WBL and write global bit lines WGBL. Thus, the multiple transistors WTbl connected to the selected write select line WSEL transmit data from the latch circuit LAT or the sense amplifier SA from their respective write global bit lines WGBL to the write bit line WBL.

[0043] Preferably, a transistor WTbl is provided to reduce the capacitance of the write bit line WBL, thereby enabling the write bit line WBL to operate at high speed. However, if the operating speed is not a concern, the transistor WTbl can be omitted.

[0044] Multiple transistors RTbl are connected between multiple read bit lines RBL and read global bit line RGBL. One electrode of each transistor RTbl is connected to one of the read bit lines RBL. The other electrodes of the transistors RTbl, arranged along the Y direction, are all connected to one read global bit line RGBL. The gates of the transistors RTbl, arranged along the X direction, are all connected to the read select line RSEL. The read select lines RSEL extend in the X direction and are arranged along the Y direction. Transistor RTbl connects one of the read bit lines RBL to one read global bit line RGBL.

[0045] During the read operation, one of the multiple read select lines RSEL is selectively driven. Multiple transistors RTbl connected to the selected read select line RSEL are turned on, electrically connecting their respective read bit lines RBL and read global bit lines RGBL. Thus, the multiple transistors RTbl connected to the selected read select line RSEL transfer data from the memory cell MC from their respective read bit lines RBL to the read global bit line RGBL.

[0046] Multiple memory cells MC are configured to correspond to the intersections of pairs of adjacent write word lines WWL and read word lines RWL in the Y direction and pairs of adjacent write bit lines WBL and read bit lines RBL in the X direction. Therefore, the memory of this embodiment can write data to one memory cell MC by selecting one write word line WWL and one write bit line WBL during writing. Furthermore, the memory can read data from one memory cell MC by selecting one read word line RWL and one read bit line RBL during reading.

[0047] A layer containing multiple write word lines (WWL), multiple read word lines (RWL), and multiple memory cells (MC) corresponding to one drive line (WDRV) is designated as one group. In this case, one write master word line (WMWL) is commonly connected to the gate of multiple transistors (WT1) corresponding to multiple groups. Additionally, one read master word line (RMWL) is commonly connected to the gate of multiple transistors (RT1) corresponding to multiple groups. Furthermore, one non-select master word line (bWMWL) is commonly connected to the gate of multiple transistors (WT2) corresponding to multiple groups. One write master word line (WMWL) is commonly configured for the multiple write word lines (WWL) corresponding to multiple groups. One read master word line (RMWL) is commonly configured for the multiple read word lines (RWL) corresponding to multiple groups.

[0048] One end of the write word line WWL is connected to the drive line WDRV via transistor WT1, and the other end is connected to the non-write voltage line VUW via transistor WT2. On the other hand, one end of the read word line RWL is connected to the drive line WDRV via transistor RT1, but the other end is not connected to any transistor or drive line.

[0049] Figure 3 This is a diagram illustrating a configuration example of the gain unit memory in the first embodiment. Figure 3 In the text, the configuration relationship between the storage unit MC and the global bit lines RGBL and WGBL is explained. Figure 2A The configuration shown is reversed in the Z direction. However, Figure 3 The composition can be related to Figure 2A They have the same composition.

[0050] Memory cell MCa(m) is configured corresponding to the intersection of read word line RWLa and read bit line RBL(m) and the intersection of write word line WWLa and write bit line WBL(m). Memory cell MCa(n) is configured corresponding to the intersection of read word line RWLa and read bit line RBL(n) and the intersection of write word line WWLa and write bit line WBL(n). Memory cells MCa(m) and MCa(n) are located at... Figure 3 It is shown in the middle with a dashed box surrounding the "black dot".

[0051] The memory cell MCb(m) is configured corresponding to the intersection of the read word line RWLb and the read bit line RBL(m) and the write word line WWLb and the write bit line WBL(m). The memory cell MCb(n) is configured corresponding to the intersection of the read word line RWLb and the read bit line RBL(n) and the write word line WWLb and the write bit line WBL(n). The memory cells MCb(m) and MCb(n) are... Figure 3 The image is shown within a dashed box enclosing the "black triangle". m and n can be any integers. Figure 3 The diagram shows the configuration corresponding to columns m and n, but configurations corresponding to three or more columns can be set.

[0052] A column is a unit that can be selected via the column selection signal (CSL) during read and write operations. Each column can read or write 1 bit of data at a time. Multiple columns of data that can be read or written simultaneously are called a "page".

[0053] Multiple readout bit lines RBL(m) are connected to the sense amplifier SA(m) via multiple transistors RTbl(m).

[0054] Multiple readout bit lines RBL(n) are connected to the sense amplifier SA(n) via multiple transistors RTbl(n).

[0055] The detection unit SAC includes multiple sensing amplifiers SA(m) and SA(n). The number of sensing amplifiers included in the detection unit SAC is not limited. In the following description, configurations marked with (m) will be explained, and descriptions of configurations marked with (n) may sometimes be omitted. Furthermore, when not distinguishing between m and n, descriptions of (m) and (n) may sometimes be omitted.

[0056] Furthermore, m represents the column number of the multiple memory cell groups that share global bit lines WGBL(m) and RGBL(m). n represents the column number of the multiple memory cell groups that share global bit lines WGBL(n) and RGBL(n).

[0057] The sense amplifier SA is configured corresponding to each read global bit line RGBL. That is, the sense amplifier SA is configured for each column. For example, the sense amplifier SA(m) is connected to its corresponding read global bit line RGBL(m), but not to the write global bit line WGBL(m). The input of the sense amplifier SA(m) is connected to the corresponding read global bit line RGBL(m). The output of the sense amplifier SA(m) is connected to the latch circuit LAT(m) and the transistor Tref(m).

[0058] The REFC update unit includes multiple transistors Tref(m) and Tref(n), and multiple inverters INref(m) and INref(n).

[0059] Both the transistor Tref and the inverter INref are configured corresponding to the write global bit line WGBL or the sense amplifier SA. That is, the pair formed by the transistor Tref and the inverter INref is configured for each column. For example, the transistor Tref(m) and the inverter INref(m) are connected in series between the output of the corresponding sense amplifier SA(m) and the write global bit line WGBL(m). The transistor Tref(m) and the latch circuit LAT(m) are connected in parallel between the output of the corresponding sense amplifier SA(m) and the write global bit line WGBL(m). The inverter INref(m) is connected between the corresponding transistor Tref(m) and the write global bit line WGBL(m). The transistor Tref(m) can be, for example, an n-type MOSFET. The inverter INref(m) can be, for example, a CMOS (Complementary MOS).

[0060] One end (e.g., the drain) of transistor Tref(m) is connected to the output of sense amplifier SA(m). In this embodiment, one end of transistor Tref(m) is connected to the non-inverting signal output of sense amplifier SA(m). The other end (e.g., the source) of transistor Tref(m) is connected to the input of inverter INref(m). The gate of transistor Tref(m) is connected to the signal line that transmits the update signal REF. The update signal REF is a signal activated during the update operation.

[0061] The input of the inverter INref(m) is connected to the other end of the transistor Tref(m). The output of the inverter INref(m) is connected to the global write bit line WGBL(m).

[0062] Therefore, transistor Tref(m) and inverter INref(m) can directly write the read data detected by sense amplifier SA(m) back to the write global bit line WGBL(m) without going through latch circuit LAT(m) and sense amplifier SA(m). That is, in the update operation, transistor Tref(m) and inverter INref(m) function as bypass paths.

[0063] In this embodiment, transistor Tref(m) receives a non-inverted signal of the read data from sense amplifier SA(m). Inverter INref(m) outputs the read data in an inverted manner. Thus, the inverted signal of the read data is transmitted to the global bit line WGBL(m). Figure 1 The storage unit MC and the sensing node SN transmit data with the opposite logic. Figure 1The storage cell MC outputs a voltage level that is logically opposite to the voltage level of the sensing node SN. Therefore, the write-back of the read data is completed normally by writing the logically opposite data back to the sensing node SN.

[0064] The transistor Tref(n) and the inverter INref(n) have the same configuration as the sense amplifier SA(n) and the write global bit line WGBL(n), and also function as bypass paths.

[0065] The latch unit LATC includes multiple latch circuits LAT(m) and LAT(n). Each latch circuit LAT is configured corresponding to either the write global bit line WGBL or the sense amplifier SA. That is, each latch circuit LAT is configured for each column. For example, a latch circuit LAT(m) is connected between the output of the corresponding sense amplifier SA(m) and the write global bit line WGBL(m). In this embodiment, the latch circuit LAT(m) is connected to the output of the non-inverting signal of the sense amplifier SA(m) and receives the non-inverting signal of the read data.

[0066] The latch circuit LAT(m) operates based on control signals LTI, LTO, and column select signal CSL(m). Control signal LTI is the signal that inputs read data from the sense amplifier SA(m) into the latch circuit LAT(m). Control signal LTO is the signal that outputs write data fetched from the external source from the latch circuit LAT(m) to the write global bit line WGBL(m). Column select signal CSL(m) is the signal that outputs latched read data to the input / output signal line LIO, or the signal that fetches write data into the latch circuit LAT(m). Furthermore, the signal lines for the update signal REF, control signals LTI and LTO, and input / output signal line LIO are commonly provided for each column in the detection unit SAC, update unit REFC, and latch unit LATC.

[0067] Figure 4 This is a circuit diagram illustrating an example of the internal structure of a latch circuit. Furthermore, the internal structure of latch circuit LAT(n) is the same as that of latch circuit LAT(m), so its description is omitted.

[0068] The latch circuit LAT(m) includes transistors Tlti, Tlto, Tlio and inverters INlat1 and INlat2.

[0069] One end of transistor Tlti (e.g., the drain) is connected to the output of sense amplifier SA(m). The other end of transistor Tlti (e.g., the source) is connected to the input (node ​​Nsa) of inverter INlat1 and the output of inverter INlat2. The gate of transistor Tlti is connected to the signal line of control signal LTI.

[0070] One end of transistor Tlto (e.g., the drain) is connected to the output (node ​​bNsa) of inverter INlat1 and the input of inverter INlat2. The other end of transistor Tlto (e.g., the source) is connected to the write global bit line WGBL(m). The gate of transistor Tlto is connected to the signal line of control signal LTO.

[0071] One end (e.g., the drain) of transistor Tlio is connected to the input (node ​​Nsa) of inverter INlat1 and the output of inverter INlat2. The other end (e.g., the source) of transistor Tlio is connected to the input / output signal line LIO. The gate of transistor Tlio is connected to the signal line of the column selection signal CSL(m), which selectively connects one of the multiple latch circuits LAT to the input / output signal line LIO.

[0072] Transistors Tlti, Tlto, and Tlio can be constructed, for example, from n-type MOSFETs.

[0073] Inverters INlat1 and INlat2 form a latching circuit by connecting the input of one to the output of the other. For example, the input of inverter INlat1 and the output of inverter INlat2 are connected at node Nsa. The output of inverter INlat1 and the input of inverter INlat2 are connected at node bNsa. Inverters INlat1 and INlat2 can be constructed using CMOS.

[0074] Node Nsa holds the non-inverted signal of the data from the sense amplifier SA(m). Node bNsa holds the logic opposite to that of node Nsa (the inverted signal of the data from the sense amplifier SA(m)).

[0075] During the readout operation, when the control signal LTI is activated to a high level voltage, the transistor Tlti becomes on (connected), and the readout data from the sensing amplifier SA(m) is stored in the inverters INlat1 and INlat2.

[0076] When the column select signal CSL(m) is activated to a high level, transistor Tlio is turned on, and the read data stored by cross-coupled inverters INlat1 and INlat2 is transmitted to the input / output signal line LIO. This allows the read data to be output to the outside.

[0077] Additionally, when the control signal LTO is activated to a high level, the transistor Tlto is turned on, and the read data stored by inverters INlat1 and INlat2 is transmitted to the write global bit line WGBL(m). This allows the read data to be written back to memory cells MCa(m) or MCb(m).

[0078] When the control signal LTI is activated to a high level, the read data from the sense amplifier SA is stored by inverters INlat1 and INlat2. During the write operation, the column select signal CSL(m) is then activated to a high level, and the write data from the input / output signal line LIO is transmitted to inverters INlat1 and INlat2, updating the stored data in inverters INlat1 and INlat2.

[0079] Subsequently, the control signal LTO is activated to a high level, and the write data stored by inverters INlat1 and INlat2 is transmitted to the write global bit line WGBL(m). This allows the write data to be written to memory cells MCa(m) or MCb(m).

[0080] Furthermore, the data transferred from the latch circuit LAT(m) to the write global bit line WGBL(m) is inverted data, logically opposite to the read data from the sense amplifier SA(m) or the write data from the input / output signal line LIO. This is because, from Figure 1 The read data transmitted from the storage cell MCa(m) or MCb(m) to the read bit line RBL(m) is logically opposite to the data stored in the sensing node SN(m).

[0081] During the update operation, when the update signal REF is activated to a high level, the transistor Tref(m) is turned on. Consequently, the read data from the sense amplifier SA(m) is inverted by the inverter INref(m) and transmitted to the write global bit line WGBL(m). At this time, the update unit REFC transmits the read data to the write global bit line WGBL(m) without passing through the latch circuit LAT(m) and the sense amplifier SA(m). This allows the memory cell MCa(m) or MCb(m) to be updated. The update operation is the process of temporarily reading the data stored in memory cell MCa(m) or MCb(m) and then writing that data back to the same memory cell.

[0082] Furthermore, as described above, the read data transmitted from the storage cell MC to the read bit line RBL is logically opposite to the data stored in the sensing node SN. Therefore, the read data is inverted by the inverter INref before being transmitted to the write global bit line WGBL. Thus, the update operation is completed normally.

[0083] The operation of the sense amplifier SA(n), transistor Tref(n), latch circuit LAT(n), etc. can be the same as the operation of the sense amplifier SA(m), transistor Tref(m), latch circuit LAT(m), etc.

[0084] The array chip containing memory cells MCa(m), MCa(n), MCb(m), and MCb(n) is configured as a semiconductor chip different from the peripheral circuit chip containing the detection unit SAC, the update unit REFC, and the latch unit LATC, and can also be stacked with the peripheral circuit chip. This allows for a reduction in chip area.

[0085] Next, the operation of the gain unit memory in this embodiment will be explained in more detail.

[0086] Figure 5 This is a timing diagram illustrating an operational example of the gain unit memory according to the first embodiment. In this operational example, from... Figure 3 Data is read from storage cells MCa(m) and MCa(n) and written to storage cell MCa(m). Simultaneously, updates are performed on storage cells MCb(m) and MCb(n).

[0087] First, at time t0, an activation instruction ACTa is issued, followed by an update instruction REF at time t1. The activation instruction ACTa is, for example, an instruction used to access memory locations MCa(m) and MCa(n) marked with index "a". The update instruction REF is used to perform the update operation. Here, for convenience, the update operation is performed on memory locations MCb(m) and MCb(n) marked with index "b". The address b to be updated is determined by a counter inside the memory.

[0088] By issuing the activation instruction ACTa, at time t2, the read word line RWLa is activated to a high level. Consequently, at time t3, the data Am of memory cell MCa(m) is transferred to the read bit line RBL(m), and the data An of memory cell MCa(n) is transferred to the read bit line RBL(n). Furthermore, at this time... Figure 3 The readout transistors RTbl(m) and RTbl(n) corresponding to the memory cells MCa(m) and MCa(n) are turned on.

[0089] Next, at time t4, the sensing amplifier SA(m) detects and amplifies the data Am. The sensing amplifier SA(n) detects and amplifies the data An.

[0090] Next, at time t5, when the control signal LTI is activated to a high level, the transistor Tlti (refer to) of the latch circuits LAT(m) and LAT(n)... Figure 4The latch circuits LAT(m) and LAT(n) are connected. Therefore, at time t6, the latch circuits LAT(m) and LAT(n) acquire and latch the data Am and An, respectively. At time t7, when the control signal LTI fails to a low level, the transistor Tlti of the latch circuits LAT(m) and LAT(n) is disconnected. Thus, the latch circuits LAT(m) and LAT(n) are electrically disconnected from the sense amplifiers SA(m) and SA(n). At this time, transistors Tlio and Tlto also remain disconnected. Therefore, the latch circuits LAT(m) and LAT(n) store the data Am and An at node Nsa, respectively. The latch circuits LAT(m) and LAT(n) hold the inverted signals of the data Am and An at node bNsa.

[0091] At time t8, when the read word line RWLa fails to a low level, the memory cells MCa(m) and MCa(n) are electrically disconnected from the read bit lines RBL(m) and RBL(n). At this time, the latch circuits LAT(m) and LAT(n), while holding data Am and An, are electrically disconnected from the sense amplifiers SA(m) and SA(n). Therefore, the sense amplifiers SA(m) and SA(n) can operate independently of the latch circuits LAT(m) and LAT(n). Consequently, the read operation of the latches LAT(m) and LAT(n) and the update operation of the sense amplifiers SA(m) and SA(n) can then be performed simultaneously and in parallel.

[0092] (The read operation of data Am and An from latches LAT(m) and LAT(n)) At time t9, a read command RED(m) is issued. Therefore, at time t11, the column select signal CSL(m) is activated to a high level. Figure 4 The transistor Tlio of the latch circuit LAT(m) is turned on. When transistor Tlio is turned on, the data Am latched in the latch circuit LAT(m) is output to the input / output signal line LIO. Thus, from t11 to t15, the data Am is transmitted to the input / output signal line LIO, and from t18 to t19, it is read out as data Qm.

[0093] At time t13, a read command RED(n) is issued. Consequently, at time t14, the column select signal CSL(m) is deactivated to a low level, and the column select signal CSL(n) is activated to a high level. Therefore, Figure 4The transistor Tlio of the latch circuit LAT(m) is turned off, and the transistor Tlio of the latch circuit LAT(n) is turned on. When transistor Tlio is turned on, the data An latched in the latch circuit LAT(n) is output to the input / output signal line LIO. Thus, from t15 to t16, the data An is transmitted to the input / output signal line LIO. At t16, when the column select signal CSL(n) goes low, the output of data An from the latch circuit LAT(n) to the input / output signal line LIO ends. From t19 to t21, the data An is read out as data Qn.

[0094] (Update operations of memory cells MCb(m) and MCb(n)) On the other hand, with the issuance of the update instruction REF, after the read word line RWLa is deactivated at t8, the read word line RWLb is activated to a high level voltage at t10. Therefore, at t11, the data Bm of memory cell MCb(m) is transferred to the read bit line RBL(m). The data Bn of memory cell MCb(n) is transferred to the read bit line RBL(n). Furthermore, Figure 3 The read transistors RTbl(m) and RTbl(n) corresponding to the memory cells MCb(m) and MCb(n) are turned on. At this time, since the read word line RWLa is disabled, the memory cells MCa(m) and MCa(n) are electrically disconnected from the read global bit lines RGBL(m) and RGBL(n). Therefore, it is not a problem to transfer the data Bm and Bn of the memory cells MCb(m) and MCb(n) to the read global bit lines RGBL(m) and RGBL(n).

[0095] Next, at t12, the sensing amplifier SA(m) detects and amplifies the data Bm. The sensing amplifier SA(n) detects and amplifies the data Bn.

[0096] Next, at t14, when the update signal REF is activated to a high level, transistors Tref(m) and Tref(n) (refer to...) Figure 4 The signal is turned on. Therefore, the data Bm detected by the sense amplifier SA(m) is transmitted to the write bit line WBL(m) via the transistor Tref(m) and the inverter INref(m). That is, the data Bm detected by the sense amplifier SA(m) is transmitted from the sense amplifier SA(m) to the write bit line WBL(m) via the latch circuit LAT(m). The data Bn detected by the sense amplifier SA(n) is transmitted to the write bit line WBL(n) via the transistor Tref(n) and the inverter INref(n). That is, the data Bn detected by the sense amplifier SA(n) is transmitted from the sense amplifier SA(n) to the write bit line WBL(n) via the latch circuit LAT(n). Furthermore, at this time, Figure 3The write transistors WTbl(m) and WTbl(n) corresponding to the memory cells MCb(m) and MCb(n) are turned on.

[0097] At time t20, when the write word line WWLb is activated to a high level, the memory cells MCb(m) and MCb(n) (refer to...) Figure 3 transistor MW1 (reference) Figure 1 The connection is established. Data Bm is then written back to the sensing node SN of storage cell MCb(m). Data Bn is written back to the sensing node SN of storage cell MCb(n). The write-back (update operation) of storage cells MCb(m) and MCb(n) is performed at t25 until the update signal REF and the write word line WWLb become low (just before pre-charging begins).

[0098] The update operation for memory cells MCb(m) and MCb(n) can be performed after the data Am and An of the memory cells MCa(m) and MCa(n) being read are latched into the latch circuits LAT(m) and LAT(n), and the control signal LTI and the read word line RWLa are deactivated. Even when the latch circuits LAT(m) and LAT(n) are outputting data Am and An to the outside (e.g., t11 to t21), the update operation for memory cells MCb(m) and MCb(n) can be performed (e.g., t14 to t25). That is, this embodiment can perform the read operation and the update operation in an overlapping manner.

[0099] (Write operation to memory cell MCa(m)) In this embodiment, at t17, a write command WRT(m) is issued for memory cell MCa(m). With the issuance of the write command, data Dm is retrieved at t22 to t23.

[0100] Between t23 and t24, data Dm is transmitted as data Awm to the input / output signal line LIO. Additionally, when the column select signal CSL(m) is activated to a high level, data Awm is latched into the latch circuit LAT(m). Therefore, at t23, the read data Am stored in the latch circuit LAT(m) is written to and updated with data Awm.

[0101] At time t24, when the column select signal CSL(m) goes low, the latch circuit LAT(m) saves the written data Awm.

[0102] At time t25, the update operation ends. Next, when the precharge command PRE is issued to perform a write-back on the sensing nodes SN of memory cells MCa(m) and MCa(n) and to precharge the write bit lines WBL(m) and WBL(n), the control signal LTO and the write word line WWLa are activated to a high level at time t26. Consequently, the transistor Tlto (refer to...) of the latch circuits LAT(m) and LAT(n)... Figure 4 Connect.

[0103] At time t26, the latch circuit LAT(m) transmits the inverted signal of the write data Awm to the write bit line WBL(m). Thus, the inverted signal of the write data Awm is stored in the sensing node SN of the memory cell MCa(m). At this time, Figure 3 The write transistor WTbl(m) corresponding to the memory cell MCa(m) is turned on. In this case, the data read from the memory cell MCa(m) becomes the non-inverted signal of the data Awm.

[0104] At time t26, the latch circuit LAT(n) directly stores the read data An, thus transmitting the inverted signal of data An to the write bit line WBL(n). Consequently, the inverted signal of data An is written back to the sensing node SN of the memory cell MCa(n). At this time, Figure 3 The write transistor WTbl(n) corresponding to the memory cell MCa(n) is turned on. Furthermore, in this case, the data read from the memory cell MCa(n) becomes a non-inverted signal of data An.

[0105] The update operation can overlap with the period during the write operation where the write data Awm is latched to the latch circuit LAT(m) until the control signal LTO is activated (e.g., t23 to t26). However, in the precharge operation, the update operation must end when the control signal LTO is activated (t26).

[0106] As described above, in the gain unit memory of this embodiment, the sense amplifier SA is connected to the read global bit line RGBL, but not directly connected to the write global bit line WGBL. Therefore, the sense amplifier SA detects the data in the memory cell MC, but is not used for writing or writing back data.

[0107] On the other hand, the transistor Tref of the update unit REFC is located between the output of the sense amplifier SA and the write global bit line WGBL. Therefore, during the update operation, the data detected by the sense amplifier SA can be bypassed to the write global bit line WGBL via the transistor Tref and written back to the original memory cell MC. That is, the transistor Tref functions as a bypass path during the update operation.

[0108] The latch circuit LAT and the transistor Tref are connected in parallel between the output of the sense amplifier SA and the write global bit line WGBL. The latch circuit LAT can temporarily store the data detected by the sense amplifier SA. The data stored in the latch circuit LAT can also be output to the outside via the input / output signal line LIO, and write data can be retrieved from the outside via the input / output signal line LIO. The write data retrieved by the latch circuit LAT can be written to the memory cell MC via the write global bit line WGBL. Thus, read and write operations can be realized.

[0109] With this configuration, the gain unit memory can perform detection and update operations via the sense amplifier SA and transistor Tref during the data retention period held by the latch circuit LAT. This is because, during the retention period, the sense amplifier SA and transistor Tref are electrically isolated from the latch circuit LAT, thus enabling them to operate independently of the latch circuit LAT without affecting the data stored in the LAT. At this time, the latch circuit LAT can read data to the outside according to a read command, or retrieve write data from the outside to update the stored data according to a write command, without being affected by the update operation.

[0110] In this way, operating in parallel with the latch circuit LAT, the sense amplifier SA can detect the data in the memory cell MC and enable the transistor Tref to write the detected data back to the same memory cell MC. That is, the sense amplifier SA and the transistor Tref can perform the update operation in parallel with the operation of the latch circuit LAT.

[0111] For example, in Figure 5 In the process, after the latch circuit LAT stores the read data (t7), during the storage period until the data (read data or write data) stored in the latch circuit LAT is written back or written to the memory cell MC (t26), the sense amplifier SA and the transistor Tref can perform update operations (t14~t25). That is, during the storage period, the sense amplifier SA can detect the data of the memory cell MC that is the target of the update operation. In addition, during the storage period, the transistor Tref is turned on by the update signal REF, thereby enabling the data detected by the sense amplifier SA to be written from the sense amplifier SA back to the memory cell MC that is the target of the update operation without passing through the latch circuit LAT. During the storage period, the latch circuit LAT is electrically isolated from the read global bit line RGBL and the write global bit line WGBL, so it is not a problem even if the sense amplifier SA and the transistor Tref perform update operations independently.

[0112] Conversely, during the periods when the latch circuit LAT is connected to the read global bit line RGBL (during periods t5-t7 when the control signal LTI is activated), and during the periods when the latch circuit LAT is connected to the write global bit line WGBL (during periods t26-t1 when the control signal LTO is activated), the transistor Tref is in the off state. That is, the transistor Tref is in the off state when either transistor Tlti or Tlto in the latch circuit LAT is turned on. This suppresses conflicts between the data Bm and Bn generated by the update operation and other read data Am, An or write data Awm in the read global bit line RGBL and write global bit line WGBL.

[0113] Furthermore, the update operation can also be performed on the memory cell MC that is being read from or written to. In this case, after the update operation, the data stored in the latch circuit LAT is written back or written to the updated memory cell MC without causing any problems.

[0114] In this embodiment, the gain unit memory can perform update operations in an overlapping manner by the detection unit SAC and the update unit REFC during the read or write operations of the latch circuit LAT. Therefore, the situation where the read and write operations can be performed is less restricted by the update operation, and the execution bandwidth can be increased.

[0115] (Second Implementation) Figure 6 This is a timing diagram illustrating an operational example of the gain unit memory in the second embodiment. Furthermore, the configuration of the second embodiment can be the same as that of the first embodiment. In the second embodiment, during the period when the sense amplifier SA detects data in the memory cell MCa, the latch circuit LAT writes the data back or writes it to the memory cell MCc.

[0116] In the first embodiment, when data is detected by the sensing amplifier SA during the readout operation, the readout global bit line RGBL is used, but the write global bit line WGBL is not used.

[0117] Therefore, in the second embodiment, when the data of memory cell MCa is detected by the sense amplifier SA during the readout operation, the latch circuit LAT writes the data to memory cell MCc via the write global bit line WGBL. Although not illustrated, memory cell MCc corresponds to the same global bit lines RGBL and WGBL as memory cell MCa, belonging to the same column but a different memory cell. Memory cell MCc, like memory cells MCa and MCb, is provided in each pair formed by global bit lines RGBL and WGBL (i.e., each of columns m and n). Memory cell MCc(m) belongs to column m, and memory cell MCc(n) belongs to column n.

[0118] For example, first, at time t0, an activation instruction ACTa is issued, and a precharge instruction PREc is issued. At time t1, an update instruction REF is issued. The operation of the gain unit memory based on the activation instruction ACTa and the update instruction REF is the same as that in the first embodiment.

[0119] Furthermore, at time t0, the latch circuits LAT(m) and LAT(n) store the predetermined data to be written back or written to the memory cell MCc, based on the actions performed before t0. The precharge instruction PREc is used for convenience to perform a write operation on the memory cell MCc, which is an instruction to precharge the write bit lines WBL(m) and WBL(n), and is issued at the address c stored in the memory.

[0120] When the precharge command PREc is issued, at time t2, the control signal LTO and the write word line WWLc are activated to a high level. Consequently, the latch circuits LAT(m) and LAT(n) are connected to the write global bit lines WGBL(m) and WGBL(n), respectively, transmitting and storing the data Cm and Cn. Thus, the data Cm from the latch circuit LAT(m) is written to the memory cell MCc(m). The data Cn from the latch circuit LAT(n) is written to the memory cell MCc(n). At this time, the write transistor WTbl(m) corresponding to the memory cell MCc(m) becomes on, and the write transistor WTbl(n) corresponding to MCc(n) becomes on.

[0121] At time t4_1, when the write word line WWLc fails to a low level voltage, the memory cells MCc(m) and MCc(n) are electrically separated from the write global bit lines WGBL(m) and WGBL(n) while storing data Cm and Cn respectively.

[0122] Additionally, at time t8, when the control signal LTO fails to a low level, the latch circuits LAT(m) and LAT(n) are electrically separated from the write global bit lines WGBL(m) and WGBL(n). Therefore, the latch circuits LAT(m) and LAT(n) can store data from different memory cells MCa or MCb within the same column, or can store data written from external sources.

[0123] On the other hand, by issuing the activation command ACTa, during t2 to t8, the data Am and An of the memory cells MCa(m) and MCa(n) are detected by the sense amplifiers SA(m) and SA(n) via the readout global bit lines RGBL(m) and RGBL(n).

[0124] At time t9, when the control signal LTI is activated, the latch circuits LAT(m) and LAT(n) are connected to the global bit lines RGBL(m) and RGBL(n) to retrieve the data Am and An.

[0125] The read, write, and update operations after t9 can be the same as those after t9 in the first embodiment. Therefore, the second embodiment can achieve the same effect as the first embodiment.

[0126] Furthermore, in the second embodiment, during the detection period (t0~t9) before the data Am and An of the memory cells MCa(m) and MCa(n) are detected by the sensing amplifier SA and stored by the latching circuits LAT(m) and LAT(n), the latching circuits LAT(m) and LAT(n) store the data Cm and Cn of the memory cells MCc(m) and MCc(n). Moreover, during this detection period, the latching circuits LAT(m) and LAT(n) write the data Cm and Cn back to the memory cells MCc(m) and MCc(n).

[0127] Alternatively, during the detection period, latch circuits LAT(m) and LAT(n) store data to be written to memory cells MCc(m) and MCc(n). Furthermore, during this detection period, latch circuits LAT(m) and LAT(n) write the data to memory cells MCc(m) and MCc(n).

[0128] In this way, in the second embodiment, the detection period (t0 to t9) of data from storage cells MCa(m) and MCa(n) can be overlapped with the write-back period (or write period) (t2 to t8) of data written back to different storage cells MCc(m) and MCc(n) that are in the same column as storage cells MCa(m) and MCa(n). Therefore, the second embodiment can further accelerate the read and write operations.

[0129] (Third Implementation) Figure 7 This diagram illustrates a configuration example of the gain unit memory according to the third embodiment. In the third embodiment, transistor Tref is connected between the output of the inverted signal of the sense amplifier SA, SABO, and the write global bit line WGBL. Transistor Tref is directly connected to the write global bit line WGBL. Therefore, details are omitted. Figure 3 The inverter INref. Other configurations in the third embodiment can be the same as in the first embodiment.

[0130] The transistor Tref is connected to the output of the inverted signal of the sense amplifier SA, SABO. Therefore, the inverted signal of the readout data is transmitted to the write global bit line WGBL. Thus, the third embodiment eliminates the need for the inverter INref, but achieves the same effect as the first embodiment. The third embodiment can also be combined with the second embodiment.

[0131] Figure 8This is a circuit diagram illustrating an example of the configuration of a sense amplifier. An actuation amplifier circuit AMP is provided between the non-inverting signal output section SAO and the inverting signal output section SABO. The actuation amplifier circuit AMP compares the reference voltage Vref with the readout data from the global readout bit line RGBL, amplifies their difference, and outputs it from the output sections SAO and SABO.

[0132] For example, when the voltage of the read data is higher than the reference voltage Vref, a high-level voltage is output from the output unit SAO as a non-inverting signal, and a low-level voltage is output from the output unit SABO as an inverting signal. When the voltage of the read data is lower than the reference voltage Vref, a low-level voltage is output from the output unit SAO as a non-inverting signal, and a high-level voltage is output from the output unit SABO as an inverting signal.

[0133] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0134] [Explanation of Symbols]

[0135] MC: Storage Unit

[0136] MW1, MR1, MR2, Tlti, Tlto, Tlio: Transistors

[0137] WWL: Write to word line

[0138] WBL: Write Bit Line

[0139] RWL: Readout Word Line

[0140] RBL: Readout bit line

[0141] WGBL: Write Global Bitline

[0142] RGBL: Read global bit lines

[0143] SAC: Testing Department

[0144] SA: Sensing Amplifier

[0145] REFC: Update Department

[0146] Tref: transistor

[0147] INref, INlat1, INlat2: Inverters

[0148] LATC: Latching Unit

[0149] LAT: Latch circuit.

Claims

1. A semiconductor memory device comprising: Multiple first data lines and multiple first control lines are used for writing data; Multiple second data lines and multiple second control lines are used for reading data; A plurality of memory cells include a first transistor, a second transistor, and a third transistor. The gate of the first transistor is connected to any one of the plurality of first control lines and one end is connected to any one of the plurality of first data lines. The gate of the second transistor is connected to any one of the plurality of second control lines and one end is connected to any one of the plurality of second data lines. The gate of the third transistor is connected to the other end of the first transistor and stores data from the first data lines. One end is connected to the other end of the second transistor and becomes in an on state according to the data. The third data line is provided corresponding to the plurality of first data lines; The fourth data line is provided corresponding to the plurality of second data lines; A detection circuit is provided corresponding to the third or fourth data line, and an input section is connected to the fourth data line to detect the data; A storage circuit, corresponding to the third or fourth data line, is disposed between the output of the detection circuit and the third data line, and stores the data detected by the detection circuit; and The fourth transistor, corresponding to the third or fourth data line, is disposed between the output of the detection circuit and the third data line.

2. The semiconductor memory device according to claim 1, further comprising an inverter circuit, the inverter circuit being disposed in series with the fourth transistor between the output of the detection circuit and the third data line. The detection circuit includes a first output section and a second output section. The first output section outputs the data from the fourth data line in a non-inverted state, and the second output section outputs the data from the fourth data line in an inverted state. The fourth transistor is connected to the first output of the detection circuit.

3. The semiconductor memory device according to claim 1, wherein the detection circuit includes a first output section and a second output section, the first output section outputting data from the fourth data line in a non-inverted state, and the second output section outputting data from the fourth data line in an inverted state. The fourth transistor is connected between the second output section of the detection circuit and the third data line.

4. The semiconductor memory device of claim 3, wherein the fourth transistor is directly connected to the third data line.

5. The semiconductor memory device according to any one of claims 2 to 4, wherein the storage circuit is connected between the first output of the detection circuit and the third data line.

6. The semiconductor memory device according to claim 1, wherein the fourth transistor is in an on state during an update operation of reading data from the memory cell and writing the data back to the same memory cell.

7. The semiconductor memory device of claim 1, wherein the fourth transistor is in a non-conducting state during the period when the storage circuit is electrically connected to the detection circuit or the third data line.

8. The semiconductor memory device of claim 1, wherein the storage circuitry comprises: Two inverters are connected between nodes 1 and 2, with the input of one inverter connected to the output of the other. The fifth transistor is disposed between the first node and the detection circuit; The sixth transistor is disposed between the input / output signal line that inputs or outputs the data from the outside and the first node; as well as The 7th transistor is disposed between the 2nd node and the 3rd data line.

9. The semiconductor memory device according to claim 8, wherein in the storage circuit, The fifth transistor becomes conductive when acquiring data from the detection circuit. The sixth transistor is turned on when transmitting the stored data to the input / output signal line or when retrieving data from the input / output signal line. The seventh transistor becomes conductive when transmitting the stored data to the third data line.

10. The semiconductor memory device according to claim 8 or 9, wherein the fourth transistor is in a non-conducting state when the fifth or seventh transistor is in a conducting state.

11. The semiconductor memory device of claim 8 or 9, wherein the gate of the sixth transistor is connected to a select signal line, the select signal line selectively connecting one of the plurality of storage circuits to the input / output signal line.

12. The semiconductor memory device according to claim 1, wherein after the storage circuit stores data of the first memory cell, which is the object of data readout, and before the data stored in the storage circuit is written back to the first memory cell, the detection circuit detects data of the second memory cell, which is the object of an update operation, the fourth transistor becomes on, the data detected by the detection circuit is transmitted to the third data line, and written back to the second memory cell.

13. The semiconductor memory device of claim 12, wherein the fourth transistor transmits the data detected by the detection circuit to the third data line without passing through the storage circuit.

14. The semiconductor memory device according to claim 1, wherein after the storage circuit stores data of the first memory cell, which is the object of data writing among the plurality of memory cells, and before the updated data in the storage circuit is written to the first memory cell, the detection circuit detects data of the second memory cell, which is the object of the update operation among the plurality of memory cells, the fourth transistor becomes in a conducting state, and transmits the data detected by the detection circuit to the third data line and writes it back to the second memory cell.

15. The semiconductor memory device of claim 14, wherein the fourth transistor transmits the data detected by the detection circuit to the third data line without passing through the storage circuit.

16. The semiconductor memory device of claim 1, wherein after the detection circuit detects data in a first memory cell that is the target of data reading from the plurality of memory cells, and during the period before the data is saved by the saving circuit, the saving circuit saves data in a second memory cell that is different from the first memory cell among the plurality of memory cells and writes the data back to the second memory cell.

17. The semiconductor memory device of claim 1, wherein after the detection circuit detects data in a first memory cell that is the target of data reading from the plurality of memory cells, and during the period before the data is saved by the saving circuit, the saving circuit saves write data to a second memory cell that is different from the first memory cell among the plurality of memory cells, and writes the write data to the second memory cell.

18. The semiconductor memory device according to claim 1, further comprising: A plurality of eighth transistors are disposed between the plurality of first data lines and the third data line; and A plurality of ninth transistors are disposed between the plurality of second data lines and the fourth data line; and The plurality of eighth transistors connect any one of the plurality of first data lines to the third data line. The plurality of ninth transistors connect any one of the plurality of second data lines to the fourth data line.

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