A memristor or gate with no voltage decay and no threshold discrimination

Abstract

This invention discloses a memristor or gate logic unit with no voltage decay and no threshold discrimination. The invention employs a complementary driving topology constructed from a memristor and a MOSFET. The memristor's resistance state switching directly controls the MOSFET's on / off state, resulting in an output level with no voltage decay; high levels are close to the operating power supply, and low levels are close to ground potential. The output level itself directly corresponds to discrete logic "0" and logic "1," eliminating the need for manually preset voltage thresholds or comparators to complete logic interpretation. The circuit structure is simple, with low requirements for device parameter consistency, and it maintains stable output even under low temperature and device characteristic drift environments. It is suitable for low-power, highly robust logic applications such as quantum computing classical control, in-memory computing, and edge computing chips.

Description

Technical Field

[0001] This invention belongs to the field of novel microelectronic devices and digital logic circuits, specifically relating to a memristor or gate circuit with no voltage decay and no threshold discrimination, which can be used as a basic unit of high-performance digital integrated circuits. Background Technology

[0002] As the feature size of integrated circuits continues to shrink, traditional CMOS logic gates face increasingly severe challenges in terms of power consumption and voltage margin. Memristors, with their advantages of nanometer-scale size, non-volatility, low power consumption, and compatibility with CMOS processes, are widely studied for constructing new logic circuits in an attempt to overcome the physical limitations of traditional logic gates.

[0003] However, existing memristor-transistor hybrid logic circuits generally face two inherent problems:

[0004] Threshold voltage decay problem: In a typical memristor-MOSFET series structure, due to the MOSFET's threshold voltage Vth, the output high level can only reach VDD−Vth (for NMOS) or the output low level can only reach |Vth| (for PMOS), failing to achieve rail-to-rail output. This voltage decay accumulates stage by stage in cascading, leading to level degradation, reduced noise margin, and even logic errors. Although some designs use bootstrap circuits or level shifters to mitigate this, these solutions typically introduce clocks, capacitors, or additional control signals, increasing power consumption and area, making them unsuitable as basic logic gate units for large-scale integration.

[0005] Threshold discrimination problem: Even if the output level is not full-scale, many designs still rely on external comparators or preset reference voltages to distinguish logic 0 / 1. This not only increases circuit complexity and power consumption, but also makes the correctness of the discrimination susceptible to the drift of memristor resistance, temperature changes and process fluctuations, resulting in insufficient reliability.

[0006] Therefore, there is an urgent need for an OR gate circuit that can completely eliminate output voltage attenuation without requiring threshold discrimination. Summary of the Invention

[0007] The purpose of this invention is to provide a memristor or gate circuit that has no voltage decay and does not require threshold discrimination, thus completely solving the dual problems of the output level not reaching the power rail (due to voltage decay) and reliance on external threshold discrimination in existing memristor logic circuits, making it suitable for high-performance digital logic systems.

[0008] The OR gate circuit according to the present invention includes an input terminal VA, an input terminal VB, a reference voltage terminal V5, an output terminal VA+B, a power supply, ground, a pull-up resistor R1, a first memristor, a second memristor, and an NMOS transistor. The input terminals VA and VB are respectively connected to the control terminals of the first and second memristors. The output terminals of the first and second memristors and the gate of the NMOS transistor are connected to the output terminal VA+B. The source of the NMOS transistor is grounded, and its drain is connected to one end of the pull-up resistor R1. The other end of the pull-up resistor R1 is connected to the power supply. The circuit controls the conduction state of the MOS transistor through the resistance switching of the memristor, ensuring that the output level does not attenuate and that logic judgment can be directly completed without setting an external threshold discrimination circuit. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an OR gate circuit constructed using memristors according to the present invention.

[0010] Figure 2 This is a logic simulation diagram of the OR gate circuit of the present invention. Detailed Implementation

[0011] To more clearly illustrate the purpose, technical solution, and advantages of this invention, the following detailed description, using schematic diagrams, will provide a comprehensive overview of the specific implementation details. The advantages and features of this invention will be fully demonstrated through the following description and claims. It should be noted that all accompanying drawings are highly simplified and not precisely proportioned; their sole purpose is to aid in understanding the essence of the embodiments of this invention in a visually clear manner. It is hereby stated that the specific embodiments shown herein are merely illustrative of the invention and not intended to limit its scope of application.

[0012] The external power supply configuration of this invention's circuit is as follows: the reference voltage V5 is 5V, and the operating power supply V5 is 5V; the circuit has a built-in fixed resistor parameter: R1=1Ω. The core components are a memristor and a MOSFET. The conduction state of the MOSFET is controlled by switching the resistance state of the memristor, thereby realizing logic operations based on the input signal.

[0013] like Figure 1 As shown, the OR gate circuit of this invention includes input terminal VA, input terminal VB, reference voltage V5, pull-up resistor R1, two memristors (i.e., a first memristor and a second memristor), an NMOS transistor, and output terminal VA+B. Input terminals VA and VB are respectively connected to the control terminals of the two memristors. The common node after the output terminals of the two memristors are shorted to the gate of the NMOS transistor serves as the output terminal VA+B. The source of the NMOS transistor is grounded, and its drain is connected to one end of the 1Ω pull-up resistor R1. The other end of the resistor R1 is connected to the operating power supply V5.

[0014] Its detailed working process is as follows:

[0015] When either input signal VA or VB is high (5V), or both are high (5V): the branch corresponding to the high input level injects current into the common output node through the first memristor and / or the second memristor. Under the influence of the potential difference, the corresponding memristor quickly switches to or maintains a low impedance state (LRS), thereby directly pulling the output terminal VA+B of the common connection and the gate voltage of the NMOS transistor to a full-scale high level (5V), realizing a lossless rail-to-rail logic "1" output. At this time, the gate of the NMOS transistor synchronously obtains sufficient drive voltage and is fully turned on. The current forms a closed loop through the working power supply V5 → pull-up resistor R1 → NMOS transistor → ground, maintaining the charge complementary balance of the overall topology and the level robustness of the output node;

[0016] When input signals VA and VB are both low (0V): both input terminals are at ground potential, and both memristors maintain or switch to a high-impedance state (HRS) under extremely low drive voltage. Because the input terminals provide a strong pull-down ground path, the residual charge on the gates of the output terminals VA+B and the NMOS transistor is rapidly discharged to the input terminals through the high-impedance memristors, reliably and firmly anchoring the common output node potential to ground potential close to 0V. This effectively avoids gate floating and external noise interference, achieving logic "0". At this time, because the gate voltage is much lower than the NMOS transistor's turn-on threshold, the NMOS transistor is completely turned off, and the pull-up resistor circuit is disconnected.

[0017] This enables the OR gate operation of VA+B=A OR B.

[0018] like Figure 2 As shown, Figure 2 The simulation waveforms of the OR gate circuit of this invention under two-channel input pulse excitation are fully displayed. The first part of the waveform is the input voltage VA, the second part is the input voltage VB, and the third part is the curve of the output voltage Vout (corresponding to the output VA+B) changing with time t. The horizontal axis of the system represents time t in milliseconds (ms), and the vertical axis represents the voltage amplitude V in volts (V).

[0019] according to Figure 2 The timing waveform characteristics of multi-channel signals, and the specific logic interpretation and full-amplitude level transformation process are described in detail below:

[0020] During the 0~50ms time period, the input voltages VA=0V and VB=0V. When both inputs are low, the corresponding output voltage Vout is precisely stable at a low level of 0V (corresponding to logic "0").

[0021] Within a 50-100ms timeframe, the input voltage VA jumps to 5V, while VB remains at 0V. Since the single input meets the high-level condition, the corresponding output voltage Vout responds instantaneously, rising to a full-scale high-level state of 5V (corresponding to logic "1").

[0022] During the 100-150ms time period, the input voltage VA remains at a high level of 5V, while VB simultaneously transitions to a high level of 5V. With both inputs reaching a high level, the corresponding output voltage Vout continues to remain stably at a full-range high level of 5V from rail to rail (corresponding to logic "1").

[0023] During the 150-250ms time period, the input voltage VA jumps to 0V, while VB remains at 5V. The input still meets the single-channel high-level condition, and the corresponding output voltage Vout remains at a high level of 5V without attenuation.

[0024] Within a 250-350ms timeframe, the input voltage VA jumps to 5V again, while VB remains at 5V. With both inputs at a high level, the corresponding output voltage Vout continues to remain stably at a high level of 5V.

[0025] Within a 350-400ms timeframe, the input voltage VA jumps to 0V, and VB simultaneously jumps to 0V. At this time, both inputs return to low level simultaneously, satisfying the all-low condition. The corresponding output voltage Vout responds quickly, pulling down and maintaining at a ground potential of 0V (corresponding to logic "0").

[0026] During the 400-450ms time period, the input voltage VA remains at 0V, while VB jumps to 5V. The output voltage Vout then synchronously rises to the full-scale high level of 5V.

[0027] During the 450-500ms timeframe, the input voltage VA jumps back to 5V, forming a double high-level state together with VB (5V). The corresponding output voltage Vout remains locked at the full-scale high level of 5V.

[0028] Figure 2 The simulation waveforms completely and intuitively demonstrate that the OR gate circuit of this invention has accurate, voltage-attenuation-free, and high-tolerance logic phase OR function under various input combinations, proving that the structure can directly complete the cascading expansion of large-scale digital integrated circuits without any external threshold discrimination or level comparison circuit.

[0029] In this invention, all voltage levels and resistance parameters are fixed and unique, and the connection relationship of each branch is clear. The working process relies on the synergistic effect of memristor resistance state switching and MOSFET conduction control. The output terminal only presents two stable levels, high and low. It can directly correspond to logic "1" and "0" without the need for an additional threshold comparison circuit. At the same time, the output level has no MOSFET threshold voltage attenuation and no voltage division attenuation, which meets the application requirements of low complexity and high robustness.

[0030] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A memristor or gate circuit with no voltage decay and no threshold discrimination required, characterized in that, The circuit includes input terminals VA and VB, a reference voltage terminal V5, an output terminal VA+B, a power supply, ground, a pull-up resistor R1, a first memristor, a second memristor, and an NMOS transistor. The conduction state of the MOS transistor is controlled by switching the resistance state of the memristor, ensuring no voltage attenuation in the output level and allowing direct logic judgment without the need for an external threshold discrimination circuit. Input terminals VA and VB are respectively connected to the control terminals of the first and second memristors. The output terminals of the first and second memristors, and the gate of the NMOS transistor, are all connected to the output terminal VA+B. The source of the NMOS transistor is grounded, and its drain is connected to one end of the pull-up resistor R1, while the other end of the pull-up resistor R1 is connected to the power supply.

Images