Non-volatile memory devices with memory cell arrays

Abstract

A non-volatile memory device includes: a memory cell array comprising multiple planes; a page buffer circuit connected to the memory cell array via multiple bit lines; an input / output circuit connected to the page buffer circuit via multiple data lines; control logic circuitry responsive to command control of operations on the planes; a first command-address pad group electrically connected to the control logic circuitry and receiving a first command; and a second command-address pad group electrically connected to the control logic circuitry and receiving a second command. The timing of the first command being received overlaps with the timing of the second command being received during the same period.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0018924, filed February 13, 2025, Korean Patent Application No. 10-2025-0020410, filed February 17, 2025, and Korean Patent Application No. 10-2025-0093103, filed July 10, 2025, all of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor memory devices, and more particularly, to non-volatile memory devices having an array of memory cells. Background Technology

[0004] Semiconductor memory devices are broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices have the advantage of fast read and write speeds, but the disadvantage of losing stored data when the power supply is cut off. On the other hand, non-volatile memory devices retain their data even when the power supply is cut off. Therefore, non-volatile memory devices are used to store data that needs to be retained, regardless of whether power is supplied.

[0005] A representative example of a non-volatile memory device is a flash memory device. Flash memory devices are widely used as storage media for voice and video data in information devices such as computers, mobile phones, smartphones, digital cameras, camcorders, recorders, MP3 players, personal digital assistants (PDAs), handheld PCs, game consoles, fax machines, scanners, and printers. With the increasing number of information devices using non-volatile memory devices as storage devices, improvements in data input / output performance have been proposed. Summary of the Invention

[0006] The embodiments of this disclosure described herein relate to a non-volatile memory device. Specifically, embodiments of this disclosure provide a non-volatile memory device capable of improving data input / output performance.

[0007] Embodiments of this disclosure provide a non-volatile memory device, comprising: a memory cell array including multiple planes; a page buffer circuit connected to the memory cell array via multiple bit lines; an input / output circuit connected to the page buffer circuit via multiple data lines; control logic circuitry that controls operation on the planes in response to commands; a first command-address pad group electrically connected to the control logic circuitry and receiving a first command; and a second command-address pad group electrically connected to the control logic circuitry and receiving a second command. The time during which the first command is received overlaps with the time during which the second command is received.

[0008] The first command includes a first read command requesting a read operation on a first plane in the plane, a first SR command requesting a check whether the read operation corresponding to the first plane has been completed, and a first data output command requesting the output of data read from the first plane. The second command includes a second read command requesting a read operation on a second plane in the plane, a second SR command requesting a check whether the read operation corresponding to the second plane has been completed, and a second data output command requesting the output of data read from the second plane.

[0009] The non-volatile memory device further includes command-address control circuitry electrically connected to a first command-address pad group and a second command-address pad group, and the command-address control circuitry selects at least one plane in the plane to which the first command-address pad group and the second command-address pad group are assigned.

[0010] The command-address control circuit determines the plane in which the first command-address pad group and the second command-address pad group are assigned based on the size of the data.

[0011] When the data size is greater than the reference size, at least two planes in the plane are assigned to the first command-address pad group.

[0012] The command-address line connected to the second command-address pad group is floated.

[0013] When the data size is smaller than the reference size, the first command-address pad group and the second command-address pad group are assigned to different planes within the plane.

[0014] The non-volatile memory device also includes a third command-address pad group electrically connected to the control logic circuit and receiving a third command, and a fourth command-address pad group electrically connected to the control logic circuit and receiving a fourth command, wherein the command-address lines connected to the third command-address pad group and the command-address lines connected to the fourth command-address pad group are floated.

[0015] The non-volatile memory device also includes a third command-address pad group electrically connected to the control logic circuitry and receiving a third command, and a fourth command-address pad group electrically connected to the control logic circuitry and receiving a fourth command. The first command-address pad group, the second command-address pad group, the third command-address pad group, and the fourth command-address pad group are assigned to different planes within the plane.

[0016] In response to a command-address change request received from the memory controller, the command-address control circuit determines the plane in which the first command-address pad group and the second command-address pad group are assigned.

[0017] The command-address change request includes a header and a body, and the body includes address information of the plane to which the first command-address pad group is assigned.

[0018] The command-address change request also includes a logical unit number (LUN) select signal, and the LUN select signal includes address information for the path to which the first command-address pad group is assigned.

[0019] The command-address control circuitry and the memory cell array are arranged on the same die.

[0020] Command-address control circuitry and memory cell arrays are arranged on different dies.

[0021] The non-volatile memory device further includes: a first data pad group electrically connected to an input / output circuit and outputting first data corresponding to a first command; and a second data pad group electrically connected to an input / output circuit and outputting second data corresponding to a second command.

[0022] Embodiments of this disclosure provide a non-volatile memory device including a first chip and a second chip stacked on the first chip. The first chip includes: a first memory cell array including multiple planes; a first page buffer circuit connected to the first memory cell array via multiple bit lines; a first input / output circuit connected to the first page buffer circuit via multiple data lines; a first control logic circuit for controlling operation on the planes in response to a first command; a first command-address pad group electrically connected to the first control logic circuit and electrically connected to the first command-address lines; and a second command-address pad group electrically connected to the first control logic circuit and electrically connected to the second command-address lines. The second chip includes: a second memory cell array including multiple planes; a second page buffer circuit connected to the second memory cell array via multiple bit lines; a second input / output circuit connected to the second page buffer circuit via multiple data lines; a second control logic circuit for controlling operation on the planes in response to a second command; a third command-address pad group electrically connected to the first command-address lines; and a fourth command-address pad group electrically connected to the second command-address lines. The time during which the first command is received via the first command-address line overlaps with the time during which the second command is received via the second command-address line.

[0023] The first die further includes a first command-address control circuit electrically connected to the first command-address line and a second command-address control circuit electrically connected to the second command-address line, and the second die further includes a third command-address control circuit electrically connected to the first command-address line and a fourth command-address control circuit electrically connected to the second command-address line.

[0024] The first and second dies are electrically connected to each other via a pad routing method.

[0025] The first die and the second die are electrically connected to each other via a through-silicon via (TSV).

[0026] Embodiments of this disclosure provide a non-volatile memory device, comprising: a memory cell array including multiple planes; a page buffer circuit connected to the memory cell array via multiple bit lines; an input / output circuit connected to the page buffer circuit via multiple data lines; control logic circuitry responsive to commands to control operations on the planes; a first command-address pad group electrically connected to the control logic circuitry and receiving a first command; a second command-address pad group electrically connected to the control logic circuitry and receiving a second command; and at least one data pad group electrically connected to the input / output circuitry and outputting first data corresponding to the first command and second data corresponding to the second command. The control logic circuitry determines the planes within the planes to which the first command-address pad group and the second command-address pad group are allocated based on the data size in the data output operation.

[0027] Embodiments of this disclosure provide a non-volatile memory device, comprising: a memory cell array including multiple planes; a page buffer circuit connected to the memory cell array via multiple bit lines; an input / output circuit connected to the page buffer circuit via multiple data lines; control logic circuitry responsive to commands to control operations on the planes; a first command-address pad group electrically connected to the control logic circuitry and assigned to a first plane within the planes; a second command-address pad group electrically connected to the control logic circuitry and assigned to a second plane within the planes; a first data pad group electrically connected to the input / output circuitry and assigned to the first plane; and a second data pad group electrically connected to the input / output circuitry and assigned to the second plane.

[0028] The first command-address pad group is further assigned to the third plane in the plane, the second command-address pad group is further assigned to the fourth plane in the plane, the first data pad group is further assigned to the third plane in the plane, and the second data pad group is further assigned to the fourth plane in the plane.

[0029] The non-volatile memory device further includes: a third command-address pad group electrically connected to the control logic circuitry and assigned to a third plane; a fourth command-address pad group electrically connected to the control logic circuitry and assigned to a fourth plane; a third data pad group electrically connected to the input / output circuitry and assigned to the third plane; and a fourth data pad group electrically connected to the input / output circuitry and assigned to the fourth plane.

[0030] The first command-address pad group is further assigned to the third plane within the plane, the second command-address pad group is further assigned to the fourth plane within the plane, and the non-volatile memory device includes a third data pad group assigned to the third plane and a fourth data pad group assigned to the fourth plane.

[0031] The first data pad group is further assigned to the fifth plane in the plane, the second data pad group is further assigned to the sixth plane in the plane, the third data pad group is further assigned to the seventh plane in the plane, the fourth data pad group is further assigned to the eighth plane in the plane, the first command-address pad group is further assigned to the fifth and seventh planes, and the second command-address pad group is further assigned to the sixth and eighth planes.

[0032] The non-volatile memory device also includes a third command-address pad group electrically connected to the control logic circuitry and assigned to the first plane, and a fourth command-address pad group electrically connected to the control logic circuitry and assigned to the second plane.

[0033] The first command-address pad group receives the first command, and the second command-address pad group receives the second command, with the time during which the first command is received overlapping with the time during which the second command is received.

[0034] Embodiments of this disclosure provide a non-volatile memory device, comprising: a first chip and a second chip stacked on the first chip and electrically connected to the first chip via wires. At least one of the first chip and the second chip includes: a memory cell array including a plurality of planes; a page buffer circuit connected to the memory cell array via a plurality of bit lines; an input / output circuit connected to the page buffer circuit via a plurality of data lines; control logic circuitry responsive to commands to control operations on the planes; a first command-address pad group electrically connected to the control logic circuitry and assigned to the first plane; a second command-address pad group electrically connected to the control logic circuitry and assigned to the second plane; a first data pad group electrically connected to the input / output circuitry and assigned to the first plane; and a second data pad group electrically connected to the input / output circuitry and assigned to the second plane.

[0035] The first command-address pad group is further assigned to the third plane within the plane, the second command-address pad group is further assigned to the fourth plane within the plane, the first data pad group is further assigned to the third plane, and the second data pad group is further assigned to the fourth plane.

[0036] The non-volatile memory device further includes: a third command-address pad group electrically connected to the control logic circuitry and assigned to a third plane; a fourth command-address pad group electrically connected to the control logic circuitry and assigned to a fourth plane; a third data pad group electrically connected to the input / output circuitry and assigned to the third plane; and a fourth data pad group electrically connected to the input / output circuitry and assigned to the fourth plane.

[0037] The first command-address pad group is further assigned to the third plane within the plane, the second command-address pad group is further assigned to the fourth plane within the plane, and the non-volatile memory device includes a third data pad group electrically connected to the input / output circuitry and assigned to the third plane, and a fourth data pad group electrically connected to the input / output circuitry and assigned to the fourth plane.

[0038] The first data pad group is further assigned to the fifth plane in the plane, the second data pad group is further assigned to the sixth plane in the plane, the third data pad group is further assigned to the seventh plane in the plane, the fourth data pad group is further assigned to the eighth plane in the plane, the first command-address pad group is further assigned to the fifth and seventh planes, and the second command-address pad group is further assigned to the sixth and eighth planes.

[0039] The non-volatile memory device also includes a third command-address pad group electrically connected to the control logic circuitry and assigned to the first plane, and a fourth command-address pad group electrically connected to the control logic circuitry and assigned to the second plane.

[0040] The first command-address pad group receives the first command, and the second command-address pad group receives the second command, with the time during which the first command is received overlapping with the time during which the second command is received.

[0041] Embodiments of this disclosure provide a non-volatile memory device including a first chip and a second chip stacked on the first chip and electrically connected to the first chip via through-silicon vias (TSVs). At least one of the first chip and the second chip includes: a memory cell array including multiple planes; a page buffer circuit connected to the memory cell array via multiple bit lines; an input / output circuit connected to the page buffer circuit via multiple data lines; control logic circuitry controlling operation on the planes in response to commands; a first command-address pad group electrically connected to the control logic circuitry and assigned to the first plane; a second command-address pad group electrically connected to the control logic circuitry and assigned to the second plane; a first data pad group electrically connected to the input / output circuitry and assigned to the first plane; and a second data pad group electrically connected to the input / output circuitry and assigned to the second plane.

[0042] The first command-address pad group is further assigned to the third plane within the plane, the second command-address pad group is further assigned to the fourth plane within the plane, the first data pad group is further assigned to the third plane, and the second data pad group is further assigned to the fourth plane.

[0043] The non-volatile memory device further includes: a third command-address pad group electrically connected to the control logic circuitry and assigned to a third plane; a fourth command-address pad group electrically connected to the control logic circuitry and assigned to a fourth plane; a third data pad group electrically connected to the input / output circuitry and assigned to the third plane; and a fourth data pad group electrically connected to the input / output circuitry and assigned to the fourth plane.

[0044] The first command-address pad group is further assigned to the third plane within the plane, the second command-address pad group is further assigned to the fourth plane within the plane, and the non-volatile memory device includes a third data pad group assigned to the third plane and a fourth data pad group assigned to the fourth plane.

[0045] The first data pad group is further assigned to the fifth plane in the plane, the second data pad group is further assigned to the sixth plane in the plane, the third data pad group is further assigned to the seventh plane in the plane, the fourth data pad group is further assigned to the eighth plane in the plane, the first command-address pad group is further assigned to the fifth and seventh planes, and the second command-address pad group is further assigned to the sixth and eighth planes.

[0046] The non-volatile memory device further includes a third command-address pad group electrically connected to the control logic circuitry and assigned to a first plane, and a fourth command-address pad group electrically connected to the control logic circuitry and assigned to a second plane.

[0047] Embodiments of this disclosure provide a non-volatile memory device comprising a plurality of chips stacked in a vertical direction. At least one of the chips includes at least one plane, the plane including non-volatile memory, a plurality of command-address pad groups electrically connected to different CA buses, and at least one command-address control circuitry electrically connected to the command-address pad groups and the at least one plane and controlling the electrical connections between the command-address pad groups.

[0048] In the chip, the first chip includes: a first plane including non-volatile memory; a second plane including non-volatile memory; a first command-address pad group electrically connected to a first CA bus via a first CA line; a second command-address pad group electrically connected to a second CA bus via a second CA line; a third command-address pad group electrically connected to a third CA bus via a third CA line; a fourth command-address pad group electrically connected to a fourth CA bus via a fourth CA line; a first command-address control circuit electrically connected to the first plane and the first to fourth command-address pad groups, and selecting CA lines to be assigned to the first plane from the first to fourth CA lines; and a second command-address control circuit electrically connected to the second plane and the first to fourth command-address pad groups, and selecting CA lines to be assigned to the second plane from the first to fourth CA lines.

[0049] In the chip, the second chip includes: a third plane including non-volatile memory; a fourth plane including non-volatile memory; a fifth command-address pad group electrically connected to a first CA bus via a first CA line; a sixth command-address pad group electrically connected to a second CA bus via a second CA line; a seventh command-address pad group electrically connected to a third CA bus via a third CA line; an eighth command-address pad group electrically connected to a fourth CA bus via a fourth CA line; a third command-address control circuit electrically connected to the third plane and the fifth to eighth command-address pad groups, and selecting CA lines to be assigned to the third plane from the first to the fourth CA lines; and a fourth command-address control circuit electrically connected to the fourth plane and the fifth to the eighth command-address pad groups, and selecting CA lines to be assigned to the fourth plane from the first to the fourth CA lines.

[0050] At least one of the first command-address control circuits to the fourth command-address control circuit includes multiple multiplexers.

[0051] At least one of the first to fourth command-address control circuits includes: a first multiplexer connected to a first CA line and a second CA line, and outputting one of the first CA line and the second CA line based on a chip ID; a second multiplexer connected to a third CA line and a fourth CA line, and outputting one of the third CA line and the fourth CA line based on a chip ID; and a third multiplexer connected to the first and second multiplexers, and outputting one of the outputs from the first multiplexer and the output from the second multiplexer.

[0052] The first command-address control circuit assigns the second CA line from the first CA line to the fourth CA line to the first plane; the second command-address control circuit assigns the fourth CA line from the first CA line to the fourth CA line to the second plane; the third command-address control circuit assigns the first CA line from the first CA line to the fourth CA line to the third plane; and the fourth command-address control circuit assigns the third CA line from the first CA line to the fourth CA line to the fourth plane.

[0053] At least two of the following times overlap: a first time during which a first command is received via a first CA bus; a second time during which a second command is received via a second CA bus; a third time during which a third command is received via a third CA bus; and a fourth time during which a fourth command is received via a fourth CA bus.

[0054] At least one of the following sizes—the size of the first data corresponding to the first command, the size of the second data corresponding to the second command, the size of the third data corresponding to the third command, and the size of the fourth data corresponding to the fourth command—is less than the reference size.

[0055] The first command-address control circuit assigns the second CA line from the first CA line to the fourth CA line to the first plane; the second command-address control circuit assigns the second CA line from the first CA line to the fourth CA line to the second plane; the third command-address control circuit assigns the first CA line from the first CA line to the fourth CA line to the third plane; and the fourth command-address control circuit assigns the first CA line from the first CA line to the fourth CA line to the fourth plane.

[0056] The first time during which a first command is received via a first CA bus overlaps with the second time during which a second command is received via a second CA bus.

[0057] The third and fourth CA lines are floated.

[0058] At least one of the first command-address control circuits to the fourth command-address control circuit includes: a first multiplexer connected to the third CA line and the fourth CA line, and outputting one of the third CA line and the fourth CA line based on the chip ID; and a second multiplexer connected to the first CA line and the first multiplexer, and outputting one of the outputs of the first CA line and the first multiplexer.

[0059] The first command-address control circuit assigns the fourth CA line from the first CA line to the fourth CA line to the first plane; the second command-address control circuit assigns the fourth CA line from the first CA line to the fourth CA line to the second plane; the third command-address control circuit assigns the third CA line from the first CA line to the fourth CA line to the third plane; and the fourth command-address control circuit assigns the third CA line from the first CA line to the fourth CA line to the fourth plane.

[0060] The first command-address control circuit assigns the first CA line from the first CA line to the fourth CA line to the first plane; the second command-address control circuit assigns the first CA line from the first CA line to the fourth CA line to the second plane; the third command-address control circuit assigns the first CA line from the first CA line to the fourth CA line to the third plane; and the fourth command-address control circuit assigns the first CA line from the first CA line to the fourth CA line to the fourth plane.

[0061] At least one of the following sizes—the size of the first data corresponding to the first command, the size of the second data corresponding to the second command, the size of the third data corresponding to the third command, and the size of the fourth data corresponding to the fourth command—is greater than the reference size.

[0062] In the chip, the first chip includes: a first plane including non-volatile memory; a second plane including non-volatile memory; a first command-address pad group electrically connected to a first CA bus via a first CA line; a second command-address pad group electrically connected to a second CA bus via a second CA line; a third command-address pad group electrically connected to a third CA bus via a third CA line; a fourth command-address pad group electrically connected to a fourth CA bus via a fourth CA line; and a first command-address control circuit electrically connected to the first plane, the second plane, and the first to fourth command-address pad groups, and selecting a CA line among the first to fourth CA lines to be assigned to at least one of the first plane or the second plane.

[0063] In the chip, the second chip includes: a third plane including non-volatile memory; a fourth plane including non-volatile memory; a fifth command-address pad group electrically connected to a first CA bus via a first CA line; a sixth command-address pad group electrically connected to a second CA bus via a second CA line; a seventh command-address pad group electrically connected to a third CA bus via a third CA line; an eighth command-address pad group electrically connected to a fourth CA bus via a fourth CA line; and a second command-address control circuit electrically connected to the third plane, the fourth plane, and the fifth to eighth command-address pad groups, and selecting, among the first to fourth CA lines, a CA line to be assigned to at least one of the third or fourth plane.

[0064] At least one of the first command-address control circuit or the second command-address control circuit includes at least one NAND gate, at least one OR gate, and at least one multiplexer.

[0065] Embodiments of this disclosure provide a non-volatile memory device including a first chip and a second chip stacked on the first chip and electrically connected to the first chip via wires, wherein at least one of the first chip and the second chip includes: at least one plane including non-volatile memory; a plurality of command-address pad groups electrically connected to different CA buses; and at least one command-address control circuit electrically connected to the command-address pad groups and at least one plane and controlling the electrical connection between the command-address pad groups.

[0066] Embodiments of this disclosure provide a non-volatile memory device including a first chip and a second chip stacked on the first chip and electrically connected to the first chip via a through-silicon via (TSV). At least one of the first chip and the second chip includes: at least one plane including non-volatile memory; a plurality of command-address pad groups electrically connected to different CA buses; and at least one command-address control circuit electrically connected to the command-address pad groups and the at least one plane and controlling the electrical connections between the command-address pad groups.

[0067] Embodiments of this disclosure provide a storage device including a memory controller and any described non-volatile memory device. The memory device can receive commands from the memory controller via multiple command-address buses. The multiple command-address buses can be electrically connected to multiple command-address pad groups. The multiple command-address buses can be electrically connected to the memory controller. A first command-address bus can be electrically connected to a first command-address pad group. A second command-address bus can be electrically connected to a second command-address pad group. The storage device may include multiple command-address buses.

[0068] The duration of command reception can include the time interval during which the command is received. Overlapping command reception durations can include the overlap between time intervals during which the command is received.

[0069] Based on the above, non-volatile memory devices send commands in parallel through multiple command-address buses, thereby improving data input and output performance. Attached Figure Description

[0070] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0071] Figure 1 This is a block diagram illustrating a storage device according to some embodiments of the present disclosure.

[0072] Figure 2A This is a block diagram showing in more detail a non-volatile memory device according to some embodiments of the present disclosure.

[0073] Figure 2B This is a circuit diagram illustrating one of a plurality of memory blocks according to some embodiments of the present disclosure.

[0074] Figure 3A , Figure 3B and Figure 3C This is a diagram illustrating a non-volatile memory device according to an embodiment of the present disclosure.

[0075] Figure 4 This is a view showing a plane, CA pad group, and DQ pad group arranged in a non-volatile memory device according to some embodiments of the present disclosure.

[0076] Figure 5A and Figure 5B This is a diagram illustrating the reduction in command-address overhead and the improvement in data input / output performance according to some embodiments of this disclosure.

[0077] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I , Figure 6J and Figure 6K This is a view showing the plane, CA pad group, and DQ pad group arranged in a non-volatile memory device according to various embodiments of the present disclosure.

[0078] Figure 7This is a block diagram illustrating a storage device according to some embodiments of the present disclosure.

[0079] Figure 8 To show in more detail Figure 7 A block diagram of a non-volatile memory device.

[0080] Figure 9 This is a flowchart illustrating the operation of a non-volatile memory device according to some embodiments of the present disclosure.

[0081] Figure 10 This is a flowchart illustrating the operation of a non-volatile memory device according to some embodiments of the present disclosure.

[0082] Figure 11 This is a view showing a plane, CA pad group, and DQ pad group arranged in a non-volatile memory device according to some embodiments of the present disclosure.

[0083] Figure 12A , Figure 12B and Figure 12C This is a view illustrating command-serial mode and command-parallel mode according to some embodiments of this disclosure.

[0084] Figure 13A , Figure 13B and Figure 13C This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0085] Figure 14 This is a view illustrating a non-volatile memory device formed by a pad routing method according to some embodiments of the present disclosure.

[0086] Figure 15 It is shown Figure 14 A view of the CA control circuit.

[0087] Figure 16 , Figure 17A , Figure 17B , Figure 17C and Figure 17D It shows the use Figure 15 The CA control circuit will Figure 14 A diagram illustrating the operation of setting a non-volatile memory device to enter command-parallel mode.

[0088] Figure 18 This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure.

[0089] Figure 19 , Figure 20A , Figure 20B , Figure 20C and Figure 20DIt shows the use Figure 15 The CA control circuit will Figure 14 A diagram illustrating the operation of setting a non-volatile memory device to enter command-parallel mode.

[0090] Figure 21 This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure.

[0091] Figure 22 It is shown Figure 14 A diagram illustrating an example of a CA control circuit.

[0092] Figure 23 , Figure 24A and Figure 24B It shows the use Figure 22 The CA control circuit will Figure 14 A diagram illustrating the operation of setting a non-volatile memory device to enter command-parallel mode.

[0093] Figure 25 This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure.

[0094] Figure 26 and Figure 27 It shows the use Figure 22 The CA control circuit will Figure 14 A diagram illustrating the operation of setting a non-volatile memory device to enter command-serial mode.

[0095] Figure 28 This is a view showing the electrical connection state of the CA line in command-serial mode according to some embodiments of the present disclosure.

[0096] Figure 29 This is a view illustrating a non-volatile memory device formed by the TSV method according to some embodiments of the present disclosure.

[0097] Figure 30 This is a diagram showing one of the paths to a non-volatile memory device.

[0098] Figure 31 It is shown Figure 29 A view of the CA control circuit.

[0099] Figure 32 , Figure 33A , Figure 33B , Figure 33C and Figure 33D It shows the use Figure 31 The CA control circuit will Figure 29 A diagram illustrating the operation of setting a non-volatile memory device to enter command-parallel mode.

[0100] Figure 34 and Figure 35 It shows the use Figure 31 The CA control circuit will Figure 29 A diagram illustrating the operation of setting a non-volatile memory device to enter command-serial mode.

[0101] Figure 36 , Figure 37 , Figure 38A , Figure 38B and Figure 38C This is a view illustrating operations according to some embodiments of the present disclosure, wherein a command is received requesting the reallocation of CA pad groups and the allocation of CA pad groups is changed in response to the request.

[0102] Figure 39 This is a block diagram illustrating a non-volatile memory device that supports the reallocation of CA pad groups during rerouting, according to some embodiments of the present disclosure.

[0103] Figure 40A It is shown Figure 39 A view of the first CA control circuit.

[0104] Figure 40B It is shown Figure 39 A view of the second CA control circuit.

[0105] Figure 41 This is a view showing the operation of the CA control circuit when rerouting is not performed.

[0106] Figure 42 and Figure 43 This is a view showing the operation of the CA control circuitry during rerouting. Detailed Implementation

[0107] The embodiments of this disclosure will now be described in detail and clearly so that those skilled in the art can easily implement this disclosure.

[0108] Figure 1 This is a block diagram illustrating a storage device 10 according to some embodiments of the present disclosure.

[0109] According to some embodiments of this disclosure, the non-volatile memory device 11 can receive commands from the memory controller 12 via multiple command-address buses CA bus #0 to CA bus #k. In this case, commands can be sent in parallel from the memory controller 12 to the non-volatile memory device 11 via command-address buses CA bus #0 to CA bus #k. Therefore, even when the data size is relatively small, command-address overhead can be reduced, and data input / output performance can be improved.

[0110] For more details, please refer to Figure 1 The storage device 10 may include a non-volatile memory device 11 and a memory controller 12.

[0111] The non-volatile memory device 11 can store data. For example, the non-volatile memory device 11 may include multiple planes, and each plane may include memory cells. As an example, the non-volatile memory device 11 may be implemented as a non-volatile memory including flash memory, such as flash memory. However, this is merely an example, and this disclosure should not be limited to or restricted by it. According to some embodiments, the non-volatile memory device 11 may be implemented as including MRAM, FRAM, ReRAM, or PCM (phase-change memory).

[0112] The non-volatile memory device 11 can perform data read operations and data input operations in response to requests from the memory controller 12.

[0113] In some implementations, the non-volatile memory device 11 can perform a data read operation in response to a request from the memory controller 12.

[0114] For example, the non-volatile memory device 11 can receive a read command from the memory controller 12 and can perform a read operation on data stored in at least one plane in response to the read command.

[0115] In addition, the non-volatile memory device 11 can receive SR commands (status read commands) from the memory controller 12, and can send status information about whether the read operation is completed to the memory controller 12 in response to the SR commands.

[0116] Subsequently, the non-volatile memory device 11 can receive a data output command from the memory controller 12, and can perform a data output operation in response to the data output command to send the read data to the memory controller 12.

[0117] In this disclosure, data read commands will be described as including read commands, SR commands, data output commands, and / or addresses corresponding to read commands, SR commands, and data output commands.

[0118] In some implementations, the non-volatile memory device 11 can perform a data input operation in response to a request from the memory controller 12.

[0119] As an example, the non-volatile memory device 11 can receive write commands and data from the memory controller 12, and can store the received data in at least one plane. In this disclosure, data input commands will be described as including a write command and / or an address corresponding to the write command.

[0120] The memory controller 12 may be electrically connected to the non-volatile memory device 11. For example, the memory controller 12 may be a controller that supports DMA (Direct Memory Access) functionality or buffer chip functionality. However, this is merely an example, and this disclosure should not be limited to or restricted by it. According to some embodiments, the memory controller 12 may be a processing unit, such as a GPU or NPU, that communicates with the non-volatile memory device 11.

[0121] The memory controller 12 can request the non-volatile memory device 11 to perform a data read operation or a data input operation.

[0122] In some implementations, the memory controller 12 can send data read commands to the non-volatile memory device 11. For example, the memory controller 12 can send read commands, SR commands, and data output commands to the non-volatile memory device 11 to read data stored in a selected plane within the plane.

[0123] In some implementations, the memory controller 12 may send data input commands to the non-volatile memory device 11. For example, the memory controller 12 may send write commands to the non-volatile memory device 11 to store data in at least one plane of the plane.

[0124] In some embodiments of this disclosure, the non-volatile memory device 11 and the memory controller 12 can send and receive data via at least one data bus (hereinafter referred to as the "DQ bus"). For example, during a data output operation, data can be sent from the non-volatile memory device 11 to the memory controller 12 via one DQ bus. However, this is merely an example, and according to some embodiments, the non-volatile memory device 11 and the memory controller 12 can send and receive data via multiple DQ buses.

[0125] In some embodiments of this disclosure, the non-volatile memory device 11 and the memory controller 12 can send and receive commands and / or addresses via at least two of the command-address buses CA bus #0 to CA bus #k (hereinafter referred to as "CA bus").

[0126] In this configuration, commands and / or addresses can be transmitted in parallel from the memory controller 12 to the non-volatile memory device 11 via multiple CA buses (CA buses #0 to #k). For example, during a data output operation, a first data read command for first data can be sent from the memory controller 12 to the non-volatile memory device 11 via the zeroth CA bus (CA bus #0 to #k), and a second data read command for second data can be sent from the memory controller 12 to the non-volatile memory device 11 via the first CA bus (CA buses #0 to #k).

[0127] In this scenario, the time it takes to send the first data read command via CA bus #0 and the time it takes to send the second data read command via the first CA bus can overlap. Therefore, even with small data sizes, command-address overhead can be reduced, and data input / output performance can be improved.

[0128] Figure 2A This is a block diagram showing in more detail a non-volatile memory device according to some embodiments of the present disclosure. Figure 2A The non-volatile memory device 110 can be used with Figure 1 The non-volatile memory device 11 corresponds to this.

[0129] Reference Figure 2A The non-volatile memory device 110 may include a memory cell array 111 and peripheral circuitry 112. The peripheral circuitry 112 may include a row decoder 113, control logic circuitry 114, page buffer circuitry 115, I / O circuitry 116, command-address pad groups CA_S0 to CA_Sk, and data pad groups DQ_S0 to DQ_Si.

[0130] The memory cell array 111 may include at least one plane PLN1 to PLNn. Each of the planes PLN1 to PLNn may include a memory block. Each of the memory blocks may have a two-dimensional structure or a three-dimensional structure. In a memory block with a two-dimensional structure (or a horizontal structure), the memory cells may be formed in a horizontal direction relative to the substrate. In a memory block with a three-dimensional structure (or a vertical structure), the memory cells may be formed in a vertical direction relative to the substrate.

[0131] The memory block may include at least one of the following: an SLC block comprising single-level cells (SLC), an MLC block comprising multi-level cells (MLC), a TLC block comprising three-level cells (TLC), and a QLC block comprising four-level cells (QLC). Some memory blocks included in the memory cell array 111 may be single-level cell blocks, and other memory blocks may be multi-level cell blocks or three-level cell blocks.

[0132] The row decoder 113 can be connected to the memory cell array 111 via row lines RL. The row lines RL may include serial select lines, ground select lines, word lines, dummy word lines, and GIDL lines.

[0133] Page buffer circuit 115 can be connected to memory cell array 111 via bit line BL. Page buffer circuit 115 can temporarily store data to be programmed into or read from a selected page. Page buffer circuit 115 may include multiple subpage buffer circuits SPBC1 to SPBCn.

[0134] Subpage buffer circuits SPBC1 to SPBCn can be connected to multiple planes PLN1 to PLNn respectively via bit line BL. For example, the first subpage buffer circuit SPBC1 can be connected to the first plane PLN1 via bit line BL, and the nth subpage buffer circuit SPBCn can be connected to the nth plane PLNn via bit line BL.

[0135] Each subpage buffer circuit may include multiple page buffers connected to multiple bit lines BL respectively. That is, a page buffer may be arranged to correspond to one bit line, and each page buffer may include at least one latch.

[0136] I / O circuit 116 can be connected to page buffer circuit 115 via data line DL. I / O circuit 116 can receive data DATA via at least one data pad group DQ_S0 to DQ_Si (hereinafter referred to as "DQ pad group"), and can transfer the received data DATA to page buffer circuit 115. In addition, I / O circuit 116 can receive data DATA from page buffer circuit 115, and can send the received data DATA to memory controller 12 via at least one DQ pad group DQ_S0 to DQ_Si.

[0137] In some embodiments of this disclosure, each of one or more DQ pad groups DQ_S0 to DQ_Si may include a plurality of input / output pins. As an example, each DQ pad group may be implemented to include eight input / output pins. For instance, the zeroth DQ pad group DQ_S0 may include eight input / output pins IOP0_1 to IOP0_8, and the i-th DQ pad group DQ_Si may also include eight input / output pins IOPi_1 to IOPi_8. However, this is merely an example, and the number of input / output pins corresponding to a DQ pad group should not be particularly limited.

[0138] In some embodiments of this disclosure, at least one DQ pad group DQ_S0 to DQ_Si may correspond to a DQ bus (see reference). Figure 1 In other words, at least one DQ pad group DQ_S0 to DQ_Si can be electrically connected to one DQ bus. However, this is just an example, and according to some implementations, multiple DQ pad groups DQ_S0 to DQ_Si can be electrically connected to two or more DQ buses.

[0139] Control logic circuit 114 can receive commands from multiple command-address pad groups CA_S0 to CA_Sk. Control logic circuit 114 can control the overall operation of non-volatile memory device 110 based on the received commands.

[0140] In some embodiments of this disclosure, each of the CA pad groups CA_S0 to CA_Sk may correspond to a plurality of command-address pins (hereinafter referred to as "CA pins"). As an example, each CA pad group may be implemented to correspond to two CA pins. For instance, the zeroth CA pad group CA_S0 may include two CA pins CAP0_1 and CAP0_2, and the kth CA pad group CA_Sk may also include two CA pins CAPk_1 and CAPk_2. However, this is merely an example, and the number of CA pins corresponding to a CA pad group should not be limited to or restricted by this.

[0141] In some embodiments of this disclosure, each of the CA pad groups CA_S0 to CA_Sk can be electrically connected to a different CA bus (see reference). Figure 1 For example, the zeroth CA pad group CA_S0 can be electrically connected to the zeroth CA bus CA bus #0, and the kth CA pad group CA_Sk can be electrically connected to the kth CA bus CA bus #k. However, this is merely an example, and according to some implementations, multiple CA pad groups can be electrically connected to a single CA bus.

[0142] As described above, the non-volatile memory device 110 can be implemented to receive commands and / or addresses in parallel via the CA pad groups CA_S0 to CA_Sk. Therefore, even when the data size is small, command-address overhead can be reduced, and data input / output performance can be improved.

[0143] It should be understood that, Figure 2A In this context, pads or pins do not refer to structures of a specific shape. For example, pads or pins can refer to pads, pins, contacts, metal joints, etc., which include conductive materials through which signals or data can be sent and received.

[0144] Figure 2B This is a circuit diagram illustrating one of the memory blocks according to some embodiments of the present disclosure. Figure 2B The storage block can be included in Figure 2A One of the storage blocks in the plane. For ease of description, assume that a storage block consists of four strings STR1 to STR4.

[0145] Reference Figure 2B The storage block BLKa may include strings STR1 to STR4 arranged vertically on the substrate. Strings STR1 to STR4 may be arranged in a first direction (X-axis direction) and a second direction (Y-axis direction).

[0146] Strings in the same column from STR1 to STR4 can be connected to the same position line. For example, the first string STR1 and the second string STR2 can be connected to the first position line BL1, and the third string STR3 and the fourth string STR4 can be connected to the second position line BL2.

[0147] Each of strings STR1 through STR4 may include multiple unit transistors. Each of the unit transistors may be a charge-trap flash memory (CTF) cell, but this disclosure should not be limited to or restricted by this. The unit transistors may be stacked along a third direction (Z-axis).

[0148] Strings STR1 through STR4 can be connected together to a common source line CSL. For example, as shown... Figure 2B As shown, the common source line CSL can be connected to the bottom of strings STR1 through STR4. However, this is merely an example, and it is sufficient that the common source line CSL is electrically connected to the bottom of strings STR1 through STR4, and is not limited to being physically located at the bottom of strings STR1 through STR4. In the following description, for ease of description, the structure and configuration of the strings will be described with reference to the first string STR1. The other strings STR2, STR3, and STR4 may have a structure similar to that of the first string STR1, and their detailed descriptions will be omitted.

[0149] The unit transistors can be connected in series between the first bit line BL1 and the common source line CSL. For example, the unit transistors may include GIDL transistors GDT1 and GDT2, a string select transistor SST, memory cells MC1 to MC5, a dummy memory cell DMC, and a ground select transistor GST.

[0150] The first GIDL transistor GDT1 can be positioned at the bottom of the string STR1. For example, the first GIDL transistor GDT1 can be connected to the common source line CSL at the bottom of the string STR1. However, this is merely an example, and this disclosure should not be limited to or restricted by it. The gate of the first GIDL transistor GDT1 can be connected to the first GIDL line GIDL1a.

[0151] The second GIDL transistor GDT2 can be positioned at the top of string STR1 and between string select transistor SST and memory cell MC5. That is, the second GIDL transistor GDT2 can be connected to the first bit line BL1 via string select transistor SST. The gate of the second GIDL transistor GDT2 can be connected to the second GIDL line GIDL2a.

[0152] Figure 2B The diagram shows a structure in which GIDL transistors GDT1 and GDT2 are arranged at the top and bottom of string STR1, respectively. However, this is merely illustrative, and according to some embodiments, GIDL transistors may be arranged only at the top of string STR1 or only at the bottom of string STR1.

[0153] A string select transistor SST can be disposed at the top of string STR1. The string select transistor SST can be connected to the first line BL1 at the top of string STR1. The gate of the string select transistor SST can be connected to the string select line SSLa. However, this is merely illustrative, and according to some embodiments, multiple string select transistors connected in series can be disposed between the first line BL1 and the second GIDL transistor GDT2.

[0154] A ground selection transistor GST can be disposed between the dummy memory cell DMC and the first GIDL transistor GDT1. The gate of the ground selection transistor GST can be connected to the ground selection line GSLa. However, this is merely illustrative, and according to some embodiments, multiple ground selection transistors connected in series can be provided between the dummy memory cell DMC and the first GIDL transistor GDT1.

[0155] The first memory cell MC1 to the fifth memory cell MC5 can be connected in series between the string select transistor SST and the dummy memory cell DMC. The gate of each of the first memory cell MC1 to the fifth memory cell MC5 can be connected to the first word line WL1 to the fifth word line WL5.

[0156] A dummy memory cell (DMC) can be disposed between the first memory cell (MC1) and the first GIDL transistor (GDT1). The gate of the dummy memory cell (DMC) can be connected to the dummy word line (DWL). However, this is merely illustrative, and according to some embodiments, multiple dummy memory cells connected in series can be disposed between the first memory cell (MC1) and the first GIDL transistor (GDT1). Alternatively, an additional dummy memory cell can be disposed between the string select transistor (SST) and the fifth memory cell (MC5). Additionally, an additional dummy memory cell can be disposed between memory cells (MC1 through MC5). Furthermore, the dummy memory cell (DMC) may not be disposed at all.

[0157] Figures 3A to 3C This is a diagram illustrating a non-volatile memory device 110 according to an embodiment of the present disclosure. Figures 3A to 3C The non-volatile memory device 110 can be used with Figures 1 to 2B The non-volatile memory devices 11 and 110 correspond to each other.

[0158] Reference Figure 3A The non-volatile memory device 110 can be implemented such that the memory cell array 111 and peripheral circuitry 112 are arranged on a single die D1. In this case, refer to Figure 2A The CA pad group and DQ pad group described herein can be arranged on die D1. Additionally, the command-address control circuit CA CTRL, which will be described later, can also be arranged on die D1.

[0159] Reference Figure 3B The non-volatile memory device 110 may include a first die D1 and a second die D2 stacked in a vertical direction. Peripheral circuitry 112 may be arranged on the first die D1, and a memory cell array 111 may be arranged on the second die D2. The first die D1 and the second die D2 may be connected to each other by a bonding method.

[0160] In this case, refer to Figure 2A The described CA pad group and DQ pad group can be arranged on the first die D1 or the second die D2. Additionally, the command-address control circuit CA CTRL, which will be described later, can also be arranged on the first die D1 or the second die D2.

[0161] According to some implementations, the CA pad group and the DQ pad group can be arranged on the first die D1, and the command-address control circuit CA CTRL can also be arranged on the first die D1.

[0162] According to some implementations, the CA pad group and the DQ pad group can be arranged on the second die D2, and the command-address control circuit CA CTRL can also be arranged on the second die D2.

[0163] According to some implementations, the CA pad group and the DQ pad group can be arranged on a different die than the die on which the command-address control circuit CA CTRL is arranged. As an example, the CA pad group and the DQ pad group can be arranged on a second die D2, and the command-address control circuit CA CTRL can be arranged on a first die D1.

[0164] Reference Figure 3C The non-volatile memory device 110 may include a first die D1, a second die D2, and a third die D3 stacked in a vertical direction. For example, peripheral circuitry 112 may be arranged on the first die D1, and memory cell arrays 111_1 and 111_2 may be arranged on the second die D2 and the third die D3, respectively. The first die D1 and the second die D2 may be connected to each other by a bonding method, and the second die D2 and the third die D3 may be connected to each other by a bonding method.

[0165] In this case, refer to Figure 2A The described CA pad group and DQ pad group can be arranged on one of the first to third dies D1, D2, and D3. Additionally, the command-address control circuit CA CTRL, which will be described later, can be arranged on one of the first to third dies D1, D2, and D3.

[0166] Figure 4 This is a diagram illustrating the planes, CA pad group, and DQ pad group arranged in a non-volatile memory device 110 according to some embodiments of the present disclosure. As an example, Figure 4 The diagram illustrates a structure with two planar pads PLN1 and PLN2, two CA pad groups CA_S0 and CA_S1, and two DQ pad groups DQ_S0 and DQ_S1. For ease of description, in... Figure 4 In this context, it is assumed that the plane, CA pad group, and DQ pad group are arranged in relation to... Figure 3A On the same bare die shown.

[0167] Reference Figure 4The zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0 can correspond to one of the first plane PLN1 and the second plane PLN2. Additionally, the first CA pad group CA_S1 and the first DQ pad group DQ_S1 can correspond to the other of the first plane PLN1 and the second plane PLN2.

[0168] As an example, assume that the zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0 correspond to the first plane PLN1, and the first CA pad group CA_S1 and the first DQ pad group DQ_S1 correspond to the second plane PLN2.

[0169] In this case, data readout and data input operations for the first plane PLN1 can be performed through the zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0.

[0170] For example, read commands, SR commands, and / or data output commands requesting data to be read from the data stored in the first plane PLN1 can be received through the zeroth CA pad group CA_S0. Data stored in the first plane PLN1 can be output to an external device through the zeroth DQ pad group DQ_S0.

[0171] For example, read commands, SR commands, and / or data output commands requesting data to be read from the second plane PLN2 can be received through the first CA pad group CA_S1. Data stored in the second plane PLN2 can be output to an external device through the first DQ pad group DQ_S1.

[0172] In this configuration, the zeroth CA pad group CA_S0 and the first CA pad group CA_S1 can be electrically connected to different CA buses. For example, the zeroth CA pad group CA_S0 can be electrically connected to the zeroth CA bus CA bus #0, and the first CA pad group CA_S1 can be electrically connected to the first CA bus CA bus #1. Therefore, it is possible to access the memory controller 12 (see reference 12) Figure 1 It receives data read commands corresponding to the first plane PLN1 and the second plane PLN2 in parallel. Therefore, even when the data size is small, the command-address overhead can be reduced, and the data input / output performance can be improved.

[0173] like Figure 4 As shown, the zeroth DQ pad group DQ_S0 and the first DQ pad group DQ_S1 can be electrically connected to the same DQ bus. However, this is merely illustrative, and according to some implementations, the zeroth DQ pad group DQ_S0 and the first DQ pad group DQ_S1 can be electrically connected to different DQ buses.

[0174] Figure 5A and Figure 5B This is a diagram illustrating the reduction in command-address overhead and the improvement in data input / output performance according to some embodiments of this disclosure. As an example, Figure 5A A comparative example of where command-address overhead occurs is shown. Figure 5B Examples of this disclosure are shown, illustrating the receipt of data readout commands via different buses. For ease of description, the data readout operation will be described primarily below.

[0175] Reference Figure 5A It receives a first data read command CMD1 for the first data DATA1 and a second data read command CMD2 for the second data DATA2 via the same CA bus.

[0176] In other words, during the time interval from t0 to t1, the first data read command CMD1 is received via the CA bus. Therefore, during the time interval from t1 to t3, the first data DATA1 is output via the DQ bus.

[0177] Additionally, during the time interval from t2 to t4, the second data read command CMD2 is received via the CA bus. Therefore, during the time interval from t4 to t5, the second data DATA2 is output via the DQ bus.

[0178] In this scenario, because the sizes of data DATA1 and DATA2 are relatively smaller than the sizes of commands CMD1 and CMD2, a gap corresponding to the first time T1 occurs between the first data DATA1 and the second data DATA2. This command-address overhead leads to a decrease in data input / output performance.

[0179] Conversely, since the non-volatile memory device 110 according to this disclosure receives commands in parallel, command-address overhead can be reduced and data input / output performance can be improved.

[0180] For more detailed information, please refer to [link / reference]. Figure 4 and Figure 5B The first data read command CMD1 can be received via the zeroth CA bus (CA bus #0) during the time interval from t0 to t1. Therefore, the first data DATA1 can be output via the DQ bus during the time interval from t2 to t4.

[0181] Additionally, the second data read command CMD2 can be received via the first CA bus (CA bus #1) during the time interval from t1 to t5. Therefore, the second data DATA2 can be output via the DQ bus during the time interval from t5 to t7.

[0182] In this way, the third data read command CMD3 can be received via the zero CA bus (CA bus #0), and the fourth data read command CMD4 can be received via the first CA bus (CA bus #1).

[0183] In this scenario, commands CMD1 and CMD3 received via the zeroth CA bus (CA bus #0) can overlap with commands CMD2 and CMD4 received via the first CA bus (CA bus #1). Therefore, even when the sizes of data DATA1 and DATA2 are relatively smaller than the sizes of commands CMD1 and CMD2, the gap (i.e., T2) between the first data DATA1 and the second data DATA2 can be less than [a certain value]. Figure 5A The gap (i.e., T1) can reduce command-address overhead and improve data input / output performance.

[0184] Figures 6A to 6K This is a diagram illustrating various embodiments of the present disclosure, wherein planes, CA pad groups, and DQ pad groups are arranged in a non-volatile memory device 110. Figures 6A to 6K The non-volatile memory devices 110A, 110B, 110C, 110D, 110E, 110F, 110G, 110H, 110I, 110J, and 110K are similar to Figure 4 The non-volatile memory device 110. Therefore, the same or similar reference numerals denote the same or similar elements, and thus, detailed descriptions of the same or similar elements will be omitted. Additionally, for ease of description, in Figures 6A to 6K In, similar to Figure 3A Assume that the plane, CA pad group, and DQ pad group are arranged on the same die.

[0185] Reference Figures 6A to 6K Each of the non-volatile memory devices 110A to 110K may include at least two CA pad groups. Therefore, each of the non-volatile memory devices 110A to 110K can receive commands in parallel, and thus, command-address overhead can be reduced.

[0186] Additionally, each of the non-volatile memory devices 110A to 110K may include at least two CA pad groups and at least two DQ pad groups. In this case, each of the at least two CA pad groups can be assigned to a specific plane, and each of the at least two DQ pad groups can also be assigned to a specific plane. As described above, since the planes corresponding to the CA pad groups and DQ pad groups are specified, the layout between the planes and the CA pad groups and / or DQ pad groups can be optimized. Therefore, core operations such as read and write operations can be performed quickly with low power.

[0187] To explain in more detail, such as Figures 6A to 6E As shown, a CA pad group can be associated with a DQ pad group, and a CA pad group can be assigned to one or more planes.

[0188] For example, such as Figure 6A As shown, a plane can be assigned to each CA pad group. For example, non-volatile memory device 110A may include two planes PLN1 and PLN2, two CA pad groups CA_S0 and CA_S1, and two DQ pad groups DQ_S0 and DQ_S1.

[0189] In this configuration, the zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1, and the first CA pad group CA_S1 and the first DQ pad group DQ_S1 can be assigned to the second plane PLN2. Therefore, commands can be sent in parallel, thus reducing command overhead. Furthermore, the layout can be optimized to enable fast, low-power core operations.

[0190] As an example, such as Figure 6B As shown, each CA pad group can be assigned to two planes. For example, the non-volatile memory device 110B may include four planes PLN1, PLN2, PLN3 and PLN4, two CA pad groups CA_S0 and CA_S1, and two DQ pad groups DQ_S0 and DQ_S1. The zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1 and the second plane PLN2, and the first CA pad group CA_S1 and the first DQ pad group DQ_S1 can be assigned to the third plane PLN3 and the fourth plane PLN4.

[0191] As an example, such as Figure 6C As shown, each CA pad group can be assigned to three planes. For example, a non-volatile memory device 110C may include six planes PLN1, PLN2, PLN3, PLN4, PLN5, and PLN6, two CA pad groups CA_S0 and CA_S1, and two DQ pad groups DQ_S0 and DQ_S1. The zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1, the second plane PLN2, and the third plane PLN3, and the first CA pad group CA_S1 and the first DQ pad group DQ_S1 can be assigned to the fourth plane PLN4, the fifth plane PLN5, and the sixth plane PLN6.

[0192] As an example, such as Figure 6DAs shown, each CA pad group can be assigned to four planes. For example, a non-volatile memory device 110D may include eight planes PLN1, PLN2, PLN3, PLN4, PLN5, PLN6, PLN7, and PLN8, two CA pad groups CA_S0 and CA_S1, and two DQ pad groups DQ_S0 and DQ_S1. The zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1, the second plane PLN2, the third plane PLN3, and the fourth plane PLN4, and the first CA pad group CA_S1 and the first DQ pad group DQ_S1 can be assigned to the fifth plane PLN5, the sixth plane PLN6, the seventh plane PLN7, and the eighth plane PLN8.

[0193] As an example, such as Figure 6E As shown, the non-volatile memory device 110E may include three or more CA pad groups. For example, the non-volatile memory device 110E may include eight planes PLN1, PLN2, PLN3, PLN4, PLN5, PLN6, PLN7 and PLN8, four CA pad groups CA_S0, CA_S1, CA_S2 and CA_S3, and four DQ pad groups DQ_S0, DQ_S1, DQ_S2 and DQ_S3. The zeroth CA pad group CA_S0 and the zeroth DQ pad group DQ_S0 may be assigned to the first plane PLN1 and the third plane PLN3, and the first CA pad group CA_S1 and the first DQ pad group DQ_S1 may be assigned to the second plane PLN2 and the fourth plane PLN4. The second CA pad group CA_S2 and the second DQ pad group DQ_S2 can be assigned to the fifth plane PLN5 and the seventh plane PLN7, and the third CA pad group CA_S3 and the third DQ pad group DQ_S3 can be assigned to the sixth plane PLN6 and the eighth plane PLN8.

[0194] In addition, refer to Figures 6F to 6I One CA pad group can correspond to multiple DQ pad groups, and one CA pad group can be assigned to multiple planes.

[0195] For example, such as Figure 6F As shown, each CA pad group can be assigned to two DQ pad groups and two planes. For example, the non-volatile memory device 110F may include four planes PLN1, PLN2, PLN3 and PLN4, two CA pad groups CA_S0 and CA_S1, and four DQ pad groups DQ_S0, DQ_S1, DQ_S2 and DQ_S3.

[0196] The zeroth CA pad group CA_S0 can be assigned to the first plane PLN1 and the second plane PLN2. The zeroth CA pad group CA_S0 can correspond to the zeroth DQ pad group DQ_S0 and the first DQ pad group DQ_S1. The zeroth DQ pad group DQ_S0 and the first DQ pad group DQ_S1 can be assigned to the first plane PLN1 and the second plane PLN2, respectively.

[0197] Similarly, the first CA pad group CA_S1 can be assigned to the third plane PLN3 and the fourth plane PLN4. The first CA pad group CA_S1 can correspond to the second DQ pad group DQ_S2 and the third DQ pad group DQ_S3. The second DQ pad group DQ_S2 and the third DQ pad group DQ_S3 can be assigned to the third plane PLN3 and the fourth plane PLN4, respectively.

[0198] For example, such as Figure 6G As shown, each CA pad group can be assigned to two DQ pad groups and four planes. For example, a non-volatile memory device 110G may include eight planes PLN1, PLN2, PLN3, PLN4, PLN5, PLN6, PLN7 and PLN8, two CA pad groups CA_S0 and CA_S1, and four DQ pad groups DQ_S0, DQ_S1, DQ_S2 and DQ_S3.

[0199] The zeroth CA pad group CA_S0 can be assigned to the first plane PLN1, the second plane PLN2, the third plane PLN3, and the fourth plane PLN4. The zeroth CA pad group CA_S0 can correspond to the zeroth DQ pad group DQ_S0 and the first DQ pad group DQ_S1. The zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1 and the third plane PLN3, and the first DQ pad group DQ_S1 can be assigned to the second plane PLN2 and the fourth plane PLN4. Similarly, the zeroth CA pad group CA_S1 can be assigned to the fifth through eighth planes PLN5, PLN6, PLN7, and PLN8.

[0200] For example, such as Figure 6H As shown, each CA pad group can be assigned to two DQ pad groups and six planes. For example, the non-volatile memory device 110H may include twelve planes PLN1, PLN2, PLN3, PLN4, PLN5, PLN6, PLN7, PLN8, PLN9, PLN10, PLN11 and PLN12, two CA pad groups CA_S0 and CA_S1, and four DQ pad groups DQ_S0, DQ_S1, DQ_S2 and DQ_S3.

[0201] The zeroth CA pad group CA_S0 can be assigned to the first plane PLN1, the second plane PLN2, the third plane PLN3, the fourth plane PLN4, the fifth plane PLN5, and the sixth plane PLN6. The zeroth CA pad group CA_S0 can correspond to the zeroth DQ pad group DQ_S0 and the first DQ pad group DQ_S1. The zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1, the third plane PLN3, and the fifth plane PLN5, and the first DQ pad group DQ_S1 can be assigned to the second plane PLN2, the fourth plane PLN4, and the sixth plane PLN6. Similarly, the first CA pad group CA_S1 can be assigned to the seventh, eighth, ninth, tenth, eleventh, and twelfth planes PLN7, PLN8, PLN9, PLN10, PLN11, and PLN12.

[0202] For example, such as Figure 6I As shown, each CA pad group can also be assigned to two DQ pad groups and eight planes. For example, the non-volatile memory device 110I may include sixteen planes PLN1, PLN2, PLN3, PLN4, PLN5, PLN6, PLN7, PLN8, PLN9, PLN10, PLN11, PLN12, PLN13, PLN14, PLN15 and PLN16, two CA pad groups CA_S0 and CA_S1, and four DQ pad groups DQ_S0, DQ_S1, DQ_S2 and DQ_S3.

[0203] The zeroth CA pad group CA_S0 can be assigned to the first, second, third, fourth, fifth, sixth, seventh, and eighth planes PLN1, PLN2, PLN3, PLN4, PLN5, PLN6, PLN7, and PLN8. The zeroth CA pad group CA_S0 can correspond to the zeroth DQ pad group DQ_S0 and the first DQ pad group DQ_S1. The zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1, the third plane PLN3, the fifth plane PLN5, and the seventh plane PLN7, and the first DQ pad group DQ_S1 can be assigned to the second plane PLN2, the fourth plane PLN4, the sixth plane PLN6, and the eighth plane PLN8. Similarly, the first CA pad group CA_S1 can be assigned to the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth planes PLN9, PLN10, PLN11, PLN12, PLN13, PLN14, PLN15 and PLN16.

[0204] Reference Figure 6J and Figure 6K Multiple CA pad groups can be assigned to a single plane.

[0205] For example, such as Figure 6JAs shown, each pair of CA pad groups can be assigned a DQ pad group and a plane. For example, the non-volatile memory device 110J may include two planes PLN1 and PLN2, four CA pad groups CA_S0, CA_S1, CA_S2 and CA_S3, and two DQ pad groups DQ_S0 and DQ_S1.

[0206] The zeroth CA pad group CA_S0 and the first CA pad group CA_S1 can be assigned to the first plane PLN1. The zeroth CA pad group CA_S0 and the first CA pad group CA_S1 can correspond to the zeroth DQ pad group DQ_S0. The zeroth DQ pad group DQ_S0 can be assigned to the first plane PLN1. Similarly, the second CA pad group CA_S2 and the third CA pad group CA_S3 can be assigned to the second plane PLN2.

[0207] For example, such as Figure 6K As shown, the non-volatile memory device 110K may include a plane, and every two CA pad groups may be assigned a DQ pad group and a plane.

[0208] As described above, each of the non-volatile memory devices 110A to 110K according to the present disclosure can receive commands in parallel, thus reducing command-address overhead. Furthermore, each of the non-volatile memory devices 110A to 110K according to the present disclosure may include at least two CA pad groups and at least two DQ pad groups, and each CA pad group and each DQ pad group can be assigned to a specific plane. Therefore, the layout between the plane and the CA pad groups and / or DQ pad groups can be optimized.

[0209] In some embodiments of this disclosure, the planes to which each CA pad group and / or each DQ pad group is assigned can be reconfigured based on the data size. This will be described in more detail below.

[0210] Figure 7 This is a block diagram illustrating a storage device 20 according to some embodiments of the present disclosure. Figure 8 To show in more detail Figure 7 A block diagram of a non-volatile memory device. Figure 7 storage device 20 and Figure 8 The non-volatile memory device 210 is similar to Figure 1 memory device 10 and Figure 2A The non-volatile memory device 110. Therefore, in Figure 7 and Figure 8 In the figures, the same or similar reference numerals indicate Figure 1 and Figure 2A The same or similar elements are used, therefore, detailed descriptions of the same elements will be omitted.

[0211] According to this disclosure, the non-volatile memory devices 21 and 210 can receive commands in parallel from the memory controller 22 via multiple command-address buses CA bus #0 to CA bus #k. Therefore, even when the data size is relatively small, command-address overhead can be reduced and data input / output performance can be improved.

[0212] Furthermore, according to this disclosure, non-volatile memory devices 21 and 210 can reconfigure the planes allocated with CA pad groups based on data size. Therefore, data input / output performance can be further improved.

[0213] refer to Figure 7 and Figure 8 ,and Figure 1 and Figure 2A Compared to non-volatile memory devices 11 and 110, non-volatile memory devices 21 and 210 may also include command-address control circuitry (hereinafter referred to as "CA control circuitry") 217.

[0214] CA control circuit 217 can be electrically connected to multiple CA pad groups CA_S0 to CA_Sk. CA control circuit 217 can receive commands CMD through CA pad groups CA_S0 to CA_Sk.

[0215] CA pad groups CA_S0 to CA_Sk can correspond to CA buses CA bus #0 to CA bus #k, respectively. For example, the zeroth CA pad group CA_S0 can correspond to the zeroth CA bus CA bus #0, and the kth CA pad group CA_Sk can correspond to the kth CA bus CA bus #k.

[0216] In some embodiments of this disclosure, the CA control circuit 217 can reconfigure the planes allocated to the CA pad groups based on the data size. In other words, based on the data size, the CA control circuit 217 can reconfigure each of planes PLN1 to PLNn to correspond to a different CA pad group, or it can reconfigure some of planes PLN1 to PLNn to correspond to the same CA pad group.

[0217] For example, when the data size is relatively small, the CA control circuit 217 can assign each of the planes PLN1 to PLNn to a different CA pad group. In this case, the memory controller 22, as well as the non-volatile memory devices 21 and 210, can send and receive commands and / or addresses via a relatively large number of CA buses.

[0218] For example, when the data size is relatively large, the CA control circuit 217 can assign at least two planes from PLN1 to PLNn to the same CA pad group. In other words, a CA pad group can be assigned to at least two planes. In this case, the memory controller 22 and the non-volatile memory devices 21 and 210 can send and receive commands and / or addresses through a relatively small number of CA buses.

[0219] Therefore, since the non-volatile memory devices 21 and 210 according to this disclosure can be reconfigured based on the data size to allocate the plane of the CA pad group, data input / output performance can be further improved.

[0220] In some embodiments of this disclosure, decisions to reconfigure the allocation of CA pad groups based on data size can be performed in non-volatile memory devices 21 and 210. For example, non-volatile memory devices 21 and 210 can reconfigure the planes to which CA pad groups are allocated based on the size of the received data. This will be referred to below. Figure 9 To describe in more detail.

[0221] Alternatively, in some embodiments of this disclosure, the decision to reconfigure the allocation of CA pad groups based on data size can be performed in the memory controller 22. For example, the memory controller 22 can send a command to non-volatile memory devices 21 and 210 to reconfigure the CA pad groups based on the size of the data to be sent, and the non-volatile memory devices 21 and 210 can reconfigure the planes to which the CA pad groups are allocated based on that command. This will be referenced below. Figure 10 and Figures 36 to 38C To describe in more detail.

[0222] Figure 9 This is a flowchart illustrating the operation of a non-volatile memory device according to some embodiments of the present disclosure. For example, Figure 9 An example is shown where a weighted nonvolatile memory device checks the data size and reconfigures the planes that assign CA pad groups to it based on the checked data size.

[0223] In operation S110, the data size can be checked. For example, non-volatile memory device 210 (see reference). Figure 8 ) control logic circuit 214 (refer to) Figure 8 You can check the data size during data output operations and / or during data input operations.

[0224] In operation S120, it can be checked whether the data size is greater than a reference size. For example, control logic circuit 214 can check whether the data size in data input and output operations is greater than a previously determined reference size.

[0225] When the data size is determined to be smaller than the reference size, operation S131 can be executed.

[0226] In operation S131, the non-volatile memory device 210 can enter command-serial mode.

[0227] In operation S132, the non-volatile memory device 210 can reassign multiple planes to the same CA pad group. In other words, a CA pad group can be reassigned to multiple planes. In this case, the non-volatile memory device 210 can be electrically connected to the memory controller 22 via a CA bus corresponding to a CA pad group.

[0228] In step S133, the non-volatile memory device 210 can perform data read operations and / or data input operations via a CA bus. In other words, data can be serially sent and received between the non-volatile memory device 210 and the memory controller 22 via a CA bus.

[0229] As mentioned above, when the data size is smaller than the reference size, commands can be sent and received serially through a single CA bus, thus reducing power consumption.

[0230] When it is determined in operation S120 that the data size is greater than the reference size, operation S141 can be executed.

[0231] In operation S141, the non-volatile memory device 210 can enter command-parallel mode.

[0232] In operation S142, the non-volatile memory device 210 can reassign multiple planes to different CA pad groups. In other words, different CA pad groups can be reassigned to different planes. In this case, the non-volatile memory device 210 can be electrically connected to the memory controller 22 via at least two CA buses corresponding to at least two CA pad groups.

[0233] In operation S143, the non-volatile memory device 210 can perform data read operations and / or data input operations via at least two CA buses. In other words, data can be sent and received in parallel between the non-volatile memory device 210 and the memory controller 22 via at least two CA buses.

[0234] As mentioned above, when the data size is larger than the reference size, commands can be sent and received in parallel through multiple CA buses, thus reducing command-address overhead.

[0235] Therefore, the non-volatile memory device 210 according to this disclosure can selectively support command-serial mode and / or command-parallel mode based on data size.

[0236] Figure 10 This is a flowchart illustrating the operation of a non-volatile memory device according to some embodiments of the present disclosure. For example, Figure 10 An example is shown in which the memory controller sends a command to reallocate CA pad groups based on data size, and the non-volatile memory device changes mode based on the command. Figure 10 The operation of non-volatile memory devices in the middle is similar to Figure 9 Therefore, descriptions of identical or similar elements will be omitted.

[0237] In operation S210, the non-volatile memory device 210 (reference) Figure 8 ) can be obtained from memory controller 22 (reference) Figure 7 The non-volatile memory device 210 can receive a command requesting the reallocation of the CA pad group. For example, the non-volatile memory device 210 can identify the command as a request to reallocate the CA pad group based on the header of the received command.

[0238] In operation S220, the non-volatile memory device 210 can examine the received command. For example, the non-volatile memory device 210 can examine the plane to which the CA pad group is assigned based on the body of the received command.

[0239] When the command requests the reassignment of a plane to the same CA pad group, the operating mode of the non-volatile memory device 210 can be changed from command-parallel mode to command-serial mode. In this case, operation S231 can be executed.

[0240] In operation S231, the non-volatile memory device 210 can reassign the plane to the same CA pad group.

[0241] In operation S232, the non-volatile memory device 210 can perform data read operations and / or data input operations via a CA bus.

[0242] When the command requests the reassignment of different planes to different CA pad groups, the operating mode of the non-volatile memory device 210 can be changed from command-serial mode to command-parallel mode. In this case, operation S241 can be executed.

[0243] In operation S241, the non-volatile memory device 210 can reassign multiple planes to different CA pad groups.

[0244] In operation S242, the non-volatile memory device 210 can perform data read operations and / or data input operations via at least two CA buses.

[0245] Therefore, the non-volatile memory device 210 according to this disclosure can selectively support command-serial mode and / or command-parallel mode based on data size.

[0246] Figure 11 This is a diagram illustrating the planes, CA pad group, and DQ pad group arranged in a non-volatile memory device 210 according to some embodiments of the present disclosure. For example, Figure 11 The diagram shows the structure in which two planes PLN1 and PLN2, two CA pad groups CA_S0 and CA_S1, two DQ pad groups DQ_S0 and DQ_S1, and two CA control circuits 217_1 and 217_2 are arranged. Figure 11 The non-volatile memory device 210 in the middle is similar to Figure 4 and Figure 6J Non-volatile memory devices. Therefore, the same or similar reference numerals indicate... Figure 4 and Figure 6J The same or similar elements will be omitted, therefore, detailed descriptions of the same elements will be omitted.

[0247] refer to Figure 11 The non-volatile memory device 210 may also include a first CA control circuit 217_1 and a second CA control circuit 217_2.

[0248] The first CA control circuit 217_1 can be electrically connected to the first plane PLN1 and the zero CA pad group CA_S0 to the third CA pad group CA_S3. Based on the control logic circuit 214 (see reference). Figure 8 Under the control of the first CA control circuit 217_1, the CA control circuit can determine the CA pad group to be assigned to the first plane PLN1 from the zero CA pad group CA_S0 to the third CA pad group CA_S3.

[0249] The second CA control circuit 217_2 can be electrically connected to the second plane PLN2 and the zero CA pad group CA_S0 to the third CA pad group CA_S3. Based on the control of the control logic circuit 214, the second CA control circuit 217_2 can determine the CA pad group to be assigned to the second plane PLN2 from the zero CA pad group CA_S0 to the third CA pad group CA_S3.

[0250] exist Figure 11 In the diagram, the first CA control circuit 217_1 and the second CA control circuit 217_2 are shown arranged on the same die. However, this is merely an example, and this disclosure should not be limited to or restricted by it. For example, similar to Figure 3B and Figure 3C As shown, the first CA control circuit 217_1 and the second CA control circuit 217_2 can be arranged on a bare die on which peripheral circuits are arranged.

[0251] Figures 12A to 12C This is a view illustrating command-serial mode and command-parallel mode according to some embodiments of this disclosure. Figures 12A to 12C Similar to Figure 5. Therefore, redundant descriptions will be omitted. For ease of explanation, the data readout operation will be described in detail below. Furthermore, the data sizes will be represented by "L1", "L2", and "L3", with L1 being the largest and L3 the smallest.

[0252] refer to Figure 11 and Figure 12A The sizes of data DATA1 and DATA2 are "L1", which are larger than the sizes of data read commands CMD1 and CMD2. In this case, the non-volatile memory device 210 (refer to...) Figure 8 It can enter command-serial mode using a single CA bus.

[0253] In some implementations, the first CA control circuit 217_1 can assign the zeroth CA pad group CA_S0 to the first plane PLN1. In other words, the first CA control circuit 217_1 can determine the zeroth CA pad group CA_S0 from the zeroth CA pad group CA_S0 to the third CA pad group CA_S3 as the CA pad group to be assigned to the first plane PLN1.

[0254] Additionally, the second CA control circuit 217_2 can assign the zeroth CA pad group CA_S0 to the second plane PLN2. In other words, the second CA control circuit 217_2 can determine the zeroth CA pad group CA_S0 from the zeroth CA pad group CA_S0 to the third CA pad group CA_S3 as the CA pad group to be assigned to the second plane PLN2.

[0255] Therefore, in command-serial mode, only the zeroth CA pad group CA_S0 can be selected. Thus, the non-volatile memory device 210 and the memory controller 22 can receive commands via the zeroth CA bus CA bus #0.

[0256] In this scenario, since the sizes of data DATA1 and DATA2 are larger than the sizes of data read commands CMD1 and CMD2, no issues arising from command overhead will occur. Furthermore, power consumption can be reduced by using a single CA bus.

[0257] refer to Figure 11 and Figure 12BThe data DATA1, DATA2, DATA3, and DATA4 are of size "L2", which is relatively smaller than the data read commands CMD1, CMD2, CMD3, and CMD4. In this case, the non-volatile memory device 210 can enter a first command-parallel mode using a relatively large amount of CA bus.

[0258] In some implementations, the first CA control circuit 217_1 can assign the zeroth CA pad group CA_S0 to the first plane PLN1. In other words, the first CA control circuit 217_1 can determine the zeroth CA pad group CA_S0 from the zeroth CA pad group CA_S0 to the third CA pad group CA_S3 as the CA pad group to be assigned to the first plane PLN1.

[0259] The second CA control circuit 217_2 can assign the second CA pad group CA_S2 to the second plane PLN2. In other words, the second CA control circuit 217_2 can determine the second CA pad group CA_S2 as one of the CA pad groups to be assigned to the second plane PLN2 from the zeroth CA pad group CA_S0 to the third CA pad group CA_S3.

[0260] Therefore, the zeroth CA pad group CA_S0 and the second CA pad group CA_S2 can be selected in the first command-parallel mode. Thus, the non-volatile memory device 210 and the memory controller 22 can receive commands via two CA buses, CA bus #0 and CA bus #2.

[0261] As a result, even when the data size is relatively small, the non-volatile memory device according to this disclosure can not only reduce command overhead by receiving commands in parallel, but also appropriately adjust power consumption.

[0262] refer to Figure 11 and Figure 12C The size of data D1 to D8 is "L3", which is the minimum. In this case, the non-volatile memory device 210 can enter a second command-parallel mode using the maximum number of CA buses.

[0263] In some implementations, the first CA control circuit 217_1 can assign the zeroth CA pad group CA_S0 and the first CA pad group CA_S1 to the first plane PLN1. In other words, the first CA control circuit 217_1 can determine the zeroth CA pad group CA_S0 and the first CA pad group CA_S1 from the zeroth CA pad group CA_S0 to the third CA pad group CA_S3 as the CA pad groups to be assigned to the first plane PLN1.

[0264] The second CA control circuit 217_2 can assign the second CA pad group CA_S2 and the third CA pad group CA_S3 to the second plane PLN2. In other words, the second CA control circuit 217_2 can determine the second CA pad group CA_S2 and the third CA pad group CA_S3 as the CA pad groups to be assigned to the second plane PLN2 from the zeroth CA pad group CA_S0 to the third CA pad group CA_S3.

[0265] Therefore, in the second command-parallel mode, the zeroth CA pad group to the third CA pad group, CA_S0, CA_S1, CA_S2, and CA_S3, can be selected. Thus, the non-volatile memory device 210 and the memory controller 22 can receive commands via four CA buses: CA bus #0, CA bus #1, CA bus #2, and CA bus #3.

[0266] Therefore, even when the data size is small, the non-volatile memory device according to this disclosure can reduce command overhead by receiving commands in parallel.

[0267] Figures 13A to 13C This is a block diagram illustrating storage devices 30A, 30B, and 30C according to embodiments of the present disclosure. Figures 13A to 13C Storage devices 30A, 30B, and 30C are similar to Figure 1 and Figure 7 Storage devices 10 and 20 are shown in the figures. Therefore, identical or similar elements are indicated by identical or similar reference numerals, and redundant descriptions will be omitted.

[0268] Reference Figures 13A to 3C According to some embodiments, the non-volatile memory device 31 may include a plurality of chips C1 to Cn. Chips C1 to Cn may be stacked in the vertical direction and may be interconnected with each other by a pad wiring method or a through-silicon via (TSV) wiring method. Each of chips C1 to Cn may correspond to the aforementioned non-volatile memory devices 11, 21, 110 and 210.

[0269] Each of chips C1 to Cn may include multiple CA pad groups. For example, the first chip C1 may include the zeroth CA pad group to the kth CA pad group, and the nth chip Cn may also include the zeroth CA pad group to the kth CA pad group.

[0270] The CA pad groups of each of chips C1 to Cn can share the same CA bus. For example, the zeroth CA pad group of each of chips C1 to Cn can be electrically connected to the zeroth CA bus, CA bus #0. The kth CA pad group of each of chips C1 to Cn can be electrically connected to the kth CA bus, CA bus #k.

[0271] Each of the chips C1 to Cn may include at least one DQ pad group.

[0272] For example, such as Figure 13A and Figure 13B As shown, each chip may include two DQ pad groups. That is, the first chip C1 may include a zeroth DQ pad group and a first DQ pad group, and the nth chip Cn may also include a zeroth DQ pad group and a first DQ pad group. According to some implementations, such as Figure 13C As shown, each chip may include a DQ pad group.

[0273] The DQ pad groups of each of the chips C1 to Cn can share the same DQ bus.

[0274] For example, such as Figure 13A As shown, the zeroth DQ pad group of each of chips C1 to Cn can be electrically connected to the zeroth DQ bus DQ bus #0, and the first DQ pad group of each of chips C1 to Cn can be electrically connected to the first DQ bus DQ bus #1. That is, the memory controller 32 and the non-volatile memory device 31 can be electrically connected to each other via two DQ buses DQ bus #0 and DQ bus #1. According to some embodiments, such as Figure 13B As shown, the zeroth DQ pad group and the first DQ pad group of each of chips C1 to Cn can be electrically connected to a single DQ bus. That is, the memory controller 32 and the non-volatile memory device 31 can be electrically connected to each other via a single DQ bus. According to some embodiments, such as... Figure 13C As shown, the DQ pad group of each of chips C1 to Cn can be electrically connected to the DQ bus.

[0275] According to this disclosure, the non-volatile memory device 31 can receive commands in parallel from the memory controller 32 via the command-address bus CA bus #0 to CA bus #k. Therefore, even when the data size is relatively small, the command-address overhead can be reduced, and the data input / output performance can be improved.

[0276] Furthermore, the non-volatile memory device 31 according to this disclosure can reconfigure the plane to which it assigns CA pad groups based on data size. Therefore, data input / output performance can be further improved.

[0277] In the following text, reference will be made to Figures 14 to 28 A more detailed description is provided of an implementation method for allocating CA pad groups in a non-volatile memory device generated via a pad routing method. Furthermore, reference will be made to... Figures 29 to 35 A more detailed description is provided of an implementation of allocating CA pad groups in a non-volatile memory device generated via the TSV method.

[0278] Figure 14 This is a view showing a non-volatile memory device 310 formed by a pad wiring method according to some embodiments of the present disclosure. Figure 14 The non-volatile memory device 310 can be used with Figure 13A This corresponds to a non-volatile memory device. For ease of illustration, it is assumed below that the non-volatile memory device 310 includes eight paths, and each path includes two planes.

[0279] Reference Figure 14 The non-volatile memory device 310 may include multiple paths WAY#0 to WAY#7 stacked in the vertical direction. In some embodiments, a path may be connected to... Figure 13A One chip corresponds to this. In this case, the four lower paths WAY#0 to WAY#3 can form the zeroth path group WG#0, and the four upper paths WAY#4 to WAY#7 can form the first path group WG#1.

[0280] Each of the paths WAY#0 to WAY#7 can include two planes.

[0281] For example, in the case of the zeroth path group WG#0, the zeroth plane can be placed to the left of the zeroth path WAY#0, ​​and the fourth plane can be placed to the right. The first plane can be placed to the left of the first path WAY#1, and the fifth plane can be placed to the right. The second plane can be placed to the left of the second path WAY#2, and the sixth plane can be placed to the right. The third plane can be placed to the left of the third path WAY#3, and the seventh plane can be placed to the right.

[0282] Additionally, for example, in the case of the first path group WG#1, the zeroth plane can be arranged to the left of the fourth path WAY#4, and the fourth plane can be arranged to the right. The first plane can be arranged to the left of the fifth path WAY#5, and the fifth plane can be arranged to the right. The second plane can be arranged to the left of the sixth path WAY#6, and the sixth plane can be arranged to the right. The third plane PLN3 can be arranged to the left of the seventh path WAY#7, and the seventh plane PLN7 can be arranged to the right.

[0283] Each of the paths WAY#0 to WAY#7 may include two CA control circuits.

[0284] For example, in the case of the zero path group WG#0, each of the zero path WAY#0 to the third path WAY#3 may include a first CA control circuit CA CTRL1 and a third CA control circuit CA CTRL3. Furthermore, for example, in the case of the first path group WG#1, each of the fourth path WAY#4 to the seventh path WAY#7 may include a second CA control circuit CACTRL2 and a fourth CA control circuit CA CTRL4.

[0285] Paths WAY#0 to WAY#7 can be electrically connected to each other using pad routing.

[0286] For example, each of the four command-address lines (hereinafter referred to as "CA lines") CA#0, CA#1, CA#2, and CA#3 can be electrically connected to paths WAY#0 through WAY#7 via pad routing. Similarly, each of the two input / output lines (hereinafter referred to as "IO lines") IO#0 and IO#1 can be electrically connected to paths WAY#0 through WAY#7 via pad routing.

[0287] Each of the four CA lines, CA#0, CA#1, CA#2, and CA#3, can be electrically connected to a CA bus.

[0288] For example, the zeroth CA line CA#0 can be electrically connected to the zeroth CA bus CA bus #0 (reference). Figure 13A ), and the first CA line CA#1 can be electrically connected to the first CA bus CA bus #1 (reference). Figure 13A Similarly, the second CA line CA#2 and the third CA line CA#3 can be electrically connected to the second CA bus and the third CA bus, respectively.

[0289] In addition, each of the four CA lines CA#0, CA#1, CA#2 and CA#3 can be electrically connected to the CA pad group.

[0290] For example, the zero CA line CA#0 can be electrically connected to the zero CA pad group included in paths WAY#0 to WAY#7. The first CA line CA#1 can be electrically connected to the first CA pad group included in paths WAY#0 to WAY#7. Similarly, the second CA line CA#2 can be electrically connected to the second CA pad group included in paths WAY#0 to WAY#7, and the third CA line CA#3 can be electrically connected to the third CA pad group included in paths WAY#0 to WAY#7.

[0291] Each of the two IO lines, IO#0 and IO#1, can be electrically connected to a DQ bus.

[0292] For example, the zeroth IO line IO#0 can be electrically connected to the zeroth DQ bus DQ bus #0 (see reference). Figure 13A ), and the first IO line IO#1 can be electrically connected to the first DQ bus DQ bus #1 (see reference). Figure 13A ).

[0293] In addition, each of the two IO lines, IO#0 and IO#1, can be electrically connected to the DQ pad group.

[0294] For example, the zero IO line IO#0 can be electrically connected to the zero DQ pad group included in paths WAY#0 to WAY#7. The first IO line IO#1 can be electrically connected to the first DQ pad group included in paths WAY#0 to WAY#7.

[0295] In some embodiments of this disclosure, the CA control circuit may correspond to a plane, and the CA lines CA#0 to CA#3 corresponding to the plane may be assigned to the plane.

[0296] For example, the seventh path WAY#7 may include a second CA control circuit CA CTRL2 and a fourth CA control circuit CACTRL4. The second CA control circuit CA CTRL2 may correspond to the third plane PLN3 and may assign one of the CA lines CA#0 to CA#3 to the third plane PLN3. Similarly, the fourth CA control circuit CA CTRL4 may correspond to the seventh plane PLN7 and may assign one of the CA lines CA#0 to CA#3 to the seventh plane PLN7.

[0297] In some embodiments of this disclosure, when the data size is relatively small, the non-volatile memory device 310 can send and receive commands in parallel via multiple CA lines. Therefore, command overhead can be reduced and data transmission efficiency can be improved.

[0298] Furthermore, in some embodiments of this disclosure, when the data size is relatively large, the non-volatile memory device 310 can serially send and receive commands via a single CA line. Therefore, power consumption can be reduced while maintaining a high level of data transfer efficiency.

[0299] Figure 15 It is shown Figure 14 A view of the CA control circuit. Figure 15 The CA control circuit CA CTRL can be used with Figure 14 It corresponds to one of the first CA control circuit CA CTRL1 to the fourth CA control circuit CA CTRL4.

[0300] refer to Figure 15The CA control circuit CA CTRL may include multiple multiplexers M1, M2 and M3.

[0301] The first multiplexer M1 can be connected to the zeroth CA line CA#0 and the first CA line CA#1, and can select one of the zeroth CA line CA#0 and the first CA line CA#1 in response to a control signal. In this case, the chip ID CID can be provided as the control signal. For example, if the chip ID CID is CID#4 to CID#7, the first multiplexer M1 can select the first CA line CA#1. If the chip ID CID is not CID#4 to CID#7, the first multiplexer M1 can select the zeroth CA line CA#0. In some embodiments, CID#4 to CID#7 can be the chip IDs of the fourth path WAY#4 to the seventh path WAY#7, respectively.

[0302] The second multiplexer M2 can be connected to the second CA line CA#2 and the third CA line CA#3, and can select one of the second CA line CA#2 and the third CA line CA#3 in response to a control signal. In this case, the chip ID CID can be provided as the control signal.

[0303] The third multiplexer M3 can be connected to the output of the first multiplexer M1 and the output of the second multiplexer M2, and can select either the output of the first multiplexer M1 or the output of the second multiplexer M2 in response to a control signal. In this case, a "1" or "0" can be provided as the control signal. For example, when the control signal is "1", the output of the second multiplexer M2 can be selected. When the control signal is "0", the output of the first multiplexer M1 can be selected.

[0304] Figure 16 and Figures 17A to 17D It shows the use Figure 15 The CA control circuit will Figure 14 A diagram illustrating the operation of a non-volatile memory device 310 configured to enter command-parallel mode. In detail, Figure 16 This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure. Figures 17A to 17D It shows when entering Figure 16 Command - Parallel Mode Figure 15 A diagram illustrating the operation of the CA control circuit. Figure 16 as well as Figures 17A to 17D As a representative example, the diagram illustrates the structure in which four CA lines, CA#0, CA#1, CA#2, and CA#3, are assigned.

[0305] refer to Figure 16 and Figure 17AThe first CA control circuit CA CTRL1 can be set to the left of each of the paths WAY#0 to WAY#3 in the zero path group WG#0.

[0306] Since the chip IDs (CIDs) of the zero path group WG#0 are CID#0 to CID#3, the first multiplexer M1 selects the zero CA line CA#0, and the second multiplexer M2 selects the second CA line CA#2. Since the control signal of the third multiplexer M3 is "0", the third multiplexer M3 selects the first multiplexer M1.

[0307] As a result, the first CA control circuit CA CTRL1 assigns the zeroth CA line CA#0 to the corresponding plane. That is, as... Figure 16 and Figure 17A As shown, the zero line CA#0 is assigned to planes PLN0 to PLN3, which are located on the left side of each of the planes included in the paths WAY#0 to WAY#3 of the zero path group WG#0.

[0308] Reference Figure 16 and Figure 17B The second CA control circuit CA CTRL2 can be set to the left of each of the paths WAY#4 to WAY#7 in the first path group WG#1.

[0309] Since the chip IDs (CIDs) of the first path group WG#1 are CID#4 to CID#7, the first multiplexer M1 selects the first CA line CA#1, and the second multiplexer M2 selects the third CA line CA#3. Since the control signal of the third multiplexer M3 is "0", the third multiplexer M3 selects the first multiplexer M1.

[0310] As a result, the second CA control circuit CA CTRL2 assigns the first CA line CA#1 to the corresponding plane. That is, as... Figure 16 and 17B As shown, the first CA line CA#1 is assigned to planes PLN0 to PLN3, which are located on the left side of each of the planes included in the paths WAY#4 to WAY#7 of the first path group WG#1.

[0311] Reference Figure 16 and Figure 17C The third CA control circuit CA CTRL3 is set to the right of each of the paths WAY#0 to WAY#3 in the zero path group WG#0.

[0312] Since the chip IDs (CIDs) of the zero path group WG#0 are CID#0 to CID#3, the first multiplexer M1 selects the zero CA line CA#0, and the second multiplexer M2 selects the second CA line CA#2. Since the control signal of the third multiplexer M3 is "1", the third multiplexer M3 selects the second multiplexer M2.

[0313] As a result, the third CA control circuit CA CTRL3 assigns the second CA line CA#2 to the corresponding plane. That is, as... Figure 16 and Figure 17C As shown, the second CA line CA#2 is assigned to planes PLN4 to PLN7, which are located on the right side of the planes included in each of the paths WAY#0 to WAY#3 of the zero path group WG#0.

[0314] Reference Figure 16 and Figure 17D The fourth CA control circuit CA CTRL4 is located to the right of each of the paths WAY#4 to WAY#7 in the first path group WG#1.

[0315] Since the chip IDs (CIDs) of the first path group WG#1 are CID#4 to CID#7, the first multiplexer M1 selects the first CA line CA#1, and the second multiplexer M2 selects the third CA line CA#3. Since the control signal of the third multiplexer M3 is "1", the third multiplexer M3 selects the second multiplexer M2.

[0316] As a result, the fourth CA control circuit CA CTRL4 assigns the third CA line CA#3 to the corresponding plane. That is, as... Figure 16 and Figure 17D As shown, the third CA line CA#3 is assigned to planes PLN4 to PLN7, which are located on the right side of each of the planes included in the paths WAY#4 to WAY#7 of the first path group WG#1.

[0317] As referenced above Figure 16 and Figures 17A to 17D The non-volatile memory device 310 can receive commands in parallel via four CA lines: CA#0, CA#1, CA#2, and CA#3. Therefore, command overhead can be reduced even when the data size is small.

[0318] Figure 18 This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure. Figure 18 The non-volatile memory device 310 is similar to Figure 16 The non-volatile memory device 310. Therefore, redundant descriptions will be omitted.

[0319] exist Figure 16 In the diagram, two input / output lines IO#0 and IO#1 are shown as electrically connected to different data buses DQ bus #0 and DQ bus #1, respectively (reference). Figure 13A However, this is merely an example, and this disclosure should not be limited to or restricted by it. For example, as Figure 18 As shown, the two input / output lines IO#0 and IO#1 can be electrically connected to each other. In this case, the two input / output lines IO#0 and IO#1 can be electrically connected to the same data bus, the DQ bus (see reference). Figure 13B ).

[0320] Figure 19 and Figures 20A to 20D It shows the use Figure 15 The CA control circuit will Figure 14 A diagram illustrating the operation of non-volatile memory device 310 configured to enter command-parallel mode. Figure 19 as well as Figures 20A to 20D As a representative example, the diagram illustrates the structure in which two CA lines, CA#0 and CA#1, are assigned. Figure 19 and Figures 20A to 20D Similar to Figure 16 and Figures 17A to 17D Therefore, redundant descriptions will be omitted.

[0321] refer to Figure 19 and Figure 20A The first CA control circuit CA CTRL1 is positioned to the left of each of the paths WAY#0 to WAY#3 in the zero path group WG#0. The first CA control circuit CA CTRL1 assigns the zero CA line CA#0 to the corresponding plane. That is, the zero CA line CA#0 is assigned to planes PLN0 to PLN3, which are positioned to the left of each of the planes included in each path WAY#0 to WAY#3 of the zero path group WG#0.

[0322] Reference Figure 19 and Figure 20B The second CA control circuit CA CTRL2 is positioned to the left of each of the paths WAY#4 to WAY#7 in the first path group WG#1. The second CA control circuit CA CTRL2 assigns the first CA line CA#1 to the corresponding plane. That is, the first CA line CA#1 is assigned to planes PLN0 to PLN3, which are positioned to the left of each of the planes included in each path WAY#4 to WAY#7 of the first path group WG#1.

[0323] Reference Figure 19 and Figure 20CThe third CA control circuit CA CTRL3 is set to the right of each of the paths WAY#0 to WAY#3 in the zero path group WG#0.

[0324] Since the chip IDs (CIDs) of the zero path group WG#0 are CID#0 to CID#3, the first multiplexer M1 selects the zero CA line CA#0, and the second multiplexer M2 selects the second CA line CA#2. Since the control signal of the third multiplexer M3 is "0", the third multiplexer M3 selects the first multiplexer M1.

[0325] Therefore, the third CA control circuit CA CTRL3 assigns the zeroth CA line CA#0 to the corresponding plane. That is, as... Figure 19 and Figure 20C As shown, the zeroth CA line CA#0 is assigned to planes PLN4 to PLN7, which are located on the right side of the planes included by each path WAY#0 to WAY#3 of the zeroth path group WG#0.

[0326] As a result, all planes of the zero path group WG#0, from path WAY#0 to WAY#3, receive commands through the zero CA line CA#0.

[0327] Reference Figure 19 and Figure 20D The fourth CA control circuit CA CTRL4 is located to the right of each of the paths WAY#4 to WAY#7 in the first path group WG#1.

[0328] Since the chip IDs (CIDs) of the first path group WG#1 are CID#4 to CID#7, the first multiplexer M1 selects the first CA line CA#1, and the second multiplexer M2 selects the third CA line CA#3. Since the control signal of the third multiplexer M3 is "0", the third multiplexer M3 selects the first multiplexer M1.

[0329] Therefore, the fourth CA control circuit CA CTRL4 assigns the first CA line CA#1 to the corresponding plane. That is, as... Figure 19 and Figure 20D As shown, the first CA line CA#1 is assigned to planes PLN4 to PLN7, which are located on the right side of the planes included in each path WAY#4 to WAY#7 of the first path group WG#1.

[0330] As a result, all planes of paths WAY#4 to WAY#7 in the first path group WG#1 receive commands through the first CA line CA#1.

[0331] like Figure 19 and Figures 20A to 20DAs described above, the non-volatile memory device 310 can receive commands in parallel via two CA lines, CA#0 and CA#1. Therefore, when the data size is relatively small, command overhead can be reduced, and power consumption can be adjusted appropriately.

[0332] exist Figure 19 and Figures 20A to 20D In the middle, the electrical connection of the two unassigned CA lines CA#2 and CA#3 can be cut off, so the two unassigned CA lines CA#2 and CA#3 can be in a floating state.

[0333] Figure 21 This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure. Figure 21 The non-volatile memory device 310 is similar to Figure 19 The non-volatile memory device 310. Therefore, redundant descriptions will be omitted.

[0334] exist Figure 19 In the diagram, two input / output lines IO#0 and IO#1 are shown as electrically connected to different data buses DQ bus #0 and DQ bus #1, respectively (reference). Figure 13A However, this is merely an example, and this disclosure should not be limited to or restricted by it. For example, as Figure 21 As shown, the two input / output lines IO#0 and IO#1 can be electrically connected to each other. In this case, the two input / output lines IO#0 and IO#1 can be electrically connected to the same data bus DQ bus (reference). Figure 13B ).

[0335] Figure 22 It is shown Figure 14 A diagram illustrating an example of a CA control circuit. Figure 22 The CA control circuit CA CTRL can be used with Figure 14 It corresponds to one of the first CA control circuit CA CTRL1 to the fourth CA control circuit CA CTRL4.

[0336] refer to Figure 22 The CA control circuit CA CTRL may include multiple multiplexers N1 and N2.

[0337] The first multiplexer N1 can be connected to the second CA line CA#2 and the third CA line CA#3, and can select one of the second CA line CA#2 and the third CA line CA#3 in response to a control signal. In this case, the chip ID CID can be provided as the control signal. For example, if the chip ID CID is CID#4 to CID#7, the first multiplexer N1 can select the third CA line CA#3. If the chip ID CID is not CID#4 to CID#7, the first multiplexer N1 can select the second CA line CA#2. In some embodiments, CID#4 to CID#7 can be the chip IDs of the fourth path WAY#4 to the seventh path WAY#7, respectively.

[0338] The second multiplexer N2 can be connected to the zero CA line CA#0 and the first multiplexer N1, and can select one of the zero CA line CA#0 and the first multiplexer N1 in response to a control signal. In this case, either "1" or "0" can be provided as the control signal. For example, when the control signal is "1", the output of the first multiplexer N1 can be selected. When the control signal is "0", the zero CA line CA#0 can be selected.

[0339] Figure 23 , Figure 24A and Figure 24B It shows the use Figure 22 The CA control circuit will Figure 14 A diagram illustrating the operation of a non-volatile memory device configured to enter command-parallel mode. In detail, Figure 23 This is a diagram illustrating the electrical connection state of the CA line in command-parallel mode according to some embodiments of the present disclosure. Figure 24A and Figure 24B It shows when entering Figure 23 Command - Parallel Mode Figure 22 A diagram illustrating the operation of the CA control circuit. Figure 23 , Figure 24A as well as Figure 24B The diagram illustrates the structure in which two CA lines, CA#2 and CA#3, are assigned.

[0340] refer to Figure 23 and Figure 24A The first CA control circuit CA CTRL1 and the third CA control circuit CA CTRL3 are set in each of the paths WAY#0 to WAY#3 in the zero path group WG#0.

[0341] Since the chip IDs (CIDs) of the zero path group WG#0 are CID#0 to CID#3, the first multiplexer N1 selects the second CA line CA#2. Since the control signal of the second multiplexer N2 is "1", the second multiplexer N2 selects the first multiplexer N1.

[0342] As a result, both the first CA control circuit CA CTRL1 and the third CA control circuit CA CTRL3 assign the second CA line CA#2 to the corresponding plane. That is, as... Figure 23 and Figure 24A As shown, the second CA line CA#2 is assigned to all planes included in each of the paths WAY#0 to WAY#3 of the zero path group WG#0.

[0343] Reference Figure 23 and Figure 24B The second CA control circuit CA CTRL2 and the fourth CA control circuit CA CTRL4 are set in each of the paths WAY#4 to WAY#7 of the first path group WG#1.

[0344] Since the chip IDs (CIDs) of the first path group WG#1 are CID#4 to CID#7, the first multiplexer N1 selects the third CA line, CA#3. Since the control signal of the second multiplexer N2 is "1", the second multiplexer N2 selects the first multiplexer N1.

[0345] As a result, both the second CA control circuit CA CTRL2 and the fourth CA control circuit CA CTRL4 assign the third CA line CA#3 to the corresponding plane. That is, as... Figure 23 and Figure 24B As shown, the third CA line CA#3 is assigned to all planes included in each of the paths WAY#4 to WAY#7 of the first path group WG#1.

[0346] For reference Figure 23 , Figure 24A and Figure 24B The non-volatile memory device 310 can receive commands in parallel via two CA lines, CA#2 and CA#3. Therefore, when the data size is relatively small, command overhead can be reduced, and power consumption can be adjusted appropriately.

[0347] exist Figure 23 , Figure 24A and Figure 24B In this process, the electrical connection between the two unassigned CA lines CA#0 and CA#1 can be cut off, so the two unassigned CA lines CA#0 and CA#1 can be in a floating state.

[0348] Figure 25This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure. Figure 25 The non-volatile memory device 310 is similar to Figure 23 The non-volatile memory device 310. Therefore, redundant descriptions will be omitted.

[0349] exist Figure 23 In the diagram, two input / output lines IO#0 and IO#1 are shown as electrically connected to different data buses DQ bus #0 and DQ bus #1, respectively (reference). Figure 13A However, this is merely an example, and this disclosure should not be limited to or restricted by it. For example, as Figure 25 As shown, the two input / output lines IO#0 and IO#1 can be electrically connected to each other. In this case, the two input / output lines IO#0 and IO#1 can be electrically connected to the same data bus DQ bus (reference). Figure 13B ).

[0350] Figure 26 and Figure 27 It shows the use Figure 22 The CA control circuit will Figure 14 A diagram illustrating the operation of a non-volatile memory device configured to enter command-serial mode. Specifically, Figure 26 This is a view showing the electrical connection status of the CA line in command-serial mode according to this disclosure. Figure 27 It is shown Figure 22 A diagram illustrating the operation of the CA control circuit when entering command-serial mode. Figure 26 and Figure 27 The diagram illustrates the structure of a CA line CA#0.

[0351] See Figure 26 and Figure 27 Since the control signal of the second multiplexer N2 is "0", the second multiplexer N2 selects the zero CA line CA#0. Therefore, all the first CA control circuits CA CTRL1 to the fourth CA control circuits CA CTRL4 assign the zero CA line CA#0 to the corresponding plane. That is, as... Figure 26 and Figure 27 As shown, the zeroth CA line CA#0 is assigned to all planes included in each of the zeroth path group WG#0 and the first path group WG#1.

[0352] Therefore, when the data size is large and command-address overhead is not a problem, command-serial mode can be executed to save power while maintaining data input / output performance.

[0353] exist Figure 26 and Figure 27In the middle, the electrical connection of the three unassigned CA lines CA#1, CA#2 and CA#3 can be cut off, so the three unassigned CA lines CA#1, CA#2 and CA#3 can be in a floating state.

[0354] Figure 28 This is a view showing the electrical connection state of the CA line in command-serial mode according to some embodiments of the present disclosure. Figure 28 The non-volatile memory device 310 is similar to Figure 26 The non-volatile memory device 310. Therefore, redundant descriptions will be omitted.

[0355] exist Figure 26 In the diagram, two input / output lines IO#0 and IO#1 are shown as electrically connected to different data buses DQ bus #0 and DQ bus #1, respectively (reference). Figure 13A However, this is merely an example, and this disclosure should not be limited to or restricted by it. For example, as Figure 28 As shown, the two input / output lines IO#0 and IO#1 can be electrically connected to each other. In this case, the two input / output lines IO#0 and IO#1 can be electrically connected to the same data bus DQ bus (reference). Figure 13B ).

[0356] Figure 29 This is a view showing a non-volatile memory device 310 formed by the TSV method according to some embodiments of the present disclosure. Figure 30 This is a diagram showing one of the paths of the non-volatile memory device 310. Figure 29 The non-volatile memory device 310 can be used with Figure 13C This corresponds to a non-volatile memory device. For ease of illustration, assume that the non-volatile memory device 310 includes four paths, and each path includes two planes.

[0357] Reference Figure 29 The non-volatile memory device 310 may include multiple paths WAY#0 to WAY#3 stacked in the vertical direction. In some embodiments, a path may be connected to... Figure 13C One chip corresponds to it.

[0358] Each of the paths WAY#0 to WAY#3 can include two planes.

[0359] For example, the first plane PLN1 and the second plane PLN2 can be arranged in the zero path WAY#0. The third plane PLN3 and the fourth plane PLN4 can be arranged in the first path WAY#1. The fifth plane PLN5 and the sixth plane PLN6 can be arranged in the second path WAY#2. The seventh plane PLN7 and the eighth plane PLN8 can be arranged in the third path WAY#3.

[0360] Each of the paths WAY#0 to WAY#4 may include a CA control circuit.

[0361] For example, the zeroth CA control circuit CA CTRL0 can be arranged in the zeroth path WAY#0. The first CA control circuit CACTRL1 can be arranged in the first path WAY#1. Similarly, the second CA control circuit CA CTRL2 and the third CA control circuit CA CTRL3 can be arranged in the second path WAY#2 and the third path WAY#3, respectively.

[0362] Paths WAY#0 to WAY#3 can be electrically connected to each other via the TSV method.

[0363] For example, four CA lines CA#0, CA#1, CA#2, and CA#3 can be electrically connected to paths WAY#0 to WAY#3 (zero path) respectively using the TSV method. Additionally, for example, one IO line IO#0 can be electrically connected to paths WAY#0 to WAY#3 (zero path) using the TSV method.

[0364] Each of the four CA lines, CA#0, CA#1, CA#2, and CA#3, can be electrically connected to a CA bus.

[0365] For example, the zeroth CA line CA#0 can be electrically connected to the zeroth CA bus CA bus #0 (reference). Figure 13C ), and the first CA line CA#1 can be electrically connected to the first CA bus CA bus #1 (see reference). Figure 13C Similarly, the second CA line CA#2 and the third CA line CA#3 can be electrically connected to the second CA bus and the third CA bus, respectively.

[0366] Each of the four CA lines CA#0, CA#1, CA#2, and CA#3 can be electrically connected to the CA pad group.

[0367] For example, such as Figure 30As shown, each path may include four CA pad groups CA_S0, CA_S1, CA_S2, and CA_S3, and one DQ pad group DQ_S0. In this case, the zeroth CA line CA#0 may be electrically connected to the zeroth CA pad group CA_S0 included in paths WAY#0 to WAY#3. The first CA line CA#1 may be electrically connected to the first CA pad group CA_S1 included in paths WAY#0 to WAY#3. Similarly, the second CA line CA#2 and the third CA line CA#3 may be electrically connected to the second CA pad group CA_S2 and the third CA pad group CA_S3, respectively.

[0368] IO line IO#0 can be electrically connected to the DQ bus. As an example, IO line IO#0 can be electrically connected to the DQ bus (see reference). Figure 13A ).

[0369] Additionally, IO line IO#0 can be electrically connected to the DQ pad group. As an example, the zeroth IO line IO#0 can be electrically connected to the zeroth DQ pad group DQ_S0, which is included in the paths WAY#0 to WAY#3.

[0370] In some embodiments of this disclosure, the CA control circuit may correspond to two planes, and CA lines corresponding to the planes may be assigned in CA lines CA#0 to CA#3.

[0371] For example, the zeroth path WAY#0 may include a zeroth CA control circuit CA CTRL0. The zeroth CA control circuit CA CTRL0 may correspond to the first plane PLN1 and the second plane PLN2. Additionally, the zeroth CA control circuit CA CTRL0 may assign one of the CA lines CA#0 to CA#3 to the first plane PLN1 and the second plane PLN2.

[0372] In some embodiments of this disclosure, when the data size is relatively small, the non-volatile memory device 310 can send and receive commands in parallel via the CA line. Therefore, command overhead can be reduced and data transmission efficiency can be improved.

[0373] In some embodiments of this disclosure, when the data size is relatively large, the non-volatile memory device 310 can serially send and receive commands via a single CA line. Therefore, power consumption can be reduced while maintaining a high level of data transfer efficiency.

[0374] Figure 31 It is shown Figure 29 A view of the CA control circuit. Figure 31 The CA control circuit CA CTRL can be used with Figure 29It corresponds to one of the zeroth CA control circuit CA CTRL0 to the third CA control circuit CA CTRL3.

[0375] refer to Figure 31 The CA control circuit CA CTRL may include multiple logic gates G1 to G5 and a multiplexer G6.

[0376] The first logic gate G1 through the fourth logic gate G4 can be NAND gates. The first logic gate G1 can receive the signal CA#0 of the zeroth CA line and the zeroth chip ID CID#0 as input. The second logic gate G2 can receive the signal CA#1 of the first CA line and the first chip ID CID#1 as input. Similarly, the third logic gate G3 can receive the signal CA#2 of the second CA line and the second chip ID CID#2 as input, and the fourth logic gate G4 can receive the signal CA#3 of the third CA line and the third chip ID CID#3 as input.

[0377] The fifth logic gate G5 can be an OR gate. The fifth logic gate G5 can receive the output signals of the first logic gate G1 through the fourth logic gate G4 as inputs.

[0378] Multiplexer G6 can be connected to the outputs of zero-line CA (CA#0) and fifth logic gate G5, and can select either the output of zero-line CA (CA#0) or the output of fifth logic gate G5 in response to a control signal. In this case, a "1" or "0" can be provided as the control signal. For example, when the control signal is "1", the output of fifth logic gate G5 can be selected. When the control signal is "0", zero-line CA (CA#0) can be selected.

[0379] Figures 32 to 33A to Figure 33D It shows the use Figure 31 The CA control circuit will Figure 29 A diagram illustrating the operation of a non-volatile memory device configured to enter command-parallel mode. Specifically, Figure 32 This is a view showing the electrical connection state of the CA line in command-parallel mode according to some embodiments of this disclosure. Figures 33A to 33D It shows when entering Figure 32 Command - Parallel Mode Figure 31 A diagram illustrating the operation of the CA control circuit. Figure 32 as well as Figures 33A to 33D The diagram illustrates the structure of the four CA lines: CA#0, CA#1, CA#2, and CA#3.

[0380] refer to Figure 32 and Figure 33A The zeroth CA control circuit CA CTRL0 can determine the CA line to be assigned to the zeroth path WAY#0.

[0381] In detail, since the chip ID CID of the zeroth path WAY#0 is CID#0, the input signal of the first logic gate G1 corresponding to the chip ID CID can always be activated to a high state. The input signals of the second logic gate G2 to the fourth logic gate G4 corresponding to the chip ID CID can always be deactivated to a low state.

[0382] Then, when a command is received via the zero CA line CA#0, another input signal among the input signals of the first logic gate G1 can be activated high. Therefore, the command received on the zero CA line CA#0 can be sent to the multiplexer G6 via the first logic gate G1 and the fifth logic gate G5. Furthermore, since the control signal of the multiplexer G6 is "1", the multiplexer G6 can select the fifth logic gate G5.

[0383] Therefore, the zeroth CA control circuit CA CTRL0 can assign the zeroth CA line CA#0 to the zeroth path WAY#0.

[0384] Similarly, refer to Figure 32 and Figure 33B The first CA control circuit CA CTRL1 can determine the CA line to be assigned to the first path WAY#1.

[0385] In detail, since the chip ID (CID) of the first path WAY#1 is CID#1, the input signal corresponding to the chip ID (CID) in the input signals of the second logic gate G2 can always be activated to a high state. Then, when a command is received through the first CA line CA#1, the command received on the first CA line CA#1 can be sent to the multiplexer G6 through the second logic gate G2 and the fifth logic gate G5. Since the control signal of the multiplexer G6 is "1", the multiplexer G6 can select the fifth logic gate G5.

[0386] Therefore, the first CA control circuit CA CTRL1 can assign the first CA line CA#1 to the first path WAY#1.

[0387] Similarly, refer to Figure 32 and Figure 33C The second CA control circuit, CA CTRL2, can determine the CA line to be assigned to the second pass path, WAY#2. For example, the second CA control circuit, CA CTRL2, can assign the second CA line, CA#2, to the second pass path, WAY#2.

[0388] Similarly, refer to Figure 32 and Figure 33DThe third CA control circuit, CA CTRL3, can determine the CA line to be assigned to the third path, WAY#3. For example, the third CA control circuit, CA CTRL3, can assign the third CA line, CA#3, to the third path, WAY#3.

[0389] As referenced above Figure 32 and Figures 33A to 33D The non-volatile memory device 310 can receive commands in parallel via four CA lines: CA#0, CA#1, CA#2, and CA#3. Therefore, command overhead can be reduced even when the data size is small.

[0390] Figure 34 and Figure 35 It shows the use Figure 31 The CA control circuit will Figure 29 The diagram illustrates the operation of the non-volatile memory device 310 configured to enter command-serial mode. In detail, Figure 34 This is a view showing the electrical connection state of the CA line in command-serial mode according to some embodiments of the present disclosure. Figure 35 This indicates when entering command-serial mode. Figure 31 A diagram illustrating the operation of the CA control circuit. Figure 34 and Figure 35 The diagram illustrates a representative example of a structure that assigns a CA line, CA#0.

[0391] refer to Figure 34 and Figure 35 Since the control signal of multiplexer G6 is "0", multiplexer G6 can select the zeroth CA line CA#0. Therefore, all the zeroth CA control circuits CA CTRL0 to CA CTRL3 can assign the zeroth CA line CA#0 to their corresponding paths. That is, as... Figure 34 and Figure 35 As shown, CA#0 in row zero can be assigned to all paths WAY#0 to WAY#3. Therefore, in cases where the data size is large and command-address overhead is not an issue, command-serial mode can be executed, which reduces power consumption while maintaining data input / output performance.

[0392] exist Figure 34 and Figure 35 In the middle, the electrical connection of the three unassigned CA lines CA#1, CA#2 and CA#3 can be cut off, so the three unassigned CA lines CA#1, CA#2 and CA#3 can be in a floating state.

[0393] Figure 36 , Figure 37 and Figures 38A to 38CThis is a view illustrating the operation of receiving a command requesting the reallocation of CA pad groups and changing the allocation of CA pad groups in response to that request. In detail, Figure 36 The diagram illustrates a command requesting the allocation of four CA lines: CA#0, CA#1, CA#2, and CA#3. Figure 37 The command requested to allocate two CA lines, CA#0 and CA#1, is shown. Figure 38A A non-volatile memory device 310 in its initial state is shown. Figure 38B It shows that the electrical connection state responds to Figure 36 The non-volatile memory device 310 is modified by commands. Figure 38C It shows that the electrical connection state responds to Figure 37 The non-volatile memory device 310 is modified by commands. Figures 38A to 38C Non-volatile memory device 310 and Figures 14 to 28 It is similar to the non-volatile memory device 310. Therefore, redundant descriptions will be omitted.

[0394] First, the description will start from Figure 38A The state in Figure 38B An example of the redistribution of the CA line in the state.

[0395] Reference Figure 36 , Figure 38A and Figure 38B The LUN selection packet LUNSel can be received via the zero CA line CA#0. The LUN selection packet LUNSel can indicate the fourth path WAY#4.

[0396] Then, a CA change header can be received via the zero CA line CA#0. The CA change header may include information indicating that the CA line previously assigned to the fourth path WAY#4 has been changed.

[0397] Then, the CA change subject can be received via the zeroth CA line CA#0. For example, the CA change subject can include 8 bits, where the first 4 bits can indicate the target plane, and the last 4 bits can indicate the CA line to which the target plane will reassign. For example, the first 4 bits "0000" can indicate the zeroth plane PLN0, i.e., the target plane, and the last 4 bits "0001" can indicate the first CA line CA#1 to which the target plane will be reassigned.

[0398] Therefore, the non-volatile memory device 310 can reassign the zero plane PLN0 of the fourth path WAY#4 to the first CA line CA#1.

[0399] These commands can be repeatedly received on the first plane PLN1 to the third plane PLN3 for the fifth path WAY#5 to the seventh path WAY#7. Therefore, as Figure 38BAs shown, the non-volatile memory device 310 can reassign planes belonging to the first path group WG#1 and the zero plane group PG#0 to the first CA line CA#1.

[0400] Similarly, the LUN selection packet LUNSel can be received via the first CA line CA#1. The LUN selection packet LUNSel can indicate the zeroth path WAY#0.

[0401] Then, the CA change header can be received via the first CA line CA#1.

[0402] Then, the CA change subject can be received via the first CA line CA#1. For example, the CA change subject may include 8 bits, where the first 4 bits "0000" may indicate the zero plane PLN0, i.e., the target plane, and the last 4 bits "0000" may indicate the zero CA line CA#0 to which the target plane will be reassigned. Therefore, the non-volatile memory device 310 can reassign the zero plane PLN0 of the zero path WAY#0 to the zero CA line CA#0.

[0403] These commands can be repeatedly received for the first plane PLN1 to the third plane PLN3 of the first path WAY#1 to the third path WAY#3. Therefore, as Figure 38B As shown, the non-volatile memory device 310 can reassign planes belonging to the zero path group WG#0 and the zero plane group PG#0 to the zero CA line CA#0.

[0404] In this way, planes belonging to the zero path group WG#0 and the first plane group PG#1 can be reassigned to the second CA line CA#2. Furthermore, planes belonging to the first path group WG#0 and the first plane group PG#1 can be reassigned to the third CA line CA#3.

[0405] Then, the description will be from Figures 38B to 38C An example of reassigning CA lines.

[0406] refer to Figure 36 , Figure 38B and Figure 38C The LUN selection packet LUNSel can be received via the second CA line CA#2. The LUN selection packet LUNSel can indicate the zeroth path WAY#0.

[0407] Then, the CA change header can be received via the second CA line, CA#2.

[0408] Subsequently, the CA change subject can be received via the second CA line CA#2. For example, the CA change subject may include 8 bits, where the first 4 bits "0001" can indicate the fourth plane PLN4, i.e., the target plane, and the last 4 bits "0011" can indicate the zero CA line CA#0 to which the target plane will be reassigned.

[0409] Therefore, the non-volatile memory device 310 can reassign the fourth plane PLN4 of the zero path way#0 from the second CA line CA#2 to the zero CA line CA#0.

[0410] These commands can be repeatedly received for the fifth plane PLN5 to the seventh plane PLN7 of the first path WAY#1 to the third path WAY#3. Therefore, as Figure 38C As shown, the non-volatile memory device 310 can reassign planes belonging to the zero path group WG#0 and the first plane group PG#1 from the second CA line CA#2 to the zero CA line CA#0.

[0411] Similarly, the LUN selection packet LUNSel can be received via the third CA line CA#3. The LUN selection packet LUNSel can indicate the fourth path WAY#4.

[0412] Then, the CA change header can be received via the third CA line, CA#3.

[0413] Subsequently, the CA change subject can be received via the third CA line CA#3. For example, the CA change subject may include 8 bits, where the first 4 bits "0001" can indicate the fourth plane PLN4, i.e., the target plane, and the last 4 bits "0010" can indicate the first CA line CA#1, which will be used to reallocate the target plane.

[0414] Therefore, the non-volatile memory device 310 can reassign the fourth plane PLN4 of the first pass path WAY#1 from the third CA line CA#3 to the first CA line CA#1.

[0415] These commands can be repeatedly received for the fifth plane PLN5 to the seventh plane PLN7 of the fifth path WAY#5 to the seventh path WAY#7. The result is as follows: Figure 38C As shown, the non-volatile memory device 310 can reassign planes belonging to the first path group WG#1 and the first plane group PG#1 from the third CA line CA#3 to the first CA line CA#1.

[0416] As described above, the non-volatile memory device according to this disclosure can variably adjust the number of CA lines receiving commands in response to a request from the memory controller.

[0417] exist Figure 36 , Figure 37 and Figures 38A to 38C The reception of LUN selection packets has already been described. However, this is merely an example, and this disclosure should not be limited to or construed as such. According to embodiments, LUN selection packets may not be received, and path address information may be received separately.

[0418] Figure 39 This is a block diagram illustrating a non-volatile memory device 410 that supports the reallocation of CA pad groups during rerouting, according to some embodiments of the present disclosure. Figure 39 The non-volatile memory device 410 is similar to the non-volatile memory devices 110, 210, 310 described above, or to a chip or die included in a non-volatile memory device. Therefore, redundant descriptions will be omitted. For ease of explanation, it is assumed that eight planes PLN1 to PLN8 are arranged on the non-volatile memory device 410.

[0419] Reference Figure 39 The non-volatile memory device 410 may include eight planes PLN1 to PLN8. The third CA line CA#3 and the third IO line IO#3 may be assigned to the first plane PLN1 and the second plane PLN2 among the planes PLN1 to PLN8. The first CA line CA#1 and the first IO line IO#1 may be assigned to the third plane PLN3 and the fourth plane PLN4. The fourth CA line CA#4 and the fourth IO line IO#4 may be assigned to the fifth plane PLN5 and the sixth plane PLN6. The second CA line CA#2 and the second IO line IO#2 may be assigned to the seventh plane PLN7 and the eighth plane PLN8.

[0420] In some embodiments of this disclosure, the first CA control circuit CA CTRL1 may correspond to the first plane PLN1 and the second plane PLN2. During rerouting, the first CA control circuit CA CTRL1 may change the CA line corresponding to the first plane PLN1 and the second plane PLN2. For example, when the first IO line IO#1 and the third IO line IO#3 are merged due to rerouting, the first CA control circuit CA CTRL1 may change the CA line allocated to the first plane PLN1 and the second plane PLN2 from the third CA line CA#3 to the first CA line CA#1.

[0421] In some embodiments of this disclosure, the second CA control circuit CA CTRL2 may correspond to the fifth plane PLN5 and the sixth plane PLN6. During rerouting, the second CA control circuit CA CTRL2 may change the CA line corresponding to the fifth plane PLN5 and the sixth plane PLN6. For example, when the second IO line IO#2 and the fourth IO line IO#4 are merged due to rerouting, the second CA control circuit CA CTRL2 may change the CA line assigned to the fifth plane PLN5 and the sixth plane PLN6 from the fourth CA line CA#4 to the second CA line CA#2.

[0422] Figure 40A It is shown Figure 39 A view of the first CA control circuit, and Figure 40B It is shown Figure 39 A view of the second CA control circuit.

[0423] refer to Figure 40A The first CA control circuit CA CTRL1 may include multiple multiplexers R1 and R2.

[0424] The first multiplexer R1 can receive the signal from the first CA line CA#1 and the output of the second multiplexer R2 as inputs. The first multiplexer R1 can select one of the two inputs in response to a control signal. In this case, a "1" or "0" can be provided as the control signal. For example, when the control signal is "1", the first CA line CA#1 can be selected. When the control signal is "0", the output of the second multiplexer R2 can be selected. The output of the first multiplexer R1 can be configured to be distributed to the CA lines of the third plane PLN3 and the fourth plane PLN4.

[0425] The second multiplexer R2 can receive the signal from the third CA line CA#3 and the output of the first multiplexer R1 as inputs. The second multiplexer R2 can select one of the two inputs in response to a control signal. In this case, a "1" or "0" can be provided as the control signal. For example, when the control signal is "0", the third CA line CA#3 can be selected. When the control signal is "1", the output of the first multiplexer R1 can be selected. The output of the second multiplexer R2 can be configured to be allocated to the CA lines of the first plane PLN1 and the second plane PLN2.

[0426] Similarly, refer to Figure 40B The second CA control circuit CA CTRL2 may include multiple multiplexers R3 and R4.

[0427] The third multiplexer R3 can receive the signal from the second CA line CA#2 and the output of the fourth multiplexer R4 as inputs. The third multiplexer R3 can select one of the two inputs in response to a control signal. In this case, a "1" or "0" can be provided as the control signal. For example, when the control signal is "1", the second CA line CA#2 can be selected. When the control signal is "0", the output of the fourth multiplexer R4 can be selected. The output of the third multiplexer R3 can be configured to be allocated to the CA lines of the seventh plane PLN7 and the eighth plane PLN8.

[0428] The fourth multiplexer R4 can receive the signal from the fourth CA line CA#4 and the output of the third multiplexer R3 as inputs. The fourth multiplexer R4 can select one of the two inputs in response to a control signal. In this case, a "1" or "0" can be provided as the control signal. For example, when the control signal is "0", the fourth CA line CA#4 can be selected. When the control signal is "1", the output of the third multiplexer R3 can be selected. The output of the fourth multiplexer R4 can be configured to be allocated to the CA lines of the fifth plane PLN5 and the sixth plane PLN6.

[0429] Figure 41 This is a view showing the operation of the CA control circuit when rerouting is not performed. For ease of explanation, the first CA control circuit, CA CTRL1, will be described primarily below.

[0430] refer to Figure 39 and Figure 41 When rerouting is not performed, a control signal "1" can be provided to the first multiplexer R1. Therefore, the first CA line CA#1 can be assigned to the third plane PLN3 and the fourth plane PLN4. Furthermore, a control signal "0" can be provided to the second multiplexer R2. Therefore, the third CA line CA#3 can be assigned to the first plane PLN1 and the second plane PLN2.

[0431] Figure 42 and Figure 43 This is a view illustrating the operation of the CA control circuit during rerouting. For ease of explanation, the first CA control circuit, CA CTRL1, will be described primarily below.

[0432] Reference Figure 42 and Figure 43 The first IO line IO#1 and the third IO line IO#3 can be merged into each other during rerouting. In this case, the first CA control circuit CA CTRL1 can change the CA line corresponding to the first plane PLN1 and the second plane PLN2 from the third CA line CA#3 to the first CA line CA#1.

[0433] In detail, such as Figure 43 As shown, during rerouting, a control signal "1" can be provided to the first multiplexer R1. Therefore, the first CA line CA#1 can be assigned to the third plane PLN3 and the fourth plane PLN4. Furthermore, a control signal "1" can be provided to the second multiplexer R2. Therefore, the first CA line CA#1 can also be assigned to the first plane PLN1 and the second plane PLN2.

[0434] Similarly, the second IO line IO#2 and the fourth IO line IO#4 can be merged into each other during rerouting. In this case, the second CA control circuit CA CTRL2 can change the CA line corresponding to the fifth plane PLN5 and the sixth plane PLN6 from the fourth CA line CA#4 to the second CA line CA#2.

[0435] As described above, if the assigned CA lines are not changed during rerouting, some planes may become uncontrolled due to the rerouting. For example, when the first IO line IO#1 and the third IO line IO#3 are merged together through rerouting, the first plane PLN1 and the second plane PLN2 may no longer be controlled by the third CA line CA#3. Conversely, the non-volatile memory device 410 according to some embodiments of this disclosure can operate the planes error-free by changing the corresponding CA lines during rerouting.

[0436] As used herein, the term “at least one” may refer to and cover any and all possible combinations of one or more of the associated listed terms. For example, the term “at least one of A, B or C” means (i) at least one of A, (ii) at least one of B, (iii) at least one of C, (iv) at least one of A and at least one of B, (v) at least one of B and at least one of C, (vi) at least one of A and at least one of C, or (vi) at least one of A, at least one of B and at least one of C is possible, wherein A, B and C may be singular or plural.

[0437] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather as descriptions of features specific to particular embodiments of a particular invention. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0438] Although this disclosure has been described with reference to its embodiments, those skilled in the art will understand that various changes and modifications can be made thereto without departing from the spirit and scope of this disclosure as set forth in the following claims.

Claims

1. A non-volatile memory device, comprising: A memory cell array comprising multiple planes; The page buffer circuit is connected to the memory cell array via multiple bit lines; The input / output circuit is connected to the page buffer circuit via multiple data lines; The control logic circuitry is configured to control the operation of multiple planes based on commands; The first command-address pad group is electrically connected to the control logic circuit, wherein the first command-address pad group is configured to receive a first command; and The second command-address pad group is electrically connected to the control logic circuit, wherein the second command-address pad group is configured to receive a second command, and The duration of receiving the first command overlaps with the duration of receiving the second command.

2. The non-volatile memory device according to claim 1, wherein, The first command includes: The first read command requests a read operation on the first plane among multiple planes; The first state read (SR) command requests the completion status of the read operation corresponding to the first plane; and The first data output command requests the output of data read from the first plane, and the second command includes: The second read command requests a read operation on the second plane among multiple planes; The second SR command requests the completion status of the read operation corresponding to the second plane; and The second data output command requests the output of data read from the second plane.

3. The non-volatile memory device according to claim 1, comprising a command-address control circuit electrically connected to the first command-address pad group and the second command-address pad group, wherein, The command-address control circuit is configured to select at least one of a plurality of planes and assign a first command-address pad group and a second command-address pad group to the at least one plane.

4. The non-volatile memory device according to claim 3, wherein, The command-address control circuitry is configured to determine at least one of a plurality of planes based on the size of the data.

5. The non-volatile memory device according to claim 4, wherein, The command-address control circuitry is configured to assign at least two of the multiple planes to the first command-address pad group based on the data size being greater than the reference size.

6. The non-volatile memory device according to claim 5, wherein, The command-address control circuit is configured to disconnect the electrical connection of the command-address line connected to the second command-address pad group.

7. The non-volatile memory device according to claim 4, wherein, The command-address control circuitry is configured to assign the first command-address pad group and the second command-address pad group to different planes among multiple planes based on the data size being smaller than the reference size.

8. The non-volatile memory device according to claim 7, comprising: The third command-address pad group is electrically connected to the control logic circuit, wherein the third command-address pad group is configured to receive a third command; and The fourth command-address pad group is electrically connected to the control logic circuit, wherein the fourth command-address pad group is configured to receive the fourth command. The command-address control circuit is configured to disconnect the electrical connection of the command-address lines connected to the third command-address pad group and is also configured to disconnect the electrical connection of the command-address lines connected to the fourth command-address pad group.

9. The non-volatile memory device according to claim 7, comprising: The third command-address pad group is electrically connected to the control logic circuit, wherein the third command-address pad group is configured to receive a third command; and The fourth command-address pad group is electrically connected to the control logic circuit, wherein the fourth command-address pad group is configured to receive the fourth command. The first command-address pad group, the second command-address pad group, the third command-address pad group, and the fourth command-address pad group are assigned to different corresponding planes among multiple planes.

10. The non-volatile memory device according to claim 3, wherein, The command-address control circuitry is configured to determine at least one of a plurality of planes based on a command-address change request from the memory controller.

11. The non-volatile memory device according to claim 10, wherein, The command-address change request includes a header and a body, wherein the body includes address information of the plane to which the first command-address pad group is assigned.

12. The non-volatile memory device according to claim 10, wherein, The command-address change request includes a logical unit number (LUN) select signal, wherein the LUN select signal includes address information of the path assigned to the first command-address pad group.

13. The non-volatile memory device according to claim 3, wherein, The command-address control circuitry and the memory cell array are arranged on the same die.

14. The non-volatile memory device according to claim 3, wherein, Command-address control circuitry and memory cell arrays are arranged on different dies.

15. The non-volatile memory device according to claim 1, comprising: A first data pad group, electrically connected to an input / output circuit, wherein the first data pad group is configured to output first data corresponding to a first command; and The second data pad group is electrically connected to the input / output circuit, wherein the second data pad group is configured to output second data corresponding to the second command.

16. A non-volatile memory device, comprising: First chip; as well as The second chip is stacked on top of the first chip, wherein the first chip includes: The first memory cell array comprises multiple planes. The first page buffer circuit is connected to the first memory cell array via multiple bit lines. The first input / output circuit is connected to the first page buffer circuit via multiple data lines. The first control logic circuit is configured to control operations on multiple planes based on a first command. The first command-address pad group is electrically connected to the first control logic circuit and electrically connected to the first command-address line, and The second command-address pad group is electrically connected to the first control logic circuit and electrically connected to the second command-address line, wherein the second chip includes: The second memory cell array comprises multiple planes. The second page buffer circuit is connected to the second memory cell array via multiple bit lines. The second input / output circuit is connected to the second page buffer circuit via multiple data lines. The second control logic circuit is configured to control operations on multiple planes based on the second command. The third command-address pad group is electrically connected to the first command-address line, and The fourth command-address pad group is electrically connected to the second command-address line, wherein the reception duration of the first command via the first command-address line overlaps with the reception duration of the second command via the second command-address line.

17. The non-volatile memory device of claim 16, comprising a first die and a second die, wherein the first die comprises: The first command-address control circuit is electrically connected to the first command-address line; as well as The second command-address control circuit is electrically connected to the second command-address line, and The second nude film includes: The third command-address control circuit is electrically connected to the first command-address line; and The fourth command - address control circuit is electrically connected to the second command - address line.

18. The non-volatile memory device according to claim 17, wherein, The first and second dies are electrically connected to each other via pad wiring.

19. The non-volatile memory device according to claim 17, wherein, The first die and the second die are electrically connected to each other through a through-silicon via.

20. A non-volatile memory device, comprising: A memory cell array comprising multiple planes; The page buffer circuit is connected to the memory cell array via multiple bit lines; The input / output circuit is connected to the page buffer circuit via multiple data lines; The control logic circuitry is configured to control operations on multiple planes based on commands. The first command-address pad group is electrically connected to the control logic circuit, wherein the first command-address pad group is configured to receive a first command; The second command-address pad group is electrically connected to the control logic circuit, wherein the second command-address pad group is configured to receive a second command; and At least one data pad group is electrically connected to input / output circuitry, wherein the at least one data pad group is configured to output first data corresponding to a first command and second data corresponding to a second command. The control logic circuit is configured to determine, based on the data size in the data output operation, the plane to which the first command-address pad group and the second command-address pad group are assigned among multiple planes.

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