A data processing method, apparatus, and storage device

Abstract

This invention discloses a data processing method, apparatus, and storage device. After detecting a trigger event, the method determines the target word line group containing the target physical page corresponding to the trigger event, obtains the local optimal read reference voltage for each predetermined storage state of each word line in the target word line group, determines the global optimal read reference voltage for the corresponding storage state based on the local optimal read reference voltages of each word line in the same storage state, and determines a processing strategy for each word line based on the statistical relationship between the global optimal read reference voltage and the local optimal read reference voltage. The processing strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table. This reduces the consumption of internal bandwidth resources and improves the system performance, lifespan, and energy efficiency of the storage device.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a data processing method, apparatus, and storage device. Background Technology

[0002] In NAND flash-based solid-state storage devices, read interference is a key factor affecting data reliability. Repeated reads of a physical page can cause the threshold voltage of adjacent storage cells to rise due to the coupled electric field. If the original optimal read voltage is used for decision-making, the bit error rate will increase. At the same time, host data access is significantly non-uniform, and physical blocks with concentrated hot data will be subjected to a much higher number of read operations than average, exacerbating read interference.

[0003] To address this issue, existing technologies generally employ read count detection and data migration mechanisms: a read operation counter is maintained for each physical block, and when the count value exceeds a preset threshold, garbage collection or data migration is triggered, moving the valid pages in that block to a new physical location. This mechanism maintains data integrity by physically isolating blocks with severe read interference.

[0004] However, the aforementioned relocation operation not only consumes valuable internal bandwidth resources, but also introduces additional write operations, leading to increased write amplification, which in turn affects system performance, lifespan, and energy efficiency. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a data processing method, apparatus and storage device that can reduce the consumption of internal bandwidth resources and improve the system performance, lifespan and energy efficiency of the storage device.

[0006] In a first aspect, embodiments of the present invention provide a data processing method, the method comprising: Read the data from the voltmeter; In response to detecting a predetermined trigger event, the target word line group of the target physical page corresponding to the trigger event is determined, and the target word line group includes multiple word lines; Obtain the local optimal read reference voltage for each predetermined storage state of each of the word lines; The global optimal read reference voltage for the corresponding memory state is determined based on the local optimal read reference voltage of each word line in the same memory state. The processing strategy for each word line is determined based on the statistical relationship between the global optimal read reference voltage and the local optimal read reference voltage. The processing strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table.

[0007] In some embodiments, the triggering event includes at least one of the following: The count of invalid bits in the target physical page is greater than or equal to the first threshold; Read operations trigger read retry; A read operation triggers a read recovery.

[0008] In some embodiments, the predetermined storage state is the complete storage state of the word line or a pre-set partial storage state.

[0009] In some embodiments, obtaining the locally optimal read reference voltage for each predetermined storage state of each of the word lines includes: Determine multiple candidate read reference voltages corresponding to each predetermined storage state; Data is read based on the multiple candidate reference voltages; Detect the bit error rate of the read data; The reading reference voltage with the minimum bit error rate is inferred by using methods such as parabolic fitting and is determined as the local optimal reading reference voltage.

[0010] In some embodiments, determining the global optimal read reference voltage for a corresponding memory state based on the local optimal read reference voltages of each word line in the same memory state includes: The average value of the local optimal read reference voltage of each word line in the same storage state is taken as the global optimal read reference voltage in the corresponding storage state.

[0011] In some embodiments, determining the handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage includes: The variance is obtained based on the global optimal read reference voltage and the local optimal read reference voltage; In response to the variance being less than or equal to the second threshold, the reading voltage meter is updated according to the globally optimal reading reference voltage.

[0012] In some embodiments, determining the handling strategy for each word line based on the globally optimal read reference voltage further includes: In response to the variance being greater than a second threshold, hotspot word lines in the target word line group are obtained; Detect whether the offset of each hotspot character line is greater than or equal to the third threshold; In response to an offset greater than or equal to the third threshold, the valid data of the corresponding hotspot word line is migrated to the newly allocated physical page.

[0013] In some embodiments, obtaining the hotspot characters in the target character group includes: Obtain the offset of the local optimal read reference voltage of each word line relative to the global optimal read reference voltage under the same storage state; Word lines with an offset greater than or equal to the fourth threshold are identified as hotspot word lines.

[0014] In some embodiments, determining the handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage further includes: In response to an offset less than the third threshold, the valid data of the corresponding hotspot word line is pre-read and loaded into the hotspot read cache.

[0015] In a second aspect, embodiments of the present invention provide a storage device, the device comprising: NAND flash memory includes multiple memory cells, multiple bit lines, and multiple word lines. The multiple bit lines extend along a first direction, and the multiple word lines extend along a second direction perpendicular to the first direction. The multiple memory cells are arranged into multiple cell strings. Multiple memory cells in each cell string are connected in series along the first direction, and the ends of each cell string are connected to the corresponding bit lines. The control gate of each memory cell is electrically connected to the corresponding word line. Multiple memory cells connected to the same word line constitute a physical page. A controller for implementing the method described in the first aspect.

[0016] Thirdly, embodiments of the present invention provide a data processing apparatus, the apparatus comprising: The data reading unit is used to read data from the voltmeter. A word line group determination unit is used to determine the target word line group where the target physical page corresponding to the trigger event is located in response to the detection of a predetermined trigger event, wherein the target word line group includes multiple word lines; A local voltage determination unit is used to obtain the local optimal read reference voltage of each predetermined storage state of each of the word lines; The global voltage determination unit is used to determine the global optimal read reference voltage for the corresponding memory state based on the local optimal read reference voltage of each word line in the same memory state. The strategy determination unit is used to determine the handling strategy for each word line based on the statistical relationship between the global optimal read reference voltage and the local optimal read reference voltage. The handling strategy includes loading data into a predetermined hot spot read cache, migrating data to a newly allocated physical page, and updating the read voltage table.

[0017] Fourthly, embodiments of the present invention provide a computer program product comprising a computer program, wherein when the computer program is run on a computer, the computer executes the method described in the first aspect above.

[0018] Fifthly, embodiments of the present invention provide a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the method described in the first aspect.

[0019] The technical solution of this invention, upon detecting a trigger event, determines the target word line group where the target physical page corresponding to the trigger event is located, obtains the local optimal read reference voltage for each predetermined storage state of each word line in the target word line group, determines the global optimal read reference voltage for the corresponding storage state based on the local optimal read reference voltages of each word line in the same storage state, and determines the handling strategy for each word line based on the statistical relationship between the global optimal read reference voltage and the local optimal read reference voltage. The handling strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table. This reduces the consumption of internal bandwidth resources and improves the system performance, lifespan, and energy efficiency of the storage device. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of a storage device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a reading voltmeter according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the character line group according to an embodiment of the present invention; Figure 4 This is a flowchart of a data processing method according to an embodiment of the present invention; Figure 5 This is a flowchart of a data processing method according to another embodiment of the present invention; Figure 6 This is a schematic diagram of a data processing apparatus according to an embodiment of the present invention. Detailed Implementation

[0021] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0022] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0023] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0024] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0025] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0026] With the rapid development of information technology, the amount of data is also gradually increasing, which places higher demands on the performance, capacity, and reliability of data storage systems. Solid-state drives (SSDs) based on NAND flash memory have become a core storage component in modern computing architectures due to their advantages such as low latency, high throughput, and strong shock resistance. They are widely used in various fields, from consumer electronics to enterprise data centers. To meet the ever-increasing capacity demands while maintaining cost-effectiveness, NAND flash memory technology is evolving along two key directions: first, from planar structures to 3D stacked structures, significantly increasing storage density by increasing the number of storage layers; second, storing more bits in each storage cell, i.e., evolving from single-level cells (SLC) to multi-level cells (MLC), triple-level cells (TLC), and even quad-level cells (QLC). While these two technical approaches effectively expand storage capacity, they also present more severe physical challenges to the charge storage capacity of storage cells and the accuracy of read and write operations.

[0027] Read disturbance is an inherent reliability issue in NAND flash memory that has become increasingly prominent with technological advancements. Its physical root lies in the fundamental operating mechanism of NAND flash memory: reading a specific physical page essentially involves applying a series of reference voltage pulses to the word line (WL) of the target memory cell to probe the charge state in its floating gate or charge trap layer. During this process, unaddressed memory cells within the same block, especially those on word lines adjacent to the target page, inevitably suffer from unexpected, weak electric field coupling. This repeated accumulation of stress causes minute charge transitions in the floating gate, resulting in gradual charge accumulation or loss, macroscopically manifested as a shift in the threshold voltage (Vth). For TLC and QLC technologies employing multi-bit storage, because the voltage window is divided extremely finely, even a tiny threshold voltage drift is sufficient to cause errors in the storage state. As the number of reads increases, the threshold voltage distribution curve will shift towards higher voltage (or a specific direction). If the SSD controller still uses the factory-set optimal read reference voltage for ideal conditions to determine the data to be stored, it will lead to a large number of bit errors, causing the raw bit error rate (RBER) to rise sharply, eventually exceeding the error correction capability of the error correction code (ECC), resulting in data corruption or unrecoverable read errors.

[0028] In practical applications, host access patterns to storage systems exhibit significant non-uniformity. Based on the frequency of data access, it can be categorized into cold data (rarely accessed), warm data (occasionally accessed), and hot data (frequently accessed). This difference in data temperature is a typical characteristic of SSD workloads. When frequently accessed hot data is logically contiguous, or due to the physical placement strategies of existing garbage collection (GC) and wear leveling algorithms, and is concentrated in one or a few NAND physical blocks, these specific blocks will experience a much higher number of read operations than the system average. This localized concentration of read pressure caused by workload characteristics acts as an amplifier for read interference effects. Once the cumulative number of reads in a block exceeds its designed threshold, the read interference effect will worsen dramatically within that block, severely threatening the integrity and reliability of all data within it (including cold data).

[0029] With the widespread adoption of 3D NAND technology, the physical capacity of a single block has significantly increased due to the increase in the number of stacked layers. This means that a block can store more data pages. From a probabilistic perspective, the probability of a large-capacity block becoming a read hotspot increases accordingly. Once a hot data stream is allocated to a large-capacity block, the resulting local read interference effect will affect a wider range and a greater number of storage pages, multiplying the potential risk of data corruption. This undoubtedly exacerbates the severity of the local read interference problem.

[0030] While read-count-based data migration mechanisms are logically simple and effective in preventing data errors caused by read interference, they suffer from inherent resource, performance, and efficiency bottlenecks. A data migration operation essentially involves performing an additional, non-host-requested write operation. This directly leads to an increase in Write Amplification Factor (WAF). Each migration performed to mitigate read interference means the SSD needs to consume more NAND programming / erase cycles to complete work unrelated to the actual host write task. This not only consumes valuable internal bandwidth and reduces the effective throughput of the SSD in handling actual I / O requests, but also accelerates the wear and tear of the NAND flash memory, directly impacting the overall lifespan of the SSD. The garbage collection process that triggers data migration is a background task, but its execution consumes critical resources such as the controller, cache, and NAND channels. Especially under high system load, sudden data migration operations initiated to cope with read interference thresholds can compete for resources with normal read / write requests from the host, leading to significant latency spikes and I / O performance jitter. This is unacceptable for latency-sensitive enterprise applications and real-time systems. The additional data migration operations mean more chip activation, data transfer, and programming / erasing actions, directly increasing the overall power consumption of the SSD and reducing its energy efficiency. In the era of pursuing low-carbon, energy-saving green computing, this negative effect cannot be ignored. Setting the read interference threshold itself presents a dilemma. Setting it too low will trigger frequent and unnecessary migrations, excessively consuming performance and lifespan; setting it too high may expose data to the real risk of read interference, increasing the probability of data corruption. A fixed threshold cannot adaptively adapt to changes in different load characteristics and NAND aging levels.

[0031] Therefore, embodiments of the present invention provide a storage device and a corresponding data processing method to solve the above problems.

[0032] Figure 1 This is a schematic diagram of a storage device according to an embodiment of the present invention. Figure 1As shown, the storage device in this embodiment of the invention includes one or more of the following: interface 1, controller 2, NAND flash memory 3, and cache chip 4.

[0033] The storage device connects to the host via interface 1. Interface 1 is the Host Interface Protocol, a standardized protocol in SSD system architecture used for communication between the host (such as a computer or server) and controller 2. It defines the data transmission rules, translating I / O requests from the host into instructions that the SSD can process, and performing data read / write operations. Furthermore, the Host Interface Protocol defines the agreed-upon data transmission format, command set, and timing rules between the host and the SSD controller, ensuring that both parties can correctly parse and execute instructions. For example, when the host sends a read / write request via this protocol, controller 2 receives it, calls the FTL (Flash Translation Layer) to map the logical address to the physical address, and then writes data to the flash memory or reads data back to the host via the NAND channel.

[0034] In some embodiments, interface 1 can be implemented through interfaces such as PCIe (NVMe).

[0035] Controller 2 is used to manage data read and write operations, wear leveling, garbage collection, error correction (ECC), and mapping logical addresses to physical storage units. Controller 2 integrates the main controller processor, FTL (Flash Translation Layer) algorithm, ECC, NAND channel management, and other functions to achieve data read / write scheduling, address mapping, error checking, and performance optimization.

[0036] NAND flash memory 3 is used to store data. Figure 1 In the illustrated embodiment, the storage device includes multiple NAND flash memory modules. Communication between the controller 2 and the NAND flash memory 3 requires a bridge, called a channel. Each channel also has multiple NAND flash memory modules running in parallel. Figure 1 In the illustrated embodiment, two channels are shown, each containing eight NAND flash memory modules.

[0037] NAND flash memory is a non-volatile storage technology that uses electronic storage cells (called storage cells) to store data. Each storage cell is a floating-gate transistor. According to the number of bits stored by the floating-gate transistor, NAND flash memory can be divided into single-level storage cells (SLC), multi-level storage cells (MLC), triple-level storage cells (TLC), quad-level storage cells (QLC), and penta-level storage cells (PLC), etc. An n-level storage cell can store n bits.

[0038] A floating-gate transistor has a charge storage layer (floating gate or silicon nitride layer) wrapped in an insulating layer above the channel between the source and drain. This structure utilizes the FN tunneling effect or hot electron injection mechanism from quantum mechanics to achieve bidirectional migration of electrons between the channel and the storage layer: when electrons are injected into the storage layer, they shield the control gate electric field, causing the threshold voltage of the transistor to rise; conversely, when electrons are removed, the threshold voltage decreases. Subsequent read and write processes are based on this physical property: writing involves applying a high voltage to lock electrons into the storage layer to change the threshold voltage state, while reading involves applying a specific reference voltage to detect whether the channel is conducting, thereby deducing the amount of charge in the storage layer and the corresponding logic data.

[0039] Writing (programming) NAND flash memory is essentially the process of injecting electrons into the floating gate or charge trapping layer. This operation is based on the FN tunneling effect, which creates a strong electric field by applying a high positive voltage to the control gate and a low voltage or ground to the channel (source / drain), drawing electrons from the channel into the memory node within the insulating layer. Since electrons are negatively charged, their accumulation increases the threshold voltage of the memory cell. Write operations are unidirectional (only changing the state from "1" to "0", i.e., from a low threshold voltage to a high threshold voltage) and must be performed on a page-by-page basis; old data cannot be directly overwritten, and the entire block must be erased first.

[0040] For example, in a single-level cell (SLC), each cell stores only 1 bit of information and has only two states: "1" (erase state, no or few electrons, low threshold voltage) and "0" (program state, injected electrons, high threshold voltage). During writing, the controller determines based on the data bit: if "1" needs to be written, no high voltage is applied to the cell (keeping it in the erase state); if "0" needs to be written, a high voltage pulse is applied to the word line corresponding to the cell to inject electrons until its threshold voltage exceeds the preset verification voltage, thus completing the state flip from "1" to "0".

[0041] For example, in a multi-level storage cell, taking a three-level storage cell (TLC) as an example, each TLC cell can store 3 bits of information, which needs to be divided into 2... 3 =8 data states, namely: 000, 001, 010, 011, 100, 101, 110, 111. The writing process is more complex and usually uses a multi-step programming algorithm. First, the controller determines the range of target threshold voltage corresponding to the target storage state based on the 3 bits of data to be written (e.g., "010"). Then, through multiple fine voltage pulse scans, electrons are injected into the floating gate in stages so that the threshold voltage of the storage cell falls precisely into a specific one of the 8 windows. Due to the narrow voltage window, TLC writing requires stricter interference management (such as PASS voltage control) and a longer verification time to ensure that adjacent states do not overlap.

[0042] NAND flash memory reading is essentially a process of detecting the threshold voltage of the memory cell. During reading, a read voltage meter is used. The read voltage meter is a set of key parameter data stored in the controller, defining the specific value of the read reference voltage Vref that needs to be applied to the word line during data reading operations. As mentioned above, in the memory cell, data exists in the form of threshold voltages corresponding to the number of electrons in the cell. For example, SLC has 2 data states, requiring 1 read reference voltage to distinguish them, corresponding to 1 memory state; TLC has 8 data states, requiring 7 read reference voltages to distinguish them, corresponding to 7 memory states; QLC has 16 data states, requiring 15 read reference voltages to distinguish them, corresponding to 15 memory states.

[0043] Figure 2 This is a schematic diagram of a read voltage meter according to an embodiment of the present invention. Taking a three-level storage cell (TLC) as an example, the TLC has seven storage states, Vref1-Vref7. The read voltage meter stores the judgment logic and read reference voltage corresponding to each storage state, for example: Vref1 is used to distinguish between 111 and 110, and the corresponding read reference voltage is 2.0V; Vref2 is used to distinguish between 110 and 101, and the corresponding read reference voltage is 2.4V; Vref3 is used to distinguish between 101 and 100, and the corresponding read reference voltage is 2.8V; Similarly, Vref7 is used to distinguish between 001 and 000, and the corresponding read reference voltage is 4.5V.

[0044] When reading data, the controller applies a specific reference voltage to the control gate of the target memory cell, while simultaneously applying a higher turn-on voltage to other memory cells in the same string that are not the target, forcing them to turn on. Subsequently, it detects changes in current or voltage on the bit lines: if the threshold voltage of the target memory cell is lower than the read reference voltage, the target memory cell turns on, and the bit line discharges (read as "1" or a corresponding low-level state); if the threshold voltage of the target memory cell is higher than the read reference voltage, the target memory cell does not turn on, and the bit line remains high (read as "0" or a corresponding high-level state).

[0045] For example, for a single-level storage cell (SLC), the controller applies a read reference voltage to the word line that is located between the "1" and "0" states. If the storage cell is turned on (current flows through it), it means that its threshold voltage is less than the read reference voltage, and it is determined to be logic "1". If the storage cell is turned off (no current), it means that its threshold voltage is greater than the read reference voltage, and it is determined to be logic "0".

[0046] For example, in a multi-level storage cell (TLC), reading a TLC requires multiple comparisons. Since the eight data states are closely arranged, a single reference voltage cannot distinguish all states. The controller needs to apply seven different read reference voltages, Vref1-Vref7, sequentially, performing seven operations on the same storage cell. Each comparison divides the voltage distribution into two parts. Through the combination of these seven "yes / no" results (similar to binary search logic), the controller can accurately locate which interval the threshold voltage of the cell falls into, thus decoding the original 3-bit data. For example, the combination of the seven comparison results might indicate "101".

[0047] Furthermore, each NAND flash memory includes multiple memory cells, multiple bit lines, and multiple word lines. The multiple bit lines extend along a first direction, and the multiple word lines extend along a second direction perpendicular to the first direction. The multiple memory cells are arranged into multiple cell strings, and the multiple memory cells in each cell string are connected in series along the first direction. The ends of each cell string are connected to the corresponding bit lines, and the control gate of each memory cell is electrically connected to the corresponding word line. The multiple memory cells connected to the same word line constitute a physical page.

[0048] Furthermore, each NAND flash memory comprises multiple physical blocks. Figure 3 This is a schematic diagram of the character line group according to an embodiment of the present invention. For example... Figure 3 As shown, a word line group can be viewed as an array of multiple memory cells, with the first direction being vertical and the second direction being horizontal.

[0049] exist Figure 3In the illustrated embodiment, taking an 8×8 memory cell word line group as an example, in the first direction, there are 8 bit lines (bit0-bit7), each bit line is connected to a cell string, each cell string includes 8 memory cells in series, and each cell string is connected to a gate transistor at both ends. Each cell string is a vertical current channel, and the cell string can only be read or written when the gate transistors at both ends are turned on at the same time.

[0050] The selection transistors include a source-side select gate (SGS) and a drain-side select gate (SGD). SGS and SGD appear in pairs, located at opposite ends of the cell string, acting as switches to control the connection between the memory cell array and the bit line (BL) or source line (SL). Within a cell string, multiple memory cells are connected in series. The SGD is located at the end of the cell string closer to the bit line, and the SGS is located at the end closer to the source line. The memory cells that actually store the data are sandwiched between the SGD and SGS.

[0051] In the second direction, there are eight word lines (word0-word7), each connected to a physical page. The control gate of each memory cell in each physical page is electrically connected to the corresponding word line. In this embodiment of the invention, all word lines between SGD and SGS are defined as a word line group. A word line group can be a single physical block or a part of a physical block, i.e., a sub-block.

[0052] Among them, the physical block is the smallest unit of erasure. If we consider... Figure 3 Each memory cell in the system is connected to the same substrate, and the entire block can be erased by applying a high voltage to the substrate. A physical page is the smallest unit of reading and writing.

[0053] Cache chip 4 is used to store the File Table (FTL) and temporary data, and it can be a DRAM (Dynamic Random Access Memory) cache. The controller needs to know the mapping relationship between logical addresses and physical addresses. This mapping table is relatively large, and storing it in high-speed DRAM can greatly improve random read and write performance. Simultaneously, the cache chip can also be used as a hotspot read cache. When read interference occurs, data is stored in the hotspot read cache. Subsequently, if the host initiates a read request for that data, it can directly retrieve the response from the cache chip, avoiding further access to the NAND flash memory. This effectively suppresses the accumulation of read interference and reduces the FBC growth rate.

[0054] Figure 4 This is a flowchart of a data processing method according to an embodiment of the present invention. Figure 4 As shown, the data processing method of this embodiment of the invention is executed by the controller, and specifically includes the following steps: Step S101: Read data.

[0055] In this embodiment, the controller receives a read data request from the host, wherein the read data request includes a logical address of the data to be read. The controller reads the data from the NAND flash memory according to the logical address and returns it to the host.

[0056] Specifically, the controller translates logical addresses into physical addresses, which include block addresses and page addresses. Based on the block and page addresses, the controller selects the word line corresponding to the physical page to be read, and determines the bit lines of that physical page, as well as the word lines containing each memory cell within that page. The controller selects a read reference voltage based on a read voltage meter and applies this voltage to the selected word lines. Simultaneously, for unselected word lines within the physical block, a higher on-state voltage is applied, ensuring that the memory cells in the unselected word lines are fully conductive, acting as conductors. This ensures that the flow of cell string current depends solely on whether the memory cells in the selected physical page are conductive. Voltage changes on the bit lines are detected, and the result of the data read is determined based on these changes. Finally, the read data is transmitted to the host.

[0057] Step S102: A predetermined trigger event is detected.

[0058] In this embodiment, after the controller reads the data, it detects whether a predetermined trigger event exists based on the read data. The trigger event is a predetermined read error event. When a trigger event is detected, it indicates that read interference may occur, but at this point, it cannot be determined whether read interference has occurred. Whether read interference has occurred is determined in step S106.

[0059] The triggering event includes at least one of the following: the count of failed bits of the target physical page is greater than or equal to a first threshold; a read operation triggers a read retry; or a read operation triggers a read recovery. That is, in response to detecting that the count of failed bits is greater than or equal to the first threshold, or detecting that a read operation triggers a read retry, or detecting that a read operation triggers a read recovery, a triggering event is determined to have been detected.

[0060] For the failure bit count of a physical page, when the controller reads data from a physical page, it also reads the corresponding ECC checksum. The controller uses the same ECC algorithm as when writing data to recalculate the checksum value for the read data portion. The recalculated checksum value is then XORed with the original ECC checksum read from the cache to obtain the failure bit count (FBC). If the failure bit count is greater than or equal to a first threshold, it indicates a high bit error rate and potential read interference, thus triggering a detection event.

[0061] For read operations triggering read retry, when the controller reads data, if the data read for the first time cannot pass the error correction code (ECC) verification, the controller will not immediately report an error to the host, but will automatically initiate a retry internally, triggering a read retry when the host interface read operation is detected.

[0062] For read operation-triggered read recovery, when the read retry mechanism has been exhausted (i.e., all preset voltage combinations have been tried but still cannot pass ECC verification), or when a more serious media fault is detected, the controller triggers a higher-level data recovery process, which is triggered by detecting a read operation on the host interface.

[0063] Step S103: Determine the target character line group.

[0064] In this embodiment, in response to detecting a predetermined trigger event, the target word line group containing the target physical page corresponding to the trigger event is determined. The target word line group includes multiple word lines. Specifically, physical pages in the same unit string as the target physical page are determined as the target word line group; that is, the target word line group includes the target physical page and other physical pages in the same unit string as the target physical page. Figure 3 Taking this as an example, assume the target physical page is the physical page corresponding to word line word3. The physical page corresponding to word line word3 includes 8 memory cells, and the gates of these 8 memory cells are connected to word line word3. Obtain the cell strings corresponding to these 8 memory cells; each memory cell corresponds to one cell string, for a total of 8 cell strings. These 8 cell strings are connected to bit lines bit0-bit7 respectively. Since there are 8 physical pages corresponding to bit lines bit0-bit7, and they are connected to word lines word0-word7 respectively, the target word line group includes word lines word0-word7. In other words, all word lines between SGD and SGS of the target physical page are considered as the target word line group.

[0065] Step S104: Obtain the local optimal read reference voltage for each predetermined storage state of each word line.

[0066] In this embodiment, after determining the target word line group, for each word line in the target word line group, the local optimal read reference voltage for each predetermined storage state is obtained.

[0067] As mentioned above, based on the number of bits stored by the floating gate transistors, NAND flash memory can be divided into single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC). Different storage cells correspond to different storage states.

[0068] For example, in a three-level storage unit, each storage unit can store 3 bits, which can form 2 3 There are 8 data states: 000, 001, 010, 011, 100, 101, 110, and 111. For these 8 data states, 7 read reference voltages are needed as decision boundaries, corresponding to 7 memory states. The purpose of this step is to find the optimal read reference voltage for each memory state corresponding to each word line, that is, the locally optimal read reference voltage. The number of memory states is one less than the number of data states.

[0069] The predetermined storage state refers to the complete storage state of the word line or a pre-set partial storage state.

[0070] For a set of pre-defined storage states, the impact of read interference varies across different storage states. Generally, states with low threshold voltages are more affected by read interference; for example, storage states corresponding to data states such as 000, 001, and 010 are significantly affected. Conversely, storage states with high threshold voltages are less affected; for example, storage states corresponding to data states such as 111, 110, and 101 are less affected. Therefore, to reduce computational load and improve the accuracy of subsequent data processing, a subset of storage states significantly affected by read interference can be selected as the basis for calculation. Specifically, this can be achieved by combining a large amount of test data (offline NAND / SSD test data, or using AI technology combined with online SSD operating data) to analyze the impact of cumulative read counts on each storage state, identify characteristic voltages of read interference, and thus obtain the predetermined storage states.

[0071] Specifically, multiple candidate read reference voltages are determined for each predetermined storage state; data is read according to the multiple candidate read reference voltages; the bit error rate of the read data is detected; and the candidate read reference voltage with the lowest bit error rate is determined as the locally optimal read reference voltage. Specifically, for each word line, multiple rounds of trial reads are performed, and the optimal read reference voltage corresponding to each predetermined storage state is calculated and inferred based on the principle of minimizing the bit error rate. The method for calculating the optimal read reference voltage can be implemented using various existing methods, and this embodiment of the invention does not limit this approach.

[0072] As an example, a parabolic fitting method can be used to infer the candidate read reference voltage with the minimum bit error rate and determine it as the locally optimal read reference voltage. Specifically: First, select three candidate reference voltages, V ref1 V ref2 and V ref3 , where V ref1 V is the current default read reference voltage or the estimated optimal read reference voltage. ref2 =V ref1 -ΔV, V ref3 = Vref1 +ΔV, where ΔV is the preset offset step size.

[0073] Then, V was measured respectively. ref1 V ref2 and V ref3 The corresponding bit error rates BER1, BER2 and BER3 will be (V ref1 ,BER1), (V ref2 ,BER2), (V ref3 Substituting these three sets of numbers (BER3) into the following formula, we can calculate a, b, and c.

[0074]

[0075] Next, the voltage coordinates of the vertex of the parabola are calculated as follows:

[0076] Afterwards, if it's a single-step fitting, you can directly use... This serves as a locally optimal reference voltage. If multiple fitting operations are performed, it can be... As the new V ref1 Reduce the value of ΔV, repeat the above steps, and obtain a new value. And so on, after re-executing the predetermined number of times, the final result will be... As the locally optimal reference voltage.

[0077] As yet another example, obtaining the locally optimal read reference voltage for each storage state of each of the aforementioned word lines can also be achieved in the following manner: First, for each word line, the distribution histogram of the reference voltage of all memory cells on the current word line is read tentatively. For example, a set of fine step voltages covering the entire range can be used for scanning and reading, and the number of memory cells falling in each voltage range is counted to obtain the distribution curve of 8 peaks.

[0078] Then, the cost function is defined as follows:

[0079]

[0080] in, The total bit error rate, For the n locally optimal reference voltages that need to be solved, For the k-th storage state, This is the (k+1)th storage state. Storage state The corresponding probability density function, Storage state The corresponding probability density function, Store state in the data The probability of occurrence Store state in the data The probability of occurrence.

[0081] in, A right-tail error indicates that the state should have been stored. The storage unit was incorrectly identified as being in storage state by the controller due to excessively high voltage. Or a higher storage state.

[0082] A left-tail error indicates that the state should have been stored. The storage unit was misidentified as being in storage state by the controller because the voltage was too low. Or a lower storage state.

[0083] Then, minimizing the total bit error rate is taken as the objective, and adjustments are made accordingly. The value is calculated until the optimal read reference voltage is found. For example, the histogram of the read reference voltage distribution for the current word line is read and initialized. Fine-tune to the default value or the previous success value. Re-estimate the number of error bits in the above integral formula, moving in the direction that reduces the estimated total bit error rate. This process continues until convergence. By performing this process sequentially or in parallel on n voltages, the n locally optimal read reference voltages corresponding to the word line can be obtained.

[0084] The above process is performed on each word line in the target word line group to obtain the local optimal read reference voltage for each memory state corresponding to each word line.

[0085] Step S105: Determine the globally optimal read reference voltage for the corresponding storage state.

[0086] In this embodiment, the average value of the local optimal read reference voltage of each word line in the same storage state is calculated to obtain the global optimal read reference voltage in the corresponding storage state.

[0087] For example, assuming the target word line group has N word lines and M local optimal read reference voltages, let V be the j-th local optimal read reference voltage of the i-th word line. i,j If i = 1, 2, ..., N; j = 1, 2, ..., M, then there are M globally optimal reference voltages, and the k-th globally optimal reference voltage is... .

[0088] Step S106: The variance is greater than or equal to the second threshold.

[0089] In this embodiment, to further analyze the specific read reference voltage most significantly affected by read interference (e.g., the lowest read reference voltage is more sensitive to read interference), after obtaining the globally optimal read reference voltage for each storage state, the variance is calculated based on the globally optimal read reference voltage corresponding to each storage state. Assuming there are M locally optimal read reference voltages, the k-th locally optimal read reference voltage is... Then the variance is:

[0090] in, For variance, For the k-th locally optimal reference voltage, The global optimal read reference voltage is the average value of the local optimal read reference voltage, and M is the number of local optimal read reference voltages.

[0091] in:

[0092] If the variance is less than or equal to the second threshold, it indicates that there is no read access imbalance in the target word line group. At this point, it can be determined that no hotspot read interference has occurred, and the process proceeds to step S109, where the read voltage meter is updated based on the globally optimal read reference voltage. Afterwards, data is read using the updated read voltage meter.

[0093] If the variance is greater than the second threshold, it indicates that there is an imbalance in read access in the target word line group. At this time, it can be determined that hot spot read interference has occurred, and the process proceeds to step S107.

[0094] The second threshold is a variance threshold used to determine whether read interference has occurred, and it can be set according to the actual application scenario.

[0095] Step S107: Identify word lines with an offset greater than or equal to the fourth threshold as hotspot word lines.

[0096] In this embodiment, in response to the variance being greater than the second threshold, it indicates that there is an imbalance in read access in the target word line group. At this time, it can be determined that hotspot read interference has occurred, and the hotspot word lines in the target word line group are obtained.

[0097] Specifically, the offset of the local optimal read reference voltage of each word line relative to the global optimal read reference voltage under the same storage state is obtained, and word lines with an offset greater than or equal to the fourth threshold are identified as hot word lines.

[0098] In step S104 above, the local optimal read reference voltage for each memory state of each word line is obtained. In step S105 above, the global optimal read reference voltage for each memory state is obtained. For any word line in the target word line group, the difference between the local optimal read reference voltage of the word line and the global optimal read reference voltage under the same memory state is calculated. The absolute value of the difference or the percentage of the absolute value relative to the global optimal read reference voltage is used as the offset. If the offset of one or more memory states of the word line is greater than or equal to a fourth threshold, the word line is determined as the hotspot word line.

[0099] Furthermore, for the obtained hotspot characters, embodiments of the present invention can further classify different handling strategies according to the degree of reading interference affecting the hotspot characters.

[0100] Step S108: The offset is greater than or equal to the third threshold.

[0101] In this embodiment, after obtaining the hotspot character line, the offset of the hotspot character line is compared with the third threshold.

[0102] If the offset is greater than or equal to the third threshold, it indicates that the hotspot word line has seriously deviated from the group behavior, and proceed to step S110.

[0103] If the offset is less than the third threshold, it indicates that the hotspot character line is not seriously deviated, and proceed to step S111.

[0104] The third and fourth thresholds can be preset according to the actual scenario, with the third threshold being greater than the fourth threshold. The fourth threshold is used to determine whether a word is a hotspot, and the third threshold is used to determine the degree of interference from reading.

[0105] Step S109: Update the voltmeter.

[0106] In this embodiment, in response to the variance being less than or equal to the second threshold, indicating that there is no read access imbalance in the target word line group, the read reference voltage in the read voltage meter is updated to the globally optimal read reference voltage obtained above, and then data is read through the updated read voltage meter.

[0107] Step S110: Load the valid data in the hotspot word line into the predetermined hotspot read cache.

[0108] In this embodiment, in response to the offset being less than the third threshold, indicating that the hotspot word line deviates from the group behavior not significantly, the valid data in the hotspot word line is loaded into a predetermined hotspot read cache. Subsequently, if the host initiates a read request for this data, the response can be directly obtained from the hotspot read cache, avoiding further access to the NAND flash memory. This effectively suppresses the accumulation of read interference and reduces the FBC (Fail Bit Count) growth rate.

[0109] The hotspot read cache is a portion of the cache area allocated in the cache chip.

[0110] In some embodiments, for other word lines in the target word line group, such as non-hotspot word lines, the read reference voltage in the read voltage meter is updated to the globally optimal read reference voltage obtained above, and then the data in these word lines is read through the updated read voltage meter.

[0111] Step S111: Migrate the valid data of the corresponding word line to the newly allocated physical page.

[0112] In this embodiment, in response to an offset greater than or equal to the third threshold, it indicates that the hot word line is seriously deviating from the group behavior, which may soon trigger UNC (Uncorrectable Read Error) or pollute the overall read reference voltage calibration result of the target word line group. This triggers a garbage collection operation (GC) to migrate the valid data of the corresponding word line to the newly allocated physical page. Thus, data migration can be completed before the reliability deteriorates significantly, avoiding high-cost read recovery or data loss later.

[0113] In some embodiments, for other word lines in the target word line group, relevant processing is performed according to the actual situation. For example, for non-hotspot word lines, the read reference voltage in the read voltage table is updated to the globally optimal read reference voltage obtained above, and then the data in these word lines is read through the updated read voltage table. As another example, for hotspot word lines with an offset less than the third threshold, the valid data in the hotspot word lines is loaded into a predetermined hotspot read cache. Subsequently, if the host initiates a read request for this data, the response can be directly obtained from the hotspot read cache.

[0114] In summary, this embodiment of the invention, upon detecting a trigger event, acquires the local optimal read reference voltage for each storage state of each word line. Based on the local optimal read reference voltages of each word line within the same storage state, it determines the global optimal read reference voltage for that storage state. The variance is calculated based on the global optimal read reference voltage and the local optimal read reference voltage. If the variance is less than or equal to a second threshold, the read voltage table is updated based on the global optimal read reference voltage. If the variance is greater than the second threshold, hotspot word lines are acquired in the target word line group, and their offset is calculated. For hotspot word lines with an offset greater than or equal to a third threshold, the valid data of the corresponding word line is migrated to a newly allocated physical page. For hotspot word lines with an offset less than the third threshold, the valid data in the hotspot word line is loaded into a predetermined hotspot read cache. Other word lines update their read voltage tables based on the global optimal read reference voltage. Simultaneously, by dynamically updating the read reference voltage and identifying anomalies based on the word line group division method, isolation processing between word line groups can be achieved, improving the accuracy of data processing.

[0115] This invention, upon detecting a trigger event, determines the target word line group containing the target physical page corresponding to the trigger event, obtains the locally optimal read reference voltage for each predetermined storage state of each word line in the target word line group, determines the globally optimal read reference voltage for the corresponding storage state based on the locally optimal read reference voltages of each word line in the same storage state, and determines a handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage. The handling strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table. This reduces the consumption of internal bandwidth resources and improves the system performance, lifespan, and energy efficiency of the storage device.

[0116] Figure 5 This is a flowchart of a data processing method according to another embodiment of the present invention. Figure 5 As shown, the data processing method of this embodiment of the invention includes the following steps: Step S210: Read the data from the voltmeter.

[0117] Step S220: In response to detecting a predetermined trigger event, determine the target word line group where the target physical page corresponding to the trigger event is located, wherein the target word line group includes multiple word lines.

[0118] Step S230: Obtain the local optimal read reference voltage for each storage state of each word line.

[0119] Step S240: Determine the global optimal read reference voltage for the corresponding memory state based on the local optimal read reference voltage of each word line in the same memory state.

[0120] Step S250: Determine the processing strategy for each word line based on the global optimal read reference voltage. The processing strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table.

[0121] In some embodiments, the triggering event includes at least one of the following: The count of invalid bits in the target physical page is greater than or equal to the first threshold; Read operations trigger read retry; A read operation triggers a read recovery.

[0122] In some embodiments, obtaining the local optimal read reference voltage for each storage state of each of the word lines includes: Determine multiple candidate read reference voltages for each storage state; Data is read based on the multiple candidate reference voltages; Detect the bit error rate of the read data; The reading reference voltage with the minimum bit error rate is inferred by using methods such as parabolic fitting and is determined as the local optimal reading reference voltage.

[0123] In some embodiments, determining the global optimal read reference voltage for a corresponding memory state based on the local optimal read reference voltages of each word line in the same memory state includes: The average value of the local optimal read reference voltage of each word line in the same storage state is taken as the global optimal read reference voltage in the corresponding storage state.

[0124] In some embodiments, determining the handling strategy for each word line based on the globally optimal read reference voltage includes: The variance is obtained based on the global optimal read reference voltage and the local optimal read reference voltage; In response to the variance being less than or equal to the second threshold, the reading voltage meter is updated according to the globally optimal reading reference voltage.

[0125] In some embodiments, determining the handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage further includes: In response to the variance being greater than a second threshold, hotspot word lines in the target word line group are obtained; Detect whether the offset of each hotspot character line is greater than or equal to the third threshold; In response to an offset greater than or equal to the third threshold, the valid data of the corresponding hotspot word line is migrated to the newly allocated physical page.

[0126] In some embodiments, obtaining the hotspot characters in the target character group includes: Obtain the offset of the local optimal read reference voltage of each word line relative to the global optimal read reference voltage under the same storage state; Word lines with an offset greater than or equal to the fourth threshold are identified as hotspot word lines.

[0127] In some embodiments, determining the handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage further includes: In response to an offset less than the third threshold, the valid data of the corresponding hotspot word line is pre-read and loaded into the system hotspot read cache.

[0128] This invention, upon detecting a trigger event, determines the target word line group containing the target physical page corresponding to the trigger event, obtains the locally optimal read reference voltage for each predetermined storage state of each word line in the target word line group, determines the globally optimal read reference voltage for the corresponding storage state based on the locally optimal read reference voltages of each word line in the same storage state, and determines a handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage. The handling strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table. This reduces the consumption of internal bandwidth resources and improves the system performance, lifespan, and energy efficiency of the storage device.

[0129] Figure 6 This is a schematic diagram of a data processing apparatus according to an embodiment of the present invention. Figure 6As shown, the data processing apparatus of this embodiment includes a data reading unit 61, a word line group determination unit 62, a local voltage determination unit 63, a global voltage determination unit 64, and a strategy determination unit 65. The data reading unit 61 reads data according to a read voltage table. The word line group determination unit 62, in response to a detected trigger event, determines the target word line group containing the target physical page corresponding to the trigger event; the target word line group includes multiple word lines. The local voltage determination unit 63 obtains the local optimal read reference voltage for each storage state of each word line. The global voltage determination unit 64 determines the global optimal read reference voltage for the corresponding storage state based on the local optimal read reference voltages of each word line in the same storage state. The strategy determination unit 65 determines a handling strategy for each word line based on the statistical relationship between the global optimal read reference voltage and the local optimal read reference voltage; the handling strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table.

[0130] This invention, upon detecting a trigger event, determines the target word line group containing the target physical page corresponding to the trigger event, obtains the locally optimal read reference voltage for each predetermined storage state of each word line in the target word line group, determines the globally optimal read reference voltage for the corresponding storage state based on the locally optimal read reference voltages of each word line in the same storage state, and determines a handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage. The handling strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table. This reduces the consumption of internal bandwidth resources and improves the system performance, lifespan, and energy efficiency of the storage device.

[0131] In this embodiment, the controller includes at least one processor; a memory communicatively connected to at least one processor; and a communication component that receives and transmits data under the control of the processor; wherein the memory stores instructions executable by at least one processor to implement the above-described data processing method.

[0132] Specifically, the controller includes one or more processors and memory. The processors and memory can be connected via a bus or other means. Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in the memory, thereby implementing the aforementioned data processing methods.

[0133] The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store an option list, etc. Furthermore, the memory may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to external devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0134] One or more modules are stored in memory and, when executed by one or more processors, perform the data processing method in any of the above method embodiments.

[0135] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.

[0136] This invention, upon detecting a trigger event, determines the target word line group containing the target physical page corresponding to the trigger event, obtains the locally optimal read reference voltage for each predetermined storage state of each word line in the target word line group, determines the globally optimal read reference voltage for the corresponding storage state based on the locally optimal read reference voltages of each word line in the same storage state, and determines a handling strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage. The handling strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table. This reduces the consumption of internal bandwidth resources and improves the system performance, lifespan, and energy efficiency of the storage device.

[0137] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.

[0138] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0139] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data processing method, characterized in that, The method includes: Read the data from the voltmeter; In response to detecting a predetermined trigger event, the target word line group of the target physical page corresponding to the trigger event is determined, and the target word line group includes multiple word lines; Obtain the local optimal read reference voltage for each predetermined storage state of each of the word lines; The global optimal read reference voltage for the corresponding memory state is determined based on the local optimal read reference voltage of each word line in the same memory state. The processing strategy for each word line is determined based on the statistical relationship between the global optimal read reference voltage and the local optimal read reference voltage. The processing strategy includes loading data into a predetermined hotspot read cache, migrating data to a newly allocated physical page, and updating the read voltage table.

2. The method according to claim 1, characterized in that, The triggering event includes at least one of the following: The count of invalid bits in the target physical page is greater than or equal to the first threshold; Read operations trigger read retry; A read operation triggers a read recovery.

3. The method according to claim 1, characterized in that, The predetermined storage state can be either the complete storage state of the word line or a pre-set partial storage state.

4. The method according to claim 1, characterized in that, The process of obtaining the locally optimal read reference voltage for each predetermined storage state of each of the word lines includes: Determine multiple candidate read reference voltages corresponding to each predetermined storage state; Data is read based on the multiple candidate reference voltages; Detect the bit error rate of the read data; The candidate read reference voltage with the lowest bit error rate is determined as the locally optimal read reference voltage.

5. The method according to claim 1, characterized in that, The step of determining the global optimal read reference voltage for a corresponding memory state based on the local optimal read reference voltage of each word line in the same memory state includes: The average value of the local optimal read reference voltage of each word line in the same storage state is taken as the global optimal read reference voltage in the corresponding storage state.

6. The method according to claim 1, characterized in that, The method for determining the processing strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage includes: The variance is obtained based on the global optimal read reference voltage and the local optimal read reference voltage; In response to the variance being less than or equal to the second threshold, the reading voltage meter is updated according to the globally optimal reading reference voltage.

7. The method according to claim 6, characterized in that, The method for determining the processing strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage also includes: In response to the variance being greater than a second threshold, hotspot word lines in the target word line group are obtained; Detect whether the offset of each hotspot character line is greater than or equal to the third threshold; In response to an offset greater than or equal to the third threshold, the valid data of the corresponding hotspot word line is migrated to the newly allocated physical page.

8. The method according to claim 7, characterized in that, The step of obtaining the hotspot characters in the target character group includes: Obtain the offset of the local optimal read reference voltage of each word line relative to the global optimal read reference voltage under the same storage state; Word lines with an offset greater than or equal to the fourth threshold are identified as hotspot word lines.

9. The method according to claim 7, characterized in that, The method for determining the processing strategy for each word line based on the statistical relationship between the globally optimal read reference voltage and the locally optimal read reference voltage also includes: In response to an offset less than the third threshold, the valid data of the corresponding hotspot word line is pre-read and loaded into the system hotspot read cache.

10. A storage device, characterized in that, The device includes: NAND flash memory includes multiple memory cells, multiple bit lines, and multiple word lines. The multiple bit lines extend along a first direction, and the multiple word lines extend along a second direction perpendicular to the first direction. The multiple memory cells are arranged into multiple cell strings. Multiple memory cells in each cell string are connected in series along the first direction, and the ends of each cell string are connected to the corresponding bit lines. The control gate of each memory cell is electrically connected to the corresponding word line. Multiple memory cells connected to the same word line constitute a physical page. A controller for implementing the method as described in any one of claims 1-8.

11. A data processing apparatus, characterized in that, The device includes: The data reading unit is used to read data from the voltmeter. A word line group determination unit is used to determine the target word line group where the target physical page corresponding to the trigger event is located in response to the detection of a predetermined trigger event, wherein the target word line group includes multiple word lines; A local voltage determination unit is used to obtain the local optimal read reference voltage of each predetermined storage state of each of the word lines; The global voltage determination unit is used to determine the global optimal read reference voltage for the corresponding memory state based on the local optimal read reference voltage of each word line in the same memory state. The strategy determination unit is used to determine the handling strategy for each word line based on the statistical relationship between the global optimal read reference voltage and the local optimal read reference voltage. The handling strategy includes loading data into a predetermined hot spot read cache, migrating data to a newly allocated physical page, and updating the read voltage table.

12. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is run on a computer, the computer performs the method according to any one of claims 1-9.

13. A computer-readable storage medium storing computer program instructions thereon, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-9.

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