Memory devices and their operation methods

Abstract

This application relates to a memory device and its operation method. The memory device includes multiple word lines connected to multiple memory cells. The memory device also includes peripheral circuitry configured to sequentially perform a voltage application operation, a sensing voltage application operation, and an equalization voltage application operation on the multiple word lines. During the equalization voltage application operation, the peripheral circuitry is configured to provide charge from an unselected adjacent word line to a selected word line, the adjacent word line being adjacent to the selected word line.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0019535, filed with the Korean Intellectual Property Office on February 14, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The various embodiments disclosed herein generally relate to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0003] A memory device consists of a memory cell array and peripheral circuitry. The memory cell array stores data, and the peripheral circuitry drives the memory cells. The peripheral circuitry generates various voltages for memory operation and executes programming, reading, and erasing operations under the control of control logic.

[0004] A read operation involves applying a read voltage to a selected memory cell and determining whether the cell is on or off to read data. Typically, a read operation includes a pass voltage application process, a sensing voltage application process, and an equalizing voltage application process. During the equalizing voltage application process, the voltages of the selected word line and the unselected word line are adjusted to a target level.

[0005] During the equalization voltage application process, the voltage of unselected word lines can be reduced and the voltage of selected word lines can be increased by applying an equalization voltage. The voltage change of the selected word line during the equalization voltage application process may affect the voltage of adjacent word lines. Among the unselected word lines adjacent to the selected word line, overshoot interference may occur during the equalization voltage application process.

[0006] In other words, the reliability of the memory device may be reduced due to this interference between adjacent word lines during the application of equalization voltage. Summary of the Invention

[0007] According to embodiments of this disclosure, a memory device may include: a plurality of word lines connected to a plurality of memory cells; peripheral circuitry configured to sequentially perform a voltage application operation, a sensing voltage application operation, and an equalization voltage application operation on the plurality of word lines; and control logic configured to control the peripheral circuitry. The peripheral circuitry is configured to, during the equalization voltage application operation, provide charge to a selected word line from an unselected adjacent word line, the adjacent word line being located in the vicinity of the selected word line.

[0008] According to embodiments of this disclosure, a method of operating a memory device may include: applying a voltage to a plurality of word lines connected to a plurality of memory cells; applying a sense voltage to the plurality of word lines; and applying an equalizing voltage to the plurality of word lines. When the equalizing voltage is applied, charge is supplied to a selected word line, the adjacent word line being adjacent to the selected word line. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure; Figure 2 It is shown Figure 1 A diagram showing the storage blocks; Figure 3 It is shown in detail Figure 1 A diagram showing the configuration of the voltage generator, line decoder, and control logic; Figure 4 This is a diagram showing the voltage changes of adjacent word lines caused by the voltage change of the selected word line; Figure 5A This is a diagram illustrating a read operation of a memory device according to an embodiment of the present disclosure; Figure 5B yes Figure 5A A detailed view of the equalization voltage application period shown; Figure 6A This shows that during the period when the equalization voltage is applied, compared with... Figure 5B The circuit diagram showing the operation of the memory device corresponding to the portion indicated by the dashed line. Figure 6B This shows that during the period when the equalization voltage is applied, compared with... Figure 5B The circuit diagram showing the operation of the memory device corresponding to the portion represented by the solid line is shown. Figure 7 This is a circuit diagram illustrating the operation of a memory device circuit during a period of equalization voltage application according to a first embodiment of the present disclosure; Figure 8 This is a circuit diagram illustrating the operation of a memory device circuit during a period of equalization voltage application according to a second embodiment of the present disclosure; Figure 9 This is a circuit diagram illustrating the operation of a memory device circuit during a period of equalization voltage application according to a third embodiment of the present disclosure; Figure 10 This is a circuit diagram illustrating the operation of a memory device circuit during a period of equalization voltage application according to a fourth embodiment of the present disclosure; Figure 11 This is a circuit diagram illustrating the operation of a memory device circuit during a period of equalization voltage application according to a fifth embodiment of the present disclosure; Figure 12 This is a diagram illustrating a memory card system using a memory device according to an embodiment of the present disclosure; Figure 13 This is a diagram illustrating a solid-state drive (SSD) system using a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0010] The specific structural or functional descriptions disclosed herein are for illustrative purposes only. Embodiments based on the concepts of this disclosure may be implemented in various forms and may be replaced by other equivalent embodiments, and should not be construed as limited to the specific embodiments set forth herein.

[0011] It should be understood that although the terms "first," "second," etc., may be used in this document to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another, but do not imply the number or order of elements.

[0012] Various embodiments relate to a memory device and a method of operating the same, which can improve the reliability of the memory device.

[0013] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A diagram of the storage block shown.

[0014] Reference Figure 1 and Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0015] Memory cell array 110 includes first to j-th memory blocks BLK1 to BLKj. First to j-th memory blocks BLK1 to BLKj are connected to row decoder 121 via row lines RL. First to j-th memory blocks BLK1 to BLKj are connected to page buffer group 123 via bit lines BL1 to BLn. Each of the first to j-th memory blocks BLK1 to BLKj includes multiple cell strings ST, and each of the multiple cell strings ST includes multiple memory cells. In this embodiment, the multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line can be defined as a single page PG. Therefore, a memory block can include multiple pages.

[0016] The first to jth storage blocks BLK1 to BLKj can be configured identically to each other. Therefore, the structure of the storage blocks will be described in detail below using the first storage block BLK1 as an example.

[0017] Reference Figure 2 The first memory block BLK1 includes a cell string ST, which connects the first to nth bit lines BL1 to BLn to the source line SL. Since the first to nth bit lines BL1 to BLn extend in the Y direction and are spaced apart in the X direction, the cell string ST can also be spaced apart in both the X and Y directions. For example, the cell string ST can be connected between the first bit line BL1 and the source line SL, and the cell string ST can be placed between the second bit line BL2 and the source line SL. In this way, the cell string ST can be placed between the nth bit line BLn and the source line SL. The cell string ST can extend in the Z direction.

[0018] For illustration, consider a cell string ST connected to the nth bit line BLn as an example. This cell string ST may include a source selection transistor SST, first to i-th memory cells MC1 to MCi, and a drain selection transistor DST. Since the first memory block BLK1 is shown... Figure 2 This is a diagram used to schematically illustrate the structure of a memory block, and therefore the number of source selection transistors SST, first to i memory cells MC1 to MCi, and drain selection transistors DST included in the cell string ST can vary in different embodiments of the memory device.

[0019] The gates of the source selection transistors SST included in different cell strings can be connected to the first or second source selection line SSL1 or SSL2, the gates of the first to the i-th memory cells MC1 to MCi can be connected to the first to the i-th word lines WL1 to WLi, and the gates of each of the drain selection transistors DST can be connected to one of the first to the fourth drain selection lines DSL1 to DSL4.

[0020] To describe the lines connected to the first memory block BLK1 in more detail, source select transistors (SSTs) arranged in the X direction can be connected to the same source select line, while source select transistors (SSTs) arranged in the Y direction can be connected to separate source select lines. For example, among the source select transistors (SSTs) arranged in the Y direction, one or more can be connected to the first source select line SSL1, and the remaining source select transistors (SSTs) can be connected to the second source select line SSL2. The second source select line SSL2 is separate from the first source select line SSL1. Therefore, the voltage applied to the first source select line SSL1 can be the same as or different from the voltage applied to the second source select line SSL2.

[0021] Memory cells MC1 to MCI that are located at the same level can be connected to the same word line. For example, the first memory cell MC1, which is included in different cell strings ST, can be connected to the first word line WL1, and the i-th memory cell MCI, which is included in different cell strings ST, can be connected to the i-th word line WLi. A group of memory cells included in different cell strings ST and connected to the same word line constitutes a page PG. Programming and reading operations can be performed on a page PG basis, and pre-programming and erasing operations can be performed on a memory block basis. Operations performed on a memory block basis can be performed on all pages included in the selected memory block.

[0022] The drain selection transistors (DSTs) arranged in the Y direction can be connected to the first to fourth drain selection lines DSL1 to DSL4, which are separate from each other. Specifically, the drain selection transistors (DSTs) arranged in the X direction can be connected to the same drain selection line, while the drain selection transistors (DSTs) arranged in the Y direction can be connected to the first to fourth drain selection lines DSL1 to DSL4, which are separate from each other. Since the first to fourth drain selection lines DSL1 to DSL4 are separate from each other, different voltages can be applied to the first to fourth drain selection lines DSL1 to DSL4.

[0023] Reference Figure 1 and Figure 2 The row line RL may include source select lines SSL1 and SSL2, multiple word lines WL1 to WLi, and drain select lines DSL1 to DSL4. The source select lines SSL1 and SSL2, the multiple word lines WL1 to WLi, and the drain select lines DSL1 to DSL4 can be connected to each of the first to j-th memory blocks BLK1 to BLKj. Each of the bit lines BL1 to BLn can be connected to at least one cell string.

[0024] Depending on the number of bits of data stored, the memory cells included in the memory cell array 110 can be programmed using a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC) method. Each memory cell programmed using the MLC method can store two bits of data. Each memory cell programmed using the TLC method can store three bits of data. Each memory cell programmed using the QLC method can store four bits of data. Different methods can be used to program the memory cells depending on the type of memory device. In addition to the methods described above, methods can also be used to program five or more bits of data in a single memory cell.

[0025] The peripheral circuit 120 can be configured to perform programming, reading, or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. For example, under the control of the control logic 130, the peripheral circuit 120 can apply various operating voltages to the row lines RL and the first to nth bit lines BL1 to BLn, or the peripheral circuit 120 can selectively release the row lines RL and the first to nth bit lines BL1 to BLn.

[0026] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0027] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines.

[0028] Row decoder 121 is configured to decode the row address RADD received from control logic 130. Row decoder 121 selects at least one of memory blocks BLK1 to BLKj based on the decoded address. In addition, row decoder 121 can transmit the operating voltage Vop generated by voltage generator 122 to the row line RL of the selected memory block based on the decoded address.

[0029] For example, in a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line, the programming pass voltage level being lower than the programming voltage level. In a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage to the unselected word line, the verification pass voltage level being higher than the verification voltage level. In a reading operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage to the unselected word line, the read pass voltage level being higher than the read voltage level.

[0030] Erasing operations on the memory device 100 are performed on a block-by-block basis. During the erase operation, the line decoder 121 can select a memory block based on the decoded address. During the erase operation, the line decoder 121 can apply a 0V voltage or a ground voltage to the word line connected to the selected memory block, or it can float the word line connected to the selected memory block.

[0031] Voltage generator 122 operates under the control of control logic 130. Voltage generator 122 is configured to generate multiple voltages using the external power supply voltage supplied to memory device 100. Specifically, voltage generator 122 can generate various operating voltages Vop for performing programming, reading, and erasing operations in response to an operation signal OPSIG generated in control logic 130. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., in response to the control of control logic 130.

[0032] Page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to memory cell array 110 via first to nth bit lines BL1 to BLn. The first to nth page buffers PB1 to PBn operate under the control of control logic 130. Specifically, the first to nth page buffers PB1 to PBn can operate in response to the page buffer control signal PBSIGNALS. For example, during a read operation or a verification operation, the first to nth page buffers PB1 to PBn can temporarily store data received via the first to nth bit lines BL1 to BLn, or can sense the voltage or current of the first to nth bit lines BL1 to BLn.

[0033] Specifically, during the programming operation, when a programming voltage is applied to the selected word line, the first to nth page buffers PB1 to PBn transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first to nth bit lines BL1 to BLn. The memory cell in the selected page is programmed based on the transmitted data DATA. During the programming verification operation, the first to nth page buffers PB1 to PBn sense the voltage or current received from the selected memory cell via the first to nth bit lines BL1 to BLn to read the page data.

[0034] During the read operation, under the control of the column decoder 124, the first to nth page buffers PB1 to PBn read data DATA from the memory cell of the selected page through the first to nth bit lines BL1 to BLn, and output the read data DATA to the input / output circuit 125.

[0035] During the erase operation, the first to nth page buffers PB1 to PBn can either float the first to nth bit lines BL1 to BLn or apply an erase voltage to the first to nth bit lines BL1 to BLn.

[0036] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first to nth page buffers PB1 to PBn via the data lines DL, or it can exchange data with the input / output circuitry 125 via the column lines CL.

[0037] The input / output circuit 125 can transmit the command CMD and address ADDR received from the memory controller to the control logic 130, or it can exchange data DATA with the column decoder 124.

[0038] During a read or verification operation, the sensing circuit 126 can generate a reference current in response to the allowable bit VRYBIT signal, and can compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL.

[0039] Control logic 130 can output operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit VRYBIT in response to commands CMD and address ADDR to control peripheral circuitry 120. For example, control logic 130 can control read operations on selected memory blocks in response to sub-block read commands and addresses. Furthermore, control logic 130 can control erase operations on selected sub-blocks included in the selected memory blocks in response to sub-block erase commands and addresses. Additionally, control logic 130 can determine whether a verification operation passes or fails in response to pass or fail signals PASS or FAIL. Control logic 130 can be implemented in hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0040] Figure 3 It is shown in detail that includes Figure 1 A diagram illustrating the configuration of the voltage generator 122, the line decoder 121, and the control logic 130 in the memory device 100.

[0041] Reference Figure 3 The voltage generator 122 may include a plurality of regulators 122-1 to 122-n. Each of the plurality of regulators 122-1 to 122-n can generate a voltage.

[0042] The line decoder 121 includes a switch control signal generator 1211 and multiple switch circuits SW_1 to SW_n. The multiple switch circuits SW_1 to SW_n can be connected to multiple regulators 122-1 to 122-n of the voltage generator 122.

[0043] The switch control signal generator 1211 can generate a switch control signal in response to the selection signal SEL of the control logic 130. This switch control signal is used to control multiple switch circuits SW_1 to SW_n.

[0044] The selection signal SEL may include signals for selecting which switch circuit to turn on and which switch circuit to turn off from a plurality of switch circuits SW_1 to SW_n.

[0045] Multiple switching circuits SW_1 to SW_n can be connected to one of multiple word lines WL1 to WLm (where m is a natural number). Furthermore, multiple switching circuits SW_1 to SW_n can be connected to multiple regulators 122-1 to 122-n. Each of the multiple switching circuits SW_1 to SW_n can connect one of the multiple word lines WL1 to WLm to one of the multiple regulators 122-1 to 122-n.

[0046] Control logic 130 can control voltage generator 122, line decoder 121, and input / output circuitry 125. Control logic 130 can operate in response to commands (CMD) transmitted from external devices. Control logic 130 can generate various signals based on commands (CMD) and addresses (ADDR) to control peripheral circuitry.

[0047] The control logic 130 includes an address setting unit 131 and a regulator controller 132.

[0048] Address setting unit 131 can set the addresses of adjacent word lines WL_N1 (adjacent to the selected word line WL_S) and non-adjacent word lines WL_N2 (not adjacent to the selected word line WL_S) among multiple unselected word lines WL_N, based on the address of the selected word line WL_S selected during the read operation. Adjacent word lines WL_N1 are the word lines that were not selected during the read operation and are closest to the selected word line WL_S. Non-adjacent word lines WL_N2 are the word lines that were not selected during the read operation and are not close to the selected word line WL_S.

[0049] For example, assuming that the selected word line WL_S is the i-th word line WLi (i is a natural number) of a specific memory block, the address of the adjacent word line WL_N1 can be set to the address of the (i-1)-th word line WLi-1 and the address of the (i+1)-th word line WLi+1.

[0050] Additionally, for example, assuming the selected word line WL_S is the first word line WL1 of a specific memory block, only the second word line WL2 is adjacent to the selected word line WL_S. Therefore, the address of the adjacent word line WL_N1 can be set to the address of the second word line WL2.

[0051] Additionally, for example, assuming the selected word line WL_S is the last word line of a specific memory block—that is, the nth word line WLn—only the (n-1)th word line WLn-1 is adjacent to the nth word line WLn. Therefore, the address of the adjacent word line WL_N1 can be set to the address of the (n-1)th word line WLn-1.

[0052] Unlike the description above, the address setting unit 131 can set the addresses of multiple adjacent word lines WL_N1 adjacent to the selected word line WL_S based on the address of the selected word line WL_S during the read operation. That is, when c is a natural number and X is a natural number of 3 or greater, the number of adjacent word lines WL_N1 can be set to 2c to Xc.

[0053] For example, when X is 2 and it is assumed that the selected word line WL_S is the i-th word line WLi of a specific memory block, the address of the adjacent word line WL_N1 can be set to the address of the (i-1)-th word line WLi-1, the address of the (i-2)-th word line WLi-2, the address of the (i+1)-th word line WLi+1, and the address of the (i+2)-th word line WLi+2.

[0054] Additionally, for example, assuming the selected word line WL_S is the first word line WL1 of a specific memory block, the second word line WL2 and the third word line WL3 constitute the word lines adjacent to the selected word line WL_S. Therefore, the address of the adjacent word line WL_N1 can be set to the address of the second word line WL2 and the address of the third word line WL3.

[0055] Additionally, for example, assuming the selected word line WL_S is the last word line of a specific memory block—that is, the nth word line WLn—the (n-1)th word line WLn-1 and the (n-2)th word line WLn-2 constitute an adjacent word line WL_N1 adjacent to the nth word line WLn. The address of the adjacent word line WL_N1 can be set to the address of the (n-1)th word line WLn-1 and the address of the (n-2)th word line WLn-2.

[0056] Address setting unit 131 sets the address of a non-adjacent word line WL_N2 that is not adjacent to the selected word line WL_S, among a plurality of unselected word lines WL_N, based on the address of the selected word line WL_S selected during the read operation. The non-adjacent word line WL_N2 is a word line that was not selected during the read operation and does not include the selected word line WL_S or the adjacent word line WL_N1. The non-adjacent word line WL_N2 is a word line whose location is not closest to the selected word line WL_S.

[0057] For example, assuming the selected word line WL_S is the first word line WL1 of a specific memory block, the adjacent word line WL_N1 is the second word line WL2. Therefore, the third to nth word lines WL3 to WLn constitute the non-adjacent word line WL_N2.

[0058] Figure 4 This is a diagram showing the voltage change of the adjacent word line WL_N1 caused by the voltage change of the selected word line WL_S.

[0059] Reference Figure 4 As can be seen, a virtual capacitor vC is formed between the selected word line WL_S and the adjacent word line WL_N1, thereby creating coupling between them, such as capacitive coupling. Voltage changes in the selected word line WL_S may affect the voltage of the adjacent word line WL_N1 through the virtual capacitor vC.

[0060] exist Figure 4In this example, the virtual capacitor vC is formed only between each pair of adjacent word lines. The virtual capacitor vC is not shown between the selected word line WL_S and the non-adjacent word line WL_N2. However, the virtual capacitor vC may also be formed between the selected word line WL_S and the non-adjacent word line WL_N2.

[0061] When a virtual capacitor vC is formed between the selected word line WL_S and the adjacent word line WL_N1, voltage changes in the selected word line WL_S may affect the voltage of the adjacent word line WL_N1. Specifically, when the voltage of the selected word line WL_S rises, the voltage of the adjacent word line WL_N1 may rise under the influence of the rising voltage of the selected word line WL_S, even without applying a separate voltage to the adjacent word line WL_N1. Conversely, when the voltage of the selected word line WL_S falls, the voltage of the adjacent word line WL_N1 may fall under the influence of the falling voltage of the selected word line WL_S, even without applying a separate voltage to the adjacent word line WL_N1. Compared to the effect of voltage changes in the selected word line WL_S on the voltage of the adjacent word line WL_N1, the effect of voltage changes in the selected word line WL_S on the voltage of the non-adjacent word line WL_N2 may be weaker. In other words, the voltage change of the selected word line WL_S has no effect or the effect is negligible on the voltage of the non-adjacent word line WL_N2.

[0062] Figure 5A This is a diagram illustrating a read operation of a memory device according to an embodiment of the present disclosure. Figure 5B yes Figure 5A A detailed view of the equalization voltage application period (Peq) shown.

[0063] Reference Figure 5A According to embodiments of the present disclosure, the read operation of the memory device includes a first through voltage application operation during a through voltage application period Pp, a first sensing voltage application operation during a first sensing voltage application period Ps1, a second sensing voltage application operation during a second sensing voltage application period Ps2, and an equalization voltage application operation during an equalization voltage application period Peq. The above operations are performed by (…). Figure 1 The peripheral circuit 120 is in ( Figure 1 It is executed under the control of control logic 130.

[0064] During the voltage application period Pp from the first time point tt1 to the second time point tt2, ( Figure 3 The control logic 130 applies a first pass voltage Vpass_0 to multiple word lines. Specifically, during the pass voltage application period Pp, ( Figure 3The control logic 130 applies a first pass voltage Vpass_0 to all word lines in the selected word line WL_S, adjacent word line WL_N1, and non-adjacent word line WL_N2. With the application of the first pass voltage Vpass_0, the selected word line WL_S, adjacent word line WL_N1, and non-adjacent word line WL_N2 all have the same potential.

[0065] During the first sensing voltage application period Ps1 from the second time point tt2 to the third time point tt3, ( Figure 3 The control logic 130 performs a first sensing voltage application operation on multiple word lines, and during the second sensing voltage application period Ps2 from the third time point tt3 to the fourth time point tt4, ( Figure 3 The control logic 130 performs a second sensing voltage application operation on multiple word lines.

[0066] Specifically, during the first sensing voltage application period Ps1 and the second sensing voltage application period Ps2, ( Figure 3 The control logic 130 applies the target voltage Vpass_tg to the unselected word line WL_N. Then, ( Figure 3 The control logic 130 applies a first read voltage Vread1 to the selected word line WL_S during the first sensing voltage application period Ps1, and applies a second read voltage Vread2 to the selected word line WL_S during the second sensing voltage application period Ps2. The unselected word lines WL_N include adjacent word lines WL_N1 and non-adjacent word lines WL_N2.

[0067] Figure 6A This shows the relationship between the equalization voltage application period (Peq) and... Figure 5B The circuit diagram shown corresponds to the operation of the memory device circuitry for the portion indicated by the dashed lines. Figure 6B This shows the relationship between the equalization voltage application period (Peq) and... Figure 5B The solid lines shown represent the circuit diagram of the memory device's operation.

[0068] Reference Figure 5B and Figure 6A The portion represented by the dashed line within the equalization voltage application period Peq from the fourth time point tt4 to the fifth time point tt5 is described.

[0069] During the equalization voltage application period Peq, a first equalization voltage Viq1 is applied to the selected word line WL_S' (dashed line), the adjacent word line WL_N1' (dashed line), and the non-adjacent word line WL_N2' (dashed line). At the fourth time point tt4, the magnitude of the first equalization voltage Viq1 can be greater than the voltage of the selected word line WL_S' (dashed line), and can be less than the voltage of each of the adjacent word lines WL_N1' and the non-adjacent word lines WL_N2' (dashed line).

[0070] The selected word line WL_S' (dashed line) is the selected word line. The adjacent word line WL_N1' (dashed line) is the word line closest to the selected word line WL_S' (dashed line). The non-adjacent word line WL_N2' (dashed line) is the remaining word line in a memory block, excluding the selected word line WL_S' (dashed line) and the adjacent word line WL_N1' (dashed line).

[0071] During the equalization voltage application period (Peq), when the first equalization voltage (Veq1) is applied to the selected word line WL_S' (dashed line), the voltage of the selected word line WL_S' may increase due to the first equalization voltage (Veq1). The reason for the increase in the voltage of the selected word line WL_S' is the first equalization voltage (Veq1).

[0072] Due to the coupling between the adjacent word line WL_N1' and the selected word line WL_S' of the dashed line, the adjacent word line WL_N1' may be affected by the voltage rise of the selected word line WL_S'. In other words, the voltage of the adjacent word line WL_N1' may rise under the influence of the voltage rise of the selected word line WL_S'.

[0073] However, the voltage rise of the non-adjacent word line WL_N2' on the dashed line is negligible or unaffected. This is because the distance from the selected word line WL_S' to the non-adjacent word line WL_N2' is greater than the distance from the selected word line WL_S' to the adjacent word line WL_N1'. Therefore, the voltage of the non-adjacent word line WL_N2' will decrease instead of increase, and the interference phenomenon is negligible or does not occur.

[0074] Reference Figure 5B and Figure 6B First, the portion represented by the solid line within the equalization voltage application period Peq from the fourth time point tt4 to the fifth time point tt5 is described.

[0075] Figure 5BIn the diagram, the solid line selected word line WL_S and the solid line adjacent word line WL_N1 represent the following situation: During the equalization voltage application period Peq, an equalization voltage is applied to the solid line selected word line WL_S. Simultaneously, the solid line adjacent word line WL_N1 is electrically connected to the solid line selected word line WL_S, and the charge of the solid line adjacent word line WL_N1 is supplied to the solid line selected word line WL_S. During the equalization voltage application period Peq, the voltage of the solid line selected word line WL_S may rise faster than the voltage of the dashed line selected word line WL_S'.

[0076] Because a first equalization voltage Veq1, which is lower than the voltage of the adjacent word line WL_N1 of the solid line, is applied to the adjacent word line WL_N1 of the solid line, the voltage of the adjacent word line WL_N1 of the solid line is discharged and reduced. This voltage may rise in part due to the voltage rise of the selected word line WL_S of the solid line. However, because the charge of the adjacent word line WL_N1 of the solid line is supplied to the selected word line WL_S of the solid line, the voltage rise of the adjacent word line WL_N1 of the solid line during the equalization voltage application period Peq is less than the voltage rise of the adjacent word line WL_N1' of the dashed line.

[0077] Therefore, during the period when the equalization voltage is applied, when the circuit... Figure 6B When operating as shown, with the circuit Figure 6A Compared to the operation shown, this method can reduce the impact of the voltage rise of the selected word line WL_S on the voltage rise of the adjacent word line WL_N1 and the resulting interference.

[0078] Figure 7 This is a circuit diagram illustrating the operation of the circuitry of the memory device 100 during the equalization voltage application period Peq according to a first embodiment of the present disclosure.

[0079] Reference Figure 5B and Figure 7 In the portion represented by the dashed line within the equalization voltage application period Peq, ( Figure 3 The line decoder 121 applies an eleventh equalization voltage, Viq11, to the selected word line WL_S and the non-adjacent word line WL_N2, and applies a twelfth equalization voltage, Viq12, to the adjacent word line WL_N1. The twelfth equalization voltage, Viq12, is lower than the eleventh equalization voltage, Viq11.

[0080] When the eleventh equalization voltage Viq11 is applied to the selected word line WL_S during the equalization voltage application period Peq, the voltage of the selected word line WL_S rises due to the eleventh equalization voltage Viq11. The only factor contributing to the rise in voltage of the selected word line WL_S is ( Figure 3The eleventh equalization voltage Veq11 is applied by the line decoder 121.

[0081] During the equalization voltage application period (Peq), a twelfth equalization voltage (Veq12) is applied to the adjacent word line WL_N1. The twelfth equalization voltage (Veq12) is less than the eleventh equalization voltage (Veq11). When the twelfth equalization voltage (Veq12) is applied, the voltage of the adjacent word line WL_N1 is higher than that of the twelfth equalization voltage (Veq12). Therefore, when the twelfth equalization voltage (Veq12) is applied, the voltage of the adjacent word line WL_N1 is discharged and decreases. However, the adjacent word line WL_N1 is arranged to be adjacent to the selected word line WL_S at a position close to it, thereby creating coupling between the adjacent word line WL_N1 and the selected word line WL_S. Therefore, the voltage of the adjacent word line WL_N1 may rise under the influence of the rising voltage of the selected word line WL_S.

[0082] In this embodiment, taking into account the coupling effect between the adjacent word line WL_N1 and the selected word line WL_S, ( Figure 3 The line decoder 121 applies a twelfth equalization voltage, Veq12, to the adjacent word line WL_N1. This twelfth equalization voltage, Veq12, is lower than the eleventh equalization voltage, Veq1. Therefore, the voltage rise in the adjacent word line WL_N1 caused by the voltage rise of the selected word line WL_S can be partially offset by the twelfth equalization voltage, Veq12, which is lower than the eleventh equalization voltage, Veq11. This reduces interference and improves the reliability of the memory device.

[0083] During the equalization voltage application period Peq, the eleventh equalization voltage Veq11 is applied to the non-adjacent word line WL_N2. During this period, the voltage of the non-adjacent word line WL_N2 is higher than the eleventh equalization voltage Veq11. Therefore, when the eleventh equalization voltage Veq11 is applied to the non-adjacent word line WL_N2, its voltage is discharged and reduced. Since the non-adjacent word line WL_N2 is far from the selected word line WL_S, the effect of the voltage rise on the selected word line WL_S is negligible or unaffected.

[0084] Figure 8 This is a circuit diagram illustrating the operation of the circuitry of the memory device 100 during the equalization voltage application period Peq according to a second embodiment of the present disclosure.

[0085] Reference Figure 5B and Figure 8 In the portion represented by the dashed line within the equalization voltage application period Peq, ( Figure 3The line decoder 121 applies a 22nd equalization voltage, Viq22, to the selected word line WL_S, and applies a 21st equalization voltage, Viq21, to adjacent word lines WL_N1 and non-adjacent word lines WL_N2. The 22nd equalization voltage, Viq22, is higher than the 21st equalization voltage, Viq21.

[0086] During the equalization voltage application period Peq, the twenty-second equalization voltage Veq22 is applied to the selected word line WL_S. Since the voltage of the selected word line WL_S is lower than the twenty-second equalization voltage Veq22 during the equalization voltage application period Peq, the voltage of the selected word line WL_S may rise due to the twenty-second equalization voltage Veq22. The only factor causing the voltage rise of the selected word line WL_S is the application of the twenty-second equalization voltage Veq22.

[0087] During the equalization voltage application period Peq, the twenty-first equalization voltage Viq21 is applied to the adjacent word line WL_N1. The twenty-first equalization voltage Viq21 is lower than the twenty-second equalization voltage Viq22.

[0088] When the 21st equalization voltage Veq21 is applied to the adjacent word line WL_N1, the voltage of the adjacent word line WL_N1 is higher than that of the 21st equalization voltage Veq21. Therefore, when the 21st equalization voltage Veq21 is applied to the adjacent word line WL_N1, the voltage of the adjacent word line WL_N1 is discharged and reduced, but the voltage of the adjacent word line WL_N1 may rise due to the influence of the voltage rise of the adjacent selected word line WL_S. On the other hand, by applying the 22nd equalization voltage Veq22, which is higher than the 21st equalization voltage Veq21, to the selected word line WL_S, the equalization voltage application period Peq can be shortened. Therefore, the time period during which the adjacent word line WL_N1 is affected by the voltage rise of the selected word line WL_S is shortened, thereby reducing interference and improving the reliability of the memory device.

[0089] During the equalization voltage application period Peq, the twenty-first equalization voltage Veq21 is applied to the non-adjacent word line WL_N2. During this period, the voltage of the non-adjacent word line WL_N2 is higher than the twenty-first equalization voltage Veq21. Therefore, when the twenty-first equalization voltage Veq21 is applied to the non-adjacent word line WL_N2, its voltage is discharged and reduced. Since the non-adjacent word line WL_N2 is far from the selected word line WL_S, the effect of the voltage rise of the selected word line WL_S on the non-adjacent word line WL_N2 is negligible or unaffected.

[0090] Figure 9This is a circuit diagram illustrating the operation of the circuitry of the memory device 100 during the equalization voltage application period Peq according to a third embodiment of the present disclosure.

[0091] Reference Figure 5B and Figure 9 In the portion represented by the dashed line within the equalization voltage application period Peq, ( Figure 3 The line decoder 121 applies a 33rd equalization voltage, Viq33, to the selected word line WL_S, a 32nd equalization voltage, Viq32, to the adjacent word line WL_N1, and a 31st equalization voltage, Viq31, to the non-adjacent word line WL_N2. The 33rd equalization voltage, Viq33, can be higher than the 31st equalization voltage, Viq31, and the 31st equalization voltage, Viq31, can be higher than the 32nd equalization voltage, Viq32.

[0092] During the equalization voltage application period (Peq), the thirty-third equalization voltage (Veq33) is applied to the selected word line WL_S. The voltage of the selected word line WL_S is lower than the thirty-third equalization voltage (Veq33). Therefore, when the thirty-third equalization voltage (Veq33) is applied to the selected word line WL_S, the voltage of the selected word line WL_S rises. The rise in the voltage of the selected word line WL_S is caused by the application of the thirty-third equalization voltage (Veq33).

[0093] During the equalization voltage application period (Peq), the thirty-second equalization voltage (Veq32) is applied to the adjacent word line WL_N1. The thirty-second equalization voltage (Veq32) is less than the thirty-first equalization voltage (Veq31) applied to the non-adjacent word line WL_N2 and the thirty-third equalization voltage (Veq33) applied to the selected word line WL_S. When the thirty-second equalization voltage (Veq32) begins to be applied to the adjacent word line WL_N1, the voltage of the adjacent word line WL_N1 is higher than that of the thirty-second equalization voltage (Veq32). Therefore, when the thirty-second equalization voltage (Veq32) is applied to the adjacent word line WL_N1, the voltage of the adjacent word line WL_N1 is discharged and decreases. Due to the coupling between the adjacent word line WL_N1 and the selected word line WL_S, the voltage of the adjacent word line WL_N1 may rise under the influence of the rising voltage of the selected word line WL_S.

[0094] In this embodiment, ( Figure 3The line decoder 121 applies the 33rd equalization voltage Veq33, which is the highest relative voltage, to the selected word line WL_S to shorten the equalization voltage application period Peq, and applies the 32nd equalization voltage Veq32—which is less than the 33rd equalization voltage Veq33 applied to the selected word line WL_S and the 31st equalization voltage Veq31 applied to the non-adjacent word line WL_N2—to partially offset the voltage rise caused by the coupling effect with the selected word line WL_S, thereby mitigating interference.

[0095] During the equalization voltage application period Peq, the thirty-first equalization voltage Viq31 is applied to the non-adjacent word line WL_N2. During this period, the voltage of the non-adjacent word line WL_N2 is higher than that of the thirty-first equalization voltage Viq31. Therefore, when the thirty-first equalization voltage Viq31 is applied to the non-adjacent word line WL_N2, its voltage is discharged and reduced. The non-adjacent word line WL_N2 is far from the selected word line WL_S, and therefore is negligible or unaffected by the voltage rise of the selected word line WL_S. Therefore, the voltage of the non-adjacent word line WL_N2 decreases due to the application of the thirty-first equalization voltage Viq31, but is unaffected by the voltage rise of the selected word line WL_S.

[0096] Figure 10 This is a circuit diagram illustrating the operation of the circuitry of the memory device 100 during the equalization voltage application period Peq according to the fourth embodiment of this disclosure.

[0097] Reference Figure 5B and Figure 10 , ( Figure 3 The line decoder 121 applies a forty-first equalization voltage, Veq41, to the selected word line WL_S, the adjacent word line WL_N1, and the non-adjacent word line WL_N2. Unlike the previous embodiment, in this fourth embodiment, during the equalization voltage application period Peq, the selected word line WL_S and the adjacent word line WL_N1 are connected via (…). Figure 3 The line decoders 121 are electrically connected to each other.

[0098] During the equalization voltage application period Peq, the forty-first equalization voltage Viq41 is applied to the selected word line WL_S. During the equalization voltage application period Peq, the voltage of the selected word line WL_S is lower than the forty-first equalization voltage Viq41. Therefore, when the forty-first equalization voltage Viq41 is applied to the selected word line WL_S, the voltage of the selected word line WL_S rises.

[0099] During the equalization voltage application period Peq, the voltage of the adjacent word line WL_N1 is higher than the voltage of the selected word line WL_S and the forty-first equalization voltage Viq41. During the equalization voltage application period Peq, ( Figure 3 The line decoder 121 applies the forty-first equalization voltage Veq41 to the adjacent word line WL_N1. Figure 3 The line decoder 121 electrically connects the adjacent word line WL_N1 and the selected word line WL_S. When the adjacent word line WL_N1 is connected to the selected word line WL_S, the charge of the adjacent word line WL_N1, which has a high voltage, is transferred to the selected word line WL_S. That is, the voltage rise factor of the selected word line WL_S during the equalization voltage application period Peq is the application of the forty-first equalization voltage Veq41 and the charge provided from the adjacent word line WL_N1.

[0100] Compared to the case where the voltage of the selected word line WL_S rises due to the application of the forty-first equalization voltage Veq41, the voltage of the selected word line WL_S rises much faster due to the application of the forty-first equalization voltage Veq41 and the inflow of charge into the adjacent word line WL_N1. Therefore, the voltage of the selected word line WL_S can be stabilized quickly.

[0101] During the equalization voltage application period Peq, the forty-first equalization voltage Veq41 is applied to the adjacent word line WL_N1, and the adjacent word line WL_N1 is electrically connected to the selected word line WL_S. At the start of the equalization voltage application period Peq, the voltage of the adjacent word line WL_N1 is higher than the forty-first equalization voltage Veq41, and also higher than the voltage of the selected word line WL_S. Therefore, during the equalization voltage application period Peq, the adjacent word line WL_N1 directly supplies charge to the selected word line WL_S, causing its voltage to decrease. Thus, because the adjacent word line WL_N1 loses charge due to its electrical connection to the selected word line WL_S, the effect of the voltage rise in the selected word line WL_S can be reduced. In other words, because the impact of the voltage rise in the selected word line WL_S on the adjacent word line WL_N1 is reduced, interference is reduced, thereby improving the reliability of the memory device.

[0102] During the equalization voltage application period (Peq), the forty-first equalization voltage (Veq41) is applied to the non-adjacent word line WL_N2. When the forty-first equalization voltage (Veq41) begins to be applied to the non-adjacent word line WL_N2, the voltage of the non-adjacent word line WL_N2 is higher than that of the forty-first equalization voltage (Veq41). Therefore, when the forty-first equalization voltage (Veq41) is applied to the non-adjacent word line WL_N2, the voltage of the non-adjacent word line WL_N2 is discharged and reduced. The non-adjacent word line WL_N2 is far from the selected word line WL_S, so the effect of the voltage rise of the selected word line WL_S is negligible or unaffected.

[0103] Figure 11 This is a circuit diagram illustrating the operation of the circuitry of the memory device 100 during the equalization voltage application period Peq according to the fifth embodiment of this disclosure.

[0104] Reference Figure 5B and Figure 11 In the portion represented by the solid line within the equalization voltage application period Peq, ( Figure 3 The line decoder 121 applies a 52nd equalization voltage, Viq52, to the selected word line WL_S and the adjacent word line WL_N1, and applies a 51st equalization voltage, Viq51, to the non-adjacent word line WL_N2. The magnitude of the 52nd equalization voltage, Viq52, can be different from the magnitude of the 51st equalization voltage, Viq51. For example, the magnitude of the 51st equalization voltage, Viq51, can be smaller than the magnitude of the 52nd equalization voltage, Viq52.

[0105] During the equalization voltage application period Peq, the fifty-second equalization voltage Viq52 is applied to the selected word line WL_S. The magnitude of the voltage on the selected word line WL_S is less than the magnitude of each of the fifty-first equalization voltage Viq51 and the fifty-second equalization voltage Viq52. Therefore, when the fifty-second equalization voltage Viq52 is applied to the selected word line WL_S, the voltage on the selected word line WL_S rises.

[0106] During the equalization voltage application period (Peq), the voltage of the adjacent word line WL_N1 is higher than the voltage of the selected word line WL_S. Furthermore, during the equalization voltage application period (Peq), ( Figure 3 The line decoder 121 electrically connects the adjacent word line WL_N1 to the selected word line WL_S. Therefore, the charge of the adjacent word line WL_N1, which has a high voltage, can be supplied to the selected word line WL_S. That is, the voltage rise factor of the selected word line WL_S during the equalization voltage application period Peq is not only due to the application of the 52nd equalization voltage Veq52, but also includes the inflow of charge from the adjacent word line WL_N1.

[0107] Compared to the case where the voltage of the selected word line WL_S rises due to the application of the 52nd equalization voltage Veq52, the voltage of the selected word line WL_S rises much faster due to the application of the 52nd equalization voltage Veq52 and the inflow of charge into the adjacent word line WL_N1. Therefore, the voltage of the selected word line WL_S can be stabilized quickly.

[0108] During the equalization voltage application period Peq, the 52nd equalization voltage Viq52 is applied to the adjacent word line WL_N1, and the adjacent word line WL_N1 is electrically connected to the selected word line WL_S. During the equalization voltage application period Peq, the voltage of the adjacent word line WL_N1 is higher than the 52nd equalization voltage Viq52. During the equalization voltage application period Peq, the voltage of the adjacent word line WL_N1 is higher than the voltage of the selected word line WL_S.

[0109] Therefore, during the equalization voltage application period Peq, the voltage of the adjacent word line WL_N1 may decrease not only because its charge is supplied to the selected word line WL_S, but also because it is discharged and decreased due to the application of the fifty-second equalization voltage Veq52. Specifically, since the adjacent word line WL_N1 is electrically connected to the selected word line WL_S and directly loses its charge, the effect of the voltage rise of the selected word line WL_S is reduced. In other words, during the equalization voltage application period Peq, since the effect of the voltage rise of the selected word line WL_S on the adjacent word line WL_N1 is reduced, the occurrence of interference is reduced, and the reliability of the memory device can be improved.

[0110] During the equalization voltage application period Peq, the 51st equalization voltage Viq51 is applied to the non-adjacent word line WL_N2. When the 51st equalization voltage Viq51 begins to be applied to the non-adjacent word line WL_N2, the voltage of the non-adjacent word line WL_N2 is higher than both the 51st and 52nd equalization voltages Viq51 and Viq52. Therefore, when the 51st equalization voltage Viq51 is applied to the non-adjacent word line WL_N2, the voltage of the non-adjacent word line WL_N2 is discharged and reduced. The non-adjacent word line WL_N2 is far from the selected word line WL_S, so the effect of the voltage rise of the selected word line WL_S is negligible or unaffected.

[0111] Figure 12 This is a diagram illustrating a memory card system 3000 employing a memory device 3200 according to an embodiment of the present disclosure.

[0112] Reference Figure 12 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0113] Controller 3100 is connected to memory device 3200. Controller 3100 is configured to access memory device 3200. For example, controller 3100 may be configured to control programming, reading, or erasing operations on memory device 3200, or to control background operations. Controller 3100 is configured to provide an interface between memory device 3200 and a host. Controller 3100 is configured to run firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit.

[0114] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on a specific communication protocol. For example, controller 3100 can communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe). For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0115] Memory device 3200 may include memory cells and may be configured to... Figure 1 The memory device 100 shown is the same. For example, memory device 3200 may include ( Figure 1 The line decoder 121. Therefore, the memory device 3200 can be configured to perform at least one of the operations of the circuit described in the first to fifth embodiments above.

[0116] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form memory cards such as those from the Personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) cards, Smart Media Cards (SM, SMC), Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD (SD, Mini SD, Micro SD, or SDHC) cards, Universal Flash Memory (UFS), etc.

[0117] Figure 13This is a diagram illustrating a solid-state drive (SSD) system 4000 that applies a memory device according to an embodiment of the present disclosure.

[0118] Reference Figure 13 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals SIG with the host 4100 through a signal connector 4001 and receives power PWR through a power connector 4002. The SSD 4200 includes a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0119] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signal could be based on the interface between the host 4100 and the SSD 4200. For example, the signal could be defined by at least one of various communication standards or interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, or NVMe standards or interfaces.

[0120] The plurality of memory devices 4221 to 422n may include units capable of storing data. Each of the plurality of memory devices 4221 to 422n can be coupled with... Figure 1 The memory device 100 shown is configured in the same manner. For example, each of the plurality of memory devices 4221 to 422n may include ( Figure 1 The line decoder 121. Therefore, each of the plurality of memory devices 4221 to 422n can be configured to perform at least one of the operations of the circuit described above according to the first to fifth embodiments.

[0121] Auxiliary power supply 4230 is connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power voltage from host 4100 and charge it. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power voltage to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located within the motherboard and provide auxiliary power to SSD 4200.

[0122] Buffer memory 4240 operates as a buffer memory for SSD 4200. For example, buffer memory 4240 may temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it may temporarily store metadata (e.g., a mapping table) of memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0123] According to some embodiments of this disclosure, the reliability of a memory device can be improved by preventing or mitigating interference caused by voltage variations between adjacent word lines during equalization operations of read operations.

Claims

1. A memory device, comprising: Multiple word lines connect to multiple memory cells; as well as The peripheral circuitry sequentially performs voltage application, sensing voltage application, and equalization voltage application operations on the multiple word lines. During the equalization voltage application operation, the peripheral circuit provides charge to the selected word line from the unselected adjacent word line, which is adjacent to the selected word line.

2. The memory device according to claim 1, wherein, The peripheral circuit electrically connects the selected word line to the adjacent word line during the equalization voltage application operation.

3. The memory device according to claim 1, wherein, The peripheral circuit applies a first equalization voltage to the selected word line and the adjacent word line during the equalization voltage application operation.

4. The memory device according to claim 3, wherein, The first equalization voltage is provided from a first regulator.

5. The memory device according to claim 3, wherein, The peripheral circuit applies a second equalization voltage to non-adjacent word lines. The second equalization voltage is different from the first equalization voltage. The non-adjacent word lines are word lines among the multiple word lines that are not adjacent to the selected word line.

6. The memory device according to claim 5, wherein, The second equalization voltage is less than the first equalization voltage.

7. The memory device according to claim 6, wherein, During the equalization voltage application operation, the voltage of the selected word line is lower than the first equalization voltage and the second equalization voltage, and the voltage of each of the adjacent word lines and the non-adjacent word lines is higher than the first equalization voltage and the second equalization voltage.

8. The memory device of claim 4, further comprising control logic that controls the peripheral circuitry. in, The control logic includes: The address setting unit sets the address of the adjacent word line based on the address of the selected word line; and A regulator controller controls the first regulator to supply the first equalization voltage to the selected word line and the adjacent word line based on the address of the selected word line and the address of the adjacent word line during the equalization voltage application operation.

9. A method of operating a memory device, the method comprising: Voltage will be applied to multiple word lines, which are connected to multiple memory cells; Apply the sensed voltage to the multiple word lines; as well as Apply equalization voltage to the multiple word lines. When the equalization voltage is applied, the charge of the unselected adjacent word line is provided to the selected word line, which is adjacent to the selected word line.

10. The method according to claim 9, wherein, When the equalization voltage is applied, the selected word line is electrically connected to the adjacent word line.

11. The method according to claim 10, wherein, When the equalization voltage is applied, the first equalization voltage is applied to the selected word line and the adjacent word line.

12. The method according to claim 11, wherein, The first equalization voltage is provided from a first regulator.

13. The method according to claim 12, wherein, When the equalization voltage is applied, at least one second regulator applies a second equalization voltage to an unselected non-adjacent word line, the non-adjacent word line being the word line other than the selected word line and the adjacent word line among the plurality of word lines.

14. The method according to claim 13, wherein, When the equalization voltage is applied, the first equalization voltage and the second equalization voltage are set to be different from each other.

15. The method according to claim 13, wherein, When the equalization voltage is applied, the first equalization voltage is lower than the voltage of the adjacent word line and higher than the voltage of the selected word line.

16. The method according to claim 13, wherein, When the equalization voltage is applied, the first equalization voltage is higher than the second equalization voltage.

17. The method according to claim 12, wherein, Applying the equalization voltage includes: The addresses of the adjacent word lines are set based on the address of the selected word line; and The first regulator is controlled to supply the first equalization voltage to the selected word line and the adjacent word line based on the address of the selected word line and the address of the adjacent word line.

18. The method according to claim 17, wherein, When the equalization voltage is applied, the addresses of the adjacent word lines are set to multiple addresses.

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