A method, apparatus, and medium for implementing a physically unclonable circuit.

Abstract

This application discloses a method, apparatus, and medium for implementing a physically unclonable circuit. The method first configures a memory chip structure including an odd number of memory arrays, each array including at least one memory cell. Then, the memory cells are irradiated with ultraviolet light until no electrons are stored in the floating gate, resulting in a memory cell in the UV state. Next, the erase / write function of the memory array corresponding to the cell is removed, and the threshold voltage of the cell in the UV state is locked, resulting in a threshold voltage-locked memory array. Subsequently, based on the normal distribution characteristics of the threshold voltage of the cells in the UV state, the cell data in the threshold voltage-locked memory array is read, and a majority vote is performed on the cell data to obtain a physically unclonable number. This application effectively improves the stability of the memory cell threshold voltage and the accuracy of data reading, and can generate a physically unclonable number with high reliability.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of semiconductor memory, and particularly to a method, apparatus, and medium for implementing a physically unclonable circuit. Background Technology

[0002] Physically Unclonable Functions (PUFs) are a security technology based on differences in the physical characteristics of hardware. They generate a unique, uncopyable, and highly random digital fingerprint for each chip by extracting unavoidable microscopic process variations (such as transistor threshold voltage and path delay) during chip manufacturing. However, in practical applications, the threshold voltage of memory cells is susceptible to external operational interference, resulting in insufficient stability. Furthermore, the accuracy of data retrieval is difficult to guarantee due to the influence of process variation distribution. These issues limit the reliable application of physically unclonable functions. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This application provides a method, device, and medium for implementing physically unclonable circuits, which can generate physically unclonable numbers with high reliability, ensuring the reliable implementation of hardware-level security protection.

[0005] This application provides a method for implementing a physically unclonable circuit, comprising: configuring a memory chip structure, the memory chip structure including an odd number of independent memory arrays, each memory array including at least one memory cell; performing ultraviolet light irradiation on the memory cell until no electrons are stored in the floating gate of the memory cell, obtaining a memory cell in the floating gate UV state; removing the erase / write function of the memory array corresponding to the memory cell in the floating gate UV state, and locking the threshold voltage of the memory cell in the floating gate UV state after removing the erase / write function, obtaining a threshold voltage locked memory array; reading the memory cell data in the threshold voltage locked memory array based on the normal distribution characteristics of the threshold voltage of the memory cell in the floating gate UV state; and performing majority voting on the memory cell data to obtain a physically unclonable number.

[0006] In one embodiment of this application, the step of performing majority voting on the storage unit data to obtain a physical unclonable number includes: counting the number of 0 data in the storage unit data; when the number of 0 data is greater than (N-1) / 2, outputting 0 as a 1-bit physical unclonable number; when the number of 0 data is less than or equal to (N-1) / 2, outputting 1 as a 1-bit physical unclonable number; where N is the number of storage arrays, and N≥1.

[0007] In one embodiment of this application, the step of performing ultraviolet light irradiation on the memory cell until no electrons are stored in the floating gate of the memory cell, thereby obtaining a memory cell in the floating gate UV state, includes: controlling the ultraviolet light wavelength, irradiation intensity, and irradiation time to irradiate the memory cell; monitoring the threshold voltage value of the memory cell during the irradiation process; and stopping the ultraviolet light irradiation when the threshold voltage value stabilizes at a target value and no longer changes, thereby obtaining a memory cell in the floating gate UV state.

[0008] In one embodiment of this application, removing the erase / write function of the memory array corresponding to the memory cell in the UV state of the floating gate includes: identifying the programming circuit in the memory array used to inject charge into the floating gate, and deleting the programming circuit to obtain a memory array intermediate without programming function; based on the memory array intermediate without programming function, identifying the erase circuit used to electrically clear the charge of the floating gate, and removing the erase circuit.

[0009] In one embodiment of this application, when the dielectric layer of the memory cell is a composite dielectric layer, the method further includes: detecting the penetration capability of the composite dielectric layer to ultraviolet light of different wavelengths to obtain ultraviolet light data of the dielectric layer; determining the target ultraviolet wavelength that can penetrate the composite dielectric layer based on the ultraviolet light data of the dielectric layer, and calculating the photon energy required for electrons to overcome the potential barrier of the composite dielectric layer based on the target ultraviolet wavelength; and adjusting the irradiation intensity of the ultraviolet light according to the photon energy to obtain irradiation parameters adapted to the composite dielectric layer.

[0010] On the other hand, embodiments of this application provide an electronic device, which includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the method for implementing physically unclonable circuits as described above.

[0011] On the other hand, embodiments of this application provide a computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to perform the implementation method of the physically unclonable circuit as described above.

[0012] This application provides a method for implementing a physically unclonable circuit, an electronic device, and a computer-readable storage medium. The method first configures a memory chip structure including an odd number of independent memory arrays, each array including at least one memory cell. Then, it performs ultraviolet light irradiation on the memory cells until no electrons are stored in the floating gate, obtaining memory cells in the UV state. Next, it removes the erase / write function of the memory array corresponding to the UV-state memory cells and locks the threshold voltage of the memory cells in the UV state, obtaining a threshold voltage-locked memory array. Subsequently, based on the normal distribution characteristics of the threshold voltage of the memory cells in the UV state, it reads the memory cell data in the threshold voltage-locked memory array, performs majority voting on the memory cell data, and obtains the physically unclonable number. This application, through targeted memory chip structure design, combined with ultraviolet light irradiation to achieve an electron-free state in the floating gate of the memory cells, and then removing the erase / write function and locking the threshold voltage, effectively improves the stability of the threshold voltage of the memory cells. Meanwhile, by utilizing the normal distribution characteristics of the threshold voltage and combining it with majority voting to determine the data reading, the accuracy of data reading is effectively improved. The resulting physically unclonable number maintains both the uniqueness based on the hardware physical characteristics and good reliability, ensuring the reliable implementation of hardware-level security protection. Attached Figure Description

[0013] Figure 1 This is a flowchart of a method for implementing a physically unclonable circuit according to an embodiment of this application; Figure 2 This is provided in one embodiment of the present application. Figure 1 The detailed flowchart of step 120; Figure 3 This is provided in one embodiment of the present application. Figure 1 The detailed flowchart of step 130; Figure 4 This is a UV threshold distribution diagram of a memory chip provided in one embodiment of this application; Figure 5 This is a block diagram of a memory chip structure provided in one embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0015] It should be noted that although the flowchart shows a logical order, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. The terms "first," "second," etc., used in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the structures, proportions, sizes, etc., depicted in the drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and purposes achieved by this application, should still fall within the scope of the technical content disclosed in this application. Similarly, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are only for clarity of description and are not used to limit the scope of implementation of this application. Changes or adjustments in their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this application.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0017] Physically unclonable technology is a security technique based on differences in the physical characteristics of hardware. It generates a unique, uncopyable, and highly random digital fingerprint for each chip by extracting unavoidable microscopic process deviations (such as transistor threshold voltage and path delay) during chip manufacturing. However, in practical applications, the threshold voltage of memory cells is susceptible to external operational interference, resulting in insufficient stability. Furthermore, the accuracy of data reading is difficult to guarantee due to the influence of process deviation distribution. These problems limit the reliable application of physically unclonable technology.

[0018] In view of this, embodiments of this application provide a method for implementing physically unclonable circuits, an electronic device, and a computer-readable storage medium. The method first configures a memory chip structure including an odd number of independent memory arrays, each memory array including at least one memory cell; then, it performs ultraviolet light irradiation on the memory cells until no electrons are stored in the floating gate of the memory cells, obtaining memory cells in the UV floating gate state; next, it removes the erase / write function of the memory array corresponding to the memory cells in the UV floating gate state, and locks the threshold voltage of the memory cells in the UV floating gate state after the erase / write function is removed, obtaining a memory array with a locked threshold voltage; subsequently, based on the normal distribution characteristics of the threshold voltage of the memory cells in the UV floating gate state, it reads the memory cell data in the memory array with locked threshold voltage, performs majority voting on the memory cell data, and obtains the physically unclonable number. Embodiments of this application, through targeted memory chip structure design, combined with ultraviolet light irradiation treatment to achieve an electron-free state in the floating gate of the memory cells, and then removing the erase / write function and locking the threshold voltage, effectively improve the stability of the threshold voltage of the memory cells. Meanwhile, by utilizing the normal distribution characteristics of the threshold voltage and combining it with majority voting to determine the data reading, the accuracy of data reading is effectively improved. The resulting physically unclonable number maintains both the uniqueness based on the hardware physical characteristics and good reliability, ensuring the reliable implementation of hardware-level security protection.

[0019] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0020] Reference Figure 1 , Figure 1 This is a flowchart of a method for implementing a physically unclonable circuit according to an embodiment of this application. The process may specifically include, but is not limited to, steps 110 to 150.

[0021] Step 110: Configure the memory chip structure, which includes an odd number of independent memory arrays, each memory array including at least one memory cell; Step 120: Perform ultraviolet light irradiation on the memory cell until no electrons are stored in the floating gate of the memory cell, and obtain the memory cell in the UV state of the floating gate; Step 130: Remove the erase / write function of the memory array corresponding to the memory cell in the floating gate UV state, and lock the threshold voltage of the memory cell in the floating gate UV state after the erase / write function is removed, so as to obtain the memory array with threshold voltage locked. Step 140: Based on the normal distribution characteristics of the threshold voltage of the memory cell in the floating gate UV state, read the memory cell data in the memory array with threshold voltage locked. Step 150: Perform majority voting on the data in the storage unit to obtain the number of physically unclonable cells.

[0022] Steps 110 to 150 will be described in detail below.

[0023] In one feasible embodiment, in step 110, the memory array is a hardware module composed of multiple memory cells, where a memory cell is the smallest element in the chip capable of storing a single bit of data. An odd number of independent memory arrays are configured in the chip. The internal structure of each memory array can be flexibly designed according to actual needs, such as using a common row-column layout, for example, a combination of 1024 word lines and 512 bit lines. All memory arrays are designed identically, and the threshold voltage distribution of each array is independent of each other.

[0024] In one feasible embodiment, the core of step 120 is to bring the floating gate of the memory cell into the UV state, that is, to completely de-electronize the floating gate of the memory cell and restore it to its original electrically neutral state. The floating gate is a suspended gate completely encased in an insulating medium, and its key characteristic is its ability to store charge for a long time.

[0025] In one feasible embodiment, such as Figure 2 As shown, the execution process of step 120 may include, but is not limited to, steps 210 and 220.

[0026] Step 210: Control the ultraviolet light wavelength, irradiation intensity and irradiation time to irradiate the storage cell; during the irradiation process, monitor the threshold voltage value of the storage cell. Step 220: Based on the threshold voltage value, when the threshold voltage value stabilizes at the target value and no longer changes, stop the ultraviolet light irradiation to obtain the memory cell in the floating gate UV state.

[0027] In a feasible embodiment, in step 210, the parameters of the ultraviolet light can be determined first. Typically, UVC wavelength ultraviolet light at 253.7 nm is selected because the photon energy at this wavelength is high enough to allow electrons in the floating gate to overcome the potential barrier of approximately 4.3 electron volts and escape. The irradiation intensity and irradiation time together determine the total irradiation dose. A dose of 10 to 15 J / cm² is generally a reliable reference, corresponding to an irradiation duration of 15 to 20 minutes. During irradiation, the threshold voltage of the memory cell needs to be continuously monitored. The threshold voltage refers to the minimum gate voltage required to turn on the transistor. By monitoring this value, the progress of charge removal from the floating gate can be determined.

[0028] In one feasible embodiment, when the dielectric layer of the memory cell is a composite dielectric layer, the penetration capability of the composite dielectric layer to ultraviolet light of different wavelengths can be detected first to obtain ultraviolet light data of the dielectric layer. Then, based on the ultraviolet light data of the dielectric layer, the target ultraviolet wavelength that can penetrate the composite dielectric layer is determined, and the photon energy required for electrons to overcome the potential barrier of the composite dielectric layer is calculated based on the target ultraviolet wavelength. Subsequently, the irradiation intensity of the ultraviolet light is adjusted according to the photon energy to obtain irradiation parameters suitable for the composite dielectric layer. In short, when encountering a memory cell using a composite dielectric layer, the penetration capability of the dielectric layer to ultraviolet light of different wavelengths can be detected first to find the target wavelength that can effectively penetrate, then the photon energy required for electrons to break through the potential barrier of the composite dielectric layer can be calculated, and finally the irradiation intensity of the ultraviolet light can be adjusted according to this energy to obtain irradiation parameters suitable for the composite dielectric layer.

[0029] In a feasible embodiment, in step 220, when the threshold voltage is monitored to stabilize at the lowest value and no longer change, it indicates that the floating gate has completely lost electrons and reached an electrically neutral UV state, at which point ultraviolet irradiation can be stopped. This stable lowest value is the target value, which represents that there is no residual charge in the floating gate, and the subsequent threshold voltage can be reliably locked.

[0030] In one feasible embodiment, step 130 aims to prevent external modification of the threshold voltage of the memory cell at the hardware level. The erase and write functions of the memory cell rely on two types of core circuitry: a programming circuit responsible for injecting charge into the floating gate to write data, and an erasing circuit responsible for electrically clearing the charge from the floating gate to erase the data.

[0031] In one feasible embodiment, such as Figure 3 As shown, the execution process of removing the erase / write function of the memory array corresponding to the memory cell in the floating gate UV state in step 130 may include, but is not limited to, steps 310 and 320.

[0032] Step 310: Identify the programming circuit in the memory array used to inject charge into the floating gate, and delete the programming circuit to obtain a memory array intermediate without programming function; Step 320: Based on the memory array intermediate without programming functionality, identify the erase circuit used for electrically clearing floating gate charge and remove the erase circuit.

[0033] In one feasible embodiment, in step 310, the programming circuits in the memory array can be located first. These circuits function to inject charge into the floating gate electrically, thereby changing the threshold voltage of the memory cell. After deleting these circuits, the memory array loses its programming capability and can no longer write data electrically, resulting in a memory array intermediate without programming functionality.

[0034] In a feasible embodiment, in step 320, based on the intermediate that has lost its programming function, the erase circuit is located and removed. The function of this type of circuit is to electrically remove the charge from the floating gate. After removal, the memory array completely loses all erase and write functions, and the charge state of the floating gate can no longer be changed through any electrical operation. At this point, the threshold voltage of the memory cell can be permanently locked at a value in the UV state, and it cannot be modified externally, thus ensuring the stability of subsequent data at the hardware level.

[0035] In one feasible embodiment, in step 140, due to unavoidable micro-process variations during manufacturing, such as slight differences in transistor size and fluctuations in dielectric layer thickness, the threshold voltage of each memory cell will exhibit a normal distribution characteristic, such as... Figure 4 As shown, the threshold voltage of most cells is concentrated around a certain intermediate value, and the number of cells deviating from this intermediate value gradually decreases. This natural randomness ensures that the read result of each memory cell is unique. Figure 5 As shown, a sensitive amplifier comparator can be used during reading. This is a circuit that can amplify a small voltage signal and compare it with a reference voltage. It compares the threshold voltage of each memory cell with a preset reference voltage and outputs the corresponding 0 or 1 bit data based on the comparison result.

[0036] In one feasible embodiment, in step 150, majority voting is a method of eliminating individual errors by statistically analyzing the majority results. In actual reading, the difference between the threshold voltage of some memory cells and the read voltage window may be less than the resolution of the sensitive amplifier comparator, which can lead to a certain degree of randomness in a single read. To eliminate this effect, each physically unclonable bit can be determined jointly by the corresponding bits of all odd-numbered memory arrays.

[0037] In a feasible embodiment, the process of performing majority voting on the storage cell data to obtain the physically unclonable number includes: counting the number of 0 data in the storage cell data; when the number of 0 data is greater than (N-1) / 2, outputting 0 as a 1-bit physically unclonable number; when the number of 0 data is less than or equal to (N-1) / 2, outputting 1 as a 1-bit physically unclonable number; where N is the number of storage arrays, N≥1 and N is the base. For example, if there are 15 storage arrays, outputting 0 when the number of 0 is greater than 7, and outputting 1 otherwise. As long as the number of arrays is large enough, it can effectively cover the read error of individual cells, making the final result stable and reliable. Each storage array contains M storage cells, and can ultimately generate a physically unclonable number with the same number of bits as the number of storage cells, because each storage cell corresponds to one bit of data.

[0038] The execution process of this method will be explained in detail below through a specific example.

[0039] Taking a 15-array floating-gate physically unclonable chip as an example, the execution process is as follows: In configuring the memory chip structure, the chip incorporates 15 independent memory arrays, with an odd number of arrays to mitigate the risk of a tie in subsequent majority voting. Each memory array uses a row and column layout of 1024 word lines × 512 bit lines, with a single array containing 52,428 memory cells. All arrays are designed identically, relying on microscopic process variations naturally occurring during the manufacturing process to ensure the independence of the threshold voltage distribution for each array.

[0040] In the ultraviolet (UV) irradiation process, UVC wavelengths of 253.7 nm can be used, with an irradiation intensity of 0.067 W / cm², an irradiation duration of 18 minutes, and a total dose of approximately 12 joules / cm². The threshold voltage of the memory cells is monitored in real time during irradiation. Irradiation is stopped when the threshold voltage of all cells stabilizes at 4.5V, and the floating gate enters an electron-free UV state. If the memory cell uses a composite dielectric layer, the penetration capability of the dielectric layer to different wavelengths of UV light must first be tested. 248 nm is determined as the target wavelength, and the photon energy at this wavelength is calculated to be sufficient to overcome the composite dielectric layer barrier. The irradiation intensity is then adjusted to 0.12 W / cm², and irradiation is continued for 20 minutes to ensure complete charge removal.

[0041] In the process of removing the erase / write function and locking the threshold voltage, the programming circuits used to inject charge into the floating gate in each memory array can be removed first to obtain an array intermediate without programming function. Then, the erase circuits used to electrically clear the floating gate charge in the intermediate are removed, and the memory array completely loses its erase / write capability, and the threshold voltage of all memory cells is permanently locked at the UV state value of 4.5V.

[0042] In the data reading stage of the memory cells, a sensitive amplifier comparator can be used, with 4.6V as the reference voltage, to compare the threshold voltage of each memory cell. Cells with threshold voltages lower than the reference voltage output 0, and cells with threshold voltages higher than the reference voltage output 1. Due to the influence of manufacturing process deviations, the threshold voltages of each cell follow a normal distribution, ensuring the natural uniqueness of the reading result. One bit of data is read from each corresponding position in the 15 arrays to obtain 15 bits of raw data.

[0043] In the majority voting stage for generating the physically unclonable number, the number of 0s in the 15-bit original data is counted. If the number of 0s is greater than 7, 0 is output as 1 bit of the physically unclonable number; otherwise, 1 is output. For example, if a read yields 9 0s and 6 1s, since 9 is greater than 7, the output is 0; if a read yields 6 0s and 9 1s, the output is 1. Each storage array contains 52,428 storage cells, ultimately generating a 52,428-bit physically unclonable number, which is directly used for hardware device authentication.

[0044] This application also discloses an electronic device, which includes a processor, a memory, and a computer program stored in the memory and executable by the processor. When the computer program is executed by the processor, it implements the previously described method for implementing physically unclonable circuits.

[0045] This application also discloses a computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to perform the implementation method of the physically unclonable circuit as described above.

[0046] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for implementing a physically unclonable circuit, characterized in that, include: A memory chip structure is configured, the memory chip structure comprising an odd number of independent memory arrays, each of the memory arrays comprising at least one memory cell; The memory cell is subjected to ultraviolet light irradiation until no electrons are stored in the floating gate of the memory cell, thus obtaining a memory cell in the UV state of the floating gate; Remove the erase / write function of the memory array corresponding to the memory cell in the floating gate UV state, and lock the threshold voltage of the memory cell in the floating gate UV state after removing the erase / write function to obtain a memory array with threshold voltage locked. Based on the normal distribution characteristics of the threshold voltage of the memory cell in the floating gate UV state, the data of the memory cell in the memory array locked by the threshold voltage is read. A majority vote is performed on the data in the storage unit to obtain the number of physically unclonable cells.

2. The method for implementing a physically unclonable circuit according to claim 1, characterized in that, The step of performing a majority vote on the data in the storage unit to obtain a physically unclonable number includes: Count the number of zero data in the storage unit; When the number of 0 data is greater than (N-1) / 2, output 0 as a 1-bit physical unclonable number; When the number of 0 data is less than or equal to (N-1) / 2, output 1 as a 1-bit physical unclonable number; Where N is the number of storage arrays, N≥1.

3. The method for implementing a physically unclonable circuit according to claim 1, characterized in that, The step of performing ultraviolet light irradiation on the memory cell until no electrons are stored in the floating gate of the memory cell, thereby obtaining a memory cell in the UV state of the floating gate, includes: The storage cell is irradiated by controlling the ultraviolet light wavelength, irradiation intensity, and irradiation time; during the irradiation process, the threshold voltage value of the storage cell is monitored. Based on the threshold voltage value, when the threshold voltage value stabilizes at the target value and no longer changes, ultraviolet light irradiation is stopped, and a memory cell in the floating gate UV state is obtained.

4. The method for implementing a physically unclonable circuit according to claim 1, characterized in that, The step of removing the erase / write function of the memory array corresponding to the memory cell in the floating gate UV state includes: Identify the programming circuit in the memory array used to inject charge into the floating gate, and delete the programming circuit to obtain a memory array intermediate without programming function; Based on the memory array intermediate without programming functionality, an erase circuit for electrically clearing floating gate charge is identified and the erase circuit is removed.

5. The method for implementing a physically unclonable circuit according to claim 1, characterized in that, When the dielectric layer of the memory cell is a composite dielectric layer, the method further includes: The ability of the composite dielectric layer to transmit ultraviolet light of different wavelengths was detected to obtain ultraviolet light data of the dielectric layer; Based on the ultraviolet light data of the dielectric layer, the target ultraviolet wavelength that can penetrate the composite dielectric layer is determined, and the photon energy required for electrons to overcome the potential barrier of the composite dielectric layer is calculated based on the target ultraviolet wavelength. Based on the photon energy, the intensity of ultraviolet light is adjusted to obtain irradiation parameters suitable for the composite dielectric layer.

6. An electronic device, wherein, The electronic device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements a method for implementing a physically unclonable circuit as described in any one of claims 1 to 6.

7. A computer-readable storage medium storing a processor-executable program, characterized in that, The processor-executable program, when executed by the processor, is used to perform a method for implementing a physically unclonable circuit as described in any one of claims 1 to 6.

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