Memory systems and their operating methods, memory controllers and storage media

Abstract

This application discloses a storage system and its operating method, a memory controller, and a storage medium. The storage system includes a memory controller and a memory device coupled to the memory controller. The memory device includes multiple storage regions. The memory controller is configured to: perform a redundancy array encoding operation on received user data to generate check data; allocate a first physical address pointing to a first storage region among the multiple storage regions to store the user data; allocate a second physical address pointing to a second storage region different from the first storage region to store the check data, and record the second physical address; send a first write instruction including the first physical address to the memory device; the first write instruction instructs the user data to be written to the first storage region; send a second write instruction including the second physical address and different from the first write instruction to the memory device; the second write instruction instructs the check data to be written to the second storage region.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of integrated circuits, and particularly to a storage system and its operation method, a memory controller, and a storage medium. Background Technology

[0002] Memory devices are storage equipment used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production costs, and suitable erase / encode speeds. However, as people's requirements for storage devices continue to increase, memory devices and their systems still have considerable room for improvement. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a storage system and its operation method, a memory controller and a storage medium.

[0004] According to a first aspect of the embodiments of this application, a memory system is provided, comprising: a memory controller and a memory device coupled to the memory controller, the memory device including a plurality of storage regions; the memory controller being configured to: perform a redundancy array encoding operation on received user data to generate check data; allocate a first physical address for storing the user data; wherein the first physical address points to a first storage region among the plurality of storage regions; allocate a second physical address for storing the check data, and record the second physical address; wherein the second physical address points to a second storage region among the plurality of storage regions that is different from the first storage region; send a first write instruction including the first physical address to the memory device; the first write instruction instructs the user data to be written to the first storage region; send a second write instruction including the second physical address and different from the first write instruction to the memory device; the second write instruction instructs the check data to be written to the second storage region.

[0005] According to a second aspect of the present application, a storage system is provided, comprising: a memory controller and a memory device coupled to the memory controller, the memory device including a plurality of dies, the plurality of dies being divided into a plurality of storage regions; the memory controller being configured to: based on the existence of at least one faulty storage block in a first storage region of the plurality of storage regions, migrate a portion of user data stored in the faulty storage block in the first storage region to a target storage block in the first storage region; based on the migration of the portion of user data to the target storage block in the first storage region, update a first physical address storing the user data; wherein the first physical address points to the first storage region; re-execute a redundancy array encoding operation on the portion of user data migrated to the target storage block in the first storage region and the remaining unmigrated user data in the first storage region, generating first check data; allocate a third physical address for storing the first check data, and record the third physical address; wherein the third physical address points to a second storage region in the plurality of storage regions that is different from the first storage region; send a third write instruction including the third physical address to the memory device; wherein the third write instruction instructs the first check data to be written to the second storage region.

[0006] According to a third aspect of the embodiments of this application, a memory controller is provided, the memory controller being coupled to a memory device, the memory device including a plurality of storage regions; the memory controller including: a cache, and a processor, the processor being configured to: perform a redundancy array encoding operation on received user data to generate check data; allocate a first physical address for storing the user data; wherein the first physical address points to a first storage region among the plurality of storage regions; allocate a second physical address for storing the check data, and record the second physical address; wherein the second physical address points to a second storage region among the plurality of storage regions that is different from the first storage region; send a first write instruction including the first physical address to the memory device; wherein the first write instruction indicates that the user data be written to the first storage region; send a second write instruction including the second physical address and different from the first write instruction to the memory device; wherein the second write instruction indicates that the check data be written to the second storage region.

[0007] According to a fourth aspect of the present application, a method for operating a storage system is provided, comprising: performing a redundancy array encoding operation on received user data to generate check data; allocating a first physical address for storing the user data; wherein the first physical address points to a first storage area in a plurality of storage areas of a memory device in the storage system; allocating a second physical address for storing the check data, and recording the second physical address; wherein the second physical address points to a second storage area in the plurality of storage areas that is different from the first storage area; sending a first write instruction including the first physical address to the memory device; wherein the first write instruction instructs the user data to be written to the first storage area; sending a second write instruction including the second physical address and different from the first write instruction to the memory device; wherein the second write instruction instructs the check data to be written to the second storage area.

[0008] According to a fifth aspect of the present application, a storage medium is provided, wherein executable instructions are stored on the storage medium, and when the executable instructions are executed, the steps of any of the operation methods provided in the fourth aspect are implemented.

[0009] In this embodiment, redundant array encoding is performed on the received user data to generate corresponding check data. Different first physical addresses and second physical addresses are assigned to the user data and check data, respectively. The first physical address points to a first storage area within multiple storage areas, and the second physical address points to a second storage area within multiple storage areas that is different from the first storage area. Furthermore, by sending different first write instructions including the first physical address and second write instructions including the second physical address, the user data and check data are stored in the first and second storage areas respectively. On one hand, this embodiment achieves independent management of user data and check data by storing them separately, improving the performance and flexibility of the storage system. Furthermore, recording the second physical address provides a condition for quickly locating the check data, thereby improving the fault tolerance and data recovery speed of the storage system. On the other hand, the independent writing of user data and check data through different write instructions, along with the parallel processing of the independent first and second write instructions, further improves the efficiency of data writing. In addition, the risk of simultaneous loss of user data and check data is reduced. Attached Figure Description

[0010] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0011] Figure 1 This is a schematic diagram of an exemplary system having a storage system according to an embodiment of this application. Figure 1 ;

[0012] Figure 2 This is a schematic diagram of an exemplary memory card having a storage system according to an embodiment of this application;

[0013] Figure 3 This is a schematic diagram of an exemplary solid-state drive with a storage system according to an embodiment of this application;

[0014] Figure 4 This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of this application;

[0015] Figure 5 This is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of this application;

[0016] Figure 6 This is a schematic diagram of an exemplary system having a storage system according to an embodiment of this application. Figure 2 .

[0017] Figure 7 A schematic diagram of a die, memory block, superblock, and stripe in a memory device provided in an embodiment of this application;

[0018] Figure 8 A schematic diagram of a storage surface, storage block, and superblock in a memory device provided in an embodiment of this application;

[0019] Figure 9 This is a schematic diagram of the channel layout between the memory controller and the memory device provided in an embodiment of this application;

[0020] Figure 10 A schematic diagram illustrating the principle of RAID 5 provided in this application embodiment;

[0021] Figure 11 This is one of the timing diagrams for performing a write operation provided in an embodiment of this application;

[0022] Figure 12 The second timing diagram for performing a write operation provided in the embodiments of this application;

[0023] Figure 13 A schematic diagram of the first and second storage areas. Figure 1 ;

[0024] Figure 14 A schematic diagram of the first and second storage areas. Figure 2 ;

[0025] Figure 15 for Figure 14 The diagram shows the relationship between user data stored in a superblock and verification data stored in a second storage block.

[0026] Figure 16 This is a schematic diagram illustrating the relationship between index information and mapping tables provided in an embodiment of this application;

[0027] Figure 17A Flowchart of an operation method for a storage system provided in an embodiment of this application Figure 1 ;

[0028] Figure 17B Flowchart of an operation method for a storage system provided in an embodiment of this application Figure 2 ;

[0029] Figure 18 A schematic diagram of the operation method of the storage system provided in an embodiment of this application Figure 1 ;

[0030] Figure 19 A schematic diagram of the operation method of the storage system provided in an embodiment of this application Figure 1 ;

[0031] Figure 20 Flowchart of an operation method for a storage system provided in an embodiment of this application Figure 3 ;

[0032] Figure 21A A schematic diagram of a data writing process provided in one embodiment of this application Figure 1 ;

[0033] Figure 21B A schematic diagram of a data writing process provided in one embodiment of this application Figure 2 ;

[0034] Figure 22 This is a schematic diagram of a data reading process provided in an embodiment of this application;

[0035] Figure 23 This is a block diagram of a storage medium provided in an embodiment of this application. Detailed Implementation

[0036] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0039] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] The memory devices in the embodiments of this application include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0042] Figure 1 This is a schematic diagram of an exemplary system with a storage system provided for embodiments of this application. In embodiments of this application, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1As shown, system 100 may include a host 101 and a storage system 102. The storage system 102 may include one or more memory devices 103 and a memory controller 104. The host 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 101 may be configured to send data to or receive data from the storage system 102.

[0043] In some embodiments, memory controller 104 is coupled to memory device 103 and host 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host 101. In some embodiments, memory controller 104 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 104 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0044] In some embodiments, the memory controller 104 is configured to perform mapping management on data stored in the memory device 103. Specifically, the memory controller 104 can update and maintain an L2P table, where each mapping entry represents a mapping relationship between a logical address and a physical address. When the host 101 sends a read request including a logical address to the memory controller 104, the memory controller 104 can obtain the corresponding physical address based on the L2P table and the logical address in the read request, and read data from the memory device 103 according to the physical address and send it to the host 101.

[0045] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the storage system 102 can be implemented and packaged into different types of terminal electronic products.

[0046] In such Figure 2In one example shown, the memory controller 104 and a single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a connection between the memory card 201 and a host device (e.g., Figure 1 The memory card connector 202 is coupled to the host 101. Figure 3 In another example shown, the memory controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include components for connecting the SSD 203 to host devices (e.g., Figure 1 The SSD connector 204 is coupled to the host 101. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0047] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuitry provided for embodiments of this application. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0048] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, a quad-level cell (QLC) storing four bits per cell, or a penta-level cell (PLC) storing five bits per cell.

[0049] like Figure 4As shown, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of memory cell strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0050] like Figure 4 As shown, the memory cell string 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0051] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0052] Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0053] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 404.

[0054] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0055] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0056] Figure 6 A system diagram including a host and a storage system is provided for embodiments of this application, such as... Figure 6As shown, the storage system 102 is connected to the host 101. The storage system 102 may include a memory controller 104 and a memory device 103. The memory controller 104 controls the memory device 103 to perform read, write, and erase operations. The memory controller 104 and the memory device 103 can also be coupled in any suitable manner. The memory controller 104 may include a host interface (I / F) 1041, a memory interface (I / F) 1042, a processor 1043, a register 1048, and a bus 1040. The host interface 1041 is the connection interface between the host 101 and the memory controller 104, allowing the host 101 and the memory controller 104 to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1042 is the connection interface between the memory controller 104 and the memory device 103, and is used to implement data transfer between the memory controller 104 and the memory device 103. The processor 1043 is used to control the storage system 102 as a whole.

[0057] In some specific embodiments, the processor 1043 may include one or more units with logical operation capabilities, such as a central processing unit (CPU) and / or a microcontroller unit (MCU).

[0058] It should be noted that the processor 1043 described in the embodiments of this application may include multiple functional modules. Each functional module of the processor 1043 may be a software module running on a processor (e.g., a microcontroller unit (MCU)) that is part of the processor 1043, or it may be a hardware module of a finite state machine (FSM) (e.g., an integrated circuit (IC, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) etc.)), or it may be a combination of software modules and hardware modules.

[0059] In some specific embodiments, the buffer 1048 is used to cache data. For example, the data cached by the buffer 1048 includes, but is not limited to, data received from the host 101, data to be sent to the host 101, data to be written to the memory device 103 (write data), data read from the memory device 103 (read data), and various management data that represent the state of the memory device 103 and are referenced by the processor 1043 for the control of the memory device 103.

[0060] For example, the cache 1048 includes, but is not limited to, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR SDRAM).

[0061] To improve the reliability of data transmission and storage, error-correcting code (ECC) technology has been widely used in the field of data storage. For example, among various error-correcting codes, low-density parity check (LDPC) codes are simple to decode and can be operated in parallel, making them one of the most widely used error-correcting codes.

[0062] As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the storage market due to its high storage density, controllable production costs, and suitable erasure speed. During data transmission and storage in NAND memory, data errors may occur due to hardware failures, software failures, hard drive errors, etc. To ensure the integrity of user data, LDPC codes have been proposed for error detection and correction of data stored in storage systems including NAND memory.

[0063] To further meet the need for storing and accessing reliable data, Redundant Array of Independent Disks (RAID) technology has also been used to improve the performance and reliability of storage systems, including those using NAND flash memory. RAID algorithms employ striping, mirroring, and / or parity checking techniques to achieve reliable data storage.

[0064] In some embodiments, such as Figure 6 As shown, the memory controller 104 also includes an error correction code (ECC) engine 1047 and a RAID engine 1049.

[0065] In some specific embodiments, the error correction code engine 1047 can be configured to encode and decode data in the memory system using ECC technology. Specifically, the error correction code engine 1047 may include an encoder and a decoder, wherein the encoder can be configured to: in a write operation, perform ECC encoding on the data to be written to the memory device; and the decoder can be configured to: in a read operation, perform ECC decoding on the codewords to be decoded in the read data.

[0066] In some specific embodiments, the RAID engine 1049 can be configured to encode and decode data in a memory system using RAID technology. Specifically, the RAID engine 1049 may include an encoder and a decoder, wherein the encoder can be configured to perform RAID encoding on data to be written to the memory device during a write operation; and the decoder can be configured to perform RAID decoding on codewords to be decoded in the read data during a read operation.

[0067] like Figure 6 and Figure 7 As shown, the memory device 103 includes multiple memory regions 1030. Each memory region 1030 includes L dies, where the L dies are die 0, die 1, ..., die L-1, and L is an integer greater than 1. It can be understood that when L is 4, the memory region 1030 includes 4 dies, namely die 0, die 1, die 2, and die 3. Each die includes multiple memory blocks; exemplarily, Figure 7 The diagram shows that each die includes P memory blocks, which are memory block 0, memory block 1, ..., memory block P-1, where P is an integer greater than 1. It can be understood that when P is 4, each die includes 4 memory blocks: memory block 0, memory block 1, memory block 2, and memory block 3.

[0068] The memory controller 104 can manage multiple memory blocks in the memory device 103. Specifically, the memory controller 104 can group multiple memory blocks within different dies into a superblock, that is, multiple memory blocks within different dies constitute a superblock. For example, as shown... Figure 7 As shown, storage block 0 in each die constitutes superblock SPB0, storage block 1 in each die constitutes superblock SPB1, ..., storage block P-1 in each die constitutes superblock SPBP-1.

[0069] In some embodiments, a superblock may include one or more stripes. In some embodiments, a strip may be referred to as a superpage. A strip or superpage may include multiple pages. For example, Figure 7The diagram shows that each storage block consists of K pages, namely page 0, page 1, ..., page K-1, where K is an integer greater than 1.

[0070] like Figure 7 As shown, pages 0 in storage block 0 of each die constitute stripe 0, pages 1 in storage block 0 of each die constitute stripe 1, ..., pages K-1 in storage block 0 of each die constitute stripe K-1.

[0071] It should be noted that, Figure 7 The example shown is only an illustration of how the same numbered memory blocks within each die constitute a superblock and the same numbered pages within each superblock constitute a stripe. The grouping method of superblocks and stripes is not limited to this, and other methods known in the art can also be used.

[0072] Figure 8 This is a schematic diagram of a memory surface, memory block, and superblock in a memory device provided in an embodiment of this application. Figure 8 The superblock shown and Figure 7 The superblock shown is different. For example... Figure 6 and Figure 8 As shown, the memory device 103 includes a plurality of memory regions 1030. Each memory region 1030 includes L dies, where the L dies are dies 0, dies 1, ..., dies L-1, and L is an integer greater than 1. Each die includes multiple memory planes. For example, Figure 8 The diagram shows that each die includes two storage surfaces, designated storage surface 0 and storage surface 1. Each storage surface includes multiple storage blocks, exemplarily... Figure 8 The diagram shows that each storage surface includes P storage blocks, namely storage block 0, storage block 1, ..., storage block P-1, where P is an integer greater than 1. It can be understood that when P is 4, each storage surface includes 4 storage blocks, namely storage block 0, storage block 1, storage block 2, and storage block 3.

[0073] In some embodiments, such as Figure 8 As shown, storage surface 0 and storage block 0 in storage surface 1 of each die constitute superblock SPB0, storage surface 0 and storage block 1 in storage surface 1 of each die constitute superblock SPB1, ..., storage surface 0 and storage block P-1 in storage surface 1 of each die constitute superblock SPBP-1. Figure 9 This is a schematic diagram of the channel layout between the memory controller and the memory device provided in an embodiment of this application. Figure 9 As shown, the memory controller 104 can be connected to multiple dies (dies 0 to dies 7) via the first channel 1051 and the second channel 1052.

[0074] For example, die 0, die 1, die 2 and die 3 can be connected together to the first channel 1051 and communicate with the memory controller 104 through the first channel 1051.

[0075] For example, die 4, die 5, die 6 and die 7 can be connected together to the second channel 1052 and communicate with the memory controller 104 through the second channel 1052.

[0076] Memory devices using multiple dies can improve performance by employing data interleaving. To achieve data interleaving, the memory device can be managed on a channel and path basis. For example, memory controller 104 can send commands, control signals including addresses, and data to die 0 via a first channel 1051. Die 0 receives data sent from memory controller 104. While die 0 is programming the data received from memory controller 104 into memory cells, memory controller 104 can send commands, control signals including addresses, and data to die 1.

[0077] exist Figure 9 In this configuration, multiple dies can be arranged to form four pathways (first pathway, second pathway, third pathway, and fourth pathway). The first pathway may include dies 0 and dies 4, the second pathway may include dies 1 and dies 5, the third pathway may include dies 2 and dies 6, and the fourth pathway may include dies 3 and dies 7.

[0078] exist Figure 9 The document describes data interleaving with two channels and four paths. In practice, data interleaving can be performed with other structures, and it can become more efficient as the number of channels and paths increases.

[0079] It should be noted that, Figure 9 The example described uses a memory device with a storage area containing 8 dies, 2 channels, and 4 pathways as an example, and is not intended to limit the number of dies, channels, and pathways in this application.

[0080] Next, combine Figure 10 This section introduces RAID 5, a type of RAID technology. Figure 10 As shown, the storage area of ​​the storage device includes four dies (die 0, die 1, die 2, and die 3). Storage blocks with the same number in the four dies form a superblock SPB0, and each storage block includes four pages. For example... Figure 10As shown, pages 0 in storage block 0 within each die constitute stripe 0, pages 1 in storage block 0 within each die constitute stripe 1, pages 2 in storage block 0 within each die constitute stripe 2, and pages 3 in storage block 0 within each die constitute stripe 3.

[0081] In some embodiments, the received user data is RAID encoded to generate check data, and the user data and check data are written into the same superblock.

[0082] For example, such as Figure 10 As shown, user data and parity data are written to superblock SPB0. Specifically, the user data Data_0 to be written to Stripe0 is XORed to generate parity data Parity_0, and both user data Data_0 and parity data Parity_0 are stored in Stripe0. The user data Data_1 to be written to Stripe1 is XORed to generate parity data Parity_1, and both user data Data_1 and parity data Parity_1 are stored in Stripe1. The user data Data_2 to be written to Stripe2 is XORed to generate parity data Parity_2, and both user data Data_2 and Parity_2 are stored in Stripe2. The user data Data_3 to be written to Stripe3 is XORed to generate parity data Parity_3, and both user data Data_3 and parity data Parity_3 are stored in Stripe3. (Reference) Figure 10 In RAID 5 technology, parity data is interleaved and stored on all dies in the same superblock. For example, parity data Parity_0, parity data Parity_1, parity data Parity_2 and parity data Parity_3 are stored in die 3, die 2, die 1 and die 0, respectively.

[0083] in addition, Figure 10 The following example illustrates the storage location of user data and verification data using a left-ward dyn approach. Specifically, the verification data starts from the last die (e.g., ...). Figure 10 Starting with die 3 as shown, move forward sequentially to the first die (as shown). Figure 10 The die shown is 0). In actual use of RAID 5 technology, user data and parity data can be stored in a manner including but not limited to right-symmetric (Forward Dyn) storage.

[0084] In the above embodiments, verification data is used to verify the integrity of user data, ensuring that the read data is not damaged or lost. However, storing user data and its verification data in the same storage area, such as the same superblock within the same storage area, has two drawbacks. First, it prevents independent management of user data and verification data. For example, during data migration or backup, user data and verification data must be processed together, leading to a heavy I / O burden or an inability to use different access modes based on the difference in data volume between user data and verification data. Second, it increases the risk of data loss, thereby reducing the reliability of the storage system. For instance, when the superblock is damaged, user data and verification data stored in the same superblock may be lost simultaneously, resulting in unrecoverable data. Therefore, improving the performance and reliability of the storage system has become an urgent problem to be solved at present.

[0085] In response, this application proposes the following implementation methods.

[0086] In a first aspect, embodiments of this application provide a storage system, such as Figure 6 As shown, the storage system 102 includes a memory controller 104 and a memory device 103 coupled to the memory controller 104. The memory device 103 includes a plurality of storage regions 1030. The memory controller 104 is configured to: perform a redundancy array encoding operation on received user data to generate check data; allocate a first physical address for storing the user data, wherein the first physical address points to a first storage region among the plurality of storage regions 1030; allocate a second physical address for storing the check data, and record the second physical address, wherein the second physical address points to a second storage region among the plurality of storage regions 1030 that is different from the first storage region; send a first write instruction including the first physical address to the memory device, wherein the first write instruction indicates that the user data is written to the first storage region; and send a second write instruction including the second physical address and different from the first write instruction to the memory device, wherein the second write instruction indicates that the check data is written to the second storage region.

[0087] In this embodiment, redundant array encoding is performed on the received user data to generate corresponding check data. Different first physical addresses and second physical addresses are assigned to the user data and check data, respectively. The first physical address points to a first storage area within multiple storage areas, and the second physical address points to a second storage area within multiple storage areas that is different from the first storage area. Furthermore, by sending different first write instructions including the first physical address and second write instructions including the second physical address, the user data and check data are stored in the first and second storage areas respectively. On one hand, this embodiment achieves independent management of user data and check data by storing them separately, improving the performance and flexibility of the storage system. Furthermore, recording the second physical address provides a condition for quickly locating the check data, thereby improving the fault tolerance and data recovery speed of the storage system. On the other hand, the independent writing of user data and check data through different write instructions, along with the parallel processing of the independent first and second write instructions, further improves the efficiency of data writing. In addition, the risk of simultaneous loss of user data and check data is reduced.

[0088] In some embodiments, user data includes, but is not limited to, data received from host 101 and data received from storage device 103. For example, user data may be data received from storage device 103 during the garbage collection (GC) phase or the wear leveling (WL) phase.

[0089] In some embodiments, the redundant array coding operation includes RAID coding operation.

[0090] In some embodiments, the memory controller 104 can be accessed via Figure 9 The first channel 1051 shown sends a first write instruction to the memory device, wherein the first write instruction includes a first write command, a first physical address, and user data, and the first storage area of ​​the memory device receives the user data sent from the memory controller 104. When the first storage area of ​​the memory device (e.g., dies 0 to 3) programs the user data received from the memory controller 104 into the memory cell, the memory controller 104 can send a second write instruction to the second storage area of ​​the memory device (e.g., die 4) via the second channel 1052, wherein the second write instruction includes a second write command, a second physical address, and verification data.

[0091] In some embodiments, the timing of the first write instruction and the second write instruction is different.

[0092] Figure 11This is one of the timing diagrams for the write operation provided in the embodiments of this application, such as... Figure 11 As shown, Cycle Type indicates the input type; CMD indicates the input command; ADDR indicates the input address; DIN indicates the input data; DQ[7:0] indicates chip pins with input / output functions; R / B_n indicates chip pins that monitor the chip's (busy / ready) status, with a low level representing a busy state; tADL indicates the time interval between address input and data input; tWB indicates the time interval between the command and R / B_n being pulled low.

[0093] For example, a first write instruction for instructing the execution of a first write operation may include, for example, two subcommands (e.g., 80h and 10h). In an exemplary embodiment, after receiving subcommand 80h, memory device 103 receives the address ADDR of user data for which a write / programming operation will be performed. After receiving address ADDR, memory device 103 may receive user data DATA for which a write / programming operation will be performed. After receiving subcommand 10h, memory device 103 writes user data DATA to a first storage area within a write / programming time tPROG.

[0094] Exemplarily, the second write instruction for instructing the execution of a second write operation may also include, for example, two subcommands (e.g., 80h and 10h). In an exemplary embodiment, after receiving subcommand 80h, memory device 103 receives the address ADDR of verification data for which a write / programming operation will be performed. After receiving address ADDR, memory device 103 may receive the verification data for which a write / programming operation will be performed. After receiving subcommand 10h, memory device 103 writes the verification data to the first memory area within the write / programming time tPROG.

[0095] It should be noted that, Figure 11 This can be used to represent a timing diagram for performing a first write operation, or it can be used to represent a timing diagram for a second write operation. The first write instruction and the two sub-commands of the second write instruction are identical. However, in the first write operation (writing user data to the first storage area) and the second write operation (writing checksum data to the second storage area), the first write instruction includes a first physical address and user data, and the second write instruction includes a second physical address and checksum data. In other words, in... Figure 11 In the timing diagram shown, the first write instruction and the second write instruction have different addresses ADDR after subcommand 80h and data DATA before subcommand 10h.

[0096] Figure 12 This is the second timing diagram for performing a write operation provided in the embodiments of this application, as shown below. Figure 12 As shown, the second write instruction for instructing the execution of a second write operation may include, for example, two subcommands (e.g., 85h and 10h). In an exemplary embodiment, after receiving subcommand 85h, memory device 103 receives the address ADDR of verification data for which a write / programming operation will be performed. After receiving address ADDR, memory device 103 may receive the verification data for which a write / programming operation will be performed. After receiving subcommand 10h, memory device 103 writes the verification data to the second storage area within the write / programming time tPROG.

[0097] It should be noted that in the above embodiment, the subcommand 85h of the second write instruction is predefined and specifically used to indicate the start of writing the verification data. By distinguishing the subcommand 85h of the second write instruction from the subcommand 80h of the first write instruction, it is ensured that user data and verification data are written to different storage areas. In actual use, if the first write instruction and the second write instruction are different, the subcommands in the first write instruction and the second write instruction can also be predefined as other types of subcommands.

[0098] In some embodiments, the first storage region includes a plurality of first dies, and each first die includes a plurality of first storage blocks; wherein, the plurality of first storage blocks within different first dies constitute a superblock; the memory controller is specifically configured to: allocate a first physical address based on the plurality of superblocks under management, wherein the first physical address points to a target superblock among the plurality of superblocks.

[0099] In some embodiments, the second storage region includes at least one second die, the second die including a plurality of second storage blocks; the memory controller is further specifically configured to: allocate a second physical address based on the managed plurality of second storage blocks, wherein the second physical address points to a target second storage block among the plurality of second storage blocks.

[0100] In some embodiments, the memory controller is also configured to manage a plurality of superblocks and a plurality of second memory blocks.

[0101] Combination Figure 6 and Figure 13 The first storage region in the plurality of storage regions 1030 of the memory device 103 includes L first dies, namely first die 0, first die 1, ..., first die L-1, where L is an integer greater than 1. It can be understood that when L is 4, the storage region 1030 includes 4 first dies, namely first die 0, first die 1, first die 2, and first die 3. Each first die includes a plurality of first storage blocks, exemplarily... Figure 13 Each first die is shown to include P first memory blocks, where the P first memory blocks are designated as first memory block 0, first memory block 1, ..., first memory block P-1, and P is an integer greater than 1. It can be understood that when P is 4, each first die includes 4 first memory blocks, designated as first memory block 0, first memory block 1, first memory block 2, and first memory block 3. The second memory region in the plurality of memory regions 1030 of the memory device 103 includes Q second dies, where the Q second dies are designated as second die 0, second die 1, ..., second die Q-1, and Q is an integer greater than or equal to 1. Each second die includes multiple second memory blocks; exemplarily, Figure 13 It is shown that each second die includes P second memory blocks, namely second memory block 0, second memory block 1, ..., second memory block P-1, where P is an integer greater than 1.

[0102] Here, multiple first memory blocks within different first dies in the first memory region constitute a superblock, for example... Figure 13 The first memory blocks with the same number within each first die, as shown, constitute a superblock, and the pages with the same number within each superblock constitute a stripe. For information on the division of superblocks and stripes, please refer to [reference needed]. Figure 7 The details and related descriptions will not be repeated here.

[0103] In some embodiments, the number of first dies included in the first storage region and the number of second dies included in the second region may be the same or different.

[0104] In some implementations, since the amount of user data is greater than the amount of verification data, the number of first dies included in the first storage area is greater than the number of second dies included in the second area; for example, L is greater than Q.

[0105] In some embodiments, the first physical address points to a target superblock among multiple superblocks, wherein the number of target superblocks can be one or more, and the number of target superblocks depends on the size of the actual amount of user data to be written.

[0106] Similarly, the number of target second storage blocks can be one or more, depending on the size of the actual amount of verification data to be written.

[0107] In this embodiment, by employing different management granularities (superblock and storage block) in the first and second storage areas based on the difference in the amount of user data and verification data, efficient management of user data and fine-grained control of verification data are achieved. This differentiated strategy optimizes storage resource allocation, improves the overall performance of the storage system, and simultaneously ensures both flexibility and efficiency in data management.

[0108] In some embodiments, the memory controller is further configured to: obtain first metadata related to user data from the memory device; wherein the first metadata includes index information related to verification data; and determine a second physical address for storing the verification data by looking up a mapping table based on the index information; wherein the mapping table includes a mapping relationship between the index information and the second physical address.

[0109] In some embodiments, such as Figure 14 As shown, the first storage region includes four first dies (first die 0, first die 1, first die 2, and first die 3), and each first die includes four first memory blocks. The second storage region includes two second dies, and each second die includes four second memory blocks.

[0110] Figure 15 for Figure 14 This diagram illustrates the relationship between user data stored in a superblock and verification data stored in a second storage block.

[0111] like Figure 14 and Figure 15 As shown, when writing user data to the superblock SPB0 of the first storage area, first metadata is also written to the superblock SPB0 of the first storage area. For example, the user data and the first metadata are stored in the same page of the first storage block 0 of the superblock SPB0.

[0112] In some embodiments, the first metadata includes basic information and index information related to the verification data. The basic information includes, but is not limited to, the mapping relationship between the logical address and physical address of the user data, wear leveling information (e.g., the number of erase / write cycles of the storage block), or timestamps (recording the write time of the data).

[0113] In some embodiments, during the power-on phase, the memory controller 104 loads a mapping table from the memory device 103, for example, by loading the mapping table into a cache 1048 of the memory controller 104 to support fast access and real-time updates. During power-off, the memory controller flushes the mapping table back to the memory device 103.

[0114] In some embodiments, the mapping table includes multiple entries, each entry recording a second physical address corresponding to an index; the memory controller is further specifically configured to: search the mapping table based on the index information to determine a target entry among the multiple entries; and determine a second physical address for storing the verification data based on the target entry.

[0115] like Figure 15As shown, the mapping table includes X entries, which are entry 0, entry 1, entry 2, entry 3, ..., entry X-2 and entry X-1, where X is an integer greater than or equal to 1.

[0116] In some embodiments, a superblock includes at least one stripe, and a first physical address specifically points to a target stripe among multiple stripes of the target superblock. The target stripe is used to store user data. The memory controller is specifically configured to: determine a corresponding second identifier in the index information based on a first identifier in the index information; wherein the first identifier is used to indicate the location of the target stripe, and the second identifier is used to indicate the location of the target entry; and obtain the target entry based on the second identifier.

[0117] Here you can refer to Figure 7 and Figure 13 The relationship between superblocks and stripes will be understood in detail here, and will not be elaborated further.

[0118] In some embodiments, the number of target stripes can be one or more, and the specific number of target stripes depends on the size of the user data.

[0119] Figure 16 This is a diagram illustrating the relationship between index information and the mapping table. For example... Figure 16 As shown, the index information includes a first identifier and a second identifier. The memory controller can determine the position of the target strip by the first identifier and further obtain the target entry by determining the position of the target entry by the second identifier.

[0120] In some implementations, such as Figure 16 As shown, the information recorded in the mapping table related to the second physical address includes at least the die ID and the block ID.

[0121] In other implementations, when the verification data is stored in Figure 14 When a superblock is formed by two storage blocks with the same number in the second storage region shown, the information recorded in the mapping table related to the second physical address includes at least: die ID, raid stripe start ID, raid stripe end ID, and block ID.

[0122] In some implementations, when the verification data is stored in Figure 14When a superblock is formed by two storage blocks with the same number in the second storage region shown, the information recorded in the mapping table related to the second physical address includes at least: die number, stripe start position, address offset, and storage block number. The end position of the stripe can be determined by the stripe start position and address offset.

[0123] It should be noted that, at this time, the number of second storage blocks in the superblock used to store verification data is less than the number of first storage blocks in the superblock used to store user data.

[0124] In other implementations, the index information includes the logical address of the verification data and the mapping relationship between the logical address and the physical address of the verification data.

[0125] In some embodiments, the memory controller is specifically configured to: allocate a blank entry among a plurality of entries, and record a second physical address into the blank entry.

[0126] like Figure 15 As shown, entry 2 in the mapping table is a blank entry. In some embodiments, a blank entry represents an entry in the mapping table for which no information is recorded.

[0127] In other embodiments, when multiple entries in the mapping table already contain information, a blank entry can be provided for the second physical address to be recorded by adding a blank entry to the mapping table.

[0128] In some embodiments, the memory controller is further configured to: obtain second metadata related to verification data from the memory device; wherein the second metadata includes address information related to user data; determine that the second physical address of the target entry record is incorrect based on the mismatch between the address information in the second metadata and the first physical address; and reconstruct the target entry based on the error in the second physical address of the target entry record.

[0129] In some embodiments, the memory controller is further configured to determine that the second physical address of the target entry record is correct based on the matching of address information in the second metadata with the first physical address.

[0130] In some embodiments, such as Figure 15 As shown, when write verification data to the second storage block of the second storage area, second metadata is also written to the second storage block of the second storage area. For example, user data and second metadata are stored on the same page of the second storage block 0 of the second storage area.

[0131] In some embodiments, the address information in the second metadata includes the start bit and the end bit of the physical address where the user data is stored. For example, as shown... Figure 15As shown, the address information in the second metadata includes the start and end bits of Stripe0 of the superblock SPB0 that stores user data.

[0132] In this embodiment of the application, the storage location (i.e., the first physical address) of the user data corresponding to the verification data can be determined according to the address information in the second metadata. When the address information in the second metadata does not match the first physical address, it means that the verification data obtained based on the second physical address of the target entry record in the mapping table does not match the user data. In other words, the second physical address of the target entry record is incorrect, so the target entry needs to be reconstructed.

[0133] Specifically, based on the address information of the acquired second metadata, other user data and other first metadata stored at the physical address corresponding to the address information can be obtained. Other entries in the mapping table can be searched again using the index information in the other first metadata. When the address information of the second metadata obtained based on the latest searched other entries matches the physical address of the other user data, it is determined that the second physical address of the latest searched other entries is correct, and the target entry that has an error is modified based on the information of the latest other entries.

[0134] When the address information in the second metadata matches the first physical address, it means that the verification data obtained based on the second physical address of the target entry record in the mapping table matches the user data. In other words, the second physical address of the target entry record is correct.

[0135] In this embodiment, by matching the address information of the second metadata with the first physical address, erroneous entries in the mapping table can be quickly located and repaired, thereby avoiding data read failures caused by errors in the mapping table. By dynamically reconstructing the entries in the mapping table, the reliability of the mapping table can be ensured, the reliability of data access can be improved, and the risk of data loss or damage caused by mapping errors can be reduced, thereby enhancing the fault tolerance and long-term stability of the storage system.

[0136] In some embodiments, the storage units of the first storage region and the storage units of the second storage region are configured with different storage modes.

[0137] In some embodiments, the storage units of the first storage region are configured to store M bits of data, and the storage units of the second storage region are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M.

[0138] In some embodiments, the storage mode can be SLC mode, MLC mode, TLC mode, QLC mode or PLC mode.

[0139] In some implementations, the storage units in the first storage area are configured in QLC mode, and the storage units in the second storage area are configured in SLC mode. In other words, the storage units in the first storage area are configured to store 4 bits of data, and the storage units in the second storage area are configured to store 1 bit of data. It is understood that different storage modes are used to store user data in the first storage area and to store verification data in the second storage area.

[0140] In this embodiment of the application, by dividing the multiple storage areas of the memory device into a first storage area and a second storage area, wherein the first storage area is used to store user data with high capacity requirements and the second storage area is used to store verification data with high reliability requirements, and different storage modes are used in the first storage area and the second storage area, the storage space can be fully utilized and the performance of the storage system can be effectively optimized.

[0141] Of course, in other examples, N can be equal to M.

[0142] In some embodiments, the memory controller 104 is further configured to: acquire user data stored in a first storage area from the memory device 103; if the error correction code verification fails based on the acquired user data, send a read instruction including a second physical address to the memory device; wherein the read instruction indicates reading verification data stored in the second storage area; and perform a redundancy array verification on the user data using the read verification data.

[0143] Secondly, embodiments of this application provide a storage system, including: a memory controller and a memory device coupled to the memory controller, the memory device including a plurality of dies, the plurality of dies being divided into a plurality of storage regions; the memory controller is configured to: based on the existence of at least one faulty storage block in a first storage region among the plurality of storage regions, migrate a portion of user data stored in the faulty die in the first storage region to a target storage block in the first storage region; based on the partial user data being migrated to the target storage block in the first storage region, update a first physical address storing the user data; wherein the first physical address points to the first storage region; re-execute a redundancy array encoding operation on the partial user data migrated to the target storage block in the first storage region and the remaining unmigrated user data in the first storage region, generating first check data; allocate a third physical address for storing the first check data, and record the third physical address; wherein the third physical address points to a second storage region among the plurality of storage regions that is different from the first storage region; send a third write instruction including the third physical address to the memory device; wherein the third write instruction instructs the first check data to be written to the second storage region.

[0144] In some embodiments, the memory controller is configured to determine the memory region where the faulty memory block is located based on the presence of at least one faulty memory block among a plurality of dies.

[0145] In some embodiments, a faulty storage block may also be referred to as a bad block, such as... Figure 14 As shown, when the number of error bits in one or more pages of the first memory block 0 of the first die 0 exceeds the threshold, the first memory block 0 is identified as a faulty memory block.

[0146] In some embodiments, combined with Figure 14 and Figure 18 As shown, the first storage block 0 within the first die 1 in the first storage area is a faulty storage block, and the remaining first storage blocks within the first die 1 are qualified storage blocks. For example, when migrating some user data stored in the first storage block 0 within the first die 1, the target storage block in the first storage area can be the first storage block 1 of the first die 1 or the first storage block 1 of the first die 2.

[0147] It should be noted that the target storage block can be an idle first storage block in the first storage area or an occupied first storage block with sufficient capacity. An occupied first storage block means that the data is not full and the remaining storage capacity is greater than or equal to the amount of user data.

[0148] In some embodiments, a redundancy array encoding operation (e.g., RAID encoding operation) is re-executed on a portion of the user data of the target storage block migrated to the first storage area and the remaining user data that has not been migrated in the first storage area to generate first verification data; a third physical address is allocated to store the first verification data, and the third physical address is recorded; wherein the third physical address points to a second storage area in multiple storage areas that is different from the first storage area, for example, the third physical address points to the second storage block 1 in the second die 0 in the second storage area.

[0149] In this embodiment, when a storage block containing some user data fails, it is not necessary to migrate the data in all storage blocks involved in the superblock containing the user data. Moreover, the first verification data can be regenerated based on the migrated user data and the remaining unmigrated user data, and the first verification data can be stored in the second storage area. This reduces the amount of data migration while ensuring the reliability of the storage system.

[0150] In some embodiments, the memory controller is configured to determine at least one die as a faulty die based on the fact that the number of faulty memory blocks in at least one die among a plurality of dies is greater than a preset threshold.

[0151] In some embodiments, the preset threshold may be an upper limit for the number of bad blocks that can be pre-set based on chip design specifications, process maturity and reliability requirements, through statistical analysis of test data.

[0152] In some embodiments, combined with Figure 14 and Figure 19 As shown, if the die containing the superblock SPB0 in the first storage area fails, some user data stored in the first storage block 0 of the faulty die (e.g., the first die 1) in the first storage area will be migrated to a qualified die in the first storage area, such as the first storage block 1 of the qualified die in the superblock SPB1 of the first storage area.

[0153] It should be noted that during the data migration of some user data stored in the faulty dies within the first storage area, due to... Figure 19 The first die 1 in the process is a faulty die. Figure 16 During the process of migrating a portion of user data from superblock SPB0 to superblock SPB1, the first physical address allocated to the user data to be migrated will bypass the first storage block 1 in superblock SPB1 that belongs to the faulty die (first die 1) and point to the first storage block 1 in superblock SPB1 that belongs to other qualified dies (e.g., first die 0, first die 2, and first die 3).

[0154] In some embodiments, a redundancy array encoding operation (e.g., RAID encoding operation) is re-executed on a portion of the user data of qualified dies migrated to the first storage area and the remaining user data not migrated in the first storage area to generate first verification data; a third physical address is allocated to store the first verification data, and the third physical address is recorded; wherein the third physical address points to a second storage area different from the first storage area among multiple storage areas, for example, the third physical address points to the second storage block 1 in the second die 0 in the second storage area.

[0155] In this embodiment, when a die containing some user data fails, it is not necessary to migrate the data in all dies involved in the superblock containing the user data. Moreover, the first verification data can be regenerated based on the migrated user data and the remaining unmigrated user data, and the first verification data can be stored in the second storage area. This reduces the amount of data migration while ensuring the reliability of the storage system.

[0156] In some embodiments, the memory controller is further configured to: re-execute a redundancy array encoding operation on the user data stored in the first storage area based on the existence of at least one faulty storage block in the second storage area to generate second check data; allocate a fourth physical address for storing the second check data and record the fourth physical address; wherein the fourth physical address points to a target storage block in the second storage area; and send a fourth write instruction including the fourth physical address to the memory device; wherein the fourth write instruction instructs the second check data to be written to the target storage block in the second storage area.

[0157] In this embodiment, when the storage block containing the verification data fails, it is not necessary to migrate the data in all storage blocks involved in the superblock containing the user data. Furthermore, the user data in the first storage area can be regenerated into the second verification data and stored in the second storage area, thereby reducing the amount of data migration while ensuring the reliability of the storage system.

[0158] In some embodiments, the first storage region includes a plurality of first dies, and each first die includes a plurality of first storage blocks; wherein, the plurality of first storage blocks within different first dies constitute a superblock; the memory controller is specifically configured to: allocate a first physical address based on the plurality of superblocks under management, wherein the first physical address points to a target superblock among the plurality of superblocks.

[0159] In some embodiments, the second storage region includes at least one second die, the second die including a plurality of second storage blocks; the memory controller is further specifically configured to: allocate a fourth physical address based on the managed plurality of second storage blocks, wherein the fourth physical address points to a target second storage block within the target second die.

[0160] In some embodiments, the memory controller is also configured to manage a plurality of superblocks and a plurality of second memory blocks.

[0161] Here, the specific methods for dividing the first and second storage regions within the multiple storage regions, as well as the specific methods for dividing the superblock within the first storage region, can be found in [reference needed]. Figures 13 to 14 The relevant descriptions will not be repeated here.

[0162] In this embodiment, user data and verification data are stored separately in a first storage area and a second storage area to achieve independent management of user data and verification data. This reduces the amount of data that needs to be moved when the storage block containing user data or verification data fails. This not only reduces the burden on the storage system, but also reduces the risk of simultaneous loss of user data and verification data.

[0163] In some embodiments, the memory controller is further configured to: obtain third metadata related to user data from the memory device; wherein the third metadata includes index information related to the first verification data; and determine a third physical address for storing the first verification data by looking up a mapping table based on the index information; wherein the mapping table includes a mapping relationship between the index information and the third physical address.

[0164] Here, the third metadata can be understood by referring to the relevant description of the first metadata in the foregoing embodiments.

[0165] In some embodiments, the mapping table includes multiple entries, each entry recording a third physical address corresponding to an index; the memory controller is further specifically configured to: search the mapping table based on the index information to determine a target entry among the multiple entries; and determine a third physical address for storing the first verification data based on the target entry.

[0166] like Figure 13 As shown, the mapping table includes X entries, which are entry 0, entry 1, entry 2, entry 3, ..., entry X-2 and entry X-1, where X is an integer greater than or equal to 1.

[0167] like Figure 16 As shown, the mapping table includes 7 entries, based on the target entry (such as...). Figure 7 As shown in entry 4), determine the third physical address where the first verification data is stored.

[0168] In some embodiments, the superblock includes at least one stripe, and the updated first physical address specifically points to a target stripe among multiple stripes of the target superblock, the target stripe being used to store user data; the memory controller is further specifically configured to: determine a corresponding second identifier in the index information based on a first identifier in the index information; wherein the first identifier is used to indicate the location of the target stripe, and the second identifier is used to indicate the location of the target entry; and obtain the target entry based on the second identifier.

[0169] In some embodiments, the memory controller is further configured to: allocate a blank entry among a plurality of entries, and record a third physical address into the blank entry.

[0170] In some embodiments, a blank entry refers to an entry among multiple entries in the mapping table that has no recorded information.

[0171] In other embodiments, when multiple entries in the mapping table already contain information, a blank entry can be provided for the third physical address to be recorded by adding a blank entry to the mapping table.

[0172] In some embodiments, the memory controller is further configured to: obtain fourth metadata related to the first verification data from the memory device; wherein the fourth metadata includes address information related to user data; determine that the third physical address of the target entry record is incorrect based on the mismatch between the address information in the fourth metadata and the updated first physical address; and reconstruct the target entry based on the error in the third physical address of the target entry record.

[0173] Here, the fourth metadata can be understood by referring to the relevant description of the second metadata in the foregoing embodiments.

[0174] In some embodiments, the memory controller is further configured to determine that the third physical address of the target entry record is correct based on the address information in the fourth metadata and the new first physical address.

[0175] In some embodiments, the address information in the fourth metadata includes the start bit of the physical address where the user data is stored and the end bit of the physical address where the user data is stored.

[0176] In some embodiments, the storage units of the first storage region and the storage units of the second storage region are configured with different storage modes.

[0177] In some embodiments, the storage units of the first storage region are configured to store M bits of data, and the storage units of the second storage region are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M. In the embodiments of this application, by dividing the multiple storage regions of the memory device into a first storage region and a second storage region, wherein the first storage region is used to store user data with high capacity requirements, and the second storage region is used to store verification data with high reliability requirements, and different storage modes are used in the first storage region and the second storage region, the storage space can be fully utilized and the performance of the storage system can be effectively optimized.

[0178] In some embodiments, the memory controller is configured to determine the memory region where the faulty memory block is located based on the presence of at least one faulty memory block among a plurality of dies.

[0179] In some embodiments, the memory controller is configured to determine at least one die as a faulty die based on the fact that the number of faulty memory blocks in at least one die among a plurality of dies is greater than a preset threshold.

[0180] In some embodiments, the memory controller is further configured to: acquire user data stored in a first storage area from the memory device; if the error correction code verification fails based on the acquired user data, send a read instruction including a second physical address to the memory device; wherein the read instruction indicates reading first verification data stored in the second storage area; and perform a redundancy array check on the user data using the read first verification data.

[0181] In some embodiments, the storage system includes a solid-state drive, general-purpose flash memory, or an embedded multimedia card.

[0182] Figure 17A Flowchart of an operation method for a storage system provided in an embodiment of this application Figure 1 .like Figure 17A As shown, in step S100, it is determined that at least one faulty memory block exists in the memory device. If the determination result of step S100 is "no", the operation ends.

[0183] If the judgment result of step S100 is "yes", then step S101 is executed.

[0184] In step S101, it is determined whether the faulty storage block is located in the first storage area; in other words, it is determined whether the storage block containing the user data or the storage block containing the verification data is faulty.

[0185] If the judgment result of step S101 is "yes", it indicates that the storage block where the user data is located is faulty. Then, step S102 is executed. The storage blocks in the first storage area include the target storage block and the faulty storage block. Part of the user data stored in the faulty storage block in the first storage area is migrated to the target storage block in the first storage area. Here, the target storage block can also be understood as other qualified storage blocks in the first storage area other than the faulty storage block.

[0186] Continue with step S103, and re-execute the redundancy array encoding operation on the partial user data of the target storage block migrated to the first storage area and the remaining user data that has not been migrated in the first storage area to generate the first verification data.

[0187] Execute step S104 to allocate a third physical address for storing the first verification data.

[0188] Execute step S105, send a third write instruction including the third physical address to the memory device, and end the operation. If the judgment result of step S101 is "no", indicating that the storage block where the verification data is located is faulty, then execute step S106, re-execute the redundancy array encoding operation on the user data stored in the first storage area to generate the second verification data.

[0189] Continue with step S107 to allocate a fourth physical address for storing the second verification data. It should be noted that the storage blocks in the second storage area include faulty storage blocks and qualified storage blocks (also referred to as target second storage blocks). Here, the fourth physical address points to the target second storage block in the second storage area. The target second storage block can be an idle second storage block in the second storage area or an occupied second storage block with sufficient capacity. An occupied second storage block indicates that the verification data is not fully written and the remaining storage capacity is greater than or equal to the amount of verification data.

[0190] Execute step S108, send a fourth write instruction including the fourth physical address, and end the operation.

[0191] Figure 17B Flowchart of an operation method for a storage system provided in an embodiment of this application Figure 2 .like Figure 17B As shown, in step S110, it is determined whether the number of defective blocks in the die exceeds a preset threshold. If the determination result of step S110 is "no", the operation ends.

[0192] If the judgment result of step S110 is "yes", then step S111 is executed.

[0193] In step S111, it is determined whether the faulty die is located in the first storage area; in other words, it is determined whether the die containing the user data or the die containing the verification data is faulty.

[0194] If the judgment result of step S111 is "yes", it means that the chip where the user data is located is faulty. Then step S112 is executed. The chips in the first storage area include qualified chips and faulty chips. The user data stored in the faulty chip in the first storage area is migrated to the qualified chip in the first storage area.

[0195] Continue with step S113, and re-execute the redundant array encoding operation on the user data of qualified dies migrated to the first storage area and the remaining user data in qualified dies that have not been migrated in the first storage area to generate the first verification data.

[0196] Execute step S114 to allocate a third physical address for storing the first verification data.

[0197] Execute step S115, send a third write instruction including the third physical address to the memory device, and end the operation. If the judgment result of step S111 is "no", indicating that the die where the verification data is located is faulty, then execute step S116, re-execute the redundancy array encoding operation on the user data stored in the first storage area to generate the second verification data.

[0198] Continue with step S117 to allocate a fourth physical address for storing the second verification data. It should be noted that the dies in the second storage area include qualified dies and faulty dies; here, the fourth physical address points to a qualified die in the second storage area.

[0199] Execute step S118, send a fourth write instruction including the fourth physical address, and end the operation.

[0200] Thirdly, embodiments of this application also provide a memory controller coupled to a memory device, the memory device including multiple storage regions; the memory controller includes: a register and a processor, the processor being configured to: perform a redundancy array encoding operation on received user data to generate check data; allocate a first physical address for storing the user data; wherein the first physical address points to a first storage region among the multiple storage regions; allocate a second physical address for storing the check data, and record a second physical address; wherein the second physical address points to a second storage region among the multiple storage regions that is different from the first storage region; send a first write instruction including the first physical address to the memory device; wherein the first write instruction indicates that user data is written to the first storage region; send a second write instruction including the second physical address and different from the first write instruction to the memory device; wherein the second write instruction indicates that check data is written to the second storage region.

[0201] The memory controller here can be, for example, Figure 1 , Figure 2 , Figure 3 as well as Figure 6 The memory controller 104 is shown. The processor here can be understood as... Figure 6 The processor 1043 shown here, the cache here can be understood as... Figure 6 The register 1048 is shown. Other details about the memory controller have been described in detail above, and for the sake of brevity, they will not be repeated here.

[0202] In some embodiments, the first storage region includes a plurality of first dies, and each first die includes a plurality of first storage blocks; wherein the plurality of first storage blocks within different first dies constitute a superblock; the processor is configured to: allocate a first physical address based on the plurality of managed superblocks, wherein the first physical address points to a target superblock among the plurality of superblocks.

[0203] In some embodiments, the second storage region includes at least one second die, the second die including a plurality of second storage blocks; the processor is further configured to: allocate a second physical address based on the managed plurality of second storage blocks, wherein the second physical address points to a target second storage block among the plurality of second storage blocks.

[0204] In some embodiments, the processor is configured to manage a plurality of superblocks and a plurality of the second storage blocks.

[0205] In some embodiments, such as Figure 6 As shown, the memory controller 104 includes a first management module 1044 and a second management module 1045. The first management module 1044 is configured to manage multiple superblocks, and the second management module 1045 is configured to manage multiple second memory blocks.

[0206] In some embodiments, the processor is further configured to: obtain first metadata related to the user data from the memory device; wherein the first metadata includes index information related to the verification data; and determine the second physical address storing the verification data by looking up a mapping table based on the index information; wherein the mapping table includes a mapping relationship between the index information and the second physical address.

[0207] In some embodiments, such as Figure 6 As shown, the memory controller 104 includes a lookup module 1046. The lookup module 1046 is configured to: search the mapping table based on the index information to determine the target entry among the plurality of entries.

[0208] In some embodiments, the mapping table includes multiple entries, and each entry records the second physical address corresponding to the index information; the processor is specifically configured to: search the mapping table based on the index information to determine the target entry among the multiple entries; and determine the second physical address for storing the verification data based on the target entry.

[0209] In some embodiments, the superblock includes at least one stripe, the first physical address specifically points to a target stripe among multiple stripes of the target superblock, the target stripe being used to store the user data; the processor is specifically configured to: determine a corresponding second identifier in the index information based on a first identifier in the index information; wherein the first identifier is used to indicate the location of the target stripe, and the second identifier is used to indicate the location of the target entry; and obtain the target entry based on the second identifier.

[0210] In some embodiments, the processor is specifically configured to: allocate a blank entry from the plurality of entries, and record the second physical address into the blank entry.

[0211] In some embodiments, the processor is further configured to: obtain second metadata related to the verification data from the memory device; wherein the second metadata includes address information related to the user data; determine that the second physical address of the target entry record is incorrect based on the mismatch between the address information in the second metadata and the first physical address; and reconstruct the target entry based on the error in the second physical address of the target entry record.

[0212] In some embodiments, the processor is further configured to: determine that the second physical address of the target entry record is correct based on the matching of the address information in the second metadata with the first physical address.

[0213] In some embodiments, the address information in the second metadata includes the start bit of the physical address where the user data is stored and the end bit of the physical address where the user data is stored.

[0214] In some embodiments, the storage units of the first storage region and the storage units of the second storage region are configured with different storage modes.

[0215] In some embodiments, the storage units of the first storage region are configured to store M bits of data, and the storage units of the second storage region are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M.

[0216] In some embodiments, the processor is further configured to: acquire user data stored in a first storage area from a memory device; if the error correction code verification fails based on the acquired user data, send a read instruction including a second physical address to the memory device; wherein the read instruction indicates reading verification data stored in the second storage area; and perform a redundancy array check on the user data using the read verification data.

[0217] Fourthly, embodiments of this application also provide a method for operating a storage system. Figure 20 Flowchart of an operation method for a storage system provided in an embodiment of this application Figure 3 ,like Figure 20As shown, the specific steps of this operation method include: Step S121: Performing a redundancy array encoding operation on the received user data to generate verification data; Step S122: Allocating a first physical address for storing the user data; wherein the first physical address points to a first storage area among multiple storage areas of the memory device; Step S123: Allocating a second physical address for storing the verification data, and recording the second physical address; wherein the second physical address points to a second storage area among multiple storage areas that is different from the first storage area; Step S124: Sending a first write instruction including the first physical address to the memory device in the storage system; wherein the first write instruction indicates that the user data is written to the first storage area; Step S125: Sending a second write instruction including the second physical address and different from the first write instruction to the memory device; wherein the second write instruction indicates that the verification data is written to the second storage area.

[0218] In some embodiments, the first storage region includes a plurality of first dies, and the first die includes a plurality of first storage blocks; wherein, the plurality of first storage blocks within different first dies constitute a superblock; the allocation of a first physical address for storing the user data includes: allocating the first physical address based on the plurality of managed superblocks, wherein the first physical address points to a target superblock among the plurality of superblocks.

[0219] In some embodiments, the second storage region includes at least one second die, the second die including a plurality of second storage blocks; the allocation of a second physical address for storing the verification data includes: allocating a second physical address based on the managed plurality of second storage blocks, wherein the second physical address points to a target second storage block among the plurality of second storage blocks.

[0220] In some embodiments, the operation method further includes: obtaining first metadata related to the user data from the memory device; wherein the first metadata includes index information related to the verification data; and determining the second physical address storing the verification data by looking up a mapping table based on the index information; wherein the mapping table includes a mapping relationship between the index information and the second physical address.

[0221] In some embodiments, the mapping table includes multiple entries, and each entry records the second physical address corresponding to one of the index information; the step of searching the mapping table based on the index information to determine the second physical address for storing the verification data includes: searching the mapping table based on the index information to determine the target entry among the multiple entries; and determining the second physical address for storing the verification data based on the target entry.

[0222] In some embodiments, the superblock includes at least one stripe, and the first physical address specifically points to a target stripe among multiple stripes of the target superblock, the target stripe being used to store the user data; the step of looking up the mapping table based on the index information to determine the target entry among the multiple entries includes: determining a corresponding second identifier in the index information based on a first identifier in the index information; wherein the first identifier is used to indicate the location of the target stripe, and the second identifier is used to indicate the location of the target entry; and obtaining the target entry based on the second identifier.

[0223] In some embodiments, recording the second physical address includes: allocating a blank entry among the plurality of entries, and recording the second physical address into the blank entry.

[0224] In some embodiments, the operation method further includes: obtaining second metadata related to the verification data from the memory device; wherein the second metadata includes address information related to the user data; determining that the second physical address of the target entry record is incorrect based on the mismatch between the address information in the second metadata and the first physical address; and reconstructing the target entry based on the error in the second physical address of the target entry record.

[0225] In some embodiments, the operation method further includes: determining that the second physical address of the target entry record is correct based on the matching of the address information in the second metadata with the first physical address.

[0226] In some embodiments, the address information in the second metadata includes the start bit of the physical address where the user data is stored and the end bit of the physical address where the user data is stored.

[0227] In some embodiments, the storage units of the first storage region are configured to store M bits of data, and the storage units of the second storage region are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M.

[0228] In some embodiments, the operation method further includes: obtaining user data stored in the first storage area from a memory device; if the error correction code verification fails based on the obtained user data, sending a read instruction including a second physical address to the memory device; wherein the read instruction indicates reading verification data stored in the second storage area; and performing a redundancy array verification on the user data using the read verification data.

[0229] The operation methods mentioned in the above embodiments have been described in detail in the foregoing embodiments concerning the storage system, and will not be repeated here for the sake of brevity.

[0230] Next, combine 13 to... Figure 16 as well as Figure 21A and Figure 21B The process of writing user data and verification data into the first storage area and the second storage area, respectively, is further described.

[0231] In some embodiments, a redundancy array encoding operation is performed on the received user data to generate check data, and then a first physical address for storing the user data is allocated. Specifically, such as... Figure 21A As shown, a new superblock SPB1 is allocated for user data in the first storage area, with a corresponding Id of y.

[0232] Allocate a blank entry from the mapping table for the newly allocated superblock SPB1, such as... Figure 21B The blank entries shown are the entries corresponding to Id:m.

[0233] A second physical address is allocated for the verification data in the second storage area, and the second physical address is recorded in a blank entry in the mapping table. For example, as shown... Figure 16 As shown, the information recorded in the mapping table related to the second physical address includes at least the die ID and the block ID.

[0234] In some implementations, when the verification data is stored in Figure 14 When a superblock is formed by two storage blocks with the same number in the second storage region shown, the information recorded in the mapping table related to the second physical address includes at least: die ID, raid stripe start ID, raid stripe end ID, and block ID.

[0235] Send the first write command to write user data to superblock SPB1 and update the first metadata.

[0236] Send a second write instruction to write verification data to the second storage block of the second storage area, and update the start bit of the physical address of the user data and the end bit of the physical address of the user data to the second metadata.

[0237] Figure 22 This is a schematic diagram of a data reading process provided in an embodiment of this application.

[0238] refer to Figure 22 In step S201, the memory controller receives a read command from the host.

[0239] Execute step S201 to determine whether the data is in the cache.

[0240] If the judgment result of step S201 is "yes", the memory controller obtains data from the cache and executes step S207 to send the obtained data to the host.

[0241] If the judgment result of step S201 is "no", then step S203 is executed to read data from the memory device.

[0242] If a read error occurs during the process of retrieving target data from memory, an error correction code engine is used to correct the read data.

[0243] Execute step S204 to determine whether ECC error correction was successful.

[0244] If ECC error correction is successful, the decoded correct data will be sent to the host.

[0245] If ECC error correction fails, proceed to step S205 to perform RAID verification on the erroneous data. If the RAID verification succeeds, proceed to step S207. If the RAID verification fails, proceed to step S206, deeming the read operation a failure, and report this status to the host.

[0246] For example, combined Figure 14 As shown, the steps for performing RAID verification include: failing to perform ECC error correction based on the user data in the first storage block 0 of the first die 0 in the acquired Stripe 0; sending a read instruction including a second physical address to the memory device to obtain the verification data stored in the second storage area; sending a first read instruction including a first physical address to the memory device to obtain other user data stored in the Stripe 0 of the first storage area; and recovering the user data in the first storage block 0 of the first die 0 in the Stripe 0 based on the verification data and the other user data stored in the Stripe 0 of the first storage area.

[0247] It should be noted that the verification data, the first verification data, and the second verification data involved in the embodiments of this application are used to perform RAID verification in step S205.

[0248] Fifthly, embodiments of this application provide a storage medium storing executable instructions, which, when executed by a processor, implement the operation method as described in any of the foregoing embodiments.

[0249] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0250] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0251] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0252] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located in one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0253] Figure 23This is a block diagram of a storage medium provided in one embodiment of this application. This application provides a storage medium 2000 storing executable instructions 2001. When executed by a processor, the executable instructions 2001 can implement the operation method of the storage system as described above. The operation method includes: performing a redundancy array encoding operation on received user data to generate check data; allocating a first physical address for storing the user data; wherein the first physical address points to a first storage area among multiple storage areas of the memory device; allocating a second physical address for storing the check data, and recording the second physical address; wherein the second physical address points to a second storage area among the multiple storage areas that is different from the first storage area; sending a first write instruction including the first physical address to the memory device; wherein the first write instruction instructs the user data to be written to the first storage area; sending a second write instruction including the second physical address and different from the first write instruction to the memory device; wherein the second write instruction instructs the check data to be written to the second storage area. The features disclosed in the several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0254] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0255] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

Claims

1. A storage system, characterized in that, include: A memory controller and a memory device coupled to the memory controller, the memory device including multiple memory regions; The memory controller is configured to: Perform redundancy array encoding on the received user data to generate check data; Allocate a first physical address for storing the user data; wherein the first physical address points to a first storage area among the plurality of storage areas; Allocate a second physical address for storing the verification data, and record the second physical address; wherein the second physical address points to a second storage area in the plurality of storage areas that is different from the first storage area; Send a first write instruction, including the first physical address, to the memory device; wherein the first write instruction instructs the user data to be written to the first storage area; Send a second write instruction, which includes the second physical address and is different from the first write instruction, to the memory device; wherein the second write instruction instructs the verification data to be written to the second storage area.

2. The storage system according to claim 1, characterized in that, The first storage region includes a plurality of first dies, and each first die includes a plurality of first storage blocks; wherein, the plurality of first storage blocks within different first dies constitute a superblock; the memory controller is specifically configured to: Based on the managed superblocks, the first physical address is allocated, wherein the first physical address points to a target superblock among the multiple superblocks.

3. The storage system according to claim 2, characterized in that, The second storage region includes at least one second die, and the second die includes a plurality of second storage blocks; the memory controller is further specifically configured to: Based on the managed plurality of second storage blocks, a second physical address is allocated, wherein the second physical address points to a target second storage block among the plurality of second storage blocks.

4. The storage system according to claim 3, characterized in that, The memory controller is also configured to: Manage multiple superblocks and multiple second storage blocks.

5. The storage system according to claim 2, characterized in that, The memory controller is also configured to: Obtain first metadata related to the user data from the memory device; wherein the first metadata includes index information related to the verification data; Based on the index information, a mapping table is searched to determine the second physical address where the verification data is stored; wherein, the mapping table includes the mapping relationship between the index information and the second physical address.

6. The storage system according to claim 5, characterized in that, The mapping table includes multiple entries, each entry recording the second physical address corresponding to one of the index information; the memory controller is specifically configured to: Based on the index information, the mapping table is searched to determine the target entry among the multiple entries; Based on the target entry, determine the second physical address where the verification data is stored.

7. The storage system according to claim 6, characterized in that, The superblock includes at least one stripe, and the first physical address specifically points to a target stripe among the multiple stripes of the target superblock, the target stripe being used to store the user data; the memory controller is specifically configured to: Based on the first identifier in the index information, a corresponding second identifier in the index information is determined; wherein, the first identifier is used to indicate the position of the target strip, and the second identifier is used to indicate the position of the target entry; The target entry is obtained based on the second identifier.

8. The storage system according to claim 6, characterized in that, The memory controller is specifically configured as follows: Assign blank entries from the plurality of entries, and record the second physical address into the blank entries.

9. The storage system according to claim 6, characterized in that, The memory controller is also configured to: Obtain second metadata related to the verification data from the memory device; wherein the second metadata includes address information related to the user data; Based on the mismatch between the address information in the second metadata and the first physical address, it is determined that the second physical address of the target entry record is incorrect; The target entry is reconstructed based on the error in the second physical address recorded in the target entry.

10. The storage system according to claim 9, characterized in that, The memory controller is also configured to: Based on the matching of the address information in the second metadata with the first physical address, it is determined that the second physical address of the target entry record is correct.

11. The storage system according to claim 9, characterized in that, The address information in the second metadata includes the start bit of the physical address where the user data is stored and the end bit of the physical address where the user data is stored.

12. The storage system according to claim 1, characterized in that, The storage units in the first storage area and the storage units in the second storage area are configured with different storage modes.

13. The storage system according to claim 12, characterized in that, The storage units of the first storage area are configured to store M bits of data, and the storage units of the second storage area are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M.

14. The storage system according to claim 1, characterized in that, The memory controller is also configured to: The user data stored in the first storage area is obtained from the memory device; If the error correction code verification fails based on the acquired user data, a read instruction including the second physical address is sent to the memory device; wherein, the read instruction indicates that the verification data stored in the second storage area is read. The read verification data is used to perform a redundancy array check on the user data.

15. The storage system according to claim 1, characterized in that, The storage system includes solid-state drives, general-purpose flash memory, or embedded multimedia cards.

16. A storage system, characterized in that, include: A memory controller and a memory device coupled to the memory controller, the memory device including a plurality of dies divided into a plurality of memory regions; The memory controller is configured to: Based on the existence of at least one faulty storage block in the first storage area of ​​the plurality of storage areas, a portion of the user data stored in the faulty storage block in the first storage area is migrated to the target storage block in the first storage area; Based on the migration of the aforementioned portion of user data to the target storage block within the first storage area, the first physical address storing the user data is updated; wherein, the first physical address points to the first storage area; The redundant array encoding operation is re-executed on the portion of user data of the target storage block migrated to the first storage area and the remaining user data that has not been migrated in the first storage area to generate the first verification data; Allocate a third physical address for storing the first verification data, and record the third physical address; wherein the third physical address points to a second storage area in the plurality of storage areas that is different from the first storage area; Send a third write instruction, including the third physical address, to the memory device; wherein the third write instruction instructs the first verification data to be written to the second storage area.

17. The storage system according to claim 16, characterized in that, The memory controller is also configured to: Based on the existence of at least one faulty storage block in the second storage area, the redundant array encoding operation is re-executed on the user data stored in the first storage area to generate second verification data; Allocate a fourth physical address for storing the second verification data, and record the fourth physical address; wherein the fourth physical address points to the target storage block within the second storage area; Send a fourth write instruction, including the fourth physical address, to the memory device; wherein the fourth write instruction instructs the second verification data to be written to a target storage block within the second storage area.

18. The storage system according to claim 17, characterized in that, The first storage region includes a plurality of first dies, and each first die includes a plurality of first storage blocks; wherein, the plurality of first storage blocks within different first dies constitute a superblock; the memory controller is specifically configured to: allocate a first physical address based on the plurality of superblocks under management, wherein the first physical address points to a target superblock among the plurality of superblocks.

19. The storage system according to claim 18, characterized in that, The second storage region includes at least one second die, and the second die includes a plurality of second storage blocks; the memory controller is further specifically configured to: Based on the managed multiple second storage blocks, the fourth physical address is allocated, wherein the fourth physical address points to the target second storage block within the target second die.

20. The storage system according to claim 19, characterized in that, The memory controller is also configured to: Manage multiple superblocks and multiple second storage blocks.

21. The storage system according to claim 18, characterized in that, The memory controller is also configured to: Obtain third metadata related to the user data from the memory device; wherein the third metadata includes index information related to the first verification data; Based on the index information, a mapping table is searched to determine the third physical address where the first verification data is stored; wherein, the mapping table includes the mapping relationship between the index information and the third physical address.

22. The storage system according to claim 21, characterized in that, The mapping table includes multiple entries, each entry recording the third physical address corresponding to one of the index information; the memory controller is further specifically configured to: Based on the index information, the mapping table is searched to determine the target entry among the multiple entries; Based on the target entry, determine the third physical address where the first verification data is stored.

23. The storage system according to claim 22, characterized in that, The superblock includes at least one stripe, and the updated first physical address specifically points to a target stripe among the multiple stripes of the target superblock, the target stripe being used to store the user data; the memory controller is specifically configured to: Based on the first identifier in the index information, a corresponding second identifier in the index information is determined; wherein, the first identifier is used to indicate the position of the target strip, and the second identifier is used to indicate the position of the target entry; The target entry is obtained based on the second identifier.

24. The storage system according to claim 22, characterized in that, The memory controller is also configured to: Assign blank entries from the plurality of entries, and record the third physical address into the blank entries.

25. The storage system according to claim 22, characterized in that, The memory controller is also configured to: Obtain fourth metadata related to the first verification data from the memory device; wherein the fourth metadata includes address information related to the user data; Based on the mismatch between the address information in the fourth metadata and the updated first physical address, it is determined that the third physical address of the target entry record is incorrect; The target entry is reconstructed based on an error in the third physical address recorded in the target entry.

26. The storage system according to claim 25, characterized in that, The memory controller is also configured to: Based on the address information in the fourth metadata and the new first physical address, it is determined that the third physical address of the target entry record is correct.

27. The storage system according to claim 25, characterized in that, The address information in the fourth metadata includes the start bit of the physical address where the user data is stored and the end bit of the physical address where the user data is stored.

28. The storage system according to claim 17, characterized in that, The storage units in the first storage area and the storage units in the second storage area are configured with different storage modes.

29. The storage system according to claim 28, characterized in that, The storage units of the first storage area are configured to store M bits of data, and the storage units of the second storage area are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M.

30. The storage system according to claim 17, characterized in that, The memory controller is configured to: Based on the presence of at least one of the memory blocks among the plurality of dies, the storage region where the faulty memory block is located is determined.

31. The storage system according to claim 30, characterized in that, The memory controller is configured to: Based on the fact that the number of fault storage blocks in at least one of the plurality of dies is greater than a preset threshold, at least one of the dies is determined to be a faulty die.

32. The storage system according to claim 16, characterized in that, The memory controller is also configured to: The user data stored in the first storage area is obtained from the memory device; If the error correction code verification fails based on the acquired user data, a read instruction including the third physical address is sent to the memory device; wherein, the read instruction indicates reading the first verification data stored in the second storage area; The user data is subjected to a redundancy array check using the first verification data read.

33. The storage system according to claim 16, characterized in that, The storage system includes solid-state drives, general-purpose flash memory, or embedded multimedia cards.

34. A memory controller, characterized in that, The memory controller is coupled to a memory device, the memory device including multiple memory regions; the memory controller includes: cache, and Processor, the processor being configured to: Perform redundancy array encoding on the received user data to generate check data; Allocate a first physical address for storing the user data; wherein the first physical address points to a first storage area among the plurality of storage areas; Allocate a second physical address for storing the verification data, and record the second physical address; wherein the second physical address points to a second storage area in the plurality of storage areas that is different from the first storage area; Send a first write instruction, including the first physical address, to the memory device; wherein the first write instruction instructs the user data to be written to the first storage area; Send a second write instruction, which includes the second physical address and is different from the first write instruction, to the memory device; wherein the second write instruction instructs the verification data to be written to the second storage area.

35. The memory controller according to claim 34, characterized in that, The first storage region includes a plurality of first dies, and each first die includes a plurality of first storage blocks; wherein, the plurality of first storage blocks within different first dies constitute a superblock; the processor is specifically configured as follows: Based on the managed superblocks, the first physical address is allocated, wherein the first physical address points to a target superblock among the multiple superblocks.

36. The memory controller according to claim 35, characterized in that, The second storage region includes at least one second die, and the second die includes a plurality of second storage blocks; The processor is further configured to: allocate a second physical address based on a plurality of managed second storage blocks, wherein the second physical address points to a target second storage block among the plurality of second storage blocks.

37. The memory controller according to claim 36, characterized in that, The processor is configured to manage multiple superblocks and multiple second storage blocks.

38. The memory controller according to claim 35, characterized in that, The processor is also configured to: Obtain first metadata related to the user data from the memory device; wherein the first metadata includes index information related to the verification data; Based on the index information, a mapping table is searched to determine the second physical address where the verification data is stored; wherein, the mapping table includes the mapping relationship between the index information and the second physical address.

39. The memory controller according to claim 38, characterized in that, The mapping table includes multiple entries, each entry recording the second physical address corresponding to one of the index information; the processor is specifically configured to: Based on the index information, the mapping table is searched to determine the target entry among the multiple entries; Based on the target entry, determine the second physical address where the verification data is stored.

40. The memory controller according to claim 39, characterized in that, The superblock includes at least one stripe, and the first physical address specifically points to a target stripe among the multiple stripes of the target superblock, the target stripe being used to store the user data; the processor is specifically configured to: Based on the first identifier in the index information, a corresponding second identifier in the index information is determined; wherein, the first identifier is used to indicate the position of the target strip, and the second identifier is used to indicate the position of the target entry; The target entry is obtained based on the second identifier.

41. The memory controller according to claim 39, characterized in that, The processor is specifically configured as follows: Assign blank entries from the plurality of entries, and record the second physical address into the blank entries.

42. The memory controller according to claim 39, characterized in that, The processor is also configured to: Obtain second metadata related to the verification data from the memory device; wherein the second metadata includes address information related to the user data; Based on the mismatch between the address information in the second metadata and the first physical address, it is determined that the second physical address of the target entry record is incorrect; The target entry is reconstructed based on the error in the second physical address recorded in the target entry.

43. The memory controller according to claim 42, characterized in that, The processor is also configured to: Based on the matching of the address information in the second metadata with the first physical address, it is determined that the second physical address of the target entry record is correct.

44. The memory controller according to claim 42, characterized in that, The address information in the second metadata includes the start bit of the physical address where the user data is stored and the end bit of the physical address where the user data is stored.

45. The memory controller according to claim 34, characterized in that, The storage units in the first storage area and the storage units in the second storage area are configured with different storage modes.

46. ​​The memory controller according to claim 45, characterized in that, The storage units of the first storage area are configured to store M bits of data, and the storage units of the second storage area are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M.

47. The memory controller according to claim 34, characterized in that, The processor is also configured to: The user data stored in the first storage area is obtained from the memory device; If the error correction code verification fails based on the acquired user data, a read instruction including the second physical address is sent to the memory device; wherein, the read instruction indicates that the verification data stored in the second storage area is read. The read verification data is used to perform a redundancy array check on the user data.

48. A method for operating a storage system, characterized in that, include: Perform redundancy array encoding on the received user data to generate check data; Allocate a first physical address for storing the user data; wherein the first physical address points to a first storage area among multiple storage areas of the memory device in the storage system; Allocate a second physical address for storing the verification data, and record the second physical address; wherein the second physical address points to a second storage area in the plurality of storage areas that is different from the first storage area; Send a first write instruction, including the first physical address, to the memory device; wherein the first write instruction instructs the user data to be written to the first storage area; Send a second write instruction, which includes the second physical address and is different from the first write instruction, to the memory device; wherein the second write instruction instructs the verification data to be written to the second storage area.

49. The operating method according to claim 48, characterized in that, The first storage area includes multiple first dies, and each first die includes multiple first storage blocks; wherein, multiple first storage blocks within different first dies constitute a superblock; the allocation of the first physical address for storing the user data includes: Based on the managed superblocks, the first physical address is allocated, wherein the first physical address points to a target superblock among the multiple superblocks.

50. The operating method according to claim 49, characterized in that, The second storage region includes at least one second die, and the second die includes a plurality of second storage blocks; The allocation of the second physical address for storing the verification data includes: Based on the managed plurality of second storage blocks, a second physical address is allocated, wherein the second physical address points to a target second storage block among the plurality of second storage blocks.

51. The operating method according to claim 49, characterized in that, The operation method further includes: Obtain first metadata related to the user data from the memory device; wherein the first metadata includes index information related to the verification data; Based on the index information, a mapping table is searched to determine the second physical address where the verification data is stored; wherein, the mapping table includes the mapping relationship between the index information and the second physical address.

52. The operating method according to claim 51, characterized in that, The mapping table includes multiple entries, and each entry records the second physical address corresponding to one of the index information; the step of searching the mapping table based on the index information to determine the second physical address storing the verification data includes: Based on the index information, the mapping table is searched to determine the target entry among the multiple entries; Based on the target entry, determine the second physical address where the verification data is stored.

53. The operating method according to claim 51, characterized in that, The superblock includes at least one stripe, and the first physical address specifically points to a target stripe among multiple stripes of the target superblock. The target stripe is used to store the user data. The step of searching the mapping table based on the index information to determine the target entry among the multiple entries includes: Based on the first identifier in the index information, a corresponding second identifier in the index information is determined; wherein, the first identifier is used to indicate the position of the target strip, and the second identifier is used to indicate the position of the target entry; The target entry is obtained based on the second identifier.

54. The operating method according to claim 52, characterized in that, The record of the second physical address includes: Assign blank entries from the plurality of entries, and record the second physical address into the blank entries.

55. The operating method according to claim 52, characterized in that, The operation method further includes: Obtain second metadata related to the verification data from the memory device; wherein the second metadata includes address information related to the user data; Based on the mismatch between the address information in the second metadata and the first physical address, it is determined that the second physical address of the target entry record is incorrect; The target entry is reconstructed based on the error in the second physical address recorded in the target entry.

56. The operating method according to claim 55, characterized in that, The operation method further includes: Based on the matching of the address information in the second metadata with the first physical address, it is determined that the second physical address of the target entry record is correct.

57. The operating method according to claim 55, characterized in that, The address information in the second metadata includes the start bit of the physical address where the user data is stored and the end bit of the physical address where the user data is stored.

58. The operating method according to claim 48, characterized in that, The storage units of the first storage area are configured to store M bits of data, and the storage units of the second storage area are configured to store N bits of data; wherein M and N are both integers greater than 1, and N is less than M.

59. The operating method according to claim 48, characterized in that, The operation method further includes: The user data stored in the first storage area is obtained from the memory device; If the error correction code verification fails based on the acquired user data, a read instruction including the second physical address is sent to the memory device; wherein, the read instruction indicates that the verification data stored in the second storage area is read. The read verification data is used to perform a redundancy array check on the user data.

60. A storage medium, characterized in that, The storage medium stores executable instructions, which, when executed by a processor, implement the operation method as described in any one of claims 48 to 59.

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