Memory, memory programming methods and storage systems

Abstract

This disclosure provides a memory, a method for programming the memory, and a memory system. The memory includes: a memory cell array; word lines coupled to memory cells in the memory cell array; and peripheral circuitry, which is coupled to the memory cell array via the word lines and configured to: perform a programming operation on selected memory cells using a step-pulse voltage method; during the programming operation, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibits a trend of first decreasing and then increasing.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a memory, a memory programming method, and a memory system. Background Technology

[0002] 3D memory typically consists of multiple memory cells arranged in an array. When programming (writing data) a selected memory cell, an Increment Step Pulse Program (ISPP) method is usually used.

[0003] The rate of change of the threshold voltage of the memory cell varies at different programming stages. However, the pulse width and incremental voltage of each pulse stage in ISPP are fixed, which leads to a large difference in the read margin of the memory cell at different programming stages. The read margin is small between some programming states, which can easily cause read errors. Summary of the Invention

[0004] In view of the above, embodiments of this disclosure provide a memory, a method for programming the memory, and a memory system. The memory includes: a memory cell array; word lines coupled to memory cells in the memory cell array; and peripheral circuitry, the peripheral circuitry being coupled to the memory cell array via the word lines and configured to: perform a programming operation on selected memory cells using a step-pulse voltage method; during the programming operation, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibits a trend of first decreasing and then increasing.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a memory, including: a memory cell array; word lines coupled to memory cells in the memory cell array; and peripheral circuitry, the peripheral circuitry being coupled to the memory cell array via the word lines and configured to: perform a programming operation on selected memory cells using a step-pulse voltage method; during the programming operation, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibits a trend of first decreasing and then increasing.

[0007] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; the peripheral circuit is configured to: apply a programming pulse with a first pulse width to the selected word line in the first programming stage; apply a programming pulse with a second pulse width to the selected word line in the second programming stage; and apply a programming pulse with a third pulse width to the selected word line in the third programming stage; wherein the second pulse width is less than the first pulse width, and the second pulse width is less than the third pulse width.

[0008] In some embodiments, the peripheral circuit is further configured to: after applying the i-th programming pulse to the selected word line, perform programming verification on the selected memory cell, and determine the pulse width of the (i+1)-th programming pulse based on the verification result, where i is a positive integer.

[0009] In some embodiments, the peripheral circuit is specifically configured to: verify the selected memory cell in a first intermediate programming state; in response to the selected memory cell failing verification, determine the pulse width of the (i+1)th programming pulse as a first pulse width; and in response to the selected memory cell passing verification, determine the pulse width of the (i+1)th programming pulse as a second pulse width.

[0010] In some embodiments, the peripheral circuit is further configured to: verify the selected memory cell in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state; determine the pulse width of the (i+1)th programming pulse as a second pulse width in response to the selected memory cell failing verification; and determine the pulse width of the (i+1)th programming pulse as a third pulse width in response to the selected memory cell passing verification.

[0011] In some embodiments, the first pulse width, the second pulse width, and the third pulse width are fixed pulse widths.

[0012] In some embodiments, the programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage; the peripheral circuit is specifically configured such that: in the first programming stage, the pulse width of the programming pulse applied to the selected word line exhibits a decreasing trend; and in the second programming stage, the pulse width of the programming pulse applied to the selected word line exhibits an increasing trend.

[0013] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; the peripheral circuit is configured to: apply a programming pulse with a first incremental voltage to the selected word line in the first programming stage; apply a programming pulse with a second incremental voltage to the selected word line in the second programming stage; and apply a programming pulse with a third incremental voltage to the selected word line in the third programming stage; wherein the second incremental voltage is less than the first incremental voltage, and the second incremental voltage is less than the third incremental voltage.

[0014] In some embodiments, the peripheral circuit is further configured to: after applying the i-th programming pulse to the selected word line, perform programming verification on the selected memory cell, and determine the incremental voltage of the (i+1)-th programming pulse compared to the i-th programming pulse based on the verification result, where i is a positive integer.

[0015] In some embodiments, the peripheral circuit is specifically configured to: verify the selected memory cell in a first intermediate programming state; in response to the selected memory cell failing verification, determine the incremental voltage of the (i+1)th programming pulse compared to the i-th programming pulse as a first incremental voltage; and in response to the selected memory cell passing verification, determine the incremental voltage of the (i+1)th programming pulse compared to the i-th programming pulse as a second incremental voltage.

[0016] In some embodiments, the peripheral circuitry is further configured to: verify the selected memory cell in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state; in response to the selected memory cell failing verification, determine the incremental voltage of the (i+1)th programming pulse relative to the i-th programming pulse as a second incremental voltage; and in response to the selected memory cell passing verification, determine the incremental voltage of the (i+1)th programming pulse relative to the i-th programming pulse as a third incremental voltage.

[0017] In some embodiments, the first incremental voltage, the second incremental voltage, and the third incremental voltage are fixed incremental voltages.

[0018] In some embodiments, the programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage; the peripheral circuit is specifically configured such that: in the first programming stage, the incremental voltage of the programming pulse applied to the selected word line exhibits a decreasing trend; and in the second programming stage, the incremental voltage of the programming pulse applied to the selected word line exhibits an increasing trend.

[0019] In some embodiments, the memory is a ferroelectric memory.

[0020] Secondly, embodiments of this disclosure provide a method for programming a memory, the method comprising: performing a programming operation on a selected memory cell using a step-pulse voltage method; during the programming operation, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibits a trend of first decreasing and then increasing.

[0021] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; in the first programming stage, a programming pulse with a first pulse width is applied to the selected word line; in the second programming stage, a programming pulse with a second pulse width is applied to the selected word line; and in the third programming stage, a programming pulse with a third pulse width is applied to the selected word line; wherein the second pulse width is less than the first pulse width, and the second pulse width is less than the third pulse width.

[0022] In some embodiments, the method further includes: after applying the i-th programming pulse to the selected word line, performing programming verification on the selected memory cell, and determining the pulse width of the (i+1)-th programming pulse based on the verification result, where i is a positive integer.

[0023] In some embodiments, determining the pulse width of the (i+1)th programming pulse based on the verification result includes: verifying the selected memory cell in a first intermediate programming state; determining the pulse width of the (i+1)th programming pulse as a first pulse width in response to the selected memory cell's programming state failing verification; and determining the pulse width of the (i+1)th programming pulse as a second pulse width in response to the selected memory cell's programming state passing verification.

[0024] In some embodiments, determining the pulse width of the (i+1)th programming pulse based on the verification result further includes: verifying the selected memory cell in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state; determining the pulse width of the (i+1)th programming pulse as a second pulse width in response to the selected memory cell's programming state failing verification; and determining the pulse width of the (i+1)th programming pulse as a third pulse width in response to the selected memory cell's programming state passing verification.

[0025] In some embodiments, the first pulse width, the second pulse width, and the third pulse width are fixed pulse widths.

[0026] In some embodiments, the programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage; in the first programming stage, the pulse width of the programming pulse applied to the selected word line exhibits a decreasing trend; and in the second programming stage, the pulse width of the programming pulse applied to the selected word line exhibits an increasing trend.

[0027] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; in the first programming stage, a programming pulse having a first incremental voltage is applied to the selected word line; in the second programming stage, a programming pulse having a second incremental voltage is applied to the selected word line; in the third programming stage, a programming pulse having a third incremental voltage is applied to the selected word line; wherein the second incremental voltage is less than the first incremental voltage, and the second incremental voltage is less than the third incremental voltage.

[0028] In some embodiments, the method further includes: after applying the i-th programming pulse to the selected word line, performing programming verification on the selected memory cell, and determining the incremental voltage of the (i+1)-th programming pulse compared to the i-th programming pulse based on the verification result, where i is a positive integer.

[0029] In some embodiments, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse based on the verification result includes: verifying the selected memory cell in a first intermediate programming state; determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a first incremental voltage in response to the selected memory cell's programming state failing verification; and determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a second incremental voltage in response to the selected memory cell's programming state passing verification.

[0030] In some embodiments, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse based on the verification result further includes: verifying the selected memory cell in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state; in response to the selected memory cell's programming state failing verification, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a second incremental voltage; and in response to the selected memory cell's programming state passing verification, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a third incremental voltage.

[0031] In some embodiments, the first incremental voltage, the second incremental voltage, and the third incremental voltage are fixed incremental voltages.

[0032] In some embodiments, the programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage; in the first programming stage, the incremental voltage of the programming pulse applied to the selected word line exhibits a decreasing trend; and in the second programming stage, the incremental voltage of the programming pulse applied to the selected word line exhibits an increasing trend.

[0033] In some embodiments, the memory is a ferroelectric memory.

[0034] Thirdly, embodiments of this disclosure provide a storage system, including: a memory as described in any of the above embodiments; and a storage controller coupled to the memory, the storage controller being configured to control the memory.

[0035] This disclosure provides a memory, a method for programming the memory, and a memory system. The memory includes: a memory cell array; word lines coupled to memory cells in the memory cell array; and peripheral circuitry, which is coupled to the memory cell array via the word lines and configured to: perform a programming operation on selected memory cells using a step-pulse voltage method; during the programming operation, the pulse width and / or the increment voltage of the programming pulse applied to the selected word line exhibits a trend of first decreasing and then increasing. In the memory provided by this disclosure, the peripheral circuitry is configured such that during the programming operation, the pulse width and / or increment voltage of the programming pulse applied to the selected word line can exhibit a trend of first increasing and then decreasing. Thus, the memory cells have a larger threshold voltage change rate in the early and late stages of the programming operation, and a smaller threshold voltage change rate in the middle stage of the programming operation. Therefore, the memory has a larger read margin and higher programming efficiency in the early and late stages of the programming operation, while having a larger read margin in the middle stage of the programming operation, reducing the possibility of read operation misjudgment and improving the accuracy of the read operation. Furthermore, the difference in read margin between multiple programming states is small, significantly improving the reliability of the memory. Attached Figure Description

[0036] Figure 1A A schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0037] Figure 1B A schematic diagram of programming pulses for a first programming method provided in this embodiment of the present disclosure;

[0038] Figure 1C A schematic diagram illustrating the variation characteristics of the threshold voltage-programming voltage of a memory cell in an embodiment of this disclosure;

[0039] Figure 1DA threshold voltage distribution diagram of the memory cells obtained after the memory provided in the embodiments of this disclosure is programmed using the first programming method;

[0040] Figure 2 A schematic diagram of programming pulses for the second programming method provided in this embodiment of the present disclosure;

[0041] Figure 3 A comparison diagram of the threshold voltage distribution of memory cells obtained by programming the memory provided in the embodiments of this disclosure using the second programming method and the first programming method;

[0042] Figure 4 A schematic diagram of programming pulses for the third programming method provided in this embodiment of the disclosure;

[0043] Figure 5 A comparison diagram of the threshold voltage distribution of memory cells obtained by programming the memory provided in the embodiments of this disclosure using the third programming method and the first programming method;

[0044] Figure 6 A schematic diagram of programming pulses for the fourth programming method provided in this embodiment of the disclosure;

[0045] Figure 7 A comparison diagram of the threshold voltage distribution of memory cells obtained by programming the memory provided in the embodiments of this disclosure using the fourth programming method and the first programming method;

[0046] Figure 8 A schematic diagram of programming pulses for the fifth programming method provided in this embodiment of the disclosure;

[0047] Figure 9 A comparison diagram of the threshold voltage distribution of memory cells obtained by programming the memory provided in the embodiments of this disclosure using the fifth programming method and the first programming method;

[0048] Figure 10 A partial structural schematic diagram of a ferroelectric memory cell string provided in an embodiment of this disclosure;

[0049] Figure 11 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present disclosure. Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0054] Figure 1A This is a schematic diagram of a memory structure provided in an embodiment of this disclosure. See also... Figure 1A The memory 100 includes a memory cell array 110, a word line WL, and peripheral circuitry 120 coupled to the memory cell array 110 via the word line WL.

[0055] The memory cell array 110 may include multiple memory cell strings 112, each of which may include a bottom select transistor (BST), multiple memory cells 113, and a top select transistor (TST) connected in series. Furthermore, the memory cells involved in this embodiment may be multi-level cells (MLCs) capable of storing at least 2 bits of data. For example, if each memory cell can store 2 bits of data, then the memory cell includes three different programming states and one erase state; if each memory cell can store 3 bits of data, then the memory cell includes seven different programming states and one erase state.

[0056] like Figure 1AAs shown, a row of memory cells 113 arranged in the horizontal direction can be coupled to the same word line WL, a row of top select transistors TST arranged in the horizontal direction can be coupled to the same top select line TSL, a row of bottom select transistors BST arranged in the horizontal direction can be coupled to the same bottom select line BSL, and the drain of the top select transistor TST of each memory cell string 112 is coupled to the corresponding bit line BL.

[0057] Multiple memory cell strings 112 can be constructed as multiple memory blocks 111, with the source of the bottom selection transistor BST of the memory cell strings 112 located in the same memory block 111 being coupled to the same source line SL.

[0058] In this embodiment, peripheral circuitry 120 can be coupled to memory cell array 110 via word line WL, bit line BL, source line SL, top select line TSL, and bottom select line BSL. Here, peripheral circuitry 120 can include any suitable analog signal circuitry, digital signal circuitry, and mixed signal circuitry to facilitate operation of the memory cell array (e.g., read operation, program operation, and disable operation) by applying voltage and / or current signals to each selected memory cell via WL, BL, SL, TSL, and BSL, and sensing voltage and / or current signals from each selected memory cell. Furthermore, peripheral circuitry 120 can also include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0059] Figure 1B A schematic diagram of programming pulses for a first programming method provided in this embodiment of the disclosure. See also... Figure 1B During the programming operation, the peripheral circuit applies an initial voltage to the selected word line coupled to the selected memory cell in the first pulse phase. Then, a verification voltage Vv is applied to the selected word line to verify whether the selected memory cell has reached the target programming state. If not, an incremental voltage Step0 is added to the initial voltage to obtain a second pulse voltage. In the second pulse phase, the second pulse voltage is applied to the selected word line corresponding to the selected memory cell, and the verification of whether the selected memory cell has reached the target programming state continues. This process is repeated until the pulse voltage applied to the selected word line reaches the required programming voltage, at which point programming stops. It should be noted that in the first programming method, the pulse width W0 of each programming pulse is the same, the incremental voltage Step0 is also the same, and the verification voltage Vv can be the verification voltage corresponding to the target programming state (e.g., state 1). Furthermore, the number of programming pulses in the first programming method is not limited to a single value. Figure 1B The number of programming pulses shown.

[0060] Figure 1C A schematic diagram illustrating the threshold voltage-programming voltage variation characteristics of a memory cell in an embodiment of this disclosure. See also... Figure 1C A programming voltage Vpgm is applied to the selected word line coupled to the selected memory cell. As the programming voltage Vpgm increases, the threshold voltage Vth (amplitude) of the selected memory cell also increases. However, from... Figure 1C As can be seen, with the increase of the programming voltage Vpgm, the rate of change of the threshold voltage Vth of the selected memory cell goes from slow to fast and then back to slow. Specifically, in stages ① and ③, the rate of change of the threshold voltage of the selected memory cell is relatively small; in stage ②, the rate of change of the threshold voltage of the selected memory cell is relatively large. Therefore, when programming the selected memory cell using the ISPP method with a fixed pulse width and a fixed incremental voltage, the threshold voltage distribution of the programming states that the memory cell can reach is narrow in the early and late stages of the programming operation, and wider in the middle stage. The read margin RM between some programming states is large, while the read margin RM between other programming states is small, and the difference in read margin RM between multiple programming states is large. Programming states with small read margins are prone to read errors. It should be noted that... Figure 1C The threshold voltage Vth is negative, representing only the relative magnitude of the threshold voltage Vth to the reference voltage of the source line connected to that memory cell. It should be noted that the aforementioned programming operation refers to the initial stage... Figure 1C The first stage shown, the middle stage of programming operation, refers to... Figure 1C The second stage shown, the later stage of programming operations, refers to... Figure 1C The third stage is shown.

[0061] Figure 1D The image shows the threshold voltage distribution of the memory cells obtained after programming the memory provided in this embodiment using the first programming method. It should be noted that... Figure 1D This explanation uses a Triple Level Cell (TLC) memory cell as an example, which includes seven programming states (states L1 to L7) and an erase state L0. See [link / reference] Figure 1D The threshold voltage distribution of L3, L4, and L5 is relatively wide. Therefore, compared with the read margin between L1 and L2, L2 and L3, and L6 and L7, the read margin between L3 and L4, L4 and L5, and L5 and L6 is smaller. In other words, read errors are more likely to occur between two adjacent programming states in L3 to L6, which affects the reliability of the memory.

[0062] In view of this, embodiments of this disclosure provide a memory capable of solving the above-mentioned problems. See also Figure 1AThe memory includes: a memory cell array 110; word lines WL coupled to memory cells in the memory cell array 110; and peripheral circuitry 120, which is coupled to the memory cell array 110 via word lines WL and configured to: perform a programming operation on selected memory cells using a step-pulse voltage method; during the programming operation, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibits a trend of first decreasing and then increasing.

[0063] In some embodiments, during programming operations, the pulse width and / or incremental voltage of the programming pulse applied to a selected word line may initially increase and then decrease. Thus, the memory cell maintains a larger threshold voltage change rate in the early and later stages of the programming operation, while exhibiting a smaller threshold voltage change rate in the middle of the programming operation (compared to...). Figure 1C (Stage ② in the programming process). Therefore, the memory has a large read margin and high programming efficiency in the early and late stages of programming operations, and a large read margin in the middle stage of programming operations, which reduces the possibility of read operation misjudgment and improves the accuracy of read operations. Moreover, the difference in read margin between multiple programming states is small, and the reliability of the memory is significantly improved.

[0064] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; the peripheral circuitry is configured to: apply a programming pulse with a first pulse width to a selected word line in the first programming stage; apply a programming pulse with a second pulse width to the selected word line in the second programming stage; and apply a programming pulse with a third pulse width to the selected word line in the third programming stage; wherein the second pulse width is less than the first pulse width, and the second pulse width is less than the third pulse width.

[0065] Figure 2 A schematic diagram of programming pulses for a second programming method provided in this embodiment of the disclosure. See also... Figure 2 The peripheral circuitry is configured to: apply a programming pulse with a first pulse width W11 to the selected word line in a first programming stage; apply a programming pulse with a second pulse width W12 to the selected word line in a second programming stage; and apply a programming pulse with a third pulse width W13 to the selected word line in a third programming stage, wherein W12 < W11 and W12 < W13. It should be noted that in this embodiment, the first pulse width and the third pulse width may be different or the same.

[0066] In some embodiments, such as Figure 2 In the programming operation shown, the incremental voltage of the programming pulses in the first, second, and third programming stages can be the same. It should be noted that... Figure 2In this context, Loop 1 represents the stage where a selected cell is programmed from the erase state to the first state. Loops 2 through 7 have similar meanings to Loop 1. Any one of Loops 1 through 7 can include several programming pulses. In this embodiment, the number of programming pulses during the programming operation is not limited to... Figure 2 The quantities shown. Additionally, the other figures in this disclosure refer to Loop1 to Loop7 and... Figure 2 Similar to that in [the text]. It should be noted that... Figure 2 The other figures show that Vv1 to Vv7 are the verification voltages of L1 to L7, respectively, and Vv1 < Vv2 < Vv3 < Vv4 < Vv5 < Vv6 < Vv7.

[0067] Figure 3 A comparison diagram of the threshold voltage distribution of memory cells obtained after programming the memory provided in the embodiments of this disclosure using the second programming method and the first programming method. It should be noted that... Figure 2 and Figure 3 This explanation uses a three-level storage unit, with W11 = W13 = W0, as an example. (See also...) Figure 2 and Figure 3 Since the programming pulse in the first programming stage has a first pulse width W11 and the programming pulse in the third programming stage has a third pulse width W13, and W11 = W13 = W0, the memory cells programmed using the second programming method and the first programming method can have basically the same threshold voltage change rate in the first programming stage and the third programming stage. Therefore, the threshold voltage distributions of L1, L2, L6 and L7 corresponding to the two programming methods are basically overlapping.

[0068] See also Figure 2 and Figure 3 Since the programming pulse in the second programming stage has a second pulse width W12, and W12 < W11 = W13 = W0, the memory cell programmed using the second programming method can have a smaller threshold voltage change rate compared to the memory cell programmed using the first programming method. Therefore, in the threshold voltage distribution diagram of the memory cell programmed using the second programming method, the threshold voltage distributions of L3 to L5 are compressed and narrowed in the opposite direction of the threshold voltage offset direction. That is, the threshold voltage distribution of L3 is compressed and narrowed in the direction closer to the threshold voltage distribution of L2, the threshold voltage distribution of L4 is compressed and narrowed in the direction closer to the threshold voltage distribution of L3, and the threshold voltage distribution of L5 is compressed and narrowed in the direction closer to the threshold voltage distribution of L4.

[0069] This increases the read margin between L3 and L4, between L4 and L5, and between L5 and L6, reduces the read margin difference between multiple programming states, and improves the accuracy of read operations and the reliability of the memory.

[0070] The memory provided in this embodiment has a large read margin and high programming efficiency in the first and third programming stages, and a large read margin in the second programming stage, which reduces the possibility of read operation misjudgment and improves the accuracy of read operation. Moreover, the difference in read margin between multiple programming states is small, and the reliability of the memory is significantly improved.

[0071] In some embodiments, the peripheral circuitry is further configured to: after applying the i-th programming pulse to the selected word line, perform programming verification on the selected memory cell, and determine the pulse width of the (i+1)-th programming pulse based on the verification result, where i is a positive integer.

[0072] In some embodiments, in stage ①, the selected memory cell can be progressively programmed to a first intermediate programming state; in stage ②, the selected memory cell can be progressively programmed to a second intermediate programming state; and in stage ③, the selected memory cell can be progressively programmed to a highest programming state. Therefore, the first programming stage may include the stage before the memory cell is programmed from the erase state to the first intermediate programming state, the second programming stage may include the stage before the memory cell is programmed from the first intermediate programming state to the second intermediate programming state, and the third programming stage may include the stage where the memory cell is programmed from the second intermediate programming state to the highest programming state. The threshold voltage of the first intermediate programming state is lower than the threshold voltage of the second intermediate programming state.

[0073] In one specific example, a first intermediate programming state and a second intermediate programming state can be set according to the threshold voltage distribution width of each programming state. If the threshold voltage distribution width of states k1+1 to k2 is greater than a preset width, then state k1 is set as the first intermediate programming state and state k2 is set as the second intermediate programming state. In another specific example, the first intermediate programming state and the second intermediate programming state can be set according to the read margin between adjacent programming states. If the read margin between any two adjacent programming states from state k1+1 to k2+1 is less than a preset read margin, then state k1 is set as the first intermediate programming state and state k2 is set as the second intermediate programming state. In one specific example, the secondary memory cell includes an erase state, state 1, state 2, and state 3. The first intermediate programming state can be, for example, state 1, and the second intermediate programming state can be, for example, state 2. In another specific example, the quaternary memory cell includes an erase state and states 1 to 15. The first intermediate programming state can be, for example, state 5, and the second intermediate programming state can be, for example, state 10.

[0074] In the following description, the first intermediate programming state is named state k1, the second intermediate programming state is named state k2, and the highest programming state of the memory unit is named state n. Here, k1, k2, and n are all positive integers, where n > k2 > k1. It should be noted that a memory unit can include an erase state and n programming states, where n+1 is an exponential relationship with 2.

[0075] In some embodiments, the peripheral circuitry is specifically configured to: verify a selected memory cell in a first intermediate programming state; determine the pulse width of the (i+1)th programming pulse as a first pulse width in response to the selected memory cell failing verification; and determine the pulse width of the (i+1)th programming pulse as a second pulse width in response to the selected memory cell passing verification.

[0076] In some embodiments, the peripheral circuitry is configured to: after applying the i-th programming pulse to the selected word line, apply a first verification voltage V1 to the selected word line, determine whether the selected memory cell has been programmed to the k1-th state based on whether the selected memory cell has passed verification, and thereby determine the pulse width of the (i+1)-th programming pulse.

[0077] The peripheral circuitry is configured to: in response to the selected memory cell failing the verification of the k1-th state, i.e., the selected memory cell being in the first programming stage, determine the pulse width of the (i+1)-th programming pulse as the first pulse width W11. In response to the selected memory cell passing the verification of the k1-th state, i.e., the selected memory cell being in the second programming stage, determine the pulse width of the (i+1)-th programming pulse as the second pulse width W12.

[0078] In a specific example, such as Figure 2 As shown, the selected memory cell is a three-level memory cell, and the k1th state can be L2. The verification voltage Vv2 of L2 is the first verification voltage V1. The peripheral circuit is configured to apply the first verification voltage V1 to the selected word line. In response to the selected memory cell failing verification, i.e., the selected memory cell is in the first programming stage, the pulse width of the (i+1)th programming pulse is determined to be the first pulse width W11. Alternatively, in response to the selected memory cell passing verification, i.e., the selected memory cell is in the second programming stage, the pulse width of the (i+1)th programming pulse is determined to be the second pulse width W12.

[0079] In some embodiments, see Figure 2Taking the initial state of the selected memory cell as L0, the target programming state as L3, and the k1th state as L2 as an example: A programming pulse with a first pulse width W11 is applied to the selected word line, and then a verification voltage Vv1 is applied to the selected word line to determine whether the selected memory cell has been programmed to L1; if the selected memory cell has been programmed to L1, a programming pulse with a first pulse width W11 is applied to the selected word line, and then a verification voltage Vv2 is applied to the selected word line to determine whether the selected memory cell has been programmed to L2; if the selected memory cell has been programmed to L2, a programming pulse with a second pulse width W12 is applied to the selected word line, and then a verification voltage Vv3 is applied to the selected word line to determine whether the selected memory cell has been programmed to L3; if the selected memory cell has been programmed to L3 (target programming state), the programming operation ends.

[0080] It should be noted that, in this embodiment of the present disclosure, after applying the i-th programming pulse to the selected word line, multiple different verification voltages can be applied to the selected word line, that is, multiple different programming states can be verified on the selected memory cell to determine the programming state of each selected memory cell after applying the i-th programming pulse to the selected word line, and thereby determine the pulse width of the (i+1)-th programming pulse corresponding to each selected memory cell. In this embodiment of the present disclosure, there is no limit to the number of verifications of the selected memory cell after the i-th programming pulse.

[0081] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in their k1-th state; count the number of failure bits for memory cells that fail verification; determine the pulse width of the (i+1)-th programming pulse as a first pulse width in response to the number of failure bits being greater than or equal to a preset number; and determine the pulse width of the (i+1)-th programming pulse as a second pulse width in response to the number of failure bits being less than a preset number. This improves the programming efficiency of the memory.

[0082] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in their k1-th state; determine the proportion of memory cells that failed verification within the selected memory cells to obtain a failure bit proportion; in response to the failure bit proportion being greater than or equal to a preset proportion, determine the pulse width of the (i+1)th programming pulse as a first pulse width; and in response to the failure bit proportion being less than the preset proportion, determine the pulse width of the (i+1)th programming pulse as a second pulse width. This can improve the programming efficiency of the memory. It should be noted that this disclosure does not impose specific limitations on the preset number and preset proportion.

[0083] In some embodiments, the peripheral circuitry is further configured to: verify a selected memory cell in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state; determine the pulse width of the (i+1)th programming pulse as a second pulse width in response to the selected memory cell failing verification; and determine the pulse width of the (i+1)th programming pulse as a third pulse width in response to the selected memory cell passing verification.

[0084] In some embodiments, the peripheral circuitry is configured to: after applying the i-th programming pulse to the selected word line, apply a second verification voltage V2 to the selected word line, determine whether the selected memory cell has been programmed to the k2-th state based on whether the selected memory cell has passed verification, and thereby determine the pulse width of the (i+1)-th programming pulse.

[0085] The peripheral circuitry is configured to: in response to the selected memory cell passing the verification in state k1 but failing the verification in state k2 (i.e., the selected memory cell is in the second programming stage), determine the pulse width of the (i+1)th programming pulse as the second pulse width W12. In response to the selected memory cell passing the verification in state k2 (i.e., the selected memory cell is in the third programming stage), determine the pulse width of the (i+1)th programming pulse as the third pulse width W13.

[0086] In a specific example, such as Figure 3 As shown, the selected memory cell is a three-level memory cell. The k1th state is L2, and the verification voltage Vv2 of L2 is the first verification voltage V1; the k2th state is L5, and the verification voltage Vv5 of L5 is the second verification voltage V2. The peripheral circuit is configured to: apply the second verification voltage V2 to the selected word line; in response to the selected memory cell failing verification, i.e., the selected memory cell is in the second programming stage, thereby determining the pulse width of the (i+1)th programming pulse as the second pulse width W12. Alternatively, in response to the selected memory cell passing verification, i.e., the selected memory cell is in the third programming stage, thereby determining the pulse width of the (i+1)th programming pulse as the third pulse width W13.

[0087] In some embodiments, see Figure 3A programming pulse with a first pulse width W11 is applied to the selected word line, and then a verification voltage Vv1 is applied to the selected word line to determine whether the selected memory cell is programmed to L1; if the selected memory cell is programmed to L1, a programming pulse with a first pulse width W11 is applied to the selected word line, and then a verification voltage Vv2 is applied to the selected word line to determine whether the selected memory cell is programmed to L2; if the selected memory cell is programmed to L2, a programming pulse with a second pulse width W12 is applied to the selected word line, and then a verification voltage Vv3 is applied to the selected word line to determine whether the selected memory cell is programmed to L3; if the selected memory cell is programmed to L3, a programming pulse with a first pulse width W11 is applied to the selected word line, and then a verification voltage Vv3 is applied to the selected word line to determine whether the selected memory cell is programmed to L3; if the selected memory cell is programmed to L3, a verification voltage Vv1 is applied to the selected word line to determine whether the selected memory cell is programmed to L3. A programming pulse with a second pulse width W12 is applied, and then a verification voltage Vv4 is applied to the selected word line to determine whether the selected memory cell is programmed to L4; if the selected memory cell is programmed to L4, a programming pulse with a second pulse width W12 is applied to the selected word line, and then a verification voltage Vv5 is applied to the selected word line to determine whether the selected memory cell is programmed to L5; if the selected memory cell is programmed to L5, a programming pulse with a third pulse width W13 is applied to the selected word line, and then a verification voltage Vv6 is applied to the selected word line to determine whether the selected memory cell is programmed to L6; if the selected memory cell is programmed to L6 (target programming state), the programming operation ends.

[0088] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in their k2-th state; count the number of failure bits for memory cells that fail verification; determine the pulse width of the (i+1)th programming pulse as a second pulse width in response to the number of failure bits being greater than or equal to a preset number; and determine the pulse width of the (i+1)th programming pulse as a third pulse width in response to the number of failure bits being less than a preset number. This improves the programming efficiency of the memory.

[0089] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in their k2-th state; determine the proportion of memory cells that failed verification within the selected memory cells to obtain the failure bit proportion; in response to the failure bit proportion being greater than or equal to a preset proportion, determine the pulse width of the (i+1)th programming pulse as a second pulse width; and in response to the failure bit proportion being less than the preset proportion, determine the pulse width of the (i+1)th programming pulse as a third pulse width. This can improve the programming efficiency of the memory.

[0090] In some embodiments, the first pulse width, the second pulse width, and the third pulse width are fixed pulse widths.

[0091] In some embodiments, the first pulse width, the second pulse width, and the third pulse width are fixed pulse widths, which can reduce the programming cost of the memory.

[0092] In some embodiments, the storage unit includes an erase state and n programming states (state 1 to state n). The programming operation can then include n programming stages, namely the programming stage from state 1 to state n. It should be noted that the programming stage of state 1 refers to the stage before the storage unit is programmed from the erase state to state 1; that is, the programming stage of state 1 ends when the storage unit passes the verification of state 1. Similarly, the programming stage of state n refers to the stage before the storage unit is programmed from state n-1 to state n; that is, the programming stage of state n ends when the storage unit passes the verification of state n.

[0093] The peripheral circuit is configured to: in the programming stage of L1, perform programming verification of the selected memory cell in the first state; in the programming stage of L2, perform programming verification of the selected memory cell in the second state; and so on, in the programming stage of Ln, perform programming verification of the selected memory cell in the nth state.

[0094] In some embodiments, the peripheral circuitry is configured to prevent the selected memory cell from being programmed in response to the selected memory cell passing the verification of the target programming state. Thus, during the application of the next programming pulse, the threshold voltage of memory cells already programmed to the target programming state can be prevented from increasing, thereby reducing the possibility of overprogramming and improving programming quality.

[0095] In some embodiments, see Figure 1C During programming, as the programming voltage Vpgm increases, the rate of change of the threshold voltage of the selected memory cell first increases and then decreases. Therefore, see... Figure 1D The threshold voltage distribution width of L4 is greater than that of L3, L2, and L1. The threshold voltage distribution width of L4 is greater than that of L5, L6, and L7. This results in significant differences in read margin between multiple programming states and low uniformity of memory read margin.

[0096] In view of this, in some other embodiments, the programming operation includes a first programming stage and a second programming stage, with the first programming stage preceding the second programming stage; the peripheral circuit is specifically configured such that: in the first programming stage, the pulse width of the programming pulse applied to the selected word line shows a decreasing trend; and in the second programming stage, the pulse width of the programming pulse applied to the selected word line shows an increasing trend.

[0097] In other embodiments, the peripheral circuitry is configured such that, in the first programming phase, the pulse width of the programming pulse applied to the selected word line exhibits a decreasing trend; and in the second programming phase, the pulse width of the programming pulse applied to the selected word line exhibits an increasing trend. This ensures that the memory not only has a large read margin throughout the entire programming operation, reducing the possibility of read operation misjudgments and improving the accuracy of read operations, but also further reduces the read margin difference between multiple programming states, improving the read margin uniformity of the memory.

[0098] In some embodiments, the first programming stage may include a stage before the memory cell is programmed from the erase state to a preset programming state, and the second programming stage may include a stage where the memory cell is programmed from the preset programming state to the highest programming state.

[0099] In one specific example, the programming state with the largest threshold voltage distribution width among all programming states of the memory cell can be set as the preset programming state. In another specific example, the preset programming state can be set according to the read margin between adjacent programming states; if the read margin between state k and state (k+1) is the smallest, then state k is set as the preset programming state. In one specific example, the secondary memory cell includes erase state, state 1, state 2, and state 3, and the preset programming state can be, for example, state 2; in another specific example, the quaternary memory cell includes erase state and states 1 through 15, and the preset programming state can be, for example, state 8.

[0100] In the following description, the preset programming state is named the k-th state. Here, k and n are both positive integers, and n > k.

[0101] In some embodiments, the example is described with the memory cell including an erase state and n programming states (state 1 L1 to state n Ln). The programming operation may include a first programming stage and a second programming stage, wherein the first programming stage is the programming stage from state 1 to state k, and the second programming stage is the programming stage from state k+1 to state n.

[0102] The peripheral circuit can be configured such that, in the first programming stage, the pulse width of the programming pulse applied to the selected word line decreases; and in the second programming stage, the pulse width of the programming pulse applied to the selected word line increases. Specifically, the pulse width of the programming pulse applied to the selected word line can be different in different programming states; and the pulse width of the programming pulse applied to the selected word line is the same in the same programming state.

[0103] Specifically, the peripheral circuitry is configured to: apply a programming pulse with a pulse width of W21 to the selected word line during the programming phase of L1; apply a programming pulse with a pulse width of W22 to the selected word line during the programming phase of L2; and so on, applying a programming pulse with a pulse width of W2n to the selected word line during the programming phase of Ln. Wherein, W21 to W2k are decreasing, and W2k to W2n are increasing.

[0104] Figure 4 A schematic diagram of the programming pulse for the third programming method provided in this embodiment of the disclosure. See also... Figure 4 In a specific example, the memory cell is a three-level memory cell with a preset programming state of L4. The peripheral circuitry is configured to: apply a programming pulse with a pulse width of W21 to the selected word line during the L1 programming stage; apply a programming pulse with a pulse width of W22 to the selected word line during the L2 programming stage; and so on, applying a programming pulse with a pulse width of W27 to the selected word line during the L7 programming stage. Wherein, W21>W22>W23>W24, W27>W26>W25>W24. That is, during the programming operation, the peripheral circuitry can determine the pulse width of the next programming pulse based on the current programming state of the memory cell.

[0105] Figure 5 A comparison diagram of the threshold voltage distribution of memory cells obtained by programming the memory provided in the embodiments of this disclosure using the third programming method and the first programming method. It should be noted that... Figure 4 and Figure 5 This explanation uses a three-level storage unit, with W21 = W27 = W0, as an example. See [link / reference]. Figure 4 and Figure 5 Since the pulse width of the programming pulse in the programming stage of L1 is W21 and the pulse width of the programming pulse in the programming stage of L7 is W27, and W21=W27=W0, the memory cells programmed using the third programming method and the first programming method can have basically the same threshold voltage change rate in the programming stages of L1 and L7. Therefore, the threshold voltage distributions of L1 and L7 corresponding to the two programming methods basically overlap.

[0106] See also Figure 4 and Figure 5Since W0 = W21 > W22 > W23 > W24 and W0 = W27 > W26 > W25 > W24, the memory cell programmed using the third programming method can have a smaller threshold voltage change rate during the L2 to L6 programming stages compared to the memory cell programmed using the first programming method. Therefore, in the threshold voltage distribution diagram of the memory cell programmed using the third programming method, the threshold voltage distribution from L2 to L6 is compressed and narrowed in the opposite direction of the threshold voltage offset direction. Furthermore, the degree to which the threshold voltage distribution from L2 to L6 is compressed and narrowed is negatively correlated with the pulse width of the programming pulse in the corresponding stage; that is, the smaller the pulse width of the programming pulse in a certain programming stage, the greater the degree to which the threshold voltage distribution of the corresponding programming state is compressed and narrowed. It should be noted that the programming stage of L1 corresponds to the threshold voltage distribution of L1, the programming stage of L2 corresponds to the threshold voltage distribution of L2, and so on, with the programming stage of L7 corresponding to the threshold voltage distribution of L7.

[0107] In this way, the pulse width of the programming stage of each programming state can be determined according to the requirements (the degree to which the threshold voltage distribution of each programming state needs to be compressed or narrowed, or the degree to which the read margin between each programming state and the adjacent programming state needs to be increased), thereby adjusting the read margin between multiple programming states, further reducing the difference in read margin between multiple programming states, improving the accuracy of read operations and the reliability of the memory.

[0108] In some embodiments, the peripheral circuitry is further configured to: after applying the i-th programming pulse to the selected word line, perform programming verification on the selected memory cell, and determine the pulse width of the (i+1)-th programming pulse based on the verification result.

[0109] Specifically, the peripheral circuitry can be configured to: perform L1 verification on the selected memory cell; in response to the selected memory cell failing verification, determine the pulse width of the (i+1)th programming pulse as W21; in response to the selected memory cell passing verification, determine the pulse width of the (i+1)th programming pulse as W22. The peripheral circuitry can also be configured to: perform L2 verification on the selected memory cell; in response to the selected memory cell failing L2 verification, determine the pulse width of the (i+1)th programming pulse as W22; in response to the selected memory cell passing L2 verification, determine the pulse width of the (i+1)th programming pulse as W23. Similarly, the peripheral circuitry can be configured to: perform Ln verification on the selected memory cell; in response to the selected memory cell failing Ln verification, determine the pulse width of the (i+1)th programming pulse as W2n; in response to the selected memory cell passing Ln verification, determine that the selected memory cell has been programmed to Ln. That is, the peripheral circuit is configured to: maintain the pulse width of the next programming pulse unchanged in response to the selected memory cell failing verification; and adjust the pulse width of the next programming pulse in response to the selected memory cell passing programming verification. It should be noted that adjusting the pulse width of the next programming pulse here also includes maintaining the current pulse width.

[0110] In some embodiments, the storage unit includes an erase state and n programming states (state 1 to state n). Taking the preset programming state as state k and the target programming state as state n as an example, the following description is provided. The peripheral circuitry is configured to perform L1 programming verification on the selected memory cell during the L1 programming phase. If the selected memory cell fails L1 verification, the pulse width of the next programming pulse is determined to be W21; if the selected memory cell passes L1 verification, the pulse width of the next programming pulse is determined to be W22. Similarly, during the L2 programming phase, the selected memory cell is configured to perform L2 programming verification. If the selected memory cell fails L2 verification, the pulse width of the next programming pulse is determined to be W22; if the selected memory cell passes L2 verification, the pulse width of the next programming pulse is determined to be W23; and so on. During the Ln programming phase, the selected memory cell is configured to perform Ln programming verification. If the selected memory cell fails Ln verification, the pulse width of the next programming pulse is determined to be W2n; if the selected memory cell passes Ln verification, the selected memory cell is determined to be programmed to the target programming state Ln.

[0111] Here, other details not mentioned in the memory embodiment using the third programming method are similar to those in the memory using the second programming method described above. For the parts not mentioned, please refer to the memory embodiment using the second programming method described above, and they will not be repeated here.

[0112] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; the peripheral circuitry is configured to: apply a programming pulse with a first incremental voltage to a selected word line in the first programming stage; apply a programming pulse with a second incremental voltage to the selected word line in the second programming stage; and apply a programming pulse with a third incremental voltage to the selected word line in the third programming stage; wherein the second incremental voltage is less than the first incremental voltage, and the second incremental voltage is less than the third incremental voltage.

[0113] Figure 6 A schematic diagram of the programming pulse for the fourth programming method provided in this embodiment of the disclosure. See also... Figure 6 The peripheral circuitry is configured to: apply a programming pulse with a first incremental voltage Step11 to the selected word line in a first programming stage; apply a programming pulse with a second incremental voltage Step12 to the selected word line in a second programming stage; and apply a programming pulse with a third incremental voltage Step13 to the selected word line in a third programming stage, wherein Step12 < Step11 and Step12 < Step13. It should be noted that in this embodiment, the first incremental voltage and the third incremental voltage may be different or the same.

[0114] In some embodiments, such as Figure 6 In the programming operation shown, the pulse widths of the programming pulses in the first, second, and third programming stages can be the same.

[0115] Figure 7 A comparison diagram of the threshold voltage distribution of memory cells obtained after programming the memory provided in the embodiments of this disclosure using the fourth programming method and the first programming method. It should be noted that... Figure 6 and Figure 7 This explanation uses a three-level storage unit, with Step 11 = Step 13 = Step 0, as an example. (See also...) Figure 6 and Figure 7 Since the programming pulse in the first programming stage has a first incremental voltage Step11 and the programming pulse in the third programming stage has a third incremental voltage Step13, and Step11 = Step13 = Step0, the memory cells that are programmed using the fourth programming method and the first programming method can have basically the same threshold voltage change rate in the first programming stage and the third programming stage. Therefore, the threshold voltage distributions of L1, L2, L6 and L7 corresponding to the two programming methods are basically overlapping.

[0116] See also Figure 6 and Figure 7Since the programming pulse in the second programming stage has a second incremental voltage Step12, and Step12 < Step11 = Step13 = Step0, the memory cell programmed using the fourth programming method can have a smaller threshold voltage change rate compared to the memory cell programmed using the first programming method. Therefore, in the threshold voltage distribution diagram of the memory cell programmed using the fourth programming method, the threshold voltage distribution from L3 to L5 is compressed and narrowed in the opposite direction of the threshold voltage offset direction.

[0117] This increases the read margin between L3 and L4, between L4 and L5, and between L5 and L6, reduces the read margin difference between multiple programming states, and improves the accuracy of read operations and the reliability of the memory.

[0118] The memory provided in this embodiment has a large read margin and high programming efficiency in the first and third programming stages, and a large read margin in the second programming stage, which reduces the possibility of read operation misjudgment and improves the accuracy of read operation. Moreover, the difference in read margin between multiple programming states is small, and the reliability of the memory is significantly improved.

[0119] In some embodiments, the peripheral circuitry is further configured to: after applying the i-th programming pulse to the selected word line, perform programming verification on the selected memory cell, and determine the incremental voltage of the (i+1)-th programming pulse relative to the i-th programming pulse based on the verification result, where i is a positive integer.

[0120] In some embodiments, the peripheral circuitry is specifically configured to: verify a selected memory cell in a first intermediate programming state; in response to the selected memory cell failing verification, determine the incremental voltage of the (i+1)th programming pulse relative to the i-th programming pulse as a first incremental voltage; and in response to the selected memory cell passing verification, determine the incremental voltage of the (i+1)th programming pulse relative to the i-th programming pulse as a second incremental voltage.

[0121] In some embodiments, the peripheral circuitry is configured to: after applying the i-th programming pulse to the selected word line, apply a first verification voltage V1 to the selected word line, determine whether the selected memory cell has been programmed to the k1-th state based on whether the selected memory cell has passed verification, and thereby determine the incremental voltage of the (i+1)-th programming pulse compared to the i-th programming pulse.

[0122] The peripheral circuitry is configured to: in response to the selected memory cell failing the verification of state k1, i.e., the selected memory cell being in the first programming stage, determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as the first incremental voltage (Step 11). In response to the selected memory cell passing the verification of state k1, i.e., the selected memory cell being in the second programming stage, determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as the second incremental voltage (Step 12).

[0123] In a specific example, such as Figure 6 As shown, the selected memory cell is a three-level memory cell, and the k1th state can be L2. The verification voltage Vv2 of L2 is the first verification voltage V1. The peripheral circuit is configured to apply the first verification voltage V1 to the selected word line. In response to the selected memory cell failing verification, i.e., the selected memory cell is in the first programming stage, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined as the first incremental voltage (Step 11). Alternatively, in response to the selected memory cell passing verification, i.e., the selected memory cell is in the second programming stage, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined as the second incremental voltage (Step 12).

[0124] In some embodiments, see Figure 6 Taking the initial state of the selected memory cell as L0, the target programming state as L3, and the k1th state as L2 as an example: A programming pulse with a first incremental voltage Step11 is applied to the selected word line, and then a verification voltage Vv1 is applied to the selected word line to determine whether the selected memory cell has been programmed to L1; if the selected memory cell has been programmed to L1, a programming pulse with a first incremental voltage Step11 is applied to the selected word line, and then a verification voltage Vv2 is applied to the selected word line to determine whether the selected memory cell has been programmed to L2; if the selected memory cell has been programmed to L2, a programming pulse with a second incremental voltage Step12 is applied to the selected word line, and then a verification voltage Vv3 is applied to the selected word line to determine whether the selected memory cell has been programmed to L3; if the selected memory cell has been programmed to L3 (target programming state), the programming operation ends.

[0125] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in their k1-th state; count the number of failed bits for memory cells that fail verification; determine the increment voltage of the (i+1)-th programming pulse compared to the ith programming pulse as a first increment voltage in response to the number of failed bits being greater than or equal to a preset number; and determine the increment voltage of the (i+1)-th programming pulse compared to the ith programming pulse as a second increment voltage in response to the number of failed bits being less than a preset number. This improves the programming efficiency of the memory.

[0126] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in state k1; determine the proportion of memory cells that failed verification in the selected memory cells to obtain a failure bit proportion; in response to the failure bit proportion being greater than or equal to a preset proportion, determine the increment voltage of the (i+1)th programming pulse compared to the ith programming pulse as a first increment voltage; and in response to the failure bit proportion being less than the preset proportion, determine the increment voltage of the (i+1)th programming pulse compared to the ith programming pulse as a second increment voltage. This can improve the programming efficiency of the memory. It should be noted that this disclosure does not impose specific limitations on the preset number and preset proportion.

[0127] In some embodiments, the peripheral circuitry is further configured to: verify a selected memory cell in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state; in response to the selected memory cell failing verification, determine the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a second incremental voltage; and in response to the selected memory cell passing verification, determine the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a third incremental voltage.

[0128] In some embodiments, the peripheral circuitry is configured to: after applying the i-th programming pulse to the selected word line, apply a second verification voltage V2 to the selected word line, determine whether the selected memory cell has been programmed to the k2 state based on whether the selected memory cell has passed verification, and thereby determine the incremental voltage of the (i+1)-th programming pulse compared to the i-th programming pulse.

[0129] The peripheral circuit is configured to: in response to the selected memory cell passing the verification of state k1 but failing the verification of state k2 (i.e., the selected memory cell is in the second programming stage), determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as the second incremental voltage (Step 12). In response to the selected memory cell passing the verification of state k2 (i.e., the selected memory cell is in the third programming stage), determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as the third incremental voltage (Step 13).

[0130] In a specific example, such as Figure 7As shown, the selected memory cell is a three-level memory cell, with state k1 being L2 and verification voltage Vv2 of L2 being the first verification voltage V1; state k2 is L5 and verification voltage Vv5 of L5 is the second verification voltage V2. The peripheral circuitry is configured to apply the second verification voltage V2 to the selected word line. In response to the selected memory cell failing verification (i.e., the selected memory cell is in the second programming stage), the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined as the second incremental voltage (Step 12). Alternatively, in response to the selected memory cell passing verification (i.e., the selected memory cell is in the third programming stage), the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined as the third incremental voltage (Step 13).

[0131] In some embodiments, see Figure 7 A programming pulse with a first incremental voltage Step11 is applied to the selected word line, and then a verification voltage Vv1 is applied to the selected word line to determine whether the selected memory cell is programmed to L1; if the selected memory cell is programmed to L1, a programming pulse with a first incremental voltage Step11 is applied to the selected word line, and then a verification voltage Vv2 is applied to the selected word line to determine whether the selected memory cell is programmed to L2; if the selected memory cell is programmed to L2, a programming pulse with a second incremental voltage Step12 is applied to the selected word line, and then a verification voltage Vv3 is applied to the selected word line to determine whether the selected memory cell is programmed to L3; if the selected memory cell is programmed to L3, a programming pulse with a first incremental voltage Step11 is applied to the selected word line, and then a verification voltage Vv3 is applied to the selected word line to determine whether the selected memory cell is programmed to L3; if the selected memory cell is programmed to L3, a programming pulse with a first incremental voltage Step12 is applied to the selected word line, and then a verification voltage Vv3 is applied to the selected word line to determine whether the selected memory cell is programmed to L3. A programming pulse with a second incremental voltage Step12 is applied, and then a verification voltage Vv4 is applied to the selected word line to determine whether the selected memory cell is programmed to L4; if the selected memory cell is programmed to L4, a programming pulse with a second incremental voltage Step12 is applied to the selected word line, and then a verification voltage Vv5 is applied to the selected word line to determine whether the selected memory cell is programmed to L5; if the selected memory cell is programmed to L5, a programming pulse with a third incremental voltage Step13 is applied to the selected word line, and then a verification voltage Vv6 is applied to the selected word line to determine whether the selected memory cell is programmed to L6; if the selected memory cell is programmed to L6 (target programming state), the programming operation ends.

[0132] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in the k2 state; count the number of failed bits for memory cells that fail verification; determine the increment voltage of the (i+1)th programming pulse compared to the ith programming pulse as a second increment voltage in response to the number of failed bits being greater than or equal to a preset number; and determine the increment voltage of the (i+1)th programming pulse compared to the ith programming pulse as a third increment voltage in response to the number of failed bits being less than a preset number. This improves the programming efficiency of the memory.

[0133] In some embodiments, when programming multiple selected memory cells, the peripheral circuitry is configured to: verify the selected memory cells in their k2-th state; determine the proportion of memory cells that failed verification among the selected memory cells to obtain a failure bit proportion; in response to the failure bit proportion being greater than or equal to a preset proportion, determine the increment voltage of the (i+1)th programming pulse compared to the ith programming pulse as a second increment voltage; and in response to the failure bit proportion being less than a preset proportion, determine the increment voltage of the (i+1)th programming pulse compared to the ith programming pulse as a third increment voltage. This can improve the programming efficiency of the memory.

[0134] In some embodiments, the first incremental voltage, the second incremental voltage, and the third incremental voltage are fixed incremental voltages.

[0135] In some embodiments, the first incremental voltage, the second incremental voltage, and the third incremental voltage are fixed pulse widths, which can reduce the programming cost of the memory.

[0136] Here, other details not mentioned in the memory embodiment using the fourth programming method are similar to those in the memory using the second programming method described above. For the parts not mentioned, please refer to the memory embodiment using the second programming method described above. They will not be repeated here.

[0137] In some embodiments, the storage unit includes an erase state and n programming states (state 1 to state n). Therefore, the programming operation may include n programming stages, which are programming stages for states 1 to n respectively. Here, the programming stages for states 1 to n are referred to as the programming stages.

[0138] In some embodiments, the programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage; the peripheral circuit is specifically configured such that: in the first programming stage, the incremental voltage of the programming pulse applied to the selected word line exhibits a decreasing trend; and in the second programming stage, the incremental voltage of the programming pulse applied to the selected word line exhibits an increasing trend.

[0139] In this embodiment, the peripheral circuit is configured such that: in the first programming stage, the incremental voltage of the programming pulse applied to the selected word line shows a decreasing trend; and in the second programming stage, the incremental voltage of the programming pulse applied to the selected word line shows an increasing trend. This ensures that the memory not only has a large read margin throughout the entire programming operation, reducing the possibility of read operation misjudgment and improving the accuracy of read operations, but also further reduces the read margin difference between multiple programming states, improving the read margin uniformity of the memory.

[0140] The peripheral circuit can be configured such that, in the first programming stage, the incremental voltage of the programming pulse applied to the selected word line shows a decreasing trend; and in the second programming stage, the incremental voltage of the programming pulse applied to the selected word line shows an increasing trend. Specifically, the incremental voltage of the programming pulse applied to the selected word line can be different in different programming states; and the incremental voltage of the programming pulse applied to the selected word line is the same in the same programming state.

[0141] Specifically, the peripheral circuit is configured as follows: during the programming stage of L1, a programming pulse with an increment voltage of Step21 is applied to the selected word line; during the programming stage of L2, a programming pulse with an increment voltage of Step22 is applied to the selected word line; and so on, during the programming stage of Ln, a programming pulse with an increment voltage of Step2n is applied to the selected word line. Step21 to Step2k are decreasing, and Step2k to Step2n are increasing.

[0142] Figure 8 A schematic diagram of the programming pulse for the fifth programming method provided in this embodiment of the disclosure. See also... Figure 8 In a specific example, the memory cell is a three-level memory cell with a preset programming state of L4. The peripheral circuitry is configured as follows: during the programming stage of L1, a programming pulse with an increment voltage of Step 21 is applied to the selected word line; during the programming stage of L2, a programming pulse with an increment voltage of Step 22 is applied to the selected word line; and so on, during the programming stage of L7, a programming pulse with an increment voltage of Step 27 is applied to the selected word line. The order is: Step 21 > Step 22 > Step 23 > Step 24, Step 27 > Step 26 > Step 25 > Step 24. In other words, during the programming operation, the peripheral circuitry can determine the increment voltage of the next programming pulse relative to the previous programming pulse based on the current programming state of the memory cell.

[0143] Figure 9 A comparison diagram of the threshold voltage distribution of memory cells obtained after programming the memory provided in the embodiments of this disclosure using the fifth programming method and the first programming method. It should be noted that... Figure 8 and Figure 9This explanation uses a three-level storage unit, with Step 21 = Step 27 = Step 0, as an example. (See also...) Figure 8 and Figure 9 Since the incremental voltage of the programming pulse in the programming stage of L1 is Step21 and the incremental voltage of the programming pulse in the programming stage of L7 is Step27, and Step21 = Step27 = Step0, the memory cells programmed using the fifth programming method and the first programming method can have basically the same threshold voltage change rate in the programming stages of L1 and L7. Therefore, the threshold voltage distributions of L1 and L7 corresponding to the two programming methods basically overlap.

[0144] See also Figure 8 and Figure 9 Since Step0 = Step21 > Step22 > Step23 > Step24 and Step0 = Step27 > Step26 > Step25 > Step24, the memory cell programmed using the fifth programming method can have a smaller threshold voltage change rate in stages two through six compared to the memory cell programmed using the first programming method. Therefore, in the threshold voltage distribution diagram of the memory cell programmed using the fifth programming method, the threshold voltage distribution from L2 to L6 is compressed and narrowed in the opposite direction of the threshold voltage offset direction. Furthermore, the degree to which the threshold voltage distribution from L2 to L6 is compressed and narrowed is negatively correlated with the magnitude of the incremental voltage of the programming pulse in the corresponding stage; that is, the smaller the incremental voltage of the programming pulse in a certain programming stage, the greater the degree to which the threshold voltage distribution of the corresponding programming state is compressed and narrowed.

[0145] In this way, the incremental voltage of the programming stage of each programming state can be determined according to the requirements (the degree to which the threshold voltage distribution of each programming state needs to be compressed or narrowed, or the degree to which the read margin between each programming state and the adjacent programming state needs to be increased), thereby adjusting the read margin between multiple programming states, further reducing the difference in read margin between multiple programming states, improving the accuracy of read operations and the reliability of the memory.

[0146] In some embodiments, the peripheral circuitry is further configured to: after applying the i-th programming pulse to the selected word line, perform programming verification on the selected memory cell, and determine the incremental voltage of the (i+1)-th programming pulse relative to the i-th programming pulse based on the verification result.

[0147] Specifically, the peripheral circuit can be configured to: perform L1 verification on the selected memory cell; in response to the selected memory cell failing verification, determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as Step 21; in response to the selected memory cell passing verification, determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as Step 22. The peripheral circuit can also be configured to: perform L2 verification on the selected memory cell; in response to the selected memory cell failing verification, determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as Step 22; in response to the selected memory cell passing verification, determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as Step 23. Similarly, the peripheral circuit can be configured to: perform Ln verification on the selected memory cell; in response to the selected memory cell failing verification, determine the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse as Step 2n; in response to the selected memory cell passing verification, determine that the selected memory cell has been programmed to Ln. That is, the peripheral circuit is configured to: maintain the incremental voltage of the next programming pulse unchanged in response to the selected memory cell failing verification; and adjust the incremental voltage of the next programming pulse in response to the selected memory cell passing programming verification. It should be noted that adjusting the incremental voltage of the next programming pulse here also includes maintaining the current incremental voltage.

[0148] In some embodiments, the storage unit includes an erase state and n programming states (state 1 to state n). Taking the preset programming state as state k and the target programming state as state n as an example, the following description is provided. The peripheral circuitry is configured to perform L1 programming verification on the selected memory cell during the L1 programming phase. If the selected memory cell fails verification, the incremental voltage of the next programming pulse compared to the previous programming pulse is determined as Step 21; if the selected memory cell passes verification, the incremental voltage of the next programming pulse compared to the previous programming pulse is determined as Step 22. Similarly, during the L2 programming phase, the selected memory cell is programmed using L2 programming verification. If the selected memory cell fails verification, the incremental voltage of the next programming pulse compared to the previous programming pulse is determined as Step 22; if the selected memory cell passes verification, the incremental voltage of the next programming pulse compared to the previous programming pulse is determined as Step 23. This process continues until the Ln programming phase, where the selected memory cell is programmed using Ln programming verification. If the selected memory cell fails verification, the incremental voltage of the next programming pulse compared to the previous programming pulse is determined as Step 2n; if the selected memory cell passes verification, the selected memory cell is determined to be programmed to the target programming state Ln.

[0149] Other details not mentioned here in the memory embodiment programmed using the fifth programming method are similar to those in the memory programmed using the second, third, or fourth programming methods described above. For any parts not mentioned, please refer to the memory embodiments programmed using the second, third, or fourth programming methods described above. They will not be repeated here.

[0150] In some embodiments, this disclosure also provides a memory programmed using a sixth programming method. The sixth programming method can be a combination of a second programming method and a fourth programming method, a combination of a second programming method and a fifth programming method, a combination of a third programming method and a fourth programming method, or a combination of a third programming method and a fifth programming method. That is, the memory programmed using the sixth programming method can adjust the pulse width and / or incremental voltage of the programming pulse when it detects that a memory cell has entered the next stage.

[0151] In some embodiments, the memory is a ferroelectric memory.

[0152] In some embodiments, the ferroelectric polarization switching of a ferroelectric memory (Fe-NAND) changes non-linearly with voltage. Specifically, the change is slow at the onset and near saturation of ferroelectric polarization switching, and faster in the middle of the switching process. Therefore, during programming operations, the rate of change of the threshold voltage of the ferroelectric memory also changes from slow to fast and then back to slow (e.g., ...). Figure 1C Therefore, embodiments of this disclosure are applicable to ferroelectric memories, or those having similar characteristics. Figure 1C The threshold voltage-programming voltage variation characteristics are shown in other memories.

[0153] Figure 10 This is a partial structural diagram of a ferroelectric memory cell string provided in an embodiment of this disclosure. Specifically, please refer to... Figure 10A ferroelectric memory may include multiple strings of ferroelectric memory cells. Each string may include a bottom select transistor (BST) (not shown in the figure), multiple ferroelectric memory cells, and a top select transistor (TST) (not shown in the figure) connected in series vertically. Each string of memory cells includes a memory stack layer comprising alternating gate electrode layers and gate dielectric layers; a ferroelectric layer disposed between the gate electrode layers and the gate dielectric layers; and a channel structure extending through the memory stack layer, the channel structure comprising a channel layer and a fill layer radially inward. The channel layer, the gate electrode layer, and the ferroelectric layer disposed between the channel layer and the gate electrode layer together constitute a ferroelectric memory cell. It should be noted that the ferroelectric layer may include ferroelectric materials, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof of transition metal oxides; the channel layer may include semiconductor materials, such as polycrystalline silicon; and the filling layer may include dielectric materials, such as silicon oxide.

[0154] This disclosure also provides a method for programming a memory, the method comprising: performing a programming operation on a selected memory cell using a step-pulse voltage method; during the programming operation, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibits a trend of first decreasing and then increasing.

[0155] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; the programming method further includes: in the first programming stage, applying a programming pulse having a first pulse width to a selected word line; in the second programming stage, applying a programming pulse having a second pulse width to the selected word line; and in the third programming stage, applying a programming pulse having a third pulse width to the selected word line; wherein the second pulse width is less than the first pulse width, and the second pulse width is less than the third pulse width.

[0156] In some embodiments, the programming method further includes: after applying the i-th programming pulse to the selected word line, performing programming verification on the selected memory cell, and determining the pulse width of the (i+1)-th programming pulse based on the verification result, where i is a positive integer.

[0157] In some embodiments, determining the pulse width of the (i+1)th programming pulse based on the verification result includes: verifying a first intermediate programming state of a selected memory cell; determining the pulse width of the (i+1)th programming pulse as a first pulse width in response to the selected memory cell's programming state failing verification; and determining the pulse width of the (i+1)th programming pulse as a second pulse width in response to the selected memory cell's programming state passing verification.

[0158] In some embodiments, determining the pulse width of the (i+1)th programming pulse based on the verification result further includes: verifying a second intermediate programming state for a selected memory cell, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of a first intermediate programming state; determining the pulse width of the (i+1)th programming pulse as a second pulse width in response to the selected memory cell's programming state failing verification; and determining the pulse width of the (i+1)th programming pulse as a third pulse width in response to the selected memory cell's programming state passing verification.

[0159] In some embodiments, the first pulse width, the second pulse width, and the third pulse width are fixed pulse widths.

[0160] In some embodiments, the programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage; in the first programming stage, the pulse width of the programming pulse applied to the selected word line shows a decreasing trend; in the second programming stage, the pulse width of the programming pulse applied to the selected word line shows an increasing trend.

[0161] In some embodiments, the programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; in the first programming stage, a programming pulse having a first incremental voltage is applied to a selected word line; in the second programming stage, a programming pulse having a second incremental voltage is applied to the selected word line; in the third programming stage, a programming pulse having a third incremental voltage is applied to the selected word line; wherein the second incremental voltage is less than the first incremental voltage, and the second incremental voltage is less than the third incremental voltage.

[0162] In some embodiments, the programming method further includes: after applying the i-th programming pulse to the selected word line, performing programming verification on the selected memory cell, and determining the incremental voltage of the (i+1)-th programming pulse relative to the i-th programming pulse based on the verification result, where i is a positive integer.

[0163] In some embodiments, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse based on the verification result includes: verifying a first intermediate programming state of a selected memory cell; determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a first incremental voltage in response to the selected memory cell's programming state failing verification; and determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a second incremental voltage in response to the selected memory cell's programming state passing verification.

[0164] In some embodiments, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse based on the verification result further includes: verifying a second intermediate programming state for a selected memory cell, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of a first intermediate programming state; in response to the selected memory cell's programming state failing verification, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a second incremental voltage; and in response to the selected memory cell's programming state passing verification, determining the incremental voltage of the (i+1)th programming pulse relative to the ith programming pulse as a third incremental voltage.

[0165] In some embodiments, the first incremental voltage, the second incremental voltage, and the third incremental voltage are fixed incremental voltages.

[0166] In some embodiments, the programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage; in the first programming stage, the incremental voltage of the programming pulse applied to the selected word line shows a decreasing trend; in the second programming stage, the incremental voltage of the programming pulse applied to the selected word line shows an increasing trend.

[0167] In some embodiments, the memory is a ferroelectric memory.

[0168] Figure 11 This is a schematic diagram of a storage system provided as an embodiment of the present disclosure. See also... Figure 11 The storage system includes: a memory 100 in any of the above embodiments; and a storage controller 200 coupled to the memory 100, the storage controller 200 being configured to control the memory 100.

[0169] In some embodiments, the storage system may include one or more memories 100. It is understood that the storage controller 200 may control the peripheral circuitry within the memories 100.

[0170] In some embodiments, the storage system may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0171] The storage controller 200 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0172] The storage controller 200 is designed to operate in high duty cycle environments in solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0173] In some embodiments, the storage controller 200 may also be configured to manage various functions relating to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the storage controller 200 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 100.

[0174] Storage controller 200 can also perform any other suitable functions, such as formatting memory 100. Storage controller 200 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, storage controller 200 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0175] The storage controller 200 and one or more memories 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system can be implemented and packaged into different types of end electronic products.

[0176] It should be noted that the above description of the memory programming method and memory system is similar to the description of the memory embodiments described above, and has similar beneficial effects. For technical details not disclosed in the memory programming method and memory system embodiments of this disclosure, please refer to the description of the memory embodiments of this disclosure for understanding.

[0177] This disclosure provides a memory, a method for programming the memory, and a memory system. The memory includes: a memory cell array; word lines coupled to the memory cells in the memory cell array; and peripheral circuitry, which is coupled to the memory cell array via word lines and configured to: perform a programming operation on selected memory cells using a step-pulse voltage method; during the programming operation, the pulse width and / or the increment voltage of the programming pulse applied to the selected word line exhibits a trend of first decreasing and then increasing. In the memory provided by this disclosure, the peripheral circuitry is configured such that during the programming operation, the pulse width and / or increment voltage of the programming pulse applied to the selected word line can exhibit a trend of first increasing and then decreasing. Thus, the memory cells have a larger threshold voltage change rate in the early and late stages of the programming operation, and a smaller threshold voltage change rate in the middle stage of the programming operation. Therefore, the memory has a larger read margin and higher programming efficiency in the early and late stages of the programming operation, while having a larger read margin in the middle stage of the programming operation, reducing the possibility of read operation misjudgment and improving the accuracy of the read operation. Furthermore, the difference in read margin between multiple programming states is small, significantly improving the reliability of the memory.

[0178] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0179] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory, characterized in that, include: Storage cell array; Word lines coupled to the memory cells in the memory cell array; as well as Peripheral circuitry, which is coupled to the memory cell array via the word line and configured as follows: The selected memory cell is programmed using a step-pulse voltage method; During programming operations, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibit a trend of first decreasing and then increasing.

2. The memory according to claim 1, characterized in that, The programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; the peripheral circuit is configured as follows: In the first programming phase, a programming pulse with a first pulse width is applied to the selected word line; In the second programming phase, a programming pulse with a second pulse width is applied to the selected word line; In the third programming stage, a programming pulse with a third pulse width is applied to the selected word line; The second pulse width is smaller than the first pulse width, and the second pulse width is smaller than the third pulse width.

3. The memory according to claim 2, characterized in that, The peripheral circuit is also configured to: After applying the i-th programming pulse to the selected word line, the selected memory cell is programmed and verified, and the pulse width of the (i+1)-th programming pulse is determined based on the verification result, where i is a positive integer.

4. The memory according to claim 3, characterized in that, The peripheral circuit is specifically configured as follows: Verification of the selected memory cell in the first intermediate programming state; In response to the selected memory cell failing verification, the pulse width of the (i+1)th programming pulse is determined to be the first pulse width; In response to the selected memory cell being verified, the pulse width of the (i+1)th programming pulse is determined to be the second pulse width.

5. The memory according to claim 4, characterized in that, The peripheral circuit is also configured to: The selected memory cell is verified in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state. In response to the selected memory cell failing verification, the pulse width of the (i+1)th programming pulse is determined to be the second pulse width; In response to the selected memory cell being verified, the pulse width of the (i+1)th programming pulse is determined to be the third pulse width.

6. The memory according to claim 2, characterized in that, The first pulse width, the second pulse width, and the third pulse width are fixed pulse widths.

7. The memory according to claim 1, characterized in that, The programming operation includes a first programming stage and a second programming stage, with the first programming stage preceding the second programming stage; the peripheral circuit is specifically configured as follows: During the first programming stage, the pulse width of the programming pulse applied to the selected word line shows a decreasing trend; In the second programming phase, the pulse width of the programming pulse applied to the selected word line shows an increasing trend.

8. The memory according to claim 1, characterized in that, The programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; the peripheral circuit is configured as follows: In the first programming phase, a programming pulse with a first incremental voltage is applied to the selected word line; In the second programming phase, a programming pulse with a second incremental voltage is applied to the selected word line; In the third programming stage, a programming pulse with a third incremental voltage is applied to the selected word line; The second incremental voltage is less than the first incremental voltage, and the second incremental voltage is less than the third incremental voltage.

9. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: After applying the i-th programming pulse to the selected word line, the selected memory cell is programmed and verified, and the incremental voltage of the (i+1)-th programming pulse compared to the i-th programming pulse is determined based on the verification result, where i is a positive integer.

10. The memory according to claim 9, characterized in that, The peripheral circuit is specifically configured as follows: Verification of the selected memory cell in the first intermediate programming state; In response to the selected memory cell failing verification, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the first incremental voltage; In response to the selected memory cell being verified, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the second incremental voltage.

11. The memory according to claim 10, characterized in that, The peripheral circuit is also configured to: The selected memory cell is verified in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state. In response to the selected memory cell failing verification, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the second incremental voltage; In response to the selected memory cell being verified, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the third incremental voltage.

12. The memory according to claim 8, characterized in that, The first incremental voltage, the second incremental voltage, and the third incremental voltage are fixed incremental voltages.

13. The memory according to claim 1, characterized in that, The programming operation includes a first programming stage and a second programming stage, with the first programming stage preceding the second programming stage; the peripheral circuit is specifically configured as follows: During the first programming phase, the incremental voltage of the programming pulse applied to the selected word line shows a decreasing trend; In the second programming phase, the incremental voltage of the programming pulse applied to the selected word line shows an increasing trend.

14. The memory according to claim 1, characterized in that, The memory is a ferroelectric memory.

15. A method for programming a memory, characterized in that, The method includes: performing a programming operation on a selected memory cell using a step-pulse voltage method; During programming operations, the pulse width of the programming pulse applied to the selected word line and / or the incremental voltage of the programming pulse exhibit a trend of first decreasing and then increasing.

16. The method according to claim 15, characterized in that, The programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; In the first programming phase, a programming pulse with a first pulse width is applied to the selected word line; In the second programming phase, a programming pulse with a second pulse width is applied to the selected word line; In the third programming stage, a programming pulse with a third pulse width is applied to the selected word line; The second pulse width is smaller than the first pulse width, and the second pulse width is smaller than the third pulse width.

17. The method according to claim 16, characterized in that, The method further includes: After applying the i-th programming pulse to the selected word line, the selected memory cell is programmed and verified, and the pulse width of the (i+1)-th programming pulse is determined based on the verification result, where i is a positive integer.

18. The method according to claim 17, characterized in that, Determining the pulse width of the (i+1)th programming pulse based on the verification result includes: Verification of the selected memory cell in the first intermediate programming state; In response to the failure of the programming state of the selected memory cell to pass verification, the pulse width of the (i+1)th programming pulse is determined to be the first pulse width; In response to the successful verification of the programming state of the selected memory cell, the pulse width of the (i+1)th programming pulse is determined to be the second pulse width.

19. The method according to claim 18, characterized in that, The step of determining the pulse width of the (i+1)th programming pulse based on the verification result further includes: The selected memory cell is verified in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state. In response to the failure of the programming state of the selected memory cell to pass verification, the pulse width of the (i+1)th programming pulse is determined to be the second pulse width; In response to the successful verification of the programming state of the selected memory cell, the pulse width of the (i+1)th programming pulse is determined to be the third pulse width.

20. The method according to claim 16, characterized in that, The first pulse width, the second pulse width, and the third pulse width are fixed pulse widths.

21. The method according to claim 15, characterized in that, The programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage. During the first programming stage, the pulse width of the programming pulse applied to the selected word line shows a decreasing trend; In the second programming phase, the pulse width of the programming pulse applied to the selected word line shows an increasing trend.

22. The method according to claim 15, characterized in that, The programming operation includes a first programming stage, a second programming stage, and a third programming stage, wherein the first programming stage precedes the second programming stage, and the second programming stage precedes the third programming stage; In the first programming phase, a programming pulse with a first incremental voltage is applied to the selected word line; In the second programming phase, a programming pulse with a second incremental voltage is applied to the selected word line; In the third programming stage, a programming pulse with a third incremental voltage is applied to the selected word line; The second incremental voltage is less than the first incremental voltage, and the second incremental voltage is less than the third incremental voltage.

23. The method according to claim 22, characterized in that, The method further includes: After applying the i-th programming pulse to the selected word line, the selected memory cell is programmed and verified, and the incremental voltage of the (i+1)-th programming pulse compared to the i-th programming pulse is determined based on the verification result, where i is a positive integer.

24. The method according to claim 23, characterized in that, The step of determining the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse based on the verification result includes: Verification of the selected memory cell in the first intermediate programming state; In response to the failure of the programming state of the selected memory cell to pass the verification, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the first incremental voltage; In response to the verification of the programming state of the selected memory cell, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the second incremental voltage.

25. The method according to claim 24, characterized in that, The step of determining the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse based on the verification result further includes: The selected memory cell is verified in a second intermediate programming state, wherein the threshold voltage of the second intermediate programming state is greater than the threshold voltage of the first intermediate programming state. In response to the failure of the programming state of the selected memory cell to pass the verification, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the second incremental voltage; In response to the verification of the programming state of the selected memory cell, the incremental voltage of the (i+1)th programming pulse compared to the ith programming pulse is determined to be the third incremental voltage.

26. The method according to claim 22, characterized in that, The first incremental voltage, the second incremental voltage, and the third incremental voltage are fixed incremental voltages.

27. The method according to claim 15, characterized in that, The programming operation includes a first programming stage and a second programming stage, wherein the first programming stage precedes the second programming stage. During the first programming phase, the incremental voltage of the programming pulse applied to the selected word line shows a decreasing trend; In the second programming phase, the incremental voltage of the programming pulse applied to the selected word line shows an increasing trend.

28. The method according to claim 15, characterized in that, The memory is a ferroelectric memory.

29. A storage system, characterized in that, include: The memory as described in any one of claims 1 to 14; A storage controller coupled to the memory, the storage controller being configured to control the memory.

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