Memory and electronic devices

Abstract

This application provides a memory and an electronic device. The memory includes: a repair chip and a plurality of stacked memory chips; the repair chip includes: a redundant cell array, including a plurality of redundant memory cell groups; an on-chip network, connecting a plurality of data transmission interfaces of the redundant memory cell groups, and configured to connect at least one target transmission interface of the data transmission interfaces to a designated redundant memory cell group according to preset first configuration information, so that the redundant memory cell group replaces the corresponding first faulty memory cell group in at least one memory chip connected to the target transmission interface; wherein, the data transmission interface corresponds to the data transmission channel of the memory chip.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a memory and electronic device. Background Technology

[0002] For some memory chips that contain multiple layers of stacked chips, four layers of chips are usually used as a memory chipset for control. At the same time, if any chip in the memory chipset is damaged, the entire memory chipset needs to be repaired and replaced. The repair resources occupy a large space, which puts a lot of pressure on chip packaging. Summary of the Invention

[0003] This application provides a memory and an electronic device.

[0004] In a first aspect, embodiments of this disclosure provide a memory, the memory including a repair chip and a plurality of stacked memory chips; the repair chip includes: Redundant cell array, comprising multiple redundant memory cell groups; An on-chip network connects multiple data transmission interfaces of the redundant storage unit group and is used to connect at least one target transmission interface of the data transmission interface to the designated redundant storage unit group according to preset first configuration information, so that the redundant storage unit group replaces the corresponding first faulty storage unit group in at least one storage chip connected to the target transmission interface; wherein, the data transmission interface is connected to the data transmission channel of the storage chip.

[0005] In some embodiments, the memory further includes: a logic chip; the logic chip includes: a pre-storage unit for storing first address information of the first faulty memory cell group to be repaired; a row command monitoring unit for receiving a row access command and determining whether the row address information carried by the row access command matches the first address information; and a column command monitoring unit connected to the row command monitoring unit for outputting a repair indication signal with a first level when a column access command is received and the row command monitoring unit determines that the row address information matches the first address information, wherein the repair indication signal with the first level is used to trigger the decoding of the column address information carried by the column access command into a redundant column command carrying redundant column address information of the redundant memory cell group.

[0006] In some embodiments, the logic chip further includes: an address lookup table, used to receive the first address information broadcast by the pre-stored unit; the first address information is used to compare with the row address information, so that the row command monitoring unit determines whether the row address information matches the first address information.

[0007] In some embodiments, the logic chip further includes: a redundant column address decoding unit, configured to receive the column access command and decode it into a redundant column command carrying redundant column address information of the redundant memory unit group.

[0008] In some embodiments, the logic chip further includes: a local column address decoding unit, configured to receive the column access command and decode it into a target column command carrying target column address information of a target memory cell group in the memory chip; a selection unit, including a first input terminal, a second input terminal, and a signal selection terminal, wherein the first input terminal is connected to the redundant column address decoding unit, the second input terminal is connected to the local column address decoding unit, and the signal selection terminal is connected to the column command monitoring unit; the selection unit is configured to select outputting the redundant column command or select outputting the target column command based on the level of the repair indication signal output by the column command monitoring unit.

[0009] In some embodiments, the logic chip further includes a local row address decoding unit, configured to receive the row address information and decode and output the target row command.

[0010] In some embodiments, the memory further includes: a backup chip stacked with the memory chip and the repair chip; the backup chip includes a plurality of backup transmission channels; the repair chip further includes a channel matching unit connected to the backup transmission channels and configured to connect the backup transmission channels to a target transmission channel among the plurality of data transmission channels according to second configuration information provided by the logic chip, so that the backup memory cell group of the backup chip replaces the corresponding second fault memory cell group in at least one of the memory chips connected to the target transmission channel.

[0011] In some embodiments, the logic chip is further configured to provide the first configuration information to the repair chip.

[0012] In some embodiments, the memory includes at least one stacked memory chip group; each memory chip group includes a plurality of memory chips; each memory cell group includes 4N data transmission channels; each memory chip is connected to N of the data transmission channels; different memory chips in the same memory chip group are connected to different data transmission channels; multiple memory chip groups share the 4N data transmission channels; where N is a positive integer; the repair chip is stacked on the memory chip group and is connected one-to-one with the 4N data transmission channels through the 4N data transmission interfaces of the on-chip network.

[0013] In a second aspect, embodiments of this disclosure provide an electronic device that includes a memory as described in the first aspect.

[0014] This disclosure provides a memory and an electronic device that, when an access command requests access to a first faulty memory cell group, can replace the first faulty memory cell group with a redundant memory cell group in a redundant cell array, resulting in low repair costs, reduced costs, and improved chip yield. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of signal transmission between multi-layered memories provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another memory structure provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of the repair chip provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a logic chip according to an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a third type of memory according to an embodiment of this disclosure; Figure 7 These are cross-sectional schematic diagrams of different sections of the memory provided in the embodiments of this disclosure. Detailed Implementation

[0016] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0018] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0020] In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments, and therefore the illustrations are not necessarily drawn to scale.

[0021] It should be noted that a semiconductor chip (such as on-chip networks, redundant cell arrays, and memory chips mentioned later) may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as the first direction. The semiconductor chip includes a substrate, the side of the substrate closest to the top surface of the semiconductor chip is the top surface of the substrate, and the side of the substrate closest to the bottom surface of the semiconductor chip is the bottom surface of the substrate. The first direction is also perpendicular to the top surface of the substrate.

[0022] See Figure 1 This illustrates a schematic diagram of the structure of a memory 10 provided in an embodiment of this disclosure. For example... Figure 1 As shown, the memory 10 includes a plurality of memory chips 11 stacked sequentially along a first direction, with every four memory chips 11_0 to 11_3 forming a memory chip group (Rank).

[0023] by Figure 1 For example, the memory 10 includes 12 memory chips 11 stacked sequentially (only one feasible example), divided into 3 memory chip groups, addressed by the stack position code (Stack ID, SID) of the memory chips 11. For example, memory chips 11_0~11_3 with SID 00 are the first memory chip group, memory chips 11_0~11_3 with SID 01 are the second memory chip group, and memory chips 11_0~11_3 with SID 10 are the third memory chip group.

[0024] for Figure 1 In multiple memory chip groups, memory chips with the same number can share control signals: for example, all memory chips 11_0 share the same control signal, all memory chips 11_1 share the same control signal, all memory chips 11_2 share the same control signal, and all memory chips 11_3 share the same control signal.

[0025] Signal transmission between the memory chips 11 is achieved through hybrid bonding. Please refer to [link / reference]. Figure 2 This diagram illustrates signal transmission between multilayer memory chips 11 provided in an embodiment of the present disclosure. Figure 2 As shown, each of the memory chips 11 includes multiple contact hole groups, and each contact hole group includes a first contact hole 0, a second contact hole 1, a third contact hole 2, and a fourth contact hole 3. Figure 2 Only a portion of the contact hole group is shown.

[0026] like Figure 2 As shown, the contact holes in the same memory chip 11 are arranged in a staggered manner layer by layer according to a preset rule. The first alignment mark line AA' is parallel to the first side of the memory chip 11, and the second alignment mark line BB' is parallel to the second side of the memory chip 11. The first side and the second side are adjacent sides. The first side can be one of the long side and the short side, and the second side can be the other of the long side and the short side.

[0027] Please see Figure 2 The arrangement of different memory chips within the same memory chipset is different. Specifically: (1) The first memory chip 11_0 and the second memory chip 11_1 are stacked face to face, and the positioning marks F of the first memory chip 11_0 and the second memory chip 11_1 are located on different sides of the first alignment mark line AA' and on the same side of the second alignment mark line BB'.

[0028] (2) The second memory chip 11_1 and the third memory chip 11_2 are stacked back to back, and the positioning marks F of the second memory chip 11_1 and the third memory chip 11_2 are located on different sides of the second alignment mark line BB' and on the same side of the first alignment mark line AA'.

[0029] (3) The third memory chip 11_2 and the fourth memory chip 11_3 are stacked face to face, and the positioning marks F of the third memory chip 11_2 and the fourth memory chip 11_3 are located on different sides of the first alignment mark line AA' and on the same side of the second alignment mark line BB'.

[0030] exist Figure 2 In the example of the rectangular coordinate system formed by the first alignment mark AA' and the second alignment mark BB', the area enclosed by side A of the first alignment mark AA' and side B of the second alignment mark BB' is the first quadrant, and the positioning mark F is located in the second quadrant of each memory chip 11. Figure 2 The positioning mark F of the first memory chip 11_0 is located in the lower right corner, the positioning mark F of the second memory chip 11_1 is located in the upper right corner, the positioning mark F of the third memory chip 11_2 is located in the upper left corner, and the positioning mark F of the fourth memory chip 11_3 is located in the lower left corner.

[0031] Since the memory chips 11 adopt the above-described stacking method and the contact holes in the memory chips 11 are arranged in a staggered manner layer by layer according to a preset rule, the positions of the contact holes in the different memory chips 11 of each memory chip group are as follows: (1) such as Figure 2As shown, a first contact hole 0 of the first memory chip 11_0, a second contact hole 1 of the second memory chip 11_1, a third contact hole 2 of the third memory chip 11_2, and a fourth contact hole 3 of the fourth memory chip 11_3 are aligned along the projection of the first direction and electrically connected to form a first signal transmission channel 40, and the first signal transmission channel 40 is used to provide control signals to the first memory chip 11_0; (2) For example Figure 2 As shown, a second contact hole 1 of the first memory chip 11_0, a first contact hole 0 of the second memory chip 11_1, a fourth contact hole 3 of the third memory chip 11_2, and a third contact hole 2 of the fourth memory chip 11_3 are aligned along the projection of the first direction and electrically connected to form a second signal transmission channel 41, and the second signal transmission channel 41 is used to provide control signals to the second memory chip 11_1; (3) such as Figure 2 As shown, a third contact hole 2 of the first memory chip 11_0, a fourth contact hole 3 of the second memory chip 11_1, a first contact hole 0 of the third memory chip 11_2, and a second contact hole 1 of the fourth memory chip 11_3 are aligned along the projection of the first direction and electrically connected to form a third signal transmission channel 42, and the third signal transmission channel 42 is used to provide control signals to the third memory chip 11_2; (4) such as Figure 2 As shown, a fourth contact hole 3 of the first memory chip 11_0, a third contact hole 2 of the second memory chip 11_1, a second contact hole 1 of the third memory chip 11_2, and a first contact hole 0 of the fourth memory chip 11_3 are aligned along the projection of the first direction and electrically connected to form a fourth signal transmission channel 43, which is used to provide control signals to the fourth memory chip 11_3.

[0032] The internal circuitry of the first memory chip 11_0 is connected to the first contact hole 0, and is used to receive signals from the first contact hole 0 or send generated signals to the first contact hole 0. In other words, the memory chip 11 can obtain the required signals from its own first contact hole 0, while the second contact hole 1, the third contact hole 2, and the fourth contact hole 3 can "bypass" the first memory chip 11_0, but are not electrically connected to the internal circuitry of the first memory chip 11_0.

[0033] like Figure 1As shown, each memory chip 11 includes 4 memory cell groups, meaning each memory chip group includes 16 memory cell groups CH0~CH15. Memory cell groups with the same number in different memory chip groups transmit signals through the same contact vias (e.g., through-silicon vias). The through-silicon vias of each memory cell group within the same memory chip group are independent of each other. Therefore, if a memory cell group of a memory chip 11 fails, it can be repaired using a memory chip 11 with the same memory cell group from another memory chip group. In this way, N+1 memory chip groups can be used as N memory chip groups, improving yield. N is a positive integer greater than or equal to 1.

[0034] In other words, if one of the 16 stacked memory chips fails, the memory can be used as a 12-layer stacked memory. This approach actually uses 4 layers of memory chips as a repair unit to repair the basic unit (channel) in the chip stacking structure, which is quite costly.

[0035] See Figure 3 This illustrates a schematic diagram of another memory 10 provided in an embodiment of this disclosure. For example... Figure 3 As shown, in Figure 1 At least one layer of repair chips 30 is stacked on top of the memory 10 shown. The memory 10 includes a plurality of repair chips 30 and a plurality of stacked memory chips 11. The plurality of memory chips 11 include a plurality of memory chip groups, wherein each memory chip group includes a set of memory chips 11_0 to 11_3.

[0036] In another embodiment, all the different memory chips 11 have the same structure, and the structure of the repair chip 30 includes at least the structure of any one of the memory chips 11. The repair chip 30 may include a static random access memory (SRAM die).

[0037] See Figure 4 It shows a schematic diagram of the repair chip structure. For example... Figure 4 As shown, the repair chip 30 includes a redundant cell array 311 (SRAM Pool) and an on-chip network 312 (Re-configurable NOC). The redundant cell array includes multiple redundant memory cell groups.

[0038] like Figure 4 As shown, the on-chip network 312 connects multiple data transmission interfaces of the redundant storage unit group. Figure 4Taking a storage cell group quantity A=16 (CH0~CH15) as an example, the on-chip network 312 connects the redundant cell array 311 to the corresponding storage cell group in at least one storage chip 11 through 16 data transmission interfaces. It is also used to connect at least one target transmission interface among the data transmission interfaces to the designated redundant storage cell group according to preset first configuration information, so that the redundant storage cell group replaces the corresponding first faulty storage cell group in the at least one storage chip 11 connected to the target transmission interface; wherein, the data transmission interface corresponds to the data transmission channel of the storage chip.

[0039] For ease of explanation, see [link to documentation]. Figure 4 The redundant unit array 311 is connected to the data transmission channels (CH0~CH15) corresponding to the memory cell groups in at least one memory chip via the data transmission interface in the on-chip network 312. From a hardware resource configuration perspective, the redundant memory cell group acts as a repair unit, constructing a routing network covering all data transmission interfaces through the on-chip network 312. That is, the entire redundant unit array 311 has a pre-defined optional transmission channel to any one of the memory cell groups among the multiple memory chips 11.

[0040] In this embodiment of the present disclosure, the status of multiple memory cell groups can be detected before the memory 10 leaves the factory. When a fault is detected in the status of a memory cell group (such as the first row), it is identified as the first faulty memory cell group. And first configuration information is generated based on the first address information of the first faulty memory cell.

[0041] In some embodiments, the logic chip 12 is further configured to provide first configuration information to the repair chip 30. The first configuration information is determined based on the address information of the first fault storage unit.

[0042] Examples are given below: Please refer to... Figure 4 Suppose that during factory testing, the testing equipment detects damage to the memory cell group located at data transmission interface (CH0) 1 in the third-layer stacked memory chip 11_0, identifying it as the first faulty memory cell group. The testing system will schedule across physical channels and decide to call a healthy redundant memory cell group from the repair chip as the replacement unit, that is, to use the data transmission interface connected to this redundant memory cell group as the target transmission interface. This correspondence (i.e., the first address information of channel CH0 1 mapping to the address information of the aforementioned redundant memory cell group) will be burned and solidified into the non-volatile memory elements (such as electronic fuses or antifuse arrays) at the bottom layer of the logic chip 12.

[0043] Each time the memory executes a power-on boot or initialization sequence, the logic chip 12 reads the aforementioned fixed mapping record from its own underlying layer, packages it into a specific electrical signal sequence, and generates "first configuration information". Subsequently, the logic chip 12 transmits this first configuration information upwards and provides it to the repair chip 30 through an inter-chip data transmission interface (e.g., through-silicon via (TSV)).

[0044] Upon receiving the first configuration information, the repair chip 30 immediately loads it into the pre-storage unit 3121 of the internal on-chip network 312. Based on this, the on-chip network performs an internal routing switch operation, internally connecting the data transmission interface (target transmission interface) originally connected to channel 1 (CH0) to the fourth redundant storage unit group. Thus, without manual hardware intervention and completely transparent to the external host, the location mapping for the faulty storage unit group within channel 1 and the cross-channel switching route configuration are automatically completed.

[0045] In some embodiments, the memory further includes: logic chip 12; see also Figure 3 The logic chip 12 is located at the bottom of the stacked memory chips 11, for example, as a base die, or stacked with the memory chips 11. The logic chip 12 is responsible for receiving access commands issued by the external host and internally parsing, scheduling, and timing control.

[0046] See Figure 5 The logic chip 12 includes: Pre-store unit 3121 (Fuse IP) is used to store the first address information of the first faulty storage unit group to be repaired.

[0047] In this embodiment, the pre-store unit 3121 is constructed from an array of non-volatile memory elements, such as an electronic fuse or an anti-fuse, and can permanently store the first address information of the first faulty memory cell group determined during the factory testing phase at the time of shipment. When the memory performs a power-on reset or system initialization sequence, the pre-store unit 3121 triggers its built-in read logic to read all the first address information it has stored and transmits it to downstream nodes, such as the line command monitoring unit 3122, in the form of multiple-fuse broadcast for latching and standby. Here, the first address information is essentially a logical address label representing the first faulty memory cell group, such as the memory chip group number, memory chip number, and memory cell group row address to which the first faulty memory cell group belongs.

[0048] The Row Command Repair Bank / Row Monitor (Row Command Monitoring Unit 3122) is used to receive row access commands and determine whether the row address information carried by the row access command matches the first address information.

[0049] In this embodiment of the disclosure, the command monitoring unit 3122 is typically composed of a set of high-speed digital logic circuits embedded in the front end of the command path; it includes: a command decoding flip-flop for parsing the bus protocol, a local latch for storing broadcast data, and a high-bit-width hardware comparator composed of an XOR array.

[0050] In this embodiment, during the initialization phase, the first address information disseminated via the fuse broadcast mechanism is pre-reserved and held in the local latch of the line command unit. The access command issued by the external host is not a single pulse signal, but rather a specific command / address (C / A) truth table such as R[9:0]. The line command control unit receives the access command and obtains the line address information of the access command through a command decoding trigger. The line address information of the access command and the first address information in the local latch are sent together to a hardware comparator. The hardware comparator performs bit-by-bit comparisons using multiple parallel XOR gates at the underlying level. When the line address information of the access command is completely equivalent to the first address information (the hardware comparator outputs a single true signal), it indicates that the access command issued by the host is attempting to access the pre-registered first fault memory unit group. In this case, the row command monitoring unit 3122 determines that the row address information matches the first address information, and can pull up a synchronization hit flag bit on the dedicated signal line inside the logic chip 12 to send a row address hit activation signal (Active / Precharge Command HitBank) to the downstream column command monitoring unit 3123.

[0051] The column command monitoring unit 3123 (Column Command Repair Bank Monitor), connected to the row command monitoring unit 3122, is used to output a repair indication signal with a first level when a column access command is received and the row address information is determined by the row command monitoring unit 3122 to match the first address information. The repair indication signal with the first level is used to trigger the decoding of the column address information carried by the column access command into a redundant column command carrying redundant column address information of the redundant storage unit group.

[0052] In this embodiment of the disclosure, since there is a fixed clock delay between the row address hit activation signal and the column access command, the column command monitoring unit 3123 internally includes: a state buffer delay circuit, a column address input flip-flop, and an enable control gate array composed of multi-level logic gates.

[0053] In some embodiments, when repair is performed row-by-row, the column command monitoring unit 3123 may not have a logic gate comparator for the column address. On one hand, when the column command monitoring unit 3123 receives a row address hit activation signal from the row command monitoring unit 3122, it indicates that the next access command needs to be transmitted to the redundant memory cell group. If a column access command is received at this time, the enable control gate array will undergo a logic flip, that is, output a repair indication signal with a first level (e.g., logic high level "1") to the designated pin. On the other hand, if the column command monitoring unit 3123 does not receive a row address hit activation signal from the row command monitoring unit 3122, or receives a row address miss signal from the row command monitoring unit 3122, it indicates that the next access only needs to be transmitted to the original target memory cell group. In this case, the enable control gate array enters a normal release sleep state, that is, outputs a repair indication signal with a second level (e.g., logic low level "0") to the designated pin.

[0054] In some embodiments, the column command monitoring unit 3123 may further include a high-bit-width hardware comparator composed of an array of logic XOR NOT gates to compare the address information carried by the column access command with the first address information, and output a repair indication signal with a first level after the comparison is consistent.

[0055] In some embodiments, see Figure 5 The logic chip 12 further includes an address lookup table 3124 (Repair Bank / Row Lookup Table), used to receive the first address information broadcast by the pre-stored unit 3121; the first address information is used to compare with the row address information so that the row command monitoring unit 3122 can determine whether the row address information matches the first address information.

[0056] In this embodiment, the pre-stored unit 3121 has a slow retrieval speed for the stored first address information due to limitations in its physical read / write attributes, and cannot directly meet the high-frequency memory access and verification requirements issued by the external host at GHz-level clock rates. An address lookup table 3124 constructed from high-speed gate circuits can be configured as a relay connection.

[0057] In this embodiment of the present disclosure, during the process of the memory performing power-on startup or deep sleep wake-up, the pre-store unit 3121 will perform a fuse broadcast action, and the solidified first address information will be extracted. The address lookup table 3124, as the data receiving end of the broadcast action, can latch the first address information into the local high-speed lookup cell array.

[0058] In this embodiment of the present disclosure, after the memory performs a power-on startup, the address lookup table 3124 enters an enabled state. When the memory receives a row access command, the address lookup table 3124 will output the first address information temporarily stored inside it as a comparison basis to the row command monitoring unit 3122, so that the row command monitoring unit 3122 can quickly determine whether the row address information carried by the row access command matches the first address information.

[0059] For example, suppose that during the wafer testing stage after the memory is manufactured or packaged, the test equipment detects that the first address information of the first faulty memory cell group is "Bank 5, Row 1024". This first address information is physically burned and solidified in the pre-stored cell 3121.

[0060] Each time the memory executes a power-on reset or initialization sequence, a fuse readout and fuse broadcast mechanism is triggered. The pre-store unit 3121 transmits the first address information to the address lookup table 3124 via the internal bus through the fuse broadcast mechanism. The address lookup table 3124 receives the first address information and latches it into the internal high-speed flip-flop or static register array.

[0061] When an external host initiates an access operation, if the external host's row access command needs to access the first faulty storage unit group identified above, the issued row access command will carry row address information pointing to "Bank 5, Row 1024". At this time, the decoding circuit of the row command monitoring unit 3122 will obtain the row address information carried by the row access command, and at the same time, the address lookup table 3124 will provide the pre-latched first address information to the row command monitoring unit 3122 through internal connections.

[0062] Inside the line command monitoring unit 3122, a hardware comparator array performs a bit-by-bit comparison (such as an XOR NOT operation) on the two sets of level signals carrying line address information. The comparison determines that the level characteristics of each bit width of the externally input line address information are completely consistent with the first address information pre-stored in the address lookup table 3124. Based on this determination, the line command monitoring unit 3122 establishes a "match" logic relationship and generates a synchronization hit status flag signal at its output.

[0063] In some embodiments, see Figure 5The logic chip 12 further includes a redundant column address decoding unit 3126, which is used to receive the column access command and decode it into a redundant column command carrying redundant column address information of the redundant storage unit group.

[0064] In some embodiments, see Figure 5 The logic chip 12 further includes: a native column command decoder 3127 and a selection unit 3128 (multiplexer, MUX). The local column address decoding unit 3127 is used to receive the column access command and decode it into a target column command carrying the target column address information of the target memory cell group in the memory chip. Selection unit 3128 includes a first input terminal, a second input terminal, and a signal selection terminal (SEL). The first input terminal is connected to the redundant column address decoding unit, the second input terminal is connected to the local column address decoding unit, and the signal selection terminal is connected to the column command monitoring unit 3123. The selection unit 3128 is used to select to output the redundant column command or the target column command based on the level of the repair indication signal output by the column command monitoring unit 3123.

[0065] For example, when an external host issues a column access command C[7:0], the redundant column address decoding unit 3126 and the local column address decoding unit 3127 inside the logic chip 12 can synchronously and in parallel receive the column address information in the column access command and perform decoding operations independently. On the one hand, after the decoding operation is completed, if the column command monitoring unit 3123 determines that the current access command (row access command) hits the pre-determined first faulty memory cell group, it outputs a repair indication signal with a first level to the signal selection terminal of the selection unit 3128. Under the trigger of the repair indication signal with the first level, the selection unit 3128 connects the first input terminal and the output terminal, so that the output terminal outputs a redundant column command, that is, the column access command is decoded into a redundant column command carrying redundant column address information of the redundant memory cell group. On the other hand, after the decoding operation is completed, if the column command monitoring unit 3123 determines that the current access command (row access command) has not hit the pre-determined first fault storage unit group, it indicates that the access command is performing a normal, undamaged area access. The column command monitoring unit 3123 outputs a repair indication signal with a second level, and the selection unit 3128 turns on its second input terminal and output terminal to select and output the target column command generated by the local column address decoding unit.

[0066] In some embodiments, the logic chip 12 further includes a local row address decoding unit 3125 (Native RowCommand Decoder), used to receive the row address information and decode and output the target row command.

[0067] In this embodiment, after a row access command is input to the logic chip 12 and the row address information is parsed, the row address information is sent to the command monitoring unit 3122 to determine whether the access address matches the first address information. Simultaneously, the local row address decoding unit 3125 also decodes the received row access command to generate a target row command for driving the local word line of the memory array. That is, regardless of whether the target memory cell row to be accessed is damaged and requires a repair action, normal row activation operation instructions for the local array are still decoded, issued, and executed as usual. This architecture design reduces the strong dependence on the timeliness of hardware comparison results in the first row activation cycle, optimizes the bus pressure of front-end command address decoding, and is friendly to overall row trigger timing parameters.

[0068] In some embodiments, the memory 10 further includes: A spare chip 20 stacked with the memory chip and the repair chip; a spare chip 20 stacked with the memory chip and the repair chip; The backup chip 20 includes multiple backup transmission channels; The repair chip 20 further includes a channel matching unit, which is connected to the backup transmission channel and is used to connect the backup transmission channel with the target transmission channel among the multiple data transmission channels according to the second configuration information provided by the logic chip 12, so that the backup storage unit group of the backup chip 20 replaces the corresponding second fault storage unit group in at least one of the storage chips connected to the target transmission channel.

[0069] In this embodiment, the hardware structure of the backup chip 20 can be consistent with any memory chip, and it has an independent memory array composed of complete backup memory cell groups. In the physical stacking architecture, the backup chip 20 can be connected to the repair chip through through-silicon vias (TSVs) or hybrid bonds. When factory testing or power-on self-test determines that there is a second faulty memory cell group in a channel within the memory chip, it means that the damage to the memory chip exceeds the repair capability of the redundant cell array. The logic chip 12 will record the location of the second faulty memory cell group to form second address information, and generate second configuration information based on the second address information and send it to the repair chip.

[0070] The channel matching unit inside the repair chip 30 can be composed of a multiplexed switch matrix. After receiving the second configuration information, the channel matching unit redirects the access command that should have been directed to the target transmission channel where the second fault storage unit is located to the backup transmission channel corresponding to the backup chip 20 through hardware connection level switching.

[0071] In some embodiments, the memory 10 includes at least one stack of memory chips; each stack of memory chips includes a plurality of memory chips; Each of the memory cell groups includes 4N data transmission channels; each memory chip is connected to N of the data transmission channels; different memory chips in the same memory chip group are connected to different data transmission channels; multiple memory chip groups share the 4N data transmission channels; where N is a positive integer; The repair chip is stacked on the memory chip group and is connected one-to-one with the 4N data transmission interfaces and 4N data transmission channels of the on-chip network.

[0072] like Figure 6 As shown, when N=1, each redundant memory cell group in the on-chip network has a first data transmission interface 50, a second data transmission interface 51, a third data transmission interface 52, and a fourth data transmission interface 53. Please refer to... Figure 2 For the same redundant storage unit group, the first data transmission interface 50 is connected to the first data transmission channel 40, the second data transmission interface 51 is connected to the second data transmission channel 41, the third data transmission interface 52 is connected to the third data transmission channel 42, and the fourth data transmission interface 53 is connected to the fourth data transmission channel 43.

[0073] In this way, please combine Figure 2 (1) If the on-chip network 312 turns on the first data transmission interface 50 of a certain redundant storage unit group, the interface receives the control signal originally sent to the first storage chip 11_0, so that the redundant storage unit group accurately replaces the storage unit group that has been damaged in the first storage chip 11_0 to work; (2) If the on-chip network 312 turns on the second data transmission interface 51, it replaces the first faulty storage unit group in the second storage chip 11_1 to work; (3) If the third data transmission interface 52 turns on, it replaces the first faulty storage unit group in the third storage chip 11_2 to work; (4) If the fourth data transmission interface 53 turns on, it replaces the first faulty storage unit group in the fourth storage chip 11_3 to work.

[0074] For example: Suppose a memory cell group in the second memory chip 11_1 is damaged (i.e., identified as the first faulty memory cell group). After receiving the corresponding first configuration information, the on-chip network 312 uses an internal routing switch to activate the second data transmission interface 51 of the designated redundant memory cell group, while disconnecting the other data transmission interfaces. At this time, the data and control signals received by the redundant memory cell group are the same access signals originally intended for the damaged memory cell group, thus the redundant memory cell group replaces the faulty memory cell group in the second memory chip 11_1 and begins operation.

[0075] In this way, based on the stacking level and specific location of the faulty memory cell group, the redundant memory cell group inside the repair chip can be flexibly replaced by the routing and scheduling of the on-chip network 312, allowing it to replace any damaged memory cell group in any layer of memory chips 11_0~11_3. This breaks the previous limitation of having to replace the entire layer of memory chips, making the repair cost extremely low and significantly improving the stacking yield with minimal silicon area cost.

[0076] It should be noted that each memory chip 11 and the redundant unit array 311 each includes multiple independently operating memory cell groups (their physical mechanism is equivalent to an independent channel). The different redundant memory cell groups within the redundant unit array 311 can be used to repair multiple faulty memory cell groups within the same memory chip, or they can be used to repair multiple faulty memory cell groups distributed across different memory chips.

[0077] It should be noted that, since the data lines and gating logic of each storage unit group are relatively independent, the actual repair operation is carried out entirely at the "storage unit group" as the smallest granularity, rather than at the entire "storage chip". Specifically, multiple first-fault storage unit groups that have been damaged may be randomly and interspersed (for example, some on the first storage chip 11_0, and some on the fourth storage chip 11_3). During physical repair, within the same storage chip, only the damaged storage unit groups may be taken over and replaced by the on-chip network 312, while the remaining undamaged storage unit groups maintain their native transmission links and continue to operate. In actual access testing, the logic chip 12 only needs to pre-store the first address information of those damaged first-fault storage unit groups and instruct the on-chip network 312 to complete local physical route redirection through the first configuration information; for the undamaged storage unit groups, no address mapping or hardware intervention is required.

[0078] To further clarify the multi-level collaborative repair mechanism combining the "built-in redundant array of the repair chip" and the "external serial backup chip" in the memory of this application, the following description is based on typical chip defect scenarios that may be encountered during factory testing. In this embodiment, the memory can adaptively perform various levels of repair, such as single-row repair, multi-row repair, and large-area channel-level repair, depending on the size and density of the defect.

[0079] (1) Single-Row Repair Based on Repair Chip. During factory testing or self-testing of memory, if only an isolated wordline is damaged, or there are scattered single-bit soft / hard breakdown faults, the defect at this minute scale is identified as the "first faulty memory cell group". At this time, the pre-stored cell of the logic chip only records the first address information of the single damaged row. During routine execution of access commands, if the line command monitoring unit in the logic chip determines that the external access address accurately hits the single row target, it sends a hit activation signal. After receiving the repair instruction, the repair chip's on-chip network will call a single redundant memory cell group with extremely small granularity (e.g., covering only tens to hundreds of bytes) in the redundant cell array to take over the read / write data. This process achieves high-precision "point-to-point" replacement at the single-row level. Since the redundant SRAM resources consumed are minimal, it can accommodate similar scattered fault points throughout the entire stacked memory.

[0080] (2) Multi-Row Repair Based on Repair Chip. If the test equipment detects that multiple consecutive word lines are short-circuited in a local array block of the same memory chip, or that periodic clustered multi-row defects are caused by impurity contamination (i.e., the local defects are identified as the "first faulty memory cell group"), the pre-stored unit of the logic chip will convert a set of address ranges containing the batch of defects (e.g., using address mask technology or segment address recording) into first address information and package and store it. When an external access command falls into this multi-row address range, the logic chip maintains the output repair indication signal; the on-chip network of the repair chip then responds, continuously allocating or logically splicing multiple adjacent redundant memory cell groups to form a whole logically continuous redundant space, replacing the theoretically damaged continuous area, and completing the "multi-row repair" with block mapping.

[0081] (3) Large-area repair based on spare chips. When a large-area damage is detected in a specific layer of memory chips (e.g., the entire Bank structure is destroyed), or the vertical through-silicon via (TSV) responsible for connecting the memory cell group is broken, the cost of repairing it solely with the SRAM capacity in the repair chip is too high. This large-area defect is defined as the "second faulty memory cell group". In this case, the logic chip directly extracts the second address information embedded at the bottom layer to generate the second configuration information. After receiving the second configuration information, the repair chip no longer schedules its own redundant cell array, but instead entrusts the channel matching unit (as a hardware-level high-bandwidth cross switch) at the front end of the repair chip to intervene. The channel matching unit directly performs a global "bypass" transfer at the bus bifurcation point for all clock, control and data signal lines sent to the damaged "target data transmission channel"; that is, the data of the entire channel is physically rerouted to the spare transmission channel of the "spare chip" at the top layer (or the bottom layer). The entire large-area macroblock memory read and write is taken over by the intact spare chip.

[0082] The aforementioned memory 10 may be such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDR SDRAM), etc., and no specific limitation is made here.

[0083] In some embodiments, the aforementioned data transmission interface is selectively selected via one or more of the following devices: fuse, antifuse, and multiple-to-one data selector.

[0084] Please see Figure 7 Figure (a) shows a schematic diagram of signal transmission in the memory chipset of memory 10. Here, "0_0" refers to the contact hole location of the internal circuit connection of the first memory chip 11_0, i.e., the first contact hole 0 in the first memory chip 11_0; "0_1" refers to the contact hole location of the internal circuit connection of the second memory chip 11_1, i.e., the first contact hole 0 in the second memory chip 11_1; "0_2" refers to the contact hole location of the internal circuit connection of the third memory chip 11_2, i.e., the first contact hole 0 in the third memory chip 11_2; and "0_3" refers to the contact hole location of the internal circuit connection of the fourth memory chip 11_3, i.e., the first contact hole 0 in the fourth memory chip 11_3.

[0085] Please see Figure 7 Figure (b) shows a schematic diagram illustrating the location of the contact hole 32 in the on-chip network 312 and the location of the contact holes in the memory chipset. It can be seen that one contact hole 32 in the on-chip network 312 is shared by four memory chips 11. The first contact hole of the memory chip 11 that needs repair can be configured to connect to contact hole 32. Figure 7 Taking memory chip 11_2 as an example (marked with solid lines), the first contact holes of the remaining memory chips 11 are not connected. The routing reconnection relationship between contact hole 32 and the first contact hole in the corresponding memory chip 11 is controlled by the first configuration information during the repair phase. The root data of the first configuration information is acquired during the stacking test phase and burned into the pre-store unit 3121 of the underlying logic chip 12. During the system power-on phase, the logic chip 12 transmits the read first configuration information to the on-chip network 312 via the internal bus to perform routing switching.

[0086] Please see Figure 7 (c) shows the connection relationship between the contact hole 32 of the on-chip network 312 and the first contact hole 0 to the fourth contact hole 3 in the redundant unit array 311. It can be seen that the contact hole 32 of the on-chip network 312 is fixedly connected to the first contact hole 0 in the redundant unit array 311.

[0087] In simple terms, when the system detects a first faulty memory cell group in the memory chip, the logic chip 12 uploads the first configuration information to the on-chip network 312. The multiplexing switch network inside the on-chip network 312 then responds and allocates resources, enabling any redundant memory cell group in the repair chip to precisely take over the corresponding memory cell group in the faulty memory chip layer, achieving seamless replacement with fine granularity.

[0088] In addition, since the redundant unit array 311 and the memory chip 11 are both divided into multiple memory unit groups (like Bank / Channel) to work independently, the above-mentioned routing reorganization and repair process based on the on-chip network 312 can be refined to the point that a single memory unit group is the smallest addressing and repair unit.

[0089] In this embodiment of the disclosure, the contact hole can be a through-silicon via, a through-metal via, etc., and different contact holes in the same chip are electrically isolated.

[0090] It should be noted that the accompanying drawings are schematic diagrams of a four-quadrant stacking strategy. Multiple through-silicon vias (TSVs) within the same signal channel (i.e., TSVs corresponding to different memory chips) extend along the stacking direction (the stacking direction is perpendicular to the front side of the memory chip). In other embodiments, a spiral TSV stacking strategy can also be used. In this case, multiple TSVs corresponding to the same signal channel in the same stacking unit have different horizontal projection positions and form a rectangle. Different TSVs in the same signal channel in different stacking units have the same horizontal projection position. This application does not limit the stacking method of different memory chips within a stacking unit or the stacking method between different stacking units.

[0091] In summary, this disclosure provides a memory 10 in which a repair chip can schedule internal redundant memory cell groups via an on-chip network 312 to perform fine-grained repair on memory chips 11 in any stacked layer, based on precise faulty memory cell groups; the logic chip 12 coordinates the output of either regular access or redundant repair commands based on an address matching mechanism. Compared to the prior art, this solution has the following significant advantages: (1) Compared with the original scheme that uses an entire memory chip group (usually requiring the overall bundling and replacement of 4 layers of memory chips) as the smallest repair unit, the memory 10 provided in this embodiment adopts a scheme of repair chip embedded redundant SRAM array and on-chip network 312 route redistribution, which makes the repair granularity more refined, reduces the squeezing of redundant resources on the package volume, and reduces the repair cost.

[0092] (2) Through the configuration capabilities of the logic chip 12 and the flexible routing characteristics of the on-chip network 312, address redirection across layers and channels can be automatically completed at the physical layer based on the first address information identified during the factory testing phase. It can accurately take over the relevant fault units in any memory chip 11 without external manual physical intervention, thereby improving the overall factory yield of highly stacked chip components.

[0093] (3) The repair mechanism of this solution has extremely high scalability and flexibility. On the one hand, the repair chip is responsible for dealing with scattered or small-granular faults; on the other hand, when a large-scale outage occurs, a spare die can be introduced through the channel matching unit to replace the macroblocks at the channel level with large granularity. This multi-dimensional hierarchical repair network structure further improves the ultimate yield of stacked memory.

[0094] (4) Compared with other repair schemes that require specific processing on the basic storage die, the ordinary storage chip 11 in this scheme maintains extremely high homogeneity and design consistency, without the need to add complex repair logic circuits in the basic storage chip, and the design difficulty is small.

[0095] (5) This solution has made in-depth optimizations to the command address decoding. It relies on the normal transmission and activation of row commands in conjunction with the selection mechanism of column commands in the end-path selector (MUX) to avoid command blocking and lengthy waiting. In addition, the standard data transmission channel trunk scheme of the chip-managed 4N interface direct connection multiplexing is repaired so that the local modification does not increase the basic load of the vertical contact hole, thereby minimizing the impact on the power consumption and timing delay of the overall chip stack architecture.

[0096] In another embodiment of this disclosure, an electronic device is provided that includes the memory 10 of the foregoing embodiments.

[0097] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0098] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

[0099] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0100] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0101] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0102] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0103] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0104] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, It includes a repair chip and multiple stacked memory chips; the repair chip includes: Redundant cell array, comprising multiple redundant memory cell groups; An on-chip network connects multiple data transmission interfaces of the redundant storage unit group and is used to connect at least one target transmission interface of the data transmission interface to the designated redundant storage unit group according to preset first configuration information, so that the redundant storage unit group replaces the corresponding first faulty storage unit group in at least one storage chip connected to the target transmission interface; wherein, the data transmission interface is connected to the data transmission channel of the storage chip.

2. The memory according to claim 1, characterized in that, Also includes: Logic chip; The logic chip includes: A pre-storage unit is used to store the first address information of the first faulty storage unit group to be repaired; A line command monitoring unit is used to receive a line access command and determine whether the line address information carried by the line access command matches the first address information. A column command monitoring unit, connected to the row command monitoring unit, is used to output a repair indication signal with a first level when a column access command is received and the row command monitoring unit determines that the row address information matches the first address information. The repair indication signal with the first level is used to trigger the decoding of the column address information carried by the column access command into a redundant column command carrying redundant column address information of the redundant storage unit group.

3. The memory according to claim 2, characterized in that, The logic chip also includes: An address lookup table is used to receive the first address information broadcast by the pre-stored unit; the first address information is used to compare with the row address information so that the row command monitoring unit can determine whether the row address information matches the first address information.

4. The memory according to claim 2, characterized in that, The logic chip also includes: A redundant column address decoding unit is used to receive the column access command and decode it into a redundant column command carrying redundant column address information of the redundant storage unit group.

5. The memory according to claim 4, characterized in that, The logic chip also includes: A local column address decoding unit is used to receive the column access command and decode it into a target column command carrying the target column address information of the target memory cell group in the memory chip. The selection unit includes a first input terminal, a second input terminal, and a signal selection terminal. The first input terminal is connected to the redundant column address decoding unit, the second input terminal is connected to the local column address decoding unit, and the signal selection terminal is connected to the column command monitoring unit. The selection unit is used to select to output the redundant column command or the target column command based on the level of the repair indication signal output by the column command monitoring unit.

6. The memory according to claim 2, characterized in that, The logic chip also includes: The local line address decoding unit is used to receive the line address information and decode and output the target line command.

7. The memory according to claim 2, characterized in that, Also includes: A spare chip stacked with the memory chip and the repair chip; The backup chip includes multiple backup transmission channels; The repair chip further includes a channel matching unit, which is connected to the backup transmission channel and is used to connect the backup transmission channel with a target transmission channel among the multiple data transmission channels according to the second configuration information provided by the logic chip, so that the backup storage unit group of the backup chip replaces the corresponding second fault storage unit group in at least one of the storage chips connected to the target transmission channel.

8. The memory according to claim 2, characterized in that, The logic chip is also used to provide the first configuration information to the repair chip.

9. The memory according to any one of claims 1 to 8, characterized in that, The memory includes at least one stacked memory chip group; each memory chip group includes a plurality of memory chips; Each of the memory cell groups includes 4N data transmission channels; each memory chip is connected to N of the data transmission channels; different memory chips in the same memory chip group are connected to different data transmission channels; Multiple memory chipsets share the 4N data transmission channels; where N is a positive integer; The repair chip is stacked on the memory chip group and is connected one-to-one with the 4N data transmission interfaces and 4N data transmission channels of the on-chip network.

10. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 9.

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