Fuse detection circuit for memory and memory

Abstract

This disclosure provides a fuse detection circuit for a memory and a memory, including a state detection circuit, a first-level conversion circuit, and a second-level conversion circuit connected in sequence. The state detection circuit determines the fuse signal of each of the multiple memory arrays based on multiple state signals. The first-level conversion circuit divides the fuse signal into a first fuse signal and a second fuse signal, and combines the first fuse signal and the second fuse signal according to a first read command signal to obtain multiple fuse combination signals. The second-level conversion circuit performs parallel-to-serial conversion processing on the multiple fuse combination signals according to a second read command signal and multiple misaligned sampling clock signals to obtain at least one fuse output signal. A single signal can be used to indicate the fuse usage status of multiple memory arrays, thereby obtaining the fuse usage status of all memory arrays in the memory, and thus detecting the memory arrays in the memory where fuses are available.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of semiconductor device technology, and more particularly to a fuse detection circuit for a memory and a memory. Background Technology

[0002] Double Data Rate (DDR) memory is an advanced Dynamic Random Access Memory (DRAM) technology. DDR memory can transfer data twice within a single clock cycle, making data transfer twice as fast as traditional single-data-rate memory. It is widely used in computers, servers, mobile devices, consumer electronics, and embedded systems, covering almost all application scenarios requiring fast data storage. With continuous technological advancements, DDR memory has become one of the key technological components for improving device performance.

[0003] A fuse in DRAM is a one-time programmable element. Its main function is to repair defects, configure parameters, and adjust functions during the chip manufacturing and testing stages. Its core principle is to permanently change the circuit state by physically breaking the metal connection. Therefore, it is necessary to know whether there are available fuses in each memory array of the chip. Summary of the Invention

[0004] This disclosure provides a fuse detection circuit and a memory for a memory, which can detect the fuse usage status of all memory arrays in the memory, thereby obtaining the memory arrays in the memory where the fuses are available.

[0005] In a first aspect, this disclosure provides a fuse detection circuit for a memory, the memory including multiple memory arrays, each memory array including multiple fuse groups, and the fuse detection circuit including a status detection circuit, a first-level conversion circuit and a second-level conversion circuit connected in sequence.

[0006] The status detection circuit is configured to receive status signals of multiple fuse groups and determine the fuse signal of each of the multiple memory arrays based on the multiple status signals; wherein each status signal is used to characterize whether a fuse in a fuse group has been used, and each fuse signal is used to characterize whether a fuse in a memory array has been used.

[0007] The first-level conversion circuit is configured to divide the fuse signal into a first fuse signal and a second fuse signal, and to combine the first fuse signal and the second fuse signal according to a first read command signal to obtain multiple fuse combination signals.

[0008] The secondary conversion circuit is configured to perform parallel-to-serial conversion on the multiple fuse combination signals according to the second read command signal and multiple misaligned sampling clock signals, to obtain at least one fuse output signal.

[0009] In some embodiments of this disclosure, the state detection circuit includes multiple logic circuits connected in parallel, the number of which is equal to the number of memory arrays. For each logic circuit: multiple input terminals of the logic circuit are connected one-to-one with the state signals of all fuse groups in the same memory array, and the output terminal of the logic circuit is connected to one input terminal of the first-stage conversion circuit.

[0010] The logic circuit is configured to determine that the fuse signal is low when a low level is present among the received multiple status signals, and to determine that the fuse signal is high when no low level is present among the received multiple status signals.

[0011] In some embodiments of this disclosure, the logic circuit includes AND gates, NOR gate components, and a plurality of parallel NAND gates; for each logic circuit: the input terminals of the plurality of NAND gates are connected one-to-one with the status signals of all fuse groups in the same memory array, the output terminals of the plurality of NAND gates are connected to the input terminals of the AND gates through the NOR gate components, and the output terminals of the AND gates are connected to one input terminal of the first-level conversion circuit.

[0012] In some embodiments of this disclosure, the first-stage conversion circuit includes multiple parallel signal merging circuits; for each signal merging circuit: the two input terminals of the signal merging circuit are connected one-to-one with the two output terminals of the state detection circuit, the control terminal of the signal merging circuit is connected to the first read command signal, and the output terminal of the signal merging circuit is connected to one input terminal of the second-stage conversion circuit.

[0013] The signal merging circuit is configured to receive the first fuse signal and the second fuse signal, and when the first read command signal is high, determine the fuse combination signal based on the first fuse signal; when the first read command signal is low, determine the fuse combination signal based on the second fuse signal.

[0014] In some embodiments of this disclosure, the signal combining circuit includes a D flip-flop, a first inverter, a second inverter, a first transmission gate, and a second transmission gate. For each signal combining circuit: the first fuse signal is connected to the input of the first transmission gate via the first inverter; the input of the D flip-flop is connected to the second fuse signal; the two clock terminals of the D flip-flop are respectively connected to the first read command signal and its inverted signal; the non-inverted output of the D flip-flop is connected to the input of the second transmission gate via the second inverter; the first control terminal of the first transmission gate and the second control terminal of the second transmission gate are connected to the first read command signal; the second control terminal of the first transmission gate and the first control terminal of the second transmission gate are connected to the inverted signal of the first read command signal; and the output terminals of the first and second transmission gates are connected to the same input terminal of the two-stage conversion circuit.

[0015] Specifically, when the first control terminal is at a high level and the second control terminal is at a low level, the first transmission gate and the second transmission gate are turned on; when the first control terminal is at a low level and the second control terminal is at a high level, the first transmission gate and the second transmission gate are turned off.

[0016] In some embodiments of this disclosure, the second read command signal is the superposition of a first delayed signal of the first read command signal and a second delayed signal, wherein the delay time of the first delayed signal is greater than the level switching time of the first read command signal and less than the pulse width of the first read command signal, and the time difference between the delay time of the first delayed signal and the delay time of the second delayed signal is equal to the time difference between adjacent pulses of the sampling clock signal within one sampling period.

[0017] In some embodiments of this disclosure, the secondary conversion circuit includes at least one sampling circuit and at least one output circuit. For each sampling circuit: multiple input terminals of the sampling circuit are connected one-to-one with the output terminals of multiple signal merging circuits; the control terminal of the sampling circuit is connected to the second read command signal; and multiple output terminals of the sampling circuit are connected one-to-one with multiple input terminals of an output circuit. For each output circuit: multiple control terminals of the output circuit are connected one-to-one with multiple sampling clock signals; and the output terminal of the output circuit is connected to one output terminal of the fuse detection circuit.

[0018] The sampling circuit is configured to sample the received multiple fuse combination signals at the rising edge of the second read command signal to obtain multiple sample signals; wherein each sample signal includes the first fuse signal and the second fuse signal.

[0019] The output circuit is configured to sequentially output the plurality of sampled signals according to the plurality of sampled clock signals to obtain a fuse output signal.

[0020] In some embodiments of this disclosure, the sampling circuit includes a plurality of D flip-flops connected in parallel; for each D flip-flop: the input terminal of the D flip-flop is connected to the output terminal of a signal merging circuit, the two clock terminals of the D flip-flop are respectively connected to the second read command signal and its inverted signal, and the inverted output terminal of the D flip-flop is connected to an input terminal of an output circuit.

[0021] In some embodiments of this disclosure, the output circuit includes multiple transmission gates, a third inverter, and a fourth inverter, with the number of transmission gates and the number of D flip-flops being equal; for each transmission gate: the first control terminal of the transmission gate is connected to the inverted signal of a sampling clock signal, the second control terminal of the transmission gate is connected to the sampling clock signal, and the input terminal of the transmission gate is connected to the inverted output terminal of a D flip-flop.

[0022] The outputs of the plurality of transmission gates are connected to the input of the third inverter and the output of the fourth inverter, and the output of the third inverter and the input of the fourth inverter are connected to the same output of the fuse detection circuit.

[0023] In a second aspect, this disclosure provides a memory including a memory array and any of the fuse detection circuits provided in the first aspect.

[0024] In the technical solution of this disclosure embodiment, the fuse detection circuit includes a state detection circuit, a first-level conversion circuit, and a second-level conversion circuit connected in sequence. The state detection circuit determines the fuse signal of each of the multiple memory arrays based on multiple state signals. The first-level conversion circuit divides the fuse signal into a first fuse signal and a second fuse signal. The first fuse signal and the second fuse signal are combined according to a first read command signal to obtain multiple fuse combination signals. The second-level conversion circuit performs parallel-to-serial conversion processing on the multiple fuse combination signals according to a second read command signal and multiple misaligned sampling clock signals to obtain at least one fuse output signal. A single signal can be used to indicate the fuse usage status of multiple memory arrays, thereby obtaining the fuse usage status of all memory arrays in the memory, and thus detecting the memory arrays in the memory where fuses are available. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.

[0027] Figure 2 This is a schematic diagram of a fuse detection circuit provided in an embodiment of the present disclosure.

[0028] Figure 3 This is a circuit diagram of a logic circuit provided in an embodiment of the present disclosure.

[0029] Figure 4 This is a circuit diagram of a signal merging circuit provided in an embodiment of the present disclosure.

[0030] Figure 5 This is a timing diagram of a signal merging circuit provided in an embodiment of the present disclosure.

[0031] Figure 6 This is a circuit diagram of a two-stage conversion circuit provided in an embodiment of the present disclosure.

[0032] Figure 7 This is a timing diagram of a two-stage conversion circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0035] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0036] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0037] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0038] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0039] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the memory 100 includes M memory arrays 110 and a fuse detection circuit 200. Each memory array 110 includes N fuse groups 120, so the memory 100 includes M×N fuse groups 120. Here, M is usually 8 or 16, and N is usually 16.

[0041] The fuse detection circuit 200 can receive the fuse output values ​​of M×N fuse groups 120, and compare the multiple fuse output values ​​of each fuse group 120 with the default fuse values ​​to determine the usage status of all fuses in each fuse group 120. Based on the usage status of all fuses in each fuse group 120, a status signal ST representing whether the fuses in the fuse group 120 are in use is determined, thus obtaining the status signals ST of M×N fuse groups 120. Specifically, when the status signal ST of a fuse group 120 is low, it indicates that the fuses in that fuse group 120 are not in use; when the status signal ST of a fuse group 120 is high, it indicates that the fuses in the fuse group 120 are in use.

[0042] Figure 2 This is a schematic diagram of the structure of a fuse detection circuit provided in an embodiment of the present disclosure, as shown below. Figure 2 As shown, the fuse detection circuit 200 includes a status detection circuit 210, a first-stage conversion circuit 220, and a second-stage conversion circuit 230. The M×N input terminals of the status detection circuit 210 are connected one-to-one with the status signals ST of the M×N fuse groups 120. The M output terminals of the status detection circuit 210 are connected one-to-one with the M input terminals of the first-stage conversion circuit 220. The control terminal of the first-stage conversion circuit 220 is connected to the first read command signal RD1. The M / 2 output terminals of the first-stage conversion circuit 220 are connected one-to-one with the M / 2 input terminals of the second-stage conversion circuit 230. The first control terminal of the second-stage conversion circuit 230 is connected to the second read command signal RD2. The m second control terminals of the second-stage conversion circuit 230 are connected one-to-one with the m staggered sampling clock signals CLK (CLK_1 to CLK_m). One output terminal of the second-stage conversion circuit 230 is connected to one output terminal of the fuse detection circuit 200. Here, m is typically 4.

[0043] The status detection circuit 210 is configured to receive M×N status signals ST and determine the fuse signal F (F_1 to F_M) for each of the M memory arrays 110 based on the M×N status signals ST. Each fuse signal F is used to characterize whether the fuse in a memory array 110 has been used.

[0044] The first-stage conversion circuit 220 is configured to divide the fuse signal F (F_1 to F_M) into a first fuse signal FA (FA_1 to FA_M / 2) and a second fuse signal FB (FB_1 to FB_M / 2), and combine the first fuse signal FA (FA_1 to FA_M / 2) and the second fuse signal FB (FB_1 to FB_M / 2) according to the first read command signal RD1 to obtain multiple fuse combination signals FS (FS_1 to FS_M / 2).

[0045] The secondary conversion circuit 230 is configured to perform parallel-to-serial conversion on multiple fuse combination signals FS (FS_1 to FS_M / 2) based on the second read command signal RD2 and m misaligned sampling clock signals CLK (CLK_1 to CLK_m) to obtain at least one fuse output signal OUT.

[0046] For example, such as Figure 2 As shown, the state detection circuit 210 includes M parallel logic circuits 211. For each logic circuit 211: the N input terminals of the logic circuit 211 are connected one-to-one with the state signals ST of the N fuse groups 120 in the same memory array 110, and the output terminal of the logic circuit 211 is connected to one input terminal of the first-stage conversion circuit 220. For example, as Figure 2 As shown, the N input terminals of the first logic circuit 211 are connected one-to-one with the N state signals ST (ST_1_1 to ST_1_N), and the N input terminals of the last logic circuit 211 are connected one-to-one with the N state signals ST (ST_M_1 to ST_M_N).

[0047] Figure 3 A circuit diagram of a logic circuit provided in an embodiment of this disclosure, such as... Figure 3 As shown, logic circuit 211 includes AND gates, NOR gate components, and multiple parallel NAND gates. In each logic circuit 211, the input terminals of the multiple NAND gates are connected one-to-one with the status signals ST (ST_1 to ST_N) of the N fuse groups 120 in the same memory array 110. The output terminals of the multiple NAND gates are connected to the input terminals of the AND gates through NOR gate components, and the output terminals of the AND gates are connected to one input terminal of the first-stage conversion circuit 220.

[0048] For example, N=16, such as Figure 3 As shown, the logic circuit 211 includes four parallel NAND gates (NAND1 to NAND4). The four inputs of NAND gate NAND1 are connected to the status signals ST (ST_1 to ST_4) of the first to fourth fuse groups in the memory array 110. The four inputs of NAND gate NAND2 are connected to the status signals ST (ST_5 to ST_8) of the fifth to eighth fuse groups in the memory array 110. The four inputs of NAND gate NAND3 are connected to the status signals ST (ST_9 to ST_12) of the ninth to twelfth fuse groups in the memory array 110. The four inputs of NAND gate NAND4 are connected to the status signals ST (ST_13 to ST_16) of the thirteenth to sixteenth fuse groups in the memory array 110.

[0049] When the status signals ST (ST_1 to ST_4) of the first to fourth fuse groups are low, NAND gate NAND1 outputs a high level; when the status signals ST (ST_1 to ST_4) of the first to fourth fuse groups are not low, NAND gate NAND1 outputs a low level. When the status signals ST (ST_5 to ST_8) of the fifth to eighth fuse groups are low, NAND gate NAND2 outputs a high level; when the status signals ST (ST_5 to ST_8) of the fifth to eighth fuse groups are not low, NAND gate NAND2 outputs a low level.

[0050] When the status signals ST (ST_9 to ST_12) of the ninth to twelfth fuse groups are low, NAND gate NAND3 outputs a high level; when the status signals ST (ST_9 to ST_12) of the ninth to twelfth fuse groups are not low, NAND gate NAND3 outputs a low level. When the status signals ST (ST_13 to ST_16) of the thirteenth to sixteenth fuse groups are low, NAND gate NAND4 outputs a high level; when the status signals ST (ST_13 to ST_16) of the thirteenth to sixteenth fuse groups are not low, NAND gate NAND4 outputs a low level.

[0051] For example, the NOR gate component can be a single NOR gate or multiple NOR gates connected in parallel. The number of NOR gates depends on the number of NAND gates, and the number of NAND gates depends on the number N of fuse groups 120 in each memory array 110. For example, based on the above embodiment, see below. Figure 3 The NOR gate component includes two parallel NOR gates (NOR1 and NOR2). The first input of NOR1 is connected to the output of NAND1, the second input of NOR1 is connected to the output of NAND2, and the output of NOR1 is connected to the first input of AND gate. The first input of NOR2 is connected to the output of NAND3, the second input of NOR2 is connected to the output of NAND4, and the output of NOR2 is connected to the second input of AND gate.

[0052] When NAND gates NAND1 and / or NAND2 output a high level, NOR gate NOR1 outputs a low level; when both NAND gates NAND1 and NAND2 output a low level, NOR gate NOR1 outputs a high level. When NAND gates NAND3 and / or NAND4 output a high level, NOR gate NOR2 outputs a low level; when both NAND gates NAND3 and NAND4 output a low level, NOR gate NOR2 outputs a high level. When both NOR gates NOR1 and NOR2 output a high level, the fuse combination signal F output by the AND gate is high; when either NOR gate NOR1 or NOR2 outputs a low level, the fuse combination signal F output by the AND gate is low.

[0053] Thus, when a low level is present among the N status signals (ST_1 to ST_N) received by the logic circuit 211, the fuse signal F is determined to be low; when no low level is present among the N status signals (ST_1 to ST_N) received by the logic circuit 211, the fuse signal F is determined to be high.

[0054] See also Figure 2 The first-stage conversion circuit 220 includes M / 2 parallel signal combining circuits 221. In each signal combining circuit 221, the two input terminals of the signal combining circuit 221 are connected one-to-one with the two output terminals of the state detection circuit 210. The control terminal of the signal combining circuit 221 is connected to the first read command signal RD1, and the output terminal of the signal combining circuit 221 is connected to one input terminal of the second-stage conversion circuit 230. For example, as... Figure 2 As shown, the two input terminals of the first signal merging circuit 221 receive the first fuse signal FA_1 and the second fuse signal FB_1 output by the state detection circuit 210, respectively. The two input terminals of the last signal merging circuit 221 receive the first fuse signal FA_M / 2 and the second fuse signal FB_M / 2 output by the state detection circuit 210, respectively.

[0055] For example, Figure 4 This is a circuit diagram of a signal combining circuit provided in an embodiment of the present disclosure, as shown below. Figure 4 As shown, the signal combining circuit 221 includes a D flip-flop DFF1, a first inverter INV1, a second inverter INV2, a first transmission gate TG1, and a second transmission gate TG2. In each signal combining circuit 221, the first fuse signal FA is connected to the input of the first transmission gate TG1 through the first inverter INV1, the input of the D flip-flop DFF1 is connected to the second fuse signal FB, and the two clock terminals of the D flip-flop DFF1 are respectively connected to the first read command signal RD1 and its inverted signal. The non-inverting output of D flip-flop DFF1 is connected to the input of the second transmission gate TG2 via the second inverter INV2. The first control terminal of the first transmission gate TG1 and the second control terminal of the second transmission gate TG2 are connected to the first read command signal RD1, and the second control terminal of the first transmission gate TG1 and the first control terminal of the second transmission gate TG2 are connected to the inverted signal of the first read command signal. The output terminals of the first transmission gate TG1 and the second transmission gate TG2 are connected to the same input terminal of the secondary conversion circuit 230.

[0056] On the rising edge of the first read command signal RD1, the D flip-flop DFF1 samples and latches the second fuse signal FB. When the first read command signal RD1 is high, the first control terminal of the first transmission gate TG1 and the second control terminal of the second transmission gate TG2 are both high. Therefore, the first transmission gate TG1 is turned on and the second transmission gate TG2 is turned off. The first fuse signal FA is then output after inversion. The fuse combination signal FS at this time is the inverted signal of the first fuse signal FA. Figure 5 As shown, Figure 5 This is a timing diagram of a signal merging circuit provided in an embodiment of the present disclosure.

[0057] When the first read command signal RD1 is low, the second control terminal of the first transmission gate TG1 and the first control terminal of the second transmission gate TG2 are high. Therefore, the second transmission gate TG2 is turned on and the first transmission gate TG1 is turned off. The latched second fuse signal FB is output after inversion. At this time, the fuse combination signal FS is the inverted signal of the second fuse signal FB. Figure 5 As shown.

[0058] Thus, the signal merging circuit 221 can receive the first fuse signal FA and the second fuse signal FB, and when the first read command signal RD1 is high, it determines the fuse combination signal FS based on the first fuse signal FA; when the first read command signal RD1 is low, it determines the fuse combination signal FS based on the second fuse signal FB.

[0059] See also Figure 2The secondary conversion circuit 230 includes at least one sampling circuit 231 and at least one output circuit 232. In each sampling circuit 231, the m input terminals of the sampling circuit 231 are connected one-to-one with the output terminals of the m signal merging circuits 221. The control terminal of the sampling circuit 231 is connected to the second read command signal RD2. The m output terminals of the sampling circuit 231 are connected one-to-one with the m input terminals of the output circuit 232. In each output circuit 232, the m control terminals of the output circuit 232 are connected one-to-one with the m sampling clock signals CLK (CLK_1 to CLK_m). The output terminal of the output circuit 232 is connected to one output terminal of the fuse detection circuit 200.

[0060] For example, the second read command signal RD2 is the superposition of the first delayed signal of the first read command signal RD1 and its second delayed signal. The first delayed signal is the signal obtained by delaying the first read command signal RD1 by a first delay time TD1, and the second delayed signal is the signal obtained by delaying the first read command signal RD1 by a second delay time TD2. The time difference between the first delay time TD1 and the second delay time TD2 is the time difference T between adjacent pulses of the sampling clock signal CLK within one sampling period. Therefore, within one sampling period, the second read command signal RD2 has one more sampling pulse than the first read command signal RD1.

[0061] The first delay time TD1 is greater than the level toggling time of the first read command signal RD1 and less than the pulse width of the first read command signal RD1, so that the second read command signal RD2 toggles after the first read command signal RD1 toggles to a high level. That is, at one rising edge of the second read command signal RD2, the first read command signal RD1 is at a high level.

[0062] If M=8 and m=4=M / 2, then the second-level conversion circuit 230 includes a sampling circuit 231 and an output circuit 232, such as... Figure 2 As shown, the M / 2 input terminals of the sampling circuit 231 are connected one-to-one with the output terminals of the M / 2 signal merging circuits 221. The control terminal of the sampling circuit 231 is connected to the second read command signal RD2. The M / 2 output terminals of the sampling circuit 231 are connected one-to-one with the M / 2 input terminals of the output circuit 232. The M / 2 control terminals of the output circuit 232 are connected one-to-one with the m sampling clock signals CLK (CLK_1 to CLK_m). The output terminal of the output circuit 232 is connected to the output terminal of the fuse detection circuit 200.

[0063] If M=16 and m=4=M / 4, then the secondary conversion circuit 230 includes a first sampling circuit, a second sampling circuit, a first output circuit, and a second output circuit. Specifically, the M / 4 input terminals of the first sampling circuit are connected one-to-one with the output terminals of the first to M / 4th signal merging circuits 221; the control terminal of the first sampling circuit is connected to the second read command signal RD2; the M / 4 output terminals of the first sampling circuit are connected one-to-one with the M / 4 input terminals of the first output circuit; the M / 4 control terminals of the first output circuit are connected one-to-one with the m sampling clock signals CLK (CLK_1 to CLK_m); and the output terminal of the first output circuit is connected to the first output terminal of the fuse detection circuit 200.

[0064] The M / 4 input terminals of the second sampling circuit are connected one-to-one with the output terminals of the M / 4+1 to M / 2 signal merging circuits 221. The control terminal of the second sampling circuit is connected to the second read command signal RD2. The M / 4 output terminals of the second sampling circuit are connected one-to-one with the M / 4 input terminals of the second output circuit. The M / 4 control terminals of the second output circuit are connected one-to-one with the m sampling clock signals CLK (CLK_1 to CLK_m). The output terminal of the second output circuit is connected to the second output terminal of the fuse detection circuit 200.

[0065] Figure 6 A circuit diagram of a two-stage conversion circuit provided in an embodiment of this disclosure is shown below. Figure 6 As shown, the sampling circuit 231 includes m parallel D flip-flops (DFFs). In each DFF, the input terminal of the DFF is connected to the output terminal of a signal combining circuit 221, and the two clock terminals of the DFF are respectively connected to the second read command signal RD2 and its inverted signal. The inverted output of the D flip-flop DFF is connected to one input of the output circuit 232.

[0066] At the first rising edge of the second read command signal RD2 (when the first read command signal RD1 is high), the fuse combination signal FS is the inverted signal of the first fuse signal FA. At this time, each D flip-flop samples the received first fuse signal FA, and the output sampled signal is the first fuse signal FA. At the second rising edge of the second read command signal RD2 (when the first read command signal RD1 is low), the fuse combination signal FS is the inverted signal of the second fuse signal FB. At this time, each D flip-flop samples the received second fuse signal FB, and the output sampled signal is the second fuse signal FB.

[0067] For example, if m=4, such as Figure 6As shown, the sampling circuit 231 includes D flip-flops DFF2 to DFF5. DFF2 samples the fuse combination signal FS_1 at the first rising edge of the second read command signal RD2, obtaining a first sampled signal as the first fuse signal FA_1. At the second rising edge of the second read command signal RD2, it samples the fuse combination signal FS_1 again, obtaining a first sampled signal as the second fuse signal FB_1. Figure 7 As shown, Figure 7 This is a timing diagram of a two-stage conversion circuit provided in an embodiment of the present disclosure.

[0068] D flip-flop DFF3 samples the fuse combination signal FS_2 at the first rising edge of the second read command signal RD2, obtaining the second sampled signal as the first fuse signal FA_2. It then samples the fuse combination signal FS_2 at the second rising edge of the second read command signal RD2, obtaining the second sampled signal as the second fuse signal FB_2. Figure 7 As shown.

[0069] The D flip-flop DFF4 samples the fuse combination signal FS_3 at the first rising edge of the second read command signal RD2, and the resulting third sampled signal is the first fuse signal FA_3. It then samples the fuse combination signal FS_3 at the second rising edge of the second read command signal RD2, and the resulting third sampled signal is the second fuse signal FB_3. Figure 7 As shown.

[0070] D flip-flop DFF5 samples the fuse combination signal FS_4 at the first rising edge of the second read command signal RD2, resulting in a fourth sampled signal, which is the first fuse signal FA_4. It then samples the fuse combination signal FS_4 at the second rising edge of the second read command signal RD2, resulting in a fourth sampled signal, which is the second fuse signal FB_4. Figure 7 As shown.

[0071] Thus, the sampling circuit 231 can sample the received m fuse combination signals FS at the rising edge of the second read command signal RD2 to obtain multiple sample signals; wherein each sample signal includes the first fuse signal FA and the second fuse signal FB.

[0072] See also Figure 6 The output circuit 232 includes m transmission gates TG, a third inverter INV3, and a fourth inverter INV4. The first control terminal of each transmission gate TG is connected to the inverted signal of a sampling clock signal. The second control terminal of each transmission gate TG is connected to the sampling clock signal CLK. The input terminal of each transmission gate TG is connected to the inverted output terminal of a D flip-flop DFF in the sampling circuit 231. The output terminals of m transmission gates TG are connected to the input terminal of the third inverter INV3 and the output terminal of the fourth inverter INV4. The output terminal of the third inverter INV3 and the input terminal of the fourth inverter INV4 are connected to the same output terminal of the fuse detection circuit 200.

[0073] Specifically, when the sampling clock signal CLK is low, the transmission gate TG is turned on to output the received sampling signal. Since the sampling signal received by the transmission gate TG is the first fuse signal FA at the first rising edge of the second read command signal RD2 and the second fuse signal FB at the second rising edge of the second read command signal RD2, the transmission gate TG outputs the first fuse signal FA when the sampling clock signal CLK first flips to a low level, and outputs the second fuse signal FB when the sampling clock signal CLK flips to a low level for the second time.

[0074] For example, if m=4, such as Figure 6 As shown, the output circuit 232 includes a third transmission gate TG3, a fourth transmission gate TG4, a fifth transmission gate TG5, a sixth transmission gate TG6, a third inverter INV3, and a fourth inverter INV4. The first control terminal of the third transmission gate TG3 is connected to the inverted signal of the first sampling clock signal. The second control terminal of the third transmission gate TG3 is connected to the first sampling clock signal CLK_1, and the input terminal of the third transmission gate TG3 is connected to the inverted output terminal of the D flip-flop DFF2 to receive the first sampling signal. Specifically, when the first sampling clock signal CLK_1 is low, the third transmission gate TG3 is turned on to output the first sampling signal, as shown below. Figure 7 As shown.

[0075] The first control terminal of the fourth transmission gate TG4 is connected to the inverted signal of the second sampling clock signal. The second control terminal of the fourth transmission gate TG4 is connected to the second sampling clock signal CLK_2, and the input terminal of the fourth transmission gate TG4 is connected to the inverted output terminal of the D flip-flop DFF3 to receive the second sampling signal. Specifically, when the second sampling clock signal CLK_2 is low, the fourth transmission gate TG4 is turned on to output the second sampling signal, as shown below. Figure 7 As shown.

[0076] The first control terminal of the fifth transmission gate TG5 is connected to the inverted signal of the third sampling clock signal. The second control terminal of the fifth transmission gate TG5 is connected to the third sampling clock signal CLK_3, and the input terminal of the fifth transmission gate TG5 is connected to the inverted output terminal of the D flip-flop DFF4 to receive the third sampling signal. Specifically, when the third sampling clock signal CLK_3 is low, the fifth transmission gate TG5 is turned on to output the third sampling signal, as shown below. Figure 7 As shown.

[0077] The first control terminal of the sixth transmission gate TG6 is connected to the inverted signal of the fourth sampling clock signal. The second control terminal of the sixth transmission gate TG6 is connected to the fourth sampling clock signal CLK_4, and the input terminal of the sixth transmission gate TG6 is connected to the inverted output terminal of the D flip-flop DFF5 to receive the fourth sampling signal. Specifically, when the fourth sampling clock signal CLK_4 is low, the sixth transmission gate TG6 is turned on to output the fourth sampling signal, as shown below. Figure 7 As shown.

[0078] In summary, the third inverter INV sequentially receives m first fuse signals FA (FA_1 to FA_m) and then sequentially receives m second fuse signals FB (FB_1 to FB_m). Therefore, the fuse output signal OUT output by the third inverter INV is the inverted signal of the m first fuse signals FA (FA_1 to FA_m) and the inverted signal of the m second fuse signals FB (FB_1 to FB_m). Thus, the fuse output signal OUT can indicate whether the fuses in the M storage arrays 110 have been used.

[0079] Thus, the output circuit 232 can sequentially output multiple sampled signals based on multiple sampled clock signals CLK (CLK_1 to CLK_m) to obtain a fuse output signal OUT.

[0080] In this embodiment, the fuse detection circuit includes a state detection circuit, a first-level conversion circuit, and a second-level conversion circuit connected in sequence. The state detection circuit determines the fuse signal of each of the multiple memory arrays based on multiple state signals. The first-level conversion circuit divides the fuse signal into a first fuse signal and a second fuse signal. The first fuse signal and the second fuse signal are combined according to a first read command signal to obtain multiple fuse combination signals. The second-level conversion circuit performs parallel-to-serial conversion processing on the multiple fuse combination signals according to a second read command signal and multiple misaligned sampling clock signals to obtain at least one fuse output signal. A single signal can be used to indicate the fuse usage status of multiple memory arrays, thereby obtaining the fuse usage status of all memory arrays in the memory, and thus detecting the memory arrays in the memory where fuses are available.

[0081] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, the “example” is merely exemplary and illustrative, and should not be considered exclusive or extensive.

[0082] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A fuse detection circuit for a memory, characterized in that, The memory includes multiple memory arrays, each memory array includes multiple fuse groups, and the fuse detection circuit includes a status detection circuit, a first-level conversion circuit and a second-level conversion circuit connected in sequence. The status detection circuit is configured to receive status signals of multiple fuse groups and determine the fuse signal of each of the multiple memory arrays based on the multiple status signals; wherein each status signal is used to characterize whether a fuse in a fuse group has been used, and each fuse signal is used to characterize whether a fuse in a memory array has been used. The first-level conversion circuit is configured to divide the fuse signal into a first fuse signal and a second fuse signal, and to combine the first fuse signal and the second fuse signal according to a first read command signal to obtain multiple fuse combination signals. The secondary conversion circuit is configured to perform parallel-to-serial conversion on the multiple fuse combination signals according to the second read command signal and multiple misaligned sampling clock signals, to obtain at least one fuse output signal.

2. The fuse detection circuit according to claim 1, characterized in that, The state detection circuit includes multiple logic circuits connected in parallel, and the number of logic circuits is equal to the number of the storage array; For each logic circuit: multiple input terminals of the logic circuit are connected one-to-one with the status signals of all fuse groups in the same memory array, and the output terminal of the logic circuit is connected to one input terminal of the first-level conversion circuit; The logic circuit is configured to determine that the fuse signal is low when a low level is present among the received multiple status signals, and to determine that the fuse signal is high when no low level is present among the received multiple status signals.

3. The fuse detection circuit according to claim 2, characterized in that, The logic circuit includes AND gate, NOR gate components and multiple parallel AND and NOR gates; For each logic circuit: the inputs of multiple NAND gates are connected one-to-one with the status signals of all fuse groups in the same memory array; the outputs of the multiple NAND gates are connected to the inputs of the AND gate through the NOR gate component; and the output of the AND gate is connected to one input of the first-level conversion circuit.

4. The fuse detection circuit according to claim 1, characterized in that, The first-stage conversion circuit includes multiple parallel signal merging circuits; For each signal merging circuit: the two input terminals of the signal merging circuit are connected one-to-one with the two output terminals of the state detection circuit, the control terminal of the signal merging circuit is connected to the first read command signal, and the output terminal of the signal merging circuit is connected to one input terminal of the secondary conversion circuit; The signal merging circuit is configured to receive the first fuse signal and the second fuse signal, and when the first read command signal is high, determine the fuse combination signal based on the first fuse signal; when the first read command signal is low, determine the fuse combination signal based on the second fuse signal.

5. The fuse detection circuit according to claim 4, characterized in that, The signal merging circuit includes a D flip-flop, a first inverter, a second inverter, a first transmission gate, and a second transmission gate; For each signal merging circuit: the first fuse signal is connected to the input of the first transmission gate via the first inverter; the input of the D flip-flop is connected to the second fuse signal; the two clock terminals of the D flip-flop are respectively connected to the first read command signal and its inverted signal; the non-inverted output of the D flip-flop is connected to the input of the second transmission gate via the second inverter; the first control terminal of the first transmission gate and the second control terminal of the second transmission gate are connected to the first read command signal; the second control terminal of the first transmission gate and the first control terminal of the second transmission gate are connected to the inverted signal of the first read command signal; and the output terminals of the first and second transmission gates are connected to the same input of the two-stage conversion circuit. Specifically, when the first control terminal is at a high level and the second control terminal is at a low level, the first transmission gate and the second transmission gate are turned on; when the first control terminal is at a low level and the second control terminal is at a high level, the first transmission gate and the second transmission gate are turned off.

6. The fuse detection circuit according to claim 4, characterized in that, The second read command signal is the superposition of the first delayed signal and the second delayed signal of the first read command signal. The delay time of the first delayed signal is greater than the level switching time of the first read command signal and less than the pulse width of the first read command signal. The time difference between the delay time of the first delayed signal and the delay time of the second delayed signal is equal to the time difference between adjacent pulses of the sampling clock signal within one sampling period.

7. The fuse detection circuit according to claim 6, characterized in that, The secondary conversion circuit includes at least one sampling circuit and at least one output circuit; For each sampling circuit: multiple input terminals of the sampling circuit are connected one-to-one with the output terminals of multiple signal merging circuits, the control terminal of the sampling circuit is connected to the second read command signal, and multiple output terminals of the sampling circuit are connected one-to-one with the multiple input terminals of an output circuit. For each output circuit: multiple control terminals of the output circuit are connected to multiple sampling clock signals in a one-to-one correspondence, and the output terminal of the output circuit is connected to one output terminal of the fuse detection circuit; The sampling circuit is configured to sample the received multiple fuse combination signals at the rising edge of the second read command signal to obtain multiple sample signals; wherein each sample signal includes the first fuse signal and the second fuse signal; The output circuit is configured to sequentially output the plurality of sampled signals according to the plurality of sampled clock signals to obtain a fuse output signal.

8. The fuse detection circuit according to claim 7, characterized in that, The sampling circuit includes multiple D flip-flops connected in parallel; For each D flip-flop: the input terminal of the D flip-flop is connected to the output terminal of a signal merging circuit, the two clock terminals of the D flip-flop are respectively connected to the second read command signal and its inverted signal, and the inverted output terminal of the D flip-flop is connected to the input terminal of an output circuit.

9. The fuse detection circuit according to claim 8, characterized in that, The output circuit includes multiple transmission gates, a third inverter, and a fourth inverter, with the number of transmission gates and the number of D flip-flops being equal. For each transmission gate: the first control terminal of the transmission gate is connected to the inverted signal of a sampling clock signal, the second control terminal of the transmission gate is connected to the sampling clock signal, and the input terminal of the transmission gate is connected to the inverted output terminal of a D flip-flop; The outputs of the plurality of transmission gates are connected to the input of the third inverter and the output of the fourth inverter, and the output of the third inverter and the input of the fourth inverter are connected to the same output of the fuse detection circuit.

10. A memory, characterized in that, It includes multiple storage arrays and the fuse detection circuit according to any one of claims 1-9.

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