A method for determining and restoring the state of an eMMC chip, an electronic device, and a medium.

Abstract

This application discloses a method, electronic device, and medium for determining and restoring the state of an eMMC chip. First, based on a preset voltage bias value, and with the eMMC chip's I / O power supply VCCQ normally powered, the host performs a voltage bias operation on the eMMC chip's power supply VCC. When the current state information of the eMMC chip indicates that it is not in data transmission mode, the voltage bias value is compared with a preset first voltage threshold. If the comparison result shows that the voltage bias value is less than the first voltage threshold, it is further determined whether the eMMC chip is in a reset state. If the eMMC chip is in a reset state, a state restoration operation is performed. This application can accurately locate the chip's operating state when an anomaly occurs, effectively identify abnormal reset situations, and ensure reliable state restoration after chip reset, improving the accuracy of eMMC chip VCC bias testing and the efficiency of problem diagnosis.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of embedded storage technology, and particularly to a method for determining and restoring the state of an eMMC chip, an electronic device, and a medium. Background Technology

[0002] Embedded Multi-Media Cards (eMMCs) contain two independent power supply systems: a core power supply (VCC) and an interface I / O power supply (VCCQ). VCC powers the NAND Flash memory. In practical applications, VCC voltage is prone to momentary drops due to factors such as poor grounding, high-current transient load shedding, or PMIC regulation lag. Current traditional eMMC chip power supply testing methods, when performing VCC voltage pull-off tests, mostly focus on whether the chip can ultimately operate normally, failing to accurately identify the chip's specific operating state at the time of the fault. They struggle to distinguish between different scenarios such as idle and data transmission, making it difficult to quickly pinpoint the root cause of the problem. Furthermore, traditional tests simply verify whether the chip can recover after VCC pull-off, without verifying the compliance of the reset behavior as required by relevant protocols. They also lack effective verification of the chip's recovery process after reset, failing to promptly detect functional defects such as abnormal resets. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This application provides a method, electronic device, and medium for determining and restoring the state of an eMMC chip, which can accurately identify abnormal reset situations of the eMMC, quickly locate fault states, and achieve reliable state recovery.

[0005] This application provides a method for determining and restoring the state of an eMMC chip, comprising: according to a preset voltage bias value, under normal power supply conditions of the eMMC chip's I / O power supply VCCQ, performing a voltage bias operation on the eMMC chip's power supply VCC via a host; reading the current state information of the eMMC chip; if the current state information indicates that the eMMC chip is not in a data transmission state, comparing the voltage bias value with a preset first voltage threshold to obtain a comparison result; if the comparison result shows that the voltage bias value is less than the first voltage threshold, determining whether the eMMC chip is in a reset state; and if the eMMC chip is in a reset state, performing a state restoration operation on the eMMC chip.

[0006] In one embodiment of this application, the state recovery operation performed on the eMMC chip includes: restoring the state of the eMMC chip to a data transmission state, and maintaining the data transmission mode between the eMMC chip and the host as HS400 mode.

[0007] In one embodiment of this application, determining whether the eMMC chip is in a reset state includes: sending a first interaction instruction to the eMMC chip through the host, and receiving the operation condition register value returned by the first interaction instruction; if the operation condition register value returned by the first interaction instruction is a preset value, determining that the eMMC chip is in a reset state; if the operation condition register value returned by the first interaction instruction is not a preset value, determining that the eMMC chip is not in a reset state.

[0008] In one embodiment of this application, the preset value includes at least one of the following: 0x80FF8080, 0xC0FF8080.

[0009] In one embodiment of this application, reading the current status information of the eMMC chip includes: sending a second interaction instruction to the eMMC chip through the host, and receiving device status register data returned by the second interaction instruction; obtaining the current status information of the eMMC chip based on the device status register data.

[0010] In one embodiment of this application, the voltage bias value ranges from 1.8V to 3.3V, and the first voltage threshold is 2.7V.

[0011] In one embodiment of this application, the method further includes: determining the corresponding data loss permission based on the working state of the eMMC chip during the voltage pull-up operation.

[0012] In one embodiment of this application, the working state of the eMMC chip includes at least one of the following: the state during the execution of a write operation, and the state after the write operation is completed.

[0013] On the other hand, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the method described above.

[0014] On the other hand, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0015] This application provides a method for determining and restoring the state of an eMMC chip, an electronic device, and a computer-readable storage medium. The method first performs a voltage biasing operation on the eMMC chip's power supply VCCQ via the host, based on a preset voltage bias value, while the eMMC chip's I / O power supply VCCQ is normally powered. After reading the current state information of the eMMC chip, if the current state information indicates that the eMMC chip is not in a data transmission state, the voltage bias value is compared with a preset first voltage threshold. If the comparison result shows that the voltage bias value is less than the first voltage threshold, it is further determined whether the eMMC chip is in a reset state. If the eMMC chip is in a reset state, a state restoration operation is performed on the eMMC chip. This application embodiment performs a voltage biasing operation on the VCC of the eMMC chip when VCCQ is normally powered, reads the chip's current status information, and combines the voltage biasing value with a preset threshold to determine whether the chip has been abnormally reset and performs state recovery. This can accurately locate the chip's working state when the abnormality occurs, effectively identify abnormal reset situations that do not meet protocol requirements, and ensure that the chip can reliably complete state recovery after reset, thereby improving the accuracy of eMMC chip VCC biasing test and the efficiency of problem troubleshooting. Attached Figure Description

[0016] Figure 1 This is a flowchart of the eMMC chip state determination and recovery method provided in the embodiments of this application; Figure 2 This is a schematic diagram illustrating the interaction between the host and the eMMC chip provided in an embodiment of this application; Figure 3 This is a flowchart of a method for determining and restoring the state of an eMMC chip according to a specific embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] It should be noted that although the flowchart shows a logical order, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. The terms "first," "second," etc., used in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the structures, proportions, sizes, etc., depicted in the drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and purposes achieved by this application, should still fall within the scope of the technical content disclosed in this application. Similarly, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are only for clarity of description and are not used to limit the scope of implementation of this application. Changes or adjustments in their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this application.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] eMMC chips have two independent power supply systems, VCC and VCCQ. In actual use, the VCC voltage is easily affected by external operating conditions, causing momentary drops. Current traditional eMMC chip power supply testing methods, when performing VCC voltage pull-off tests, mostly focus only on whether the chip can ultimately operate normally, failing to accurately identify the specific operating state of the chip at the time of the fault. They struggle to distinguish between different scenarios such as idle and data transmission, making it difficult to quickly pinpoint the root cause of the problem. Furthermore, traditional tests simply verify whether the chip can recover after VCC pull-off, without verifying the compliance of the reset behavior as required by relevant protocols, and lack effective verification of the chip's state recovery process after reset, making it impossible to promptly detect functional defects such as abnormal resets.

[0021] In view of this, embodiments of this application provide a method for determining and restoring the state of an eMMC chip, an electronic device, and a computer-readable storage medium. The method first performs a voltage biasing operation on the eMMC chip's power supply VCCQ via the host, based on a preset voltage biasing value, while the eMMC chip's I / O power supply VCCQ is normally powered. After reading the current state information of the eMMC chip, if the current state information indicates that the eMMC chip is not in a data transmission state, the voltage biasing value is compared with a preset first voltage threshold. If the comparison result shows that the voltage biasing value is less than the first voltage threshold, it is further determined whether the eMMC chip is in a reset state. If the eMMC chip is in a reset state, a state restoration operation is performed on the eMMC chip. This application embodiment performs a voltage biasing operation on the VCC of the eMMC chip when VCCQ is normally powered, reads the chip's current status information, and combines the voltage biasing value with a preset threshold to determine whether the chip has been abnormally reset and performs state recovery. This can accurately locate the chip's working state when the abnormality occurs, effectively identify abnormal reset situations that do not meet protocol requirements, and ensure that the chip can reliably complete state recovery after reset, thereby improving the accuracy of eMMC chip VCC testing and the efficiency of problem troubleshooting.

[0022] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0023] Reference Figure 1 , Figure 1 This is a flowchart of the state determination and recovery method for an eMMC chip provided in the embodiments of this application. The process may specifically include, but is not limited to, steps 110 to 150.

[0024] Step 110: According to the preset voltage bias value, under the condition that the I / O power supply VCCQ of the eMMC chip is normally powered, the host performs a voltage bias operation on the power supply VCC of the eMMC chip. Step 120: Read the current status information of the eMMC chip; Step 130: If the current status information indicates that the eMMC chip is not in the data transmission state, compare the voltage bias value with the preset first voltage threshold to obtain the comparison result; Step 140: If the comparison result shows that the voltage bias value is less than the first voltage threshold, determine whether the eMMC chip is in a reset state; Step 150: Perform a state recovery operation on the eMMC chip while it is in a reset state.

[0025] Steps 110 to 150 will be described in detail below.

[0026] In one feasible embodiment, the I / O power supply (VCCQ) of the eMMC chip refers to the power supply that powers the internal controller and I / O interface of the chip, while the power supply (VCC) refers to the power supply that powers the internal NAND Flash of the chip. The two are independent of each other.

[0027] In one feasible embodiment, the voltage bias value is set between 1.8V and 3.3V, where 2.7V to 3.3V is the normal operating voltage range of VCC specified by the eMMC protocol. Within this range, the chip should maintain stable operation and should not be allowed to trigger a reset. The first voltage threshold adopts the lower limit of the standard operating voltage specified by the protocol, which is 2.7V.

[0028] In one feasible embodiment, based on a pre-set voltage bias value, and ensuring that the VCCQ of the eMMC chip remains under normal power supply without voltage anomalies or power interruptions, the host computer outputs the target bias voltage to the VCC of the eMMC chip. This simulates a test scenario where the chip's supply voltage deviates from the standard rated value in a real-world operating environment, particularly addressing typical conditions where VCC experiences a momentary drop during actual use. The host computer is a primary computer or hardware controller used to control the overall test execution process, issue various communication and control commands to the eMMC chip, and adjust the output supply voltage. It is also the core control unit that establishes a communication connection with the eMMC chip and reads and analyzes the chip's status information in real time.

[0029] In one feasible embodiment, after the host performs a voltage biasing operation on the power supply VCC of the eMMC chip, a fixed delay waiting time can be set, such as 50ms, so that the power supply circuit, status register and related control logic inside the eMMC chip can be fully stabilized after the voltage changes. This avoids the situation where the status query or reset judgment operation is performed immediately after the voltage biasing is completed and the internal state of the chip has not yet stabilized, which would lead to inaccurate status information and misjudgment of the judgment result.

[0030] In one feasible embodiment, reading the current status information of the eMMC chip specifically involves: the host sending a second interaction command to the eMMC chip, and obtaining the current status information of the eMMC chip based on the device status register data returned by the command. The second interaction command is the CMD13 command, a standard status query command explicitly defined in the eMMC protocol. Its core function is to provide the host with a way to query the current real-time operating status of the eMMC chip without interrupting the chip's normal operation, allowing for quick and accurate acquisition of the chip's operating status feedback. During this process, the CMD13 command correctly returns complete information from the device status register according to the eMMC protocol specification. By parsing the various status bits contained in the device status register, the host can monitor and determine the specific operating status of the eMMC chip in real time, such as idle state (i.e., the chip is not performing any read, write, or transmission operations and is in a standby state) or data transmission state (i.e., the chip is performing data reading or writing / transmission operations), providing a status basis for subsequent voltage bias judgment, reset detection, and status recovery operations.

[0031] In one feasible embodiment, when the current status information indicates that the eMMC chip is in the data transmission state, the chip may be performing data read, write, transmission and other related operations. In order to avoid the voltage pull operation interfering with normal data transmission, causing data errors or abnormal chip operation, the subsequent voltage pull detection, reset judgment and status recovery processes can be directly terminated and exited, and the subsequent test operations will no longer be performed, so as to ensure the integrity of chip data transmission and working stability.

[0032] In one feasible embodiment, when the status information clearly indicates that the eMMC chip is not currently in data transmission mode, it means that the chip has exited the normal data transmission working mode and entered an idle or standby state for voltage pull-up testing. At this time, the preset target voltage pull-up value is compared with a first voltage threshold (2.7V). If the voltage pull-up value is less than the first voltage threshold, it is further determined whether the eMMC chip is in a reset state. Specifically, when the voltage pull-up value is set to less than 2.7V, it means that the VCC supply voltage has been pulled outside the normal operating voltage range specified by the eMMC chip. According to the chip's electrical characteristics and protocol specifications, the chip should trigger and enter a reset state. Therefore, this test step needs to focus on verifying whether the chip's reset behavior is executed normally as expected.

[0033] In a feasible embodiment, if the currently set voltage bias value is greater than or equal to the first voltage threshold of 2.7V, it indicates that the main power supply VCC of the eMMC chip is still within the normal operating voltage range specified by the eMMC protocol after the bias operation is performed. Under this premise that the power supply conditions meet the specifications, since the chip has exited the normal data transmission mode, in order to avoid invalid detection and misjudgment, the current reset detection and subsequent related processes can be directly exited, and subsequent status judgment and operation steps will not be continued.

[0034] In a feasible embodiment, when the voltage bias is set to less than 2.7V, it means that the VCC supply voltage of the eMMC chip has been pulled outside the normal operating voltage range specified in the protocol. At this time, it can be further determined whether the eMMC chip is in a reset state. The specific determination method is as follows: the host sends a first interactive command to the eMMC chip, and the determination is made based on the operation condition register value returned by the command. If the returned operation condition register value is a preset value, it can be determined that the eMMC chip was in a reset state before sending the first interactive command. If the returned operation condition register value is not a preset value, it can be determined that the eMMC chip, under a supply voltage exceeding the normal operating range, has neither entered a reset state nor a data transmission state, and at this time, it is determined that the chip is not in a reset state. The first interactive command is specifically the CMD1 command, which is a standard command defined in the eMMC protocol. It is mainly used by the host to query the chip's operating conditions and the matching status of the supply voltage with the chip's operating requirements. During the query process, the CMD1 instruction will correctly return the corresponding operation condition register value according to the protocol specification. When the register returns the preset value, it indicates that the current power supply voltage meets the basic operating requirements of the eMMC chip, the chip has completed basic initialization and entered the ready condition, which means that the eMMC chip was already in the reset state before sending the CMD1 instruction.

[0035] In a feasible embodiment, the preset value includes at least one of the following: 0x80FF8080, 0xC0FF8080. That is, when the operation condition register value returned by CMD1 is 0x80FF8080 or 0xC0FF8080, it can be determined that the eMMC chip was already in a reset state before sending the CMD1 instruction.

[0036] In a feasible embodiment, once the eMMC chip is determined to have entered a reset state, a state recovery operation can be performed on the eMMC chip to ensure that the chip can resume normal operation and stably carry out data transmission. The relevant operations of the state recovery operation include: restoring the eMMC chip to a data transmission state while maintaining the data transmission mode between the eMMC chip and the host in HS400 mode. Specifically, the host issues relevant control commands to initialize and configure the eMMC chip, restoring its current operating state from the reset state to the data transmission state. Simultaneously, throughout the entire state recovery process, the data transmission mode between the eMMC chip and the host is maintained in HS400 mode. That is, while the initialization operation returns the eMMC chip to the data transmission state, it ensures that the host and the eMMC chip always maintain the HS400 mode transmission specifications, i.e., using a 200MHz transmission frequency and an 8-wire data transmission channel, guaranteeing the data transmission rate and stability, and meeting the requirements of the eMMC protocol for the post-reset recovery process.

[0037] In a feasible embodiment, when the eMMC chip resets due to VCC voltage bias, to ensure the chip can stably recover to HS400 mode and achieve full-specification data transmission, the mode recovery operation can be performed step by step according to the following specific sequence: Switching the operating mode: The host resends the CMD6 command to the eMMC chip, triggering the chip to switch its operating mode, explicitly switching the chip's operating mode to HS400 mode; Configuring the bus width: Continue to configure parameters using the CMD6 command, setting the communication bus width between the eMMC chip and the host to 8 bits to ensure that the width of the data transmission channel meets the transmission requirements of HS400 mode; Adjusting the clock frequency: After completing the mode switching and line width configuration, increase the communication clock frequency between the host and the eMMC chip to 200MHz to keep the clock frequency consistent with the standard requirements of HS400 mode. After completing the above three steps, the transmission status of the eMMC chip can be finally verified to confirm that the chip has successfully recovered to HS400 mode and can stably achieve a full-specification data transmission rate of 200MHz frequency and 8-wire bus, ensuring that the chip's transmission performance after reset meets the requirements of the eMMC protocol and actual application needs.

[0038] In a feasible embodiment, in the state determination and recovery process of the eMMC chip, in addition to completing the chip state detection and working mode recovery, the actual working state of the eMMC chip during the voltage pull-up operation, such as whether the chip is triggered and enters the reset state during the VCC voltage pull-up operation, can be combined to determine the data loss permission involved in this operation, thereby distinguishing the data integrity requirements under different test scenarios. For example, if the VCC voltage pull-up operation is set during or after a write operation on the eMMC chip, the test procedure can first use the CMD13 command to query and determine whether the eMMC chip is currently in a reset state. If the current status information returned by the CMD13 command clearly indicates that the eMMC chip is still in data transmission state, it means that the chip did not reset during the voltage pull-up process and is still maintaining normal data transmission operation. In this case, data integrity must be strictly guaranteed, and no data loss or damage is allowed. If it is confirmed after testing that a state recovery operation needs to be performed on the eMMC chip to restore it from the reset state to normal operating mode, it means that the eMMC chip was reset due to abnormal power supply caused by VCC voltage pull-up during or after the write operation. In this abnormal reset scenario, the relevant data corresponding to this write operation is allowed to be lost.

[0039] like Figure 2 As shown, the interaction between the host and the eMMC can be achieved through three parts. First, the power supply: the host supplies power to the eMMC's main power supply VCC via a control voltage module. This module can adjust the voltage according to the host's commands, simulating standard power supply and voltage pull-off scenarios, while the I / O power supply VCCQ remains unaffected, ensuring normal basic communication between the host and the eMMC. Second, the command interaction: the host and eMMC communicate bidirectionally via the CMD transmission line. The host can issue commands such as CMD1, CMD13, and CMD6 to query chip status, check reset status, or configure operating modes; the eMMC also returns register values ​​through this line, allowing the host to monitor the chip's real-time status. Finally, the data transmission: the host and eMMC complete data read / write operations via the DAT transmission line, supporting high-speed transmission in HS400 mode during normal operation. During voltage pull-off testing, the host also determines whether the chip is performing read / write operations based on the status of the data transmission line, thus determining whether data loss is permissible. These three parts work together to complete the voltage pull-off test, status judgment, and mode recovery of the eMMC.

[0040] The present application will now be described with reference to a specific embodiment.

[0041] In this embodiment, after constructing the controllable bias test environment and setting the VCC voltage bias value, a 50ms delay is first set to allow the VCC voltage to fully recover and stabilize after the bias operation before performing a VCC voltage range stability test. The judgment criterion for this test is: when the target voltage bias value is greater than or equal to 2.7V, the eMMC chip should not exhibit any operational abnormalities, i.e., the chip should maintain normal operation; otherwise, it is considered abnormal. Throughout the entire testing process, the status determination will be completed using CMD13 and CMD1 instructions, combined with... Figure 3 The architecture shown is implemented as follows: Step 1: Set up a controllable voltage drop test environment based on the Host test board, complete the connection between the eMMC chip and the host, set the target value of VCC voltage drop for this test, and prepare to execute the voltage drop test.

[0042] Step 2: After performing the voltage biasing operation, set a fixed delay of 50ms to wait for the VCC power supply voltage to stabilize. This is to avoid performing the status query immediately after the voltage biasing is completed and the internal state of the chip has not yet stabilized, which could lead to misjudgment of the judgment result.

[0043] Step 3: The host sends a CMD13 command to the eMMC chip to query whether the chip is currently in the Trans (data transmission) state. If the query result shows that the chip is in the Trans state, it means that the chip is still maintaining normal data transmission operation after the voltage is pulled back, and the detection process is exited and jumps to step 7 to perform data verification; if the query result shows that the chip is not in the Trans state, it means that the chip has exited the normal data transmission state, and the detection continues in step 4.

[0044] Step 4: After confirming with CMD13 that the chip has exited the data transmission state, compare the target VCC drop value of this test with the standard operating voltage lower limit of 2.7V specified by the eMMC protocol: If the target value of VCC drop is greater than or equal to 2.7V, it means that the VCC power supply voltage is still within the normal operating voltage range specified in the protocol after being pulled off, but the chip has exited the normal data transmission state and failed to maintain normal operation. At this time, it is determined that the VCC voltage range stability test has failed and the test process is terminated.

[0045] If the target value of VCC drop is less than 2.7V, it means that the VCC power supply voltage has been pulled outside the normal operating voltage range specified in the protocol. According to the chip's electrical characteristics and protocol specifications, the chip should be triggered and enter the reset state. At this time, proceed to step 5 to verify whether the chip's reset behavior is executed normally.

[0046] Step 5: The host sends a CMD1 command to the eMMC chip. The returned operation condition register value determines whether the chip was in a reset state before sending the CMD1 command. If the CMD1 command fails to send, or the returned operation condition register value is not the preset value, it indicates that the eMMC chip, under a supply voltage exceeding its normal operating range, neither entered a reset state nor was in a data transmission state. In this case, the VCC voltage range stability test is deemed a failure, and the test process exits. If the CMD1 command is successfully sent, and the returned operation condition register value is the preset value, it indicates that the chip had normally entered a reset state before sending the CMD1 command, and the process proceeds to Step 6 to perform the state recovery operation.

[0047] Step 6: Perform a state recovery operation on the eMMC chip that has entered the reset state. The host sends an initialization command to restore the chip's working state to the Trans state. At the same time, during the recovery process, the chip's working mode and bus parameters are configured through the CMD6 command to ensure that the data transmission method between the host and the eMMC chip remains in HS400 mode, that is, a full-specification configuration of 200MHz clock frequency and 8-line parallel transmission. After the state recovery operation is executed without error, proceed to Step 7 to perform data verification.

[0048] Step 7: Perform data verification. Since this VCC voltage bias setting is performed during or after a write operation on the eMMC chip, the test program will determine the data loss permission based on the current flow's source branch: If the flow jumps from Step 3 (chip not reset, still in data transmission state), it means the chip did not reset during the voltage bias process and maintained normal data transmission operation. In this case, data integrity must be guaranteed, and no data loss is allowed; if the flow enters from Step 6 (chip reset and state recovery), it means the chip was reset during or after a write operation due to abnormal power supply caused by VCC voltage bias. In this abnormal reset scenario, data loss corresponding to this write operation is allowed, and the data verification process can be completed according to preset rules.

[0049] The beneficial effects of the embodiments of this application include at least the following: (1) Comprehensive stability verification of eMMC chips under VCC voltage pull-off scenarios was achieved. The test scenario was divided into a working area and a reset area, and different verification logic was executed for the two areas respectively. The working area corresponds to a voltage pull-off value greater than or equal to 2.7V. At this time, the chip can maintain normal working state and does not have an abnormality of unexpected data transmission exit. The reset area corresponds to a voltage pull-off value less than 2.7V. At this time, the chip can trigger the reset normally according to the specification. This ensures that the verification logic under different power supply scenarios is accurately matched and avoids test omissions. The whole process starts from building a controllable pull-off test environment. By setting a delay to wait for the voltage to stabilize, and then combining multiple rounds of instruction query and voltage comparison, the working state of the chip under different power supply conditions is verified in layers. It can not only detect the anti-interference capability of the chip within the specified voltage range, but also verify whether its reset logic is normal when the voltage drops to outside the working range. This avoids the problem of incomplete testing caused by focusing on only a single indicator in traditional testing.

[0050] (2) The 50ms delay allows the voltage after biasing to stabilize sufficiently, avoiding the impact of voltage fluctuations on the state determination and effectively improving the accuracy of the test results. Simultaneously, the combined query method using CMD13 and CMD1 instructions can accurately distinguish whether the chip is in data transmission state, whether it has entered the reset state normally, and whether it is in an abnormal working condition that neither resets nor works. This solves the problem that traditional single-instruction detection cannot cover complex scenarios, making the state determination more reliable. It is worth noting that in this embodiment, after the chip is reset, it does not only perform simple device identification, but completely simulates the three stages of host initialization, frequency switching, and data verification. Initialization restores the chip to the data transmission state, frequency switching configures the transmission parameters of the HS400 mode, and data verification ensures that the chip can work normally after restoration, comprehensively verifying the device availability after reset and avoiding subsequent operational anomalies caused by incomplete initialization after reset.

[0051] (3) The embodiments of this application can effectively screen out chip batches with insufficient power supply stability or problems with reset logic, and complete the screening of abnormal chips before the chips leave the factory, reducing the probability of terminal equipment failure due to chip problems. At the same time, it realizes the combination of test process and data verification logic. Based on whether the chip resets during the voltage pull-up process, the permission for data loss is dynamically determined. When the chip does not reset, the data integrity is strictly guaranteed and no data loss is allowed. When the chip resets due to voltage pull-up, it reasonably accommodates the data loss situation under abnormal scenarios, so that the test results can truly reflect the chip's performance in actual use, providing a reliable verification basis for the application of the chip in complex power supply environments. In this way, it can significantly reduce the risk of terminal equipment crashing and data corruption in complex power supply environments, and improve the stability and reliability of terminal equipment.

[0052] In addition, embodiments of this application also provide an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the method as in any of the preceding embodiments.

[0053] In addition, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any of the preceding embodiments.

[0054] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for determining and restoring the state of an eMMC chip, characterized in that, include: According to the preset voltage bias value, under the condition that the I / O power supply VCCQ of the eMMC chip is normally powered, the host performs a voltage bias operation on the power supply VCC of the eMMC chip. Read the current status information of the eMMC chip; If the current status information indicates that the eMMC chip is not in data transmission state, the voltage bias value is compared with a preset first voltage threshold to obtain a comparison result. If the comparison result shows that the voltage bias value is less than the first voltage threshold, determine whether the eMMC chip is in a reset state; When the eMMC chip is in a reset state, a state recovery operation is performed on the eMMC chip.

2. The method according to claim 1, characterized in that, The process of performing a state recovery operation on the eMMC chip includes: The state of the eMMC chip is restored to the data transmission state, and the data transmission mode between the eMMC chip and the host is maintained in HS400 mode.

3. The method according to claim 1, characterized in that, Determining whether the eMMC chip is in a reset state includes: The host sends a first interaction instruction to the eMMC chip and receives the operation condition register value returned by the first interaction instruction. If the value of the operation condition register returned by the first interactive instruction is a preset value, it is determined that the eMMC chip is in a reset state; If the value of the operation condition register returned by the first interactive instruction is not a preset value, it is determined that the eMMC chip is not in a reset state.

4. The method according to claim 3, characterized in that, The preset value includes at least one of the following: 0x80FF8080, 0xC0FF8080.

5. The method according to claim 1, characterized in that, The step of reading the current status information of the eMMC chip includes: The host sends a second interaction command to the eMMC chip and receives device status register data returned by the second interaction command. The current status information of the eMMC chip is obtained based on the data in the device status register.

6. The method according to claim 1, characterized in that, The voltage bias value ranges from 1.8V to 3.3V, and the first voltage threshold is 2.7V.

7. The method according to claim 1, characterized in that, The method further includes: Based on the operating state of the eMMC chip during the voltage biasing operation, the corresponding data loss permission is determined.

8. The method according to claim 7, characterized in that, The operating state of the eMMC chip includes at least one of the following: the state during the execution of a write operation, and the state after the write operation is completed.

9. An electronic device comprising a processor and a memory, characterized in that, The memory stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 8.

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