Methods for detecting memory devices and their data status and semiconductor devices

Abstract

A memory device and a method for detecting its data state are disclosed. One embodiment of the memory device includes: a memory cell array comprising a plurality of memory cells; and a plurality of groups of N bit lines arranged in association with corresponding columns of the memory cells in the memory cell array. Each memory cell in the memory cell array includes a transistor, and the two drain / source terminals of the transistor are electrically coupled to the same bit line or two bit lines in the corresponding group of N bit lines in the plurality of groups of N bit lines, and the electrical coupling relationship between the two drain / source terminals and the corresponding group of N bit lines indicates one of the candidate information states.

Description

Technical Field

[0001] One embodiment of this disclosure relates to a memory device and a method for detecting the data state of memory cells in the memory device, particularly to a memory device having candidate information states and a method for detecting the data state of memory cells in the memory device. Background Technology

[0002] Modern integrated circuit (IC) manufacturing technology has enabled faster, smaller, and more efficient devices. In many applications, the size of electrical components and transistors has shrunk to include more elements in a semiconductor die, or even more layers of elements in a semiconductor die. These advances in IC manufacturing technology have enabled the development of a wide variety of digital devices, such as semiconductor devices that include one or more memory devices for storing information.

[0003] In some applications, one or more memory devices are implemented based on one or more types of memory technologies corresponding to one or more of the following: read-only memory (ROM) devices, erasable programmable read-only memory (EEPROM) devices, static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, or similar. In some applications, ROM devices are used to store fixed information that cannot be changed after the ROM device is manufactured. In some applications, ROM devices are non-volatile memory devices because the stored information is retained even when power is removed from the ROM device. There is also research on increasing the data density of each memory cell in a ROM device to increase storage capacity and / or reduce the size of the ROM device. Summary of the Invention

[0004] In some embodiments, a memory device includes a memory cell array comprising a plurality of memory cells arranged in columns and rows, a plurality of word lines arranged in association with corresponding columns of memory cells in the memory cell array, and a plurality of sets of N bit lines arranged in association with corresponding rows of memory cells in the memory cell array, where N is an integer equal to or greater than 3. Each memory cell in the memory cell array includes a transistor including a gate terminal and two drain / source terminals. The gate terminal is electrically coupled to a corresponding word line among the plurality of word lines, and the two drain / source terminals are electrically coupled to the same bit line or two bit lines in corresponding sets of N bit lines among the plurality of sets of N bit lines, and the electrical coupling relationship between the two drain / source terminals and the corresponding sets of N bit lines indicates... One of the candidate information states. Candidate information states include those of the N bit lines electrically coupled to the corresponding group. The two drain / source terminals of different parasite lines correspond to Candidate information states, and these candidate information states include one candidate information state corresponding to N different cases of two drain / source terminals of the same bit line electrically coupled to the N bit lines of the corresponding group.

[0005] In some embodiments, a method for detecting the information state of a memory cell in a memory device includes: in a precharge stage, electrically coupling the first bit line to the (N-1)th bit line of a set of N bit lines arranged in association with the memory cell of the memory device to a first power node carrying a first supply voltage, where N is an integer equal to or greater than 3, wherein the Nth bit line of this set of N bit lines is used to carry a second supply voltage. The memory cell includes a transistor, the transistor including a gate terminal and two drain / source terminals, and the electrical coupling relationship between the two drain / source terminals and the set of N bit lines indicates the information state of the memory cell. This method includes applying a word line signal to the gate terminal of the transistor to turn on the transistor, and detecting the electrical coupling relationship between the two drain / source terminals and the set of N bit lines based on (N-1) read stages. The (N-1) read stages include, during the first read stage of the (N-1) read stages, determining, based on the discharge state of the first bit line up to the (N-1) bit line, that one of the two drain / source terminals is electrically coupled to the Nth bit line, and the other of the two drain / source terminals is electrically coupled to one of the first bit line up to the (N-1) bit line. The (N-1) read stages include: for each index i ranging from 2 to (N-1), performing the i-th read stage of the (N-1) read stages, including electrically coupling the (N-i+1)-th bit line to a second power node carrying a second supply voltage during the i-th read stage; and during the i-th read stage, determining, based on the discharge state of the first bit line up to the (Ni)-th bit line, that one of the two drain / source terminals is electrically coupled to the (N-i+1)-th bit line and the other of the two drain / source terminals is electrically coupled to one of the first bit lines up to the (Ni)-th bit lines, or, based on the discharge state of the first bit line up to the (Ni)-th bit line and based on i being (N-1), determining that the two drain / source terminals are electrically coupled to the same bit line in a set of N bit lines.

[0006] In some configurations, the semiconductor device includes N conductive lines configured as N bit lines, another conductive line configured as a word line, and a first memory cell including a first transistor. This first transistor includes a first gate terminal and two first drain / source terminals, where N is an integer equal to or greater than 3. The first gate terminal is electrically coupled to the word line. The two first drain / source terminals are electrically coupled to the same bit line among the N bit lines or between two bit lines, indicating a first information state of the first memory cell. This first information state is... One of the candidate information states. Candidate information states include those electrically coupled to N bit lines. The two first drain / source terminals of different parasite lines correspond to A candidate information state, and a candidate information state corresponding to N different cases of the two drain / source terminals of the same bit line electrically coupled to N bit lines. Attached Figure Description

[0007] An embodiment of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0008] Figure 1 This is a schematic block diagram of a memory device according to some embodiments;

[0009] Figure 2A This is a schematic diagram of a memory cell associated with a set of bit lines according to some embodiments;

[0010] Figure 2B According to some embodiments Figure 2A A simplified table of candidate information states for memory cells in the memory;

[0011] Figure 2C Including those with various electrical coupling settings according to some embodiments. Figure 2A A schematic diagram of memory cells in a computer.

[0012] Figure 2D This is a summary based on some embodiments. Figure 2C A table of candidate information states for various electrical coupling settings;

[0013] Figure 3A It is a schematic block diagram of a memory device based on a first output circuit system configuration according to some embodiments;

[0014] Figure 3B According to some embodiments Figure 3A A schematic diagram of a portion of a memory device, the memory device including columns of memory cells associated with a set of bit lines, and including a portion of an output circuitry system of the memory device electrically coupled to this set of bit lines;

[0015] Figure 3C According to some embodiments Figure 3B A schematic diagram of a portion of the output circuitry system of the memory device in the diagram;

[0016] Figure 4A It is for control according to some embodiments Figure 3B Timing diagram of various control signals in the readout circuit system during the readout cycle;

[0017] Figures 4B to 4EBased on some embodiments, it is based on detecting different information states. Figure 3B Timing diagrams of signals at each terminal of the readout circuit system;

[0018] Figure 5A This is a schematic diagram of a portion of a memory device according to some embodiments, the memory device including columns of memory cells associated with a set of bit lines, and including a portion of an output circuitry system of the memory device electrically coupled to the set of bit lines.

[0019] Figure 5B According to some embodiments Figure 5A A schematic diagram of a portion of the output circuitry system of the memory device in the diagram;

[0020] Figure 5C It is for control according to some embodiments Figure 5B Timing diagram of various control signals in the readout circuit system during the readout cycle;

[0021] Figure 6A This is a schematic diagram of a portion of a memory device according to some embodiments, the memory device including columns of memory cells associated with a set of bit lines, and including a portion of an output circuitry system of the memory device electrically coupled to the set of bit lines.

[0022] Figure 6B According to some embodiments Figure 6A A schematic diagram of a portion of the output circuitry system of the memory device in the diagram;

[0023] Figure 7 This is a schematic diagram of a portion of a memory device according to some embodiments, the memory device including columns of memory cells associated with a set of bit lines, and including a portion of an output circuitry system of the memory device electrically coupled to the set of bit lines.

[0024] Figures 8A to 8C This is a schematic diagram of an example of an output circuit system including a holder according to some embodiments;

[0025] Figures 9A to 9B This is a schematic diagram of a decoder instance according to some embodiments;

[0026] Figure 10A This is a schematic diagram of a subarray comprising two memory cells based on n-type transistors and associated with a set of bit lines, according to some embodiments;

[0027] Figure 10B Including those with various electrical coupling settings according to some embodiments. Figure 10A A schematic diagram of memory cells in a computer.

[0028] Figure 11A This is a schematic diagram of a subarray comprising two memory cells based on p-type transistors and associated with a set of bit lines, according to some embodiments;

[0029] Figure 11B Including those with various electrical coupling settings according to some embodiments. Figure 10A A schematic diagram of memory cells in a computer.

[0030] Figure 12A This is a schematic block diagram of a memory device 1200 configured based on a second output circuit system according to some embodiments;

[0031] Figure 12B This is a schematic diagram of a portion of a memory device according to some embodiments, the memory device including columns of memory cells associated with a set of bit lines, and including a readout circuitry system;

[0032] Figure 12C This is a schematic diagram of a portion of another memory device according to some embodiments, the memory device including columns of memory cells associated with a set of bit lines, and including a readout circuitry system;

[0033] Figure 13 This is a flowchart of a method for detecting the information status of memory cells in a memory device according to some embodiments;

[0034] Figure 14 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments.

[0035] [Symbol Explanation]

[0036] 100: Memory Device

[0037] 110: Memory Cell Array

[0038] 120: Control circuit system

[0039] 122: Word line drive circuit system

[0040] 124: Input / Output Circuit System

[0041] 124A: Output Circuit System

[0042] 124B: Output Circuit System

[0043] 126: Controller

[0044] 210: Memory Unit

[0045] 212: Transistor

[0046] 212a: Drain / Source terminal

[0047] 212b: Drain / Source terminal

[0048] 212c: Gate terminal

[0049] 220: Simplified Table

[0050] 222: Area

[0051] 224: Area

[0052] 226: Area

[0053] 231: Schematic diagram

[0054] 232: Schematic diagram

[0055] 233: Schematic diagram

[0056] 234: Schematic diagram

[0057] 235: Schematic diagram

[0058] 236: Schematic diagram

[0059] 237: Schematic diagram

[0060] 238: Schematic diagram

[0061] 239: Schematic diagram

[0062] 240: Table

[0063] 300: Memory device

[0064] 310[0]: Memory unit

[0065] 310[M-1]: Memory unit

[0066] 320: Output Circuit System

[0067] 322: Readout Circuit System

[0068] 324: Decoder

[0069] 332: First precharge transistor

[0070] 334: Second precharge transistor

[0071] 336: Discharge transistor

[0072] 342: Unit metadata sampling device

[0073] 344: Unit metadata sampling device

[0074] 346: Unit metadata sampling device

[0075] 410: Timing Diagram

[0076] 412: Curve

[0077] 414: Curve

[0078] 416: Curve

[0079] 417: Curve

[0080] 418: Curve

[0081] 420: Timing Diagram

[0082] 421: Schematic diagram

[0083] 422: Curve

[0084] 423: Curve

[0085] 424: Curve

[0086] 426: Curve

[0087] 428: Curve

[0088] 430: Timing Diagram

[0089] 431: Schematic diagram

[0090] 432: Curve

[0091] 433: Curve

[0092] 434: Curve

[0093] 436: Curve

[0094] 438: Curve

[0095] 440: Timing Diagram

[0096] 441: Schematic diagram

[0097] 442: Curve

[0098] 443: Curve

[0099] 444: Curve

[0100] 446: Curve

[0101] 448: Curve

[0102] 450: Timing Diagram

[0103] 451: Schematic diagram

[0104] 452: Curve

[0105] 453: Curve

[0106] 454: Curve

[0107] 456: Curve

[0108] 458: Curve

[0109] 500: Memory Device

[0110] 510[0]: Memory unit

[0111] 510[M-1]: Memory unit

[0112] 520: Output Circuit System

[0113] 522: Readout Circuit System

[0114] 524: Decoder

[0115] 532: Precharge transistor

[0116] 534: Precharged transistor

[0117] 536: Precharge transistor

[0118] 542: Discharge transistor

[0119] 544: Discharge transistor

[0120] 550: Unit metadata sampling device

[0121] 560: Time Series Diagram

[0122] 562: Curve

[0123] 563: Curve

[0124] 564: Curve

[0125] 565: Curve

[0126] 566: Curve

[0127] 567: Curve

[0128] 568: Curve

[0129] 600: Memory Device

[0130] 610[0]: Memory unit

[0131] 610[M-1]: Memory unit

[0132] 620: Output Circuit System

[0133] 622: Readout Circuit System

[0134] 624: Decoder

[0135] 632: First precharge transistor

[0136] 634: Second precharge transistor

[0137] 636: Discharge transistor

[0138] 642: Unit metadata sampling device

[0139] 644: Unit metadata sampling device

[0140] 646: Unit metadata sampling device

[0141] 700: Memory Device

[0142] 710[0]: Memory unit

[0143] 710[M-1]: Memory unit

[0144] 720: Output Circuit System

[0145] 800A: Example of Output Circuit System

[0146] 800B: Example of an Output Circuit System

[0147] 800C: Example of an Output Circuit System

[0148] 810: Holder

[0149] 812: p-type transistor

[0150] 814: Inverter

[0151] 816: p-type transistor

[0152] 818: NAND gate

[0153] 820: Holder

[0154] 822: p-type transistor

[0155] 823: Inverter

[0156] 824: p-type transistor

[0157] 825: NAND gate

[0158] 826: p-type transistor

[0159] 827: NAND gate

[0160] 830: Retainer

[0161] 832: n-type transistor

[0162] 834: Inverter

[0163] 836: n-type transistor

[0164] 838: NOR gate

[0165] 900A: First Decoder Instance

[0166] 900B: Second Decoder Instance

[0167] 912: NAND gate

[0168] 914: NAND gate

[0169] 916: NAND gate

[0170] 924: Inverter

[0171] 932: NOR gate

[0172] 934: NAND gate

[0173] 936: NAND gate

[0174] 942: Inverter

[0175] 944: Inverter

[0176] 946: Inverter

[0177] 1000: Subarray

[0178] 1010: Memory unit

[0179] 1012: n-type transistor

[0180] 1012a: Common drain / source terminal

[0181] 1012b: Common drain / source terminal

[0182] 1020: Memory Unit

[0183] 1022: n-type transistor

[0184] 1022b: Common drain / source terminal

[0185] 1032: Dummy Transistor

[0186] 1032b: Drain / Source Terminal

[0187] 1034: Dummy Transistor

[0188] 1034b: Drain / Source Terminal

[0189] 1041: Schematic diagram

[0190] 1042: Schematic diagram

[0191] 1043: Schematic diagram

[0192] 1044: Schematic diagram

[0193] 1045: Schematic diagram

[0194] 1046: Schematic diagram

[0195] 1047: Schematic diagram

[0196] 1048: Schematic diagram

[0197] 1049: Schematic diagram

[0198] 1100: Subarray

[0199] 1110: Memory Unit

[0200] 1112: p-type transistor

[0201] 1112a: Common drain / source terminal

[0202] 1112b: Common drain / source terminal

[0203] 1120: Memory Unit

[0204] 1122: p-type transistor

[0205] 1122b: Common drain / source terminal

[0206] 1132: Dummy Transistor

[0207] 1132b: Drain / Source Terminal

[0208] 1134: Dummy Transistor

[0209] 1134b: Drain / Source Terminal

[0210] 1141: Schematic diagram

[0211] 1142: Schematic diagram

[0212] 1143: Schematic diagram

[0213] 1144: Schematic diagram

[0214] 1145: Schematic diagram

[0215] 1146: Schematic diagram

[0216] 1147: Schematic diagram

[0217] 1148: Schematic diagram

[0218] 1149: Schematic diagram

[0219] 1200: Memory device

[0220] 1200A: Memory device

[0221] 1200B: Memory Device

[0222] 1210[0]: Memory unit

[0223] 1210[M-1]: Memory unit

[0224] 1222: Readout Circuit System

[0225] 1230[0]: Memory unit

[0226] 1230[M-1]: Memory unit

[0227] 1242: Readout Circuit System

[0228] 1300: Method

[0229] 1310: Square

[0230] 1320: Square

[0231] 1330: Square

[0232] 1400: IC Manufacturing System

[0233] 1420: Design Studio

[0234] 1422: IC Design Layout Diagram

[0235] 1430: Shelter Room

[0236] 1432: Data Preparation

[0237] 1444: Mask Manufacturing

[0238] 1445: Mask

[0239] 1450: IC Manufacturer / Producer

[0240] 1452: Manufacturing Tools

[0241] 1453: Semiconductor wafers

[0242] 1460: IC device

[0243] VSS: Lower supply voltage

[0244] / PC: Precharge bar signal

[0245] A[*]: Address

[0246] BL[0]: Bit line

[0247] BL[1]: Bitline

[0248] BL[L-1]: Bit line

[0249] BL[#]_0: Bitline

[0250] BL[#]_1: Bitline

[0251] BL[#]_2(VSS): Bitline

[0252] BL[#]_2(VDD): Bit line

[0253] BL[#]_N-2: Bit line

[0254] BL[#]_N-1(VDD): Bit line

[0255] BLB[#]_0: Bit line

[0256] BLB[#]_1: Bitline

[0257] BLB[#]_2(VSS): Bitline

[0258] BLB[#]_2(VDD): Bitline

[0259] BLB[#]_N-1(VSS): Bitline

[0260] BLB[#]_N-1(VDD): Bit line

[0261] BLB[#]_N-2: Bit line

[0262] BLB[#]_N-3: Bit Line

[0263] BLB0: Bitline

[0264] BLB1: Bitline

[0265] CK[0:1]: Sampling clock signal

[0266] CK[0:N-2]: Sampling clock signal

[0267] CK[0]: Sampling clock signal

[0268] CK[N-1]: Sampling clock signal

[0269] CK[N-2]: Sampling clock signal

[0270] CLK: System clock signal

[0271] DC: Discharge signal

[0272] DC[0:N-2]: Discharge signal

[0273] DC[0]: Discharge signal

[0274] DC[1]: Discharge signal

[0275] / DC: Discharge bar signal

[0276] D: Data Input Node

[0277] MC: Memory Unit

[0278] Net[0]: Bit line

[0279] Net[1]: Bitline

[0280] Net[N-1]: Bit line

[0281] O[#]_[0:1]: Binary data

[0282] O[#]_[0:K-1]: Binary data

[0283] O[#]_0: Binary data

[0284] O[#]_1: Binary data

[0285] O[*]: Binary data

[0286] O[0:P-1]: Binary data

[0287] O[0]: Binary data

[0288] O[1]: Binary data

[0289] O[L-1]: Binary data

[0290] OUT[0]: part

[0291] OUT[1]: part

[0292] OUT[L-1]: Partial

[0293] OUT[#]: part

[0294] PC: Precharge signal

[0295] Q: Output node

[0296] S[#]_[0:R-1]: Output signal

[0297] S[0][0]: Output signal

[0298] S[0][1]: Output signal

[0299] S[0][N-2]: Output signal

[0300] S[1][0]: Output signal

[0301] S[1][N-3]: Output signal

[0302] S[N-2][0]: Output signal

[0303] SA[#]: Readout circuit system

[0304] SA[0]: Readout circuit system

[0305] SA[1]: Readout circuit system

[0306] SA[L-1]: Readout circuit system

[0307] T1: Time

[0308] T2: Time

[0309] T3: Time

[0310] T4: Time

[0311] T5: Time

[0312] TN: Time

[0313] TN+1: Time

[0314] TN+2: Time

[0315] VDD: Higher supply voltage

[0316] VSS: Lower supply voltage

[0317] WL: Word Line

[0318] WLB[0]: Wordline

[0319] WLB[M-1]: Word Line

[0320] WL[0]: Wordline

[0321] WL[1]: Wordline

[0322] WL[M-1]: Wordline

[0323] WL[n]: Word line signal

[0324] WL[n-1]: Word line signal Detailed Implementation

[0325] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of elements and arrangements are described below to simplify one embodiment of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, one embodiment of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0326] Additionally, for ease of description, spatially relative terms (such as “below,” “under,” “lower,” “above,” “upper,” and the like) may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. Besides the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and thus the spatially relative descriptive terms used herein may be interpreted in the same way. Furthermore, the term “made of” may mean “including” or “consisting of.” In one embodiment of this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element from A, an element from B, and an element from C, unless otherwise described.

[0327] Figure 1 This is a schematic block diagram of a memory device 100 according to some embodiments. In some embodiments, the memory device 100 is included in a semiconductor device. In some embodiments, the semiconductor device including the memory device 100 further includes other elements and / or circuitry for other functionalities. In this non-limiting example, the memory device 100 corresponds to a read-only memory (ROM) device.

[0328] exist Figure 1 In the memory device 100, there is a memory cell array 110 and a control circuit system 120 coupled to the memory cell array 110. The memory cell array 110 includes memory cells arranged in columns and rows. Figure 1 (Referring to "MC" in some embodiments). In some embodiments, the control circuitry 120 is used to control the operation of the memory cells in the memory cell array 110. Figure 1In this embodiment, as a non-limiting example, the memory device 100 further includes a plurality of word lines WL[0] to WL[M-1] extending along the column direction and a plurality of sets of bit lines BL[0] to BL[L-1] extending along the column direction. In some embodiments, each of the sets of bit lines includes N bit lines. Each of the memory cells MC is coupled to the control circuitry system 120 via at least one of the word lines and at least one of the sets of bit lines. In some embodiments, M, L, and N are positive integers. The word line is also referred to as WL in one embodiment of this disclosure, and the bit line is also referred to as BL in one embodiment of this disclosure. Various numbers of word lines and / or bit lines in the memory device 100 are within the scope of various embodiments.

[0329] exist Figure 1 In this embodiment, as a non-limiting example, the control circuit system 120 includes a word line driver circuit system 122, an input / output circuit system 124, and a controller 126. In some embodiments, the word line driver circuit system 122 includes a word line driver and / or an address decoder. In some embodiments, the input / output circuit system 124 includes a readout circuit, a precharge circuit, a hold circuit, a multiplexer for selecting an output signal, and / or a latch for holding an output signal.

[0330] In some embodiments, controller 126 includes an internal timing generator, a pre-decoder for decoding addresses, and / or a latch for holding input signals. In this example, controller 126 receives the address A[*] of the memory cell to be accessed during a read operation and a system clock signal CLK. In some embodiments, controller 126 generates various control signals and / or internal clock signals based on the system clock signal CLK. In some embodiments, controller 126 and / or the address decoder included in word line driver circuitry system 122 decode at least a portion of address A[*] and activates a corresponding word line driver included in word line driver circuitry system 122 to activate a word line corresponding to this address. In some embodiments, a selected word line driver included in word line driver circuitry system 122 activates a specific column based on activating the corresponding word line to enable access to memory cells in that column.

[0331] In some embodiments, the controller 126 and / or the input / output circuitry 124 decodes at least another portion of address A[*] and activates a portion of readout circuitry, precharge circuitry, and / or hold circuitry included in the input / output circuitry 124 and coupled to one of a plurality of sets of bit lines based on the decoded portion of the address. In some embodiments, selected portions of the input / output circuitry 124 are used to read stored information stored in memory cells specified by the decoded columns and bars via corresponding bit lines and output the stored information as output binary data O[*].

[0332] exist Figure 1 In this embodiment, as a non-limiting example, memory device 100 includes a memory cell array 110. In some embodiments, the memory device includes one or more memory cell arrays sharing a portion or all of a control circuitry system (e.g., sharing controller 126, sharing word line drive circuitry system 122 and controller 126, sharing a portion or all of input / output circuitry system 124, sharing the entire control circuitry system 120, or the like).

[0333] Figure 2A This is a schematic diagram of a memory cell 210 associated with a set of bit lines Net[0] to Net[N-1] according to some embodiments. In some embodiments, the memory cell 210 corresponds to Figure 1 The memory unit MC of the memory device 100 corresponds to the ROM memory unit. Figure 2A In this configuration, N conductive lines are configured as N bit lines Net[0] to Net[N-1], and another conductive line is configured as a word line WL. In this example, memory cell 210 includes transistor 212, which, as a non-limiting example, is an n-type transistor. In one or more other examples, a p-type transistor may be used as transistor 212.

[0334] exist Figure 2A In this transistor, transistor 212 includes two drain / source terminals 212a and 212b and a gate terminal 212c. In some embodiments, the gate terminal 212c of transistor 212 is electrically coupled to a word line WL (e.g., Figure 1 One of the word lines WL[0] to WL[M-1] in the middle, Figure 2A The middle part is marked "WL"), and it is used to receive word line signals through the word line WL. Furthermore, in Figure 2A In this group of bit lines Net[0] to Net[N-1], there are N bit lines and they correspond to... Figure 1The memory cell 210 contains one set of multiple bit lines BL[0] to BL[L-1]. In some embodiments, two drain / source terminals 212a and 212b are electrically coupled to the same bit line or two bit lines in the N bit lines Net[0] to Net[N-1], and the electrical coupling relationship between the two drain / source terminals 212a and 212b and this set of bit lines Net[0] to Net[N-1] indicates the information state of the memory cell 210. In some embodiments, each of the two drain / source terminals 212a and 212b is electrically coupled to only one bit line in this set of bit lines Net[0] to Net[N-1].

[0335] Figure 2B According to some embodiments Figure 2A A simplified table 220 shows the candidate information states of memory cell 210. In table 220, the left column indicates which bit line the drain / source terminal 212a is electrically coupled to; and the top column indicates which bit line the drain / source terminal 212b is electrically coupled to. In some embodiments, the candidate information states of memory cell 210 are based on the electrical coupling relationship between the two drain / source terminals 212a and 212b and this set of N bit lines Net[0] to Net[N-1].

[0336] In Table 220, the entries in region 222 correspond to N different cases where the two drain / source terminals 212a and 212b are electrically coupled to the same bit lines in the corresponding group of N bit lines. In Table 220, the entries in region 224 correspond to a group of N bit lines to which the two drain / source terminals 212a and 212b are electrically coupled. Different bit line pairs. Furthermore, in this example, the drain / source terminal 212a electrically coupled to the first bit line and the drain / source terminal 212b electrically coupled to the second bit line represent the same information state as the drain / source terminal 212a electrically coupled to the second bit line and the drain / source terminal 212b electrically coupled to the first bit line. Therefore, the table entry in region 226 corresponds to another bit line in a set of N bit lines. Different bit line pairs, these bit lines are mirror images of combinations represented by table entries in region 224, but correspond to the same Information status. Therefore, in this example, the following is defined: Candidate information states, which include N bit lines corresponding to the corresponding group. Different bit line pairs (e.g., table entries in regions 224 and 226) A candidate information state and a candidate information state corresponding to N different cases of the same bit line in the corresponding group (e.g., a table entry in region 222) electrically coupled to the corresponding group. In this example, memory cell 210's Candidate information states can be used to represent values. Bit.

[0337] Figure 2C Including those with various electrical coupling settings according to some embodiments. Figure 2A Schematic diagrams 231 to 239 of memory unit 210 are shown. In this example, memory unit 210 (e.g., where N is set to three (3)) is a memory unit in... Figure 2C (Unmarked) is configured in association with a set of three bit lines, BLB0, BLB1, and BLB2. Figure 2C In this, as a non-limiting example, bit line BLB2 is used to carry a lower supply voltage (represented as VSS in one embodiment of this disclosure), and bit line BLB2 thereby... Figure 2C The brackets in the text are marked "(VSS)". In one embodiment of this disclosure, the lower supply voltage VSS has a lower voltage level compared to the higher supply voltage of the memory device (represented as VDD in one embodiment of this disclosure). In some embodiments, the lower supply voltage VSS corresponds to a ground reference voltage (or may be replaced by a ground reference voltage). In some embodiments, the lower supply voltage VSS or the ground reference voltage represents logic "0", and the higher supply voltage VDD represents logic "1".

[0338] exist Figure 2C In the diagram, schematic 231 includes two drain / source terminals 212a and 212b of transistor 212 electrically coupled to transistor line BLB0; schematic 232 includes drain / source terminal 212a of transistor line BLB0 and drain / source terminal 212b of transistor line BLB1; and schematic 233 includes drain / source terminal 212a of transistor line BLB0 and drain / source terminal 212b of transistor line BLB2 (VSS). Figure 2C In the diagram, schematic 234 includes the drain / source terminal 212a of electrically coupled bit line BLB1 and the drain / source terminal 212b of electrically coupled bit line BLB0; schematic 235 includes the two drain / source terminals 212a and 212b of transistor 212 electrically coupled to bit line BLB1; and schematic 236 includes the drain / source terminal 212a of electrically coupled bit line BLB1 and the drain / source terminal 212b of electrically coupled bit line BLB2 (VSS). Furthermore, in Figure 2CIn the diagram, schematic 237 includes the drain / source terminal 212a of the electrically coupled bit line BLB2 (VSS) and the drain / source terminal 212b of the electrically coupled bit line BLB0; schematic 238 includes the drain / source terminal 212a of the electrically coupled bit line BLB2 (VSS) and the drain / source terminal 212b of the electrically coupled bit line BLB1; and schematic 239 includes the two drain / source terminals 212a and 212b of the transistor 212 that is electrically coupled to the bit line BLB2 (VSS).

[0339] Figure 2D This is a summary based on some embodiments. Figure 2C Table 240 shows the candidate information states for various electrical coupling settings. In Table 240, the left column indicates which bit line among BLB0, BLB1, and BLB2 is electrically coupled to the drain / source terminal 212a (labeled "(VSS)"); and the top column indicates which bit line among BLB0, BLB1, and BLB2 is electrically coupled to the drain / source terminal 212b (labeled "(VSS)"). In some embodiments, Figure 2C and Figure 2D The candidate information state of memory cell 210 corresponds to where N is set to three (3). Figure 2A and Figure 2B Examples in [the text].

[0340] In Table 240, based on the two drain / source terminals 212a and 212b electrically coupled to the same bit line (e.g., corresponding to the instances in diagrams 231, 235, and 237), the memory cell has an information state "0". Based on the two drain / source terminals 212a and 212b electrically coupled to bit lines BLB0 and BLB1 (e.g., corresponding to the instances in diagrams 232 and 234), the memory cell has an information state "a". Based on the two drain / source terminals 212a and 212b electrically coupled to bit lines BLB0 and BLB2 (VSS) (e.g., corresponding to the instances in diagrams 233 and 237), the memory cell has an information state "b". Furthermore, based on the two drain / source terminals 212a and 212b electrically coupled to bit lines BLB1 and BLB2 (VSS) (e.g., corresponding to the instances in diagrams 236 and 238), the memory cell has an information state "b". In this example, the candidate information states {0, a, b, c} represent four (4) different data values. In some embodiments, the candidate information states {0, a, b, c} represent binary values ​​{0b00, 0b01, 0b10, 0b11}. In this example, a memory cell with three bit lines (e.g., N=3) can record a 2-bit binary value.

[0341] According to one or more embodiments of this disclosure, the candidate information state of a memory cell is defined based on the theoretical constraint of the electrical coupling relationship using N bit lines. In some embodiments, for a configuration of N bit lines per column of memory cell, a read cycle requires (N-1) read stages. A decoder is used to convert the read output signal into binary data. In some instances based on one or more embodiments of this disclosure, for N=3, the information density is increased by 100% (relative to one or more other designs). In some instances based on one or more embodiments of this disclosure, for N=3, the die area is reduced by 50% (relative to one or more other designs for storing the same amount of information).

[0342] Figure 3A This is a schematic block diagram of a memory device 300 configured based on a first output circuit system according to some embodiments. In some embodiments, the memory device 300 corresponds to a memory device 300 configured based on a first output circuit system. Figure 1 Implementation method of memory device 100 in Figure 2A Instances of memory cells in the memory. Therefore, with... Figure 1 The same or similar in Figure 3A The components are given the same reference number or component symbol, and their descriptions are simplified or omitted.

[0343] and Figure 1 Compared to the memory device 100, the memory unit MC is a ROM memory unit, and Figure 3A The memory device 300 includes an output circuit system 124A that replaces the input / output circuit system 124, and the output circuit system 124A includes L parts (in Figure 3A In this example, each part of the output circuit system 124A is electrically coupled to the corresponding group of bit lines and is used to output the decoded binary data of the corresponding subgroup (for each group of bit lines, it is marked as O[0] to O[L-1] output, and in Figure 3A These are collectively referred to as O[0:P-1] outputs. In this example, each of the O[0] to O[L-1] outputs has K bits, where P = L × K. and .

[0344] Figure 3B According to some embodiments Figure 3AA schematic diagram of a portion of a memory device 300 (labeled "300 portion"), which includes columns of memory cells 310[0] to 310[M-1] associated with a set of bit lines BLB[#]_0, BLB[#]_1, and BLB[#]_2, and includes a portion (labeled "O[#]") of an output circuit system 320 electrically coupled to this set of bit lines of the memory device 300. In this example, Figure 3A and Figure 3B The "#" in the text corresponds to a number from 0 to (L-1).

[0345] In this non-limiting example, the columns of memory cells 310[0] to 310[M-1] are based on a combination of a set of three bit lines (e.g., N is set to three). Figure 2C and Figure 2D Configure it using an instance. In this unrestricted instance, in Figure 2C In this example, bit line BLB[#]_0 corresponds to bit line BLB0, BLB[#]_1 corresponds to bit line BLB1, and BLB[#]_2 corresponds to bit line BLB2. In this non-limiting example, bit line BLB[#]_2 is used to carry a lower supply voltage (e.g., connected to level VSS), and bit line BLB[#]_2 in Figure 3B The text is marked as "BLB[#]_2(VSS)". Additionally, in... Figure 3B In this part of the output circuit system 320, the precharge signal (labeled "PC"), the discharge signal (labeled "DC"), and two sampled clock signals (labeled "CK[0:1]"). Figure 3B In this part of the output circuit system 320, the decoded binary data (marked as O[#]_[0:1]) is output.

[0346] Figure 3C According to some embodiments Figure 3B A schematic diagram of a portion of the output circuitry system 320 of the memory device. In some embodiments, Figure 3C The schematic diagrams in this disclosure are simplified, and some components of the output circuit system 320 are simplified or omitted without compromising the clarity of one embodiment of this disclosure. Furthermore, with Figure 3B The same or similar in Figure 3C The components in the document are given the same component symbol or reference code, and their descriptions are simplified or omitted.

[0347] exist Figure 3C In this part, the output circuit system 320 includes the readout circuit system 322 and the decoder 324 (or a portion of the decoder 324). Figure 3CIn this embodiment, the readout circuit system 322 includes a first precharge transistor 332 electrically coupled between a first power node carrying a higher supply voltage VDD and a bit line BLB[#]_0, a second precharge transistor 334 electrically coupled between the first power node carrying a higher supply voltage VDD and a bit line BLB[#]_1, and a discharge transistor 336 electrically coupled between a second power node carrying a lower supply voltage VSS and a bit line BLB[#]_1. In this example, the gate terminals of the precharge transistors 332 and 334 are used to receive a precharge bar signal (labeled " / PC"), which is a logical complement of the precharge signal PC, and the gate terminal of the discharge transistor 336 is used to receive a discharge signal DC.

[0348] In addition, Figure 3C In the readout circuit system 322, two unit metadata sampling devices 342 and 344 having an electrically coupled bit line BLB[#]_0 data input node (marked as "D" therein) and a unit metadata sampling device 346 having an electrically coupled bit line BLB[#]_1 data input node (marked as "D" therein). Figure 3C In this embodiment, the unit metadata sampling devices 346, 344, and 342 have output nodes (labeled “Q”) for providing output signals S[0][0], S[0][1], and S[1][0] constituting the readout circuitry system 322. In some embodiments, each of the unit metadata sampling devices 342, 344, and 346 corresponds to a flip-flop or latch. In this example, a sampling clock signal CK[0] is applied to the clock or enable node (labeled “CLK”) of the unit metadata sampling devices 344 and 346, and a sampling clock signal CK[1] is applied to the clock or enable node of the unit metadata sampling device 342. In this example, the decoder 324 is used to convert the output signals S[0][0], S[0][1], and S[1][0] from the readout circuitry system 322 into binary data O[#]_0 and O[#]_1 as output.

[0349] In some embodiments, this portion of the output circuitry system 320 is used to detect the electrical coupling between the two drain / source terminals of the activated memory cell (activated by the corresponding word line) and the set of three (3) bit lines based on two (2) read levels.

[0350] Figure 4A It is for control according to some embodiments Figure 3C The timing diagram 410 shows the various control signals for the read cycle of the readout circuit system 322 in the middle. Figure 4A In this diagram, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Figure 4A In the sequence diagram 410, there are representations of... Figure 3B Curve 412 shows the voltage level of the precharge signal PC. This precharge signal is... Figure 3C The precharge bar signal / PC logic complementary signal. Figure 4A In the sequence diagram 410, further includes representations of... Figure 3C Curve 414 represents the voltage level of the discharge signal DC. Figure 3C Curve 416 represents the voltage level of the word line signal WL on one of the word lines WL[0] to WL[M-1]. Figure 3C The voltage level curve 417 of the sampling clock signal CK[0] and the curve representing the voltage level of the sampling clock signal CK[0] are shown in Figure 417. Figure 3C The voltage level curve of the sampling clock signal CK[1] in the curve 418.

[0351] In some embodiments, the readout circuitry 322 detects the information state of the activated memory cell based on two (2) readout stages controlled by signals described with respect to the instance in timing diagram 410. Figure 4A In the middle, before time T1, the precharge signal PC is in VDD, indicating that the precharge bar signal / PC is in VSS to be turned on. Figure 3C The precharge transistors 332 and 334 are used. Therefore, before time T1, bit lines BLB[#]_0 and BLB[#]_1 are precharged to VDD. Next, at time T1, the precharge signal PC changes from VDD to VSS, indicating that the precharge bar signal / PC changes from VSS to VDD to turn off. Figure 3C The precharge transistors 332 and 334 in the middle.

[0352] At time T2, the corresponding word line WL changes from VSS to VDD to turn on the transistor of the memory cell to be accessed. At time T2, the sampling clock signal CK[0] also changes from VSS to VDD to enable the data sampling functionality of the unit metadata sampling devices 344 and 346. In this example, the first read stage corresponds to the read operation performed from time T2 to time T3.

[0353] At time T3, the discharge signal DC changes from VSS to VDD to turn on. Figure 3C The discharge transistor 336 is used. Therefore, at time T3, bit line BLB[#]_1 is discharged to VSS. In addition, at time T3, the sampling clock signal CK[0] changes from VDD to VSS to disable the data sampling functionality of unit metadata sampling devices 344 and 346, and the sampling clock signal CK[1] changes from VSS to VDD to enable the data sampling functionality of unit metadata sampling device 342. In this example, the second read stage corresponds to the read operation performed from time T3 to time T4.

[0354] At time T4, the discharge signal DC changes from VDD to VSS to turn off the discharge transistor 336, and the corresponding word line WL changes from VDD to VSS to turn off the transistor of the memory cell to be accessed. Furthermore, at time T4, the sampling clock signal CK[1] changes from VDD to VSS to disable the data sampling function of the unit metadata sampling device 342. Therefore, after time T4, the unit metadata sampling devices 342, 344, and 346 no longer respond to the voltage levels of bit lines BLB[#]_0 and BLB[#]_1. Finally, at time T5, the precharge signal PC changes from VSS to VDD, indicating that the precharge bar signal / PC changes from VDD to VSS to turn on the precharge transistors 332 and 334. Therefore, after time T5, bit lines BLB[#]_0 and BLB[#]_1 are precharged back to VDD and ready for the next read cycle.

[0355] Figure 4B Based on some embodiments, it is based on detecting that has a corresponding Figure 2C The information state "0" in the information state (in Figure 4B The activated memory unit (also indicated by the label "0") Figure 3C The timing diagram 420 shows the signals at each terminal of the readout circuit system 322. Figure 4B Also included is schematic diagram 421 of the activated memory cell corresponding to the two drain / source terminals of the memory cell corresponding to the electrically coupled bit line BLB[#]_2(VSS). In this example, schematic diagram 421 corresponds to Figure 2C The diagram in Figure 239 is omitted, and its detailed description is omitted.

[0356] In timing diagram 420, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Figure 4B In the sequence diagram 420, there are representations of... Figure 3C The curve 422 and schematic diagram 421 of the voltage level of bit line BLB[#]_0, and the representation of Figure 3C The voltage level curve 423 and schematic diagram 421 of bit line BLB[#]_1 are shown in the figure. Figure 4B In the sequence diagram 420, further includes representations of... Figure 3C The curve 424 represents the voltage level of the output signal S[0][0]. Figure 3C The curve 426 shows the voltage level of the output signal S[0][1] and represents... Figure 3C The voltage level curve of the output signal S[1][0] is shown in curve 428. Furthermore, in timing diagram 420, time T2 and time T3 correspond to... Figure 4A The time T2 and time T3 in the middle.

[0357] exist Figure 4B Before time T2, bit lines BLB[#]_0 and BLB[#]_1 are precharged to VDD. Furthermore, before time T2, output signals S[0][0], S[0][1], and S[1][0] hold sampled data represented by VDD or VDD from the previous read cycle. At time T2, when word line WL transitions from VSS to VDD and sampling clock signal CK[0] transitions from VSS to VDD, unit metadata sampling devices 346 and 344 are enabled, and the voltage levels at output signals S[0][0] and S[0][1] are updated based on the voltage levels at bit lines BLB[#]_0 and BLB[#]_1. Because bit lines BLB[#]_0 and BLB[#]_1 are not electrically coupled to the path carrying VSS, bit lines BLB[#]_0 and BLB[#]_1 remain in VDD, and output signals S[0][0] and S[0][1] are also in VDD.

[0358] exist Figure 4B At time T3, when the sampling clock signal CK[0] changes from VDD to VSS, the unit metadata sampling devices 346 and 344 are deactivated. Furthermore, at time T3, when the sampling clock signal CK[1] changes from VSS to VDD, the unit metadata sampling device 342 is enabled, and the voltage level at the output signal S[1][0] is updated based on the voltage level at bit line BLB[#]_0. At time T3, the discharge signal DC changes from VSS to VDD to discharge bit line BLB[#]_1 to VSS. However, bit line BLB[#]_0 is not electrically coupled to the path carrying VSS, and bit line BLB[#]_0 remains at VDD and the output signal S[1][0] is also at VDD. Thus, after time T3, the output signals S[0][0], S[0][1], and S[1][0] have a voltage level VDD, indicating that the VDD of the active memory cell has an information state "0".

[0359] Figure 4C Based on some embodiments, it is based on detecting that has a corresponding Figure 2C The information state of "a" in the information state (in Figure 4C The activated memory unit (also indicated by the label "a") Figure 3C The timing diagram 430 shows the signals at each terminal of the readout circuit system 322. Figure 4C It also includes a schematic diagram 431 of the activated memory cell, and this schematic diagram corresponds to Figure 2C The diagram in Figure 232 is omitted, and its detailed description is omitted.

[0360] In timing diagram 430, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Figure 4C In the sequence diagram 430, there are representations of... Figure 3C The curve 432 and schematic diagram 431 of the voltage level of bit line BLB[#]_0, and the representation of Figure 3C The voltage level curve 433 and schematic diagram 431 of bit line BLB[#]_1 are shown in the figure. Figure 4C In the sequence diagram 430, further includes representations of... Figure 3C The curve 434 represents the voltage level of the output signal S[0][0]. Figure 3C The curve 436 represents the voltage level of the output signal S[0][1], and the curve representing... Figure 3C The voltage level curve of the output signal S[1][0] is shown in curve 438. Furthermore, in timing diagram 430, time T2 and time T3 correspond to... Figure 4A The time T2 and time T3 in the middle.

[0361] exist Figure 4C Before time T3, bit lines BLB[#]_0 and BLB[#]_1 are precharged to VDD. Furthermore, before time T2, output signals S[0][0], S[0][1], and S[1][0] hold sampled data represented by VDD or VDD from the previous read cycle. At time T2, when word line WL transitions from VSS to VDD and the sampling clock signal CK[0] transitions from VSS to VDD, unit metadata sampling devices 346 and 344 are enabled, and the voltage levels at output signals S[0][0] and S[0][1] are updated based on the voltage levels at bit lines BLB[#]_0 and BLB[#]_1. Although bit lines BLB[#]_0 and BLB[#]_1 are electrically coupled together via transistors connected to the activated memory cell, they are not electrically coupled to the path carrying VSS. Therefore, bit lines BLB[#]_0 and BLB[#]_1 remain at VDD, and output signals S[0][0] and S[0][1] are also at VDD.

[0362] exist Figure 4CAt time T3, when the sampling clock signal CK[0] changes from VDD to VSS, the unit metadata sampling devices 346 and 344 are deactivated. Furthermore, at time T3, when the sampling clock signal CK[1] changes from VSS to VDD, the unit metadata sampling device 342 is enabled, and the voltage level at the output signal S[1][0] is updated based on the voltage level at bit line BLB[#]_0. At time T3, the discharge signal DC changes from VSS to VDD to discharge bit line BLB[#]_1 to VSS. Because bit lines BLB[#]_0 and BLB[#]_1 are electrically coupled together via transistors connected to the activated memory cell, bit line BLB[#]_0 is discharged to VSS, and the output signal S[1][0] is at VSS. Therefore, after time T3, the output signals S[0][0], S[0][1], and S[1][0] have voltage levels VDD, VDD, and VSS, indicating that the active memory cell has information state "a".

[0363] Figure 4D According to some embodiments, based on the detection of activated memory units having corresponding Figure 2C The information state "b" in the information state (in Figure 4C (Also indicated by the label "b") Figure 3C The timing diagram 440 shows the signals at each terminal of the readout circuit system 322. Figure 4D Also includes those corresponding to Figure 2C The diagram 441 of the activated memory cell in the diagram 233 is omitted in its detailed description.

[0364] In timing diagram 440, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Figure 4D In the sequence diagram 440, there are representations of... Figure 3C The curve 442 and schematic diagram 441 of the voltage level of bit line BLB[#]_0, and the representation of Figure 3C The voltage level curve 443 and schematic diagram 441 of bit line BLB[#]_1 are shown in the figure. Figure 4D In the sequence diagram 440, further includes representations of... Figure 3C The curve 444 represents the voltage level of the output signal S[0][0]. Figure 3C The curve 446 represents the voltage level of the output signal S[0][1], and the curve representing... Figure 3C The voltage level curve of the output signal S[1][0] is shown in curve 448. Furthermore, in timing diagram 440, time T2 and time T3 correspond to... Figure 4A The time T2 and time T3 in the middle.

[0365] exist Figure 4DBefore time T3, bit lines BLB[#]_0 and BLB[#]_1 are precharged to VDD. Furthermore, before time T2, output signals S[0][0], S[0][1], and S[1][0] hold sampled data represented by VDD or VDD from the previous read cycle. At time T2, when word line WL transitions from VSS to VDD and the sampling clock signal CK[0] transitions from VSS to VDD, unit metadata sampling devices 346 and 344 are enabled, and the voltage levels at output signals S[0][0] and S[0][1] are updated based on the voltage levels at bit lines BLB[#]_0 and BLB[#]_1. Because bit line BLB[#]_0 is electrically coupled to bit line BLB[#]_2 (VSS) via the transistor of the activated memory cell, bit line BLB[#]_0 is pulled to VSS, while BLB[#]_1 remains at VDD. Therefore, the output signal S[0][0] is at VDD and S[0][1] is at VSS.

[0366] exist Figure 4D In time T3, when the sampling clock signal CK[0] changes from VDD to VSS, the unit data sampling devices 346 and 344 are deactivated. Furthermore, in time T3, when the sampling clock signal CK[1] changes from VSS to VDD, the unit data sampling device 342 is enabled, and the voltage level at the output signal S[1][0] is updated based on the voltage level at bit line BLB[#]_0. In time T3, the discharge signal DC changes from VSS to VDD to discharge bit line BLB[#]_1 to VSS. Because bit line BLB[#]_0 is electrically coupled to bit line BLB[#]_2 (VSS) via a transistor connected to the activated memory cell, bit line BLB[#]_0 remains in VSS, and the output signal S[1][0] is in VSS. Therefore, after time T3, the output signals S[0][0], S[0][1], and S[1][0] have voltage levels VDD, VSS, and VSS, indicating that the active memory cell has information state "b".

[0367] Figure 4E According to some embodiments, based on the detection of activated memory units having corresponding Figure 2C The information state "c" in the information state (in Figure 4C (also indicated by the label "c") Figure 3C Timing diagram 450 for the signals at each terminal of the readout circuit system 322. Figure 4E Also includes those corresponding to Figure 2C The diagram 451 of the activated memory cell in the diagram 236 is omitted in its detailed description.

[0368] In timing diagram 450, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Figure 4E In the sequence diagram 450, there are representations of... Figure 3C The curve 452 and schematic diagram 451 of the voltage level of bit line BLB[#]_0, and the representation of Figure 3C The voltage level curve 453 and schematic diagram 451 of bit line BLB[#]_1 are shown in the figure. Figure 4E In the sequence diagram 450, further includes representations of... Figure 3C The curve 454 represents the voltage level of the output signal S[0][0]. Figure 3C The curve 456 represents the voltage level of the output signal S[0][1], and the curve representing... Figure 3C The voltage level curve of the output signal S[1][0] is shown in curve 458. Furthermore, in timing diagram 450, time T2 and time T3 correspond to... Figure 4A The time T2 and time T3 in the middle.

[0369] exist Figure 4E Before time T3, bit lines BLB[#]_0 and BLB[#]_1 are precharged to VDD. Furthermore, before time T2, output signals S[0][0], S[0][1], and S[1][0] hold sampled data represented by VDD or VDD from the previous read cycle. At time T2, when word line WL transitions from VSS to VDD and the sampling clock signal CK[0] transitions from VSS to VDD, unit metadata sampling devices 346 and 344 are enabled, and the voltage levels at output signals S[0][0] and S[0][1] are updated based on the voltage levels at bit lines BLB[#]_0 and BLB[#]_1. Because bit line BLB[#]_1 is electrically coupled to bit line BLB[#]_2 (VSS) via the transistor of the activated memory cell, bit line BLB[#]_1 is pulled to VSS, while BLB[#]_0 remains at VDD. Therefore, the output signal S[0][0] is at VSS and S[0][1] is at VDD.

[0370] exist Figure 4EAt time T3, when the sampling clock signal CK[0] changes from VDD to VSS, the unit metadata sampling devices 346 and 344 are deactivated. Furthermore, at time T3, when the sampling clock signal CK[1] changes from VSS to VDD, the unit metadata sampling device 342 is enabled, and the voltage level at the output signal S[1][0] is updated based on the voltage level at bit line BLB[#]_0. At time T3, the discharge signal DC changes from VSS to VDD to discharge bit line BLB[#]_1 to VSS. Because bit line BLB[#]_0 is not electrically coupled to bit line BLB[#]_0 or any path carrying VSS, bit line BLB[#]_0 remains at VDD, and the output signal S[1][0] is at VDD. Therefore, after time T3, the output signals S[0][0], S[0][1], and S[1][0] have voltage levels VSS, VDD, and VDD, indicating that the active memory cell has an information state "c".

[0371] Figure 5A This is a schematic diagram of a portion (labeled "500 (partial)") of a memory device 500 according to some embodiments, which includes columns of memory cells 510[0] to 510[M-1] associated with a set of bit lines BLB[#]_0 to BLB[#]_N-1, and includes a portion of an output circuitry system 520 electrically coupled to this set of bit lines. In some embodiments, the memory device 500 is based on Figure 3A The memory device 300 in the middle is used for implementation, and Figure 5A The "#" in the text corresponds to a number from 0 to (L-1). In some embodiments, Figure 5A This part of the memory device 500 is based on Figure 3B A summary of instances in, where N is an integer equal to or greater than three (3).

[0372] In this non-limiting example, the columns of memory cells 510[0] to 510[M-1] are based on a combination of a set of N bit lines. Figure 2C and Figure 2D This is configured using an example. In this non-limiting example, bit line BLB[#]_N-1 is used to carry a lower supply voltage, and bit line BLB[#]_N-1 is... Figure 5A The label is "BLB[#]_N-1 (VSS)". Furthermore, in Figure 5A In this part of the output circuit system 520, a pre-charge signal (labeled "PC"), a set of discharge signals (labeled "DC[0:N-2]"), and a set of sampled clock signals (labeled "CK[0:N-2]") are received. Figure 5AIn this part of the output circuit system 520, the decoded binary data (labeled as O[#]_[0:K-1], where and ).

[0373] Figure 5B According to some embodiments Figure 5A A schematic diagram of a portion of the output circuitry system 520 of the memory device. In some embodiments, Figure 5B The schematic diagrams in this disclosure are simplified, and some components of the output circuit system 520 have been simplified or omitted without compromising the clarity of one embodiment of this disclosure. Furthermore, with... Figure 5A The same or similar in Figure 5B The elements in the document are given the same element symbols or reference codes, and their descriptions are simplified or omitted. In some embodiments, Figure 5B This part of the output circuit system 520 is based on Figure 3C A summary of instances in, where N is an integer equal to or greater than three (3).

[0374] exist Figure 5B In this part, the output circuit system 520 includes a readout circuit system 522 and a decoder 524 (or a portion of the decoder 524). Figure 5B In this embodiment, the readout circuitry 522 includes (N-1) precharge transistors 532, 534, and 536, which are electrically coupled between a first power node carrying a first supply voltage (e.g., VDD) and corresponding bit lines in a corresponding group of N bit lines (e.g., BLB[#]_0 to BLB[#]_N-1). In this example, the gates of the (N-1) precharge transistors 532, 534, and 536 are used to receive a precharge bar signal (labeled " / PC"), which is a logical complement to the precharge signal PC. Furthermore, the readout circuitry 522 includes (N-2) discharge transistors 542 and 544, which are electrically coupled between a second power node carrying a second supply voltage (e.g., VSS) and the second bit lines to the (N-1)th bit lines in a corresponding group of N bit lines (e.g., BLB[#]_1 to BLB[#]_N-2). In this example, the Nth bit line of the corresponding group (e.g., BLB[#]_N-1) is used to carry the second supply voltage (e.g., VSS), as follows: Figure 5AThe instructions are as follows. In this example, for each index i ranging from 2 to (N-1), the gate of the discharge transistor corresponding to the (N-i+1)th bit line is used to receive the (i-1)th discharge signal (labeled DC[i-2], for example, the discharge transistors corresponding to BLB[#]_1 to BLB[#]_N-2 are electrically coupled to DC[N-3] to DC[0]).

[0375] In addition, the readout circuit system 522 includes Unit metadata sampling device 550, for each index i ranging from 1 to (N-1), includes (Ni) unit metadata sampling devices, each having a data input node (labeled "D") electrically coupled to the i-th bit line of the corresponding group of N bit lines. In this example, for each index i ranging from 1 to (N-1), the i-th sampling clock signal (e.g., CK[i-1]) of the (N-1) sampling clock signals is applied to the clock or enable node (labeled "CLK") of the (Ni) unit metadata sampling devices, which are electrically coupled to the first bit line up to the (Ni)-th bit line of the corresponding group of N bit lines. In this example, for each index i ranging from 1 to (N-1), the (Ni) unit metadata sampling devices are enabled by the sampling clock signal CK[i-1] and used to provide an output signal denoted as S[i][0:N-2]. In some embodiments, each of the unit metadata sampling devices 550 corresponds to a flip-flop or a latch. In this example, the decoder 524 is used to convert the output signal from the readout circuitry 522 into binary data O[#]_[0:K-1] as output.

[0376] In some embodiments, this portion of the output circuitry system 520 is used to detect the electrical coupling between the two drain / source terminals of the activated memory cell (activated by the corresponding word line) and this set of N bit lines based on (N-1) read levels.

[0377] Figure 5C It is for control according to some embodiments Figure 5B The timing diagram 560 shows the various control signals for the read cycle of the readout circuit system 322 in the middle. Figure 5C In this diagram, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Figure 5C In the sequence diagram 560, there are representations of... Figure 5A The precharge signal PC voltage level curve 562 in the figure is... Figure 5B The precharge bar signal / PC logic complementary signal. Figure 5CIn the timing diagram 560, curves 563 and 564 are further included to represent the voltage levels of the discharge signals DC[0] and DC[N-3], and to represent... Figure 5A Curve 565 shows the voltage level of the word line signal WL on one of the word lines WL[0] to WL[M-1]. In addition, timing diagram 560 further includes curves 566, 567, and 568 representing the voltage levels of the sampled clock signals CK[0], CK[1], and CK[N-2].

[0378] In some embodiments, the readout circuitry 522 detects the information state of the activated memory cell based on N-1 read stages controlled by signals described with respect to instances in timing diagram 560. Figure 5C The timing diagram 560 in the middle is based on Figure 4A A summary of instances in, where N is an integer equal to or greater than three (3).

[0379] exist Figure 5A In the middle, before time T1, the precharge signal PC is in VDD, indicating that the precharge bar signal / PC is in VSS to be turned on. Figure 5A There are (N-1) precharge transistors. Therefore, before time T1, N-1 bit lines, bit lines BLB[#]_0 to BLB[#]_N-2, are precharged to VDD. Next, at time T1, the precharge signal PC changes from VDD to VSS, indicating that the precharge bar signal / PC changes from VSS to VDD to turn off the (N-1) precharge transistors.

[0380] At time T2, the corresponding word line WL transitions from VSS to VDD to activate the transistor of the memory cell to be accessed. At time T2, the sampling clock signal CK[0] also transitions from VSS to VDD to enable the data sampling functionality of the first set of unit metadata sampling devices (e.g., providing the output signal S[0][0:N-2]). In this example, the first read stage corresponds to the read operation performed from time T2 until time T3.

[0381] At time T3, the discharge signal DC[0] changes from VSS to VDD to turn on. Figure 5B The discharge transistor 544 is used. Therefore, at time T3, bit line BLB[#]_N-2 is discharged to VSS. In addition, at time T3, the sampling clock signal CK[0] changes from VDD to VSS, and the sampling clock signal CK[1] changes from VSS to VDD to enable the data sampling functionality of the second set of unit metadata sampling devices (e.g., to provide the output signal S[1][0:N-3]). In this example, the second read stage corresponds to the readout operation performed at the beginning of time T3.

[0382] Subsequently, for the corresponding read cycle, the sampling clock signal CK[2:N-2] and the discharge signal DK[1:N-3] are sequentially set to VDD. For example, at time TN, the discharge signal DC[N-3] changes from VSS to VDD to turn on the corresponding discharge transistor. Therefore, at time TN, bit line BLB[#]_1 is discharged to VSS. In addition, at time TN, the sampling clock signal CK[N-3] changes from VDD to VSS, and the sampling clock signal CK[N-2] changes from VSS to VDD to enable the data sampling functionality of the unit metadata sampling device (e.g., to provide the output signal S[N-2][0]). In this example, the (N-1)th read stage corresponds to the read operation performed from the beginning of time TN to time TN+1.

[0383] At time TN+1, the discharge signal DC[N-3] changes from VDD to VSS, and the corresponding word line WL changes from VDD to VSS to turn off the transistor of the memory cell to be accessed. Additionally, at time TN+1, the sampling clock signal CK[N-2] changes from VDD to VSS to enable the data sampling functionality of the unit metadata sampling device, which provides the output signal S[N-2][0]. After time TN+1, the unit metadata sampling device 550 no longer responds to the voltage levels of bit lines BLB[#]_0 to BLB[#]_N-2. Finally, at time TN+2, the precharge signal PC changes from VSS to VDD, indicating that the precharge bar signal / PC changes from VDD to VSS to turn on (N-1). Thus, after time TN+2, N-1 bit lines (bit lines BLB[#]_0 to BLB[#]_N-2) are precharged to VDD again and ready for the next read cycle.

[0384] Figure 6A This is a schematic diagram of a portion (labeled "600#") of a memory device 600 according to some embodiments, which includes columns of memory cells 610[0] to 610[M-1] associated with a set of bit lines BL[#]_0, BL[#]_1, and BL[#]_2, and includes a portion (labeled "O[#]") of an output circuitry system 620 electrically coupled to this set of bit lines of the memory device 600. In this example, Figure 6A and Figure 6B The "#" in the text corresponds to a number from 0 to (L-1).

[0385] In this non-limiting example, the columns of memory cells 610[0] to 610[M-1] are based on a combination of a set of three bit lines (e.g., N is set to three). Figure 2C and Figure 2DThe example is configured (where the modification is based on replacing the n-type transistor with a p-type transistor). Therefore, memory device 600 corresponds to a variation of memory device 300 based on the appropriate adjustment of the polarity of various control signals for memory device 600, including p-type transistors in the memory cells. In this non-limiting example, bit line BL[#]_2 is used to carry a higher supply voltage, and bit line BL[#]_2 in Figure 6A The text is marked as "BL[#]_2(VDD)". Additionally, in... Figure 6A In this part of the output circuit system 620, the precharge signal (labeled "PC"), the discharge signal (labeled "DC"), and two sampled clock signals (labeled "CK[0:1]"). Figure 6A In this part of the output circuit system 620, the decoded binary data (marked as O[#]_[0:1]) is output.

[0386] Figure 6B According to some embodiments Figure 6A A schematic diagram of a portion of the output circuitry system 620 of the memory device. In some embodiments, Figure 6B The schematic diagrams in this disclosure are simplified, and some components of the output circuit system 620 have been simplified or omitted without compromising the clarity of one embodiment of this disclosure. Furthermore, with Figure 6A The same or similar in Figure 6B The components in the document are given the same component symbol or reference code, and their descriptions are simplified or omitted.

[0387] exist Figure 6B In this embodiment, a portion of the output circuit system 620 includes a readout circuit system 622 and a decoder 624 (or a portion thereof). In some embodiments, the readout circuit system 622 is based on a configuration similar to that of the readout circuit system 322, with modifications such as the type of switching transistors (e.g., from n-type transistors to p-type transistors and vice versa) and the polarity of the switching signals and supply voltages.

[0388] For example, in Figure 6BIn this embodiment, the readout circuit system 622 includes a first precharge transistor 632 electrically coupled between a first power node carrying a lower supply voltage VSS and a bit line BL[#]_0, a second precharge transistor 634 electrically coupled between the first power node carrying a lower supply voltage VSS and a bit line BL[#]_1, and a discharge transistor 636 electrically coupled between a second power node carrying a higher supply voltage VDD and a bit line BL[#]_1. In this example, the gate terminals of the precharge transistors 632 and 634 are used to receive a precharge signal, and the gate terminal of the discharge transistor 636 is used to receive a discharge bar signal (labeled " / DC"), which is the logical complement of the discharge signal DC.

[0389] In addition, Figure 6B In the readout circuit system 622, two unit metadata sampling devices 642 and 644 having an electrically coupled bit line BL[#]_0 (marked as "D" therein) and a unit metadata sampling device 646 having an electrically coupled bit line BL[#]_1 (marked as "D" therein). Figure 6B In this embodiment, unit metadata sampling devices 646, 644, and 642 have output nodes (labeled “Q”) for providing output signals S[0][0], S[0][1], and S[1][0] constituting the readout circuitry system 622. In some embodiments, each of the unit metadata sampling devices 642, 644, and 646 corresponds to a flip-flop or latch. In this example, a sampling clock signal CK[0] is applied to the clock or enable node (labeled “CLK”) of the unit metadata sampling devices 644 and 646, and a sampling clock signal CK[1] is applied to the clock or enable node of the unit metadata sampling device 642. In this example, a decoder 624 is used to convert the output signals S[0][0], S[0][1], and S[1][0] from the readout circuitry system 622 into binary data O[#]_0 and O[#]_1 as output.

[0390] In some embodiments, such as regarding Figures 4A to 4E The example described similarly, except that the polarity of the output signals S[0][0], S[0][1], and S[1][0] is reversed, this part of the output circuit system 620 is used to detect the electrical coupling between the two drain / source terminals of the activated memory cell (activated by the corresponding word line) and the three (3) bit lines based on two (2) read stages.

[0391] Figure 7This is a schematic diagram of a portion (labeled "700 (partial)") of a memory device 700 according to some embodiments, which includes columns of memory cells 710[0] to 710[M-1] associated with a set of bit lines BL[#]_0 to BL[#]_N-1, and includes a portion of an output circuitry system 720 electrically coupled to this set of bit lines of the memory device 700. In this example, Figure 7 The "#" in the text corresponds to a number from 0 to (L-1).

[0392] In some embodiments, similar to Figure 5A The instances in are based on Figure 3B A summary of the examples in the text. Figure 7 This part of the memory device 700 is based on Figure 6A The generalization of instances in, where N is an integer equal to or greater than three (3). For example, the columns of memory cells 710[0] to 710[M-1] are based on a set of N bit lines combined with such columns. Figure 2C and Figure 2D The memory device 700 is configured based on an example (where the modification is based on replacing the n-type transistor with a p-type transistor). Therefore, the memory device 700 also corresponds to a variation of the memory device 500 based on the appropriate adjustment of the polarity of the various control signals for the memory device 500, which include p-type transistors in the memory cells.

[0393] In this non-limiting example, bit line BL[#]_N-1 is used to carry a higher supply voltage, and bit line BL[#]_N-1 in Figure 7 The label is "BL[#]_N-1 (VDD)". Furthermore, in Figure 7 In this part of the output circuit system 720, a pre-charge signal (labeled "PC"), a set of discharge signals (labeled "DC[0:N-2]"), and a set of sampled clock signals (labeled "CK[0:N-2]") are received. Figure 7 In this part of the output circuit system 720, the decoded binary data (labeled as O[#]_[0:K-1], where and ).

[0394] In some embodiments, as similarly regarding Figures 4A to 4E As described in the example, in addition to the polarity reversal of the output signal, this part of the output circuit system 720 is used to detect the electrical coupling between the two drain / source terminals of the activated memory cell (activated by the corresponding word line) and this set of N bit lines based on (N-1) read stages.

[0395] Figure 8AThis is a schematic diagram of a portion of an output circuit system example 800A including a retainer 810 according to some embodiments. In some embodiments, the output circuit system example 800A is based on adding a retainer 810... Figure 3C Example 320 shows the output circuit system. Therefore, with... Figure 3C The same or similar in Figure 8A The components are given the same reference codes and component symbols, and their descriptions are simplified or omitted.

[0396] exist Figure 8A In the example output circuit system 800A, the holder 810 includes two holders electrically coupled between a power node (e.g., carrying a higher supply voltage VDD) and bit lines (including bit lines BLB[#]_0 and BLB[#]_1). In this example, the first holder includes a p-type transistor 812 and an inverter 814. The p-type transistor 812 includes a drain / source terminal electrically coupled to the power node and another drain / source terminal electrically coupled to bit line BLB[#]_0. The inverter 814 includes an input terminal electrically coupled to bit line BLB[#]_0 and an output terminal electrically coupled to the gate terminal of the p-type transistor 812. In some embodiments, the first holder is used to pull the voltage level at bit line BLB[#]_0 toward the higher supply voltage VDD.

[0397] exist Figure 8A In this configuration, the second hold includes a p-type transistor 816 and a NAND gate 818. The p-type transistor 816 includes a drain / source terminal electrically coupled to the power node and another drain / source terminal electrically coupled to bit line BLB[#]_1. The NAND gate 818 includes a first input terminal electrically coupled to bit line BLB[#]_1 and an output terminal electrically coupled to the gate terminal of the p-type transistor 816. The NAND gate 818 further includes a second input terminal for receiving a discharge bar signal (denoted as " / DC"), which is the logical complement of the discharge signal DC. In some embodiments, the second hold is turned off based on the discharge bar signal / DC being at VSS and turned on based on the discharge bar signal / DC being at VDD. In some embodiments, based on the second hold being turned on (the discharge bar signal / DC being at VDD, which corresponds to the discharge signal DC being at VSS and the discharge transistor 336 being turned off), the second hold is used to pull the voltage level at bit line BLB[#]_1 toward the higher supply voltage VDD.

[0398] Figure 8B This is a schematic diagram of a portion of an example 800B of an output circuit system including a retainer 820, according to some embodiments. In some embodiments, the output circuit system example 800B is based on adding a retainer 820... Figure 5B Example 520 shows the output circuit system. Therefore, with... Figure 5B The same or similar in Figure 8B The components are given the same reference codes and component symbols, and their descriptions are simplified or omitted.

[0399] exist Figure 8B In the example output circuit system 800B, the hold 820 includes (N-1) holds electrically coupled between the power node (e.g., carrying a higher supply voltage VDD) and the first bit line (e.g., bit line BLB[#]_0) to the (N-1)th bit line (e.g., bit line BLB[#]_N-2) of the corresponding group of N bit lines. For example, based on... Figure 8A The configuration of the first holder is similar, and the first holder includes a p-type transistor 822 and an inverter 823 electrically coupled between the power node and the bit line BLB[#]_0. Figure 8B In China, based on and Figure 8A The second hold is configured similarly and is used to turn on or off based on the discharge bar signal / DC[1]. The (N-2) hold includes a p-type transistor 824 and a NAND gate 825 electrically coupled between the power node and the bit line BLB[#]_N-3. Furthermore, in Figure 8B In China, based on and Figure 8A The second holder is configured similarly and is used to turn on or off based on the discharge bar signal / DC[0]. The (N-1) holder includes a p-type transistor 826 and a NAND gate 827 electrically coupled between the power node and the bit line BLB[#]_N-2.

[0400] Figure 8C This is a schematic diagram of a portion of an example 800C of an output circuit system including a retainer 830, according to some embodiments. In some embodiments, the output circuit system example 800C is based on adding a retainer 830... Figure 6B Example 620 shows the output circuit system. Therefore, with... Figure 6B The same or similar in Figure 8C The components are given the same reference codes and component symbols, and their descriptions are simplified or omitted.

[0401] exist Figure 8CIn example 800C, the output circuit system includes a holder 830 comprising two holders electrically coupled between a power node (e.g., carrying a lower supply voltage VSS) and bit lines (including bit lines BL[#]_0 and BL[#]_1). In this example, the first holder includes an n-type transistor 832 and an inverter 834. The n-type transistor 832 includes a drain / source terminal electrically coupled to the power node and another drain / source terminal electrically coupled to bit line BL[#]_0. The inverter 834 includes an input terminal electrically coupled to bit line BL[#]_0 and an output terminal electrically coupled to the gate terminal of the n-type transistor 832. In some embodiments, the first holder is used to pull the voltage level at bit line BL[#]_0 toward the lower supply voltage VSS.

[0402] exist Figure 8C In this embodiment, the second hold includes an n-type transistor 836 and a NOR gate 838. The n-type transistor 836 includes a drain / source terminal electrically coupled to the power node and another drain / source terminal electrically coupled to bit line BL[#]_1. The NOR gate 838 includes a first input terminal electrically coupled to bit line BL[#]_1 and an output terminal electrically coupled to the gate terminal of the n-type transistor 836. The NOR gate 838 further includes a second input terminal for receiving a discharge signal DC. In some embodiments, the second hold is turned on based on the discharge signal DC being at VSS and turned off based on the discharge bar signal / DC being at VDD. In some embodiments, based on the second hold being turned on (the discharge signal DC being at VSS, which corresponds to the discharge bar signal / DC being at VDD and the discharge transistor 636 being turned off), the second hold is used to pull the voltage level at bit line BL[#]_1 toward a higher supply voltage VSS.

[0403] and Figure 8A Compared to output circuit system 800A, output circuit system 800C corresponds to a variation of output circuit system 800A, featuring modifications such as switching the transistor types of pre-charge and discharge transistors (e.g., from n-type to p-type and vice versa), switching the polarity of various signals and supply voltages, and implementing suitable holding circuits. In some embodiments, output circuit system 800C corresponds to a generalization of output circuit system 800C, or... Figure 8B The output circuit system 800B in the middle has variations such as switching the transistor type of the precharge transistor and discharge transistor (e.g., from n-type transistor to p-type transistor and vice versa), switching the polarity of the signal and supply voltage, and implementing appropriate holding circuits.

[0404] Figure 9AThis is a schematic diagram of a first decoder example 900A according to some embodiments. In some embodiments, the first decoder 900A is part of the output circuitry 320 and corresponds to Figure 3C A non-restricted instance of decoder 324 in [the dataset]. (And...) Figure 3C The same or similar in Figure 9A The components in the document are given the same reference code or component symbol, and their descriptions are thus simplified or omitted.

[0405] exist Figure 9A In the decoder 900A, NAND gates 912, 914, and 916, and inverter 924, are included. NAND gate 912 includes a first input for receiving output signal S[1][0], a second input for receiving output signal S[0][1], and an output for outputting O[#]_0. NAND gate 914 includes a first input for receiving the logical complement of output signal S[1][0] (inverted by inverter 924) and a second input for receiving output signal S[0][1]. NAND gate 916 includes a first input electrically coupled to the output of NAND gate 914, a second input for receiving output signal S[0][0], and an output for outputting O[#]_1.

[0406] Figure 9B This is a schematic diagram of a second decoder example 900B according to some embodiments. In some embodiments, the second decoder 900B is part of the output circuitry 620 and corresponds to Figure 6B A non-restricted instance of decoder 624 in [the dataset]. (And...) Figure 6B The same or similar in Figure 9B The components in the document are given the same reference code or component symbol, and their descriptions are thus simplified or omitted.

[0407] exist Figure 9B In the decoder 900B, there are NOR gates 932 and NAND gates 934 and 936, and inverters 942, 944, and 945. NOR gate 932 includes a first input for receiving output signal S[1][0], a second input for receiving output signal S[0][1], and an output for outputting the logical complement of O[#]_0. Inverter 942 receives the output from the output of NOR gate 932 and outputs O[#]_0. NAND gate 934 includes a first input for receiving output signal S[1][0], a second input for receiving the logical complement of output signal S[0][1] (inverted by inverter 944). NAND gate 936 includes a first input electrically coupled to the output of NAND gate 934, a second input for receiving the logical complement of output signal S[0][0] (inverted by inverter 946), and an output for outputting O[#]_1.

[0408] Figure 10A This is a schematic diagram of a subarray 1000 comprising two memory cells 1010 and 1020 based on n-type transistors and associated with a set of bit lines BLB[#]_0, BLB[#]_1, and BLB[#]_2, according to some embodiments. In this example, Figure 10A and Figure 10B The "#" in the code corresponds to a number from 0 to (L-1). In this example, bit line BLB[#]_2 is used to carry the lower supply voltage (VSS) and is represented as "BLB[#]_2 (VSS)".

[0409] exist Figure 10A In this example, memory cell 1010 includes an n-type transistor 1012, and memory cell 1020 includes an n-type transistor 1022. In this example, n-type transistors 1012 and 1022 are based on a common drain / source terminal 1012a. The gate terminal of n-type transistor 1012 is used to receive the word line signal WL[n-1], and the gate terminal of n-type transistor 1022 is used to receive the word line signal WL[n]. Figure 10A In this example, subarray 1000 further includes two dummy transistors 1032 and 1034. In this instance, n-type transistor 1012 and dummy transistor 1032 are based on a common drain / source terminal 1012b, and n-type transistor 1022 and dummy transistor 1034 are based on a common drain / source terminal 1022b. Figure 10A In this configuration, the other drain / source terminal 1032b of dummy transistor 1032 and the other drain / source terminal 1034b of dummy transistor 1034 are used to receive a lower supply voltage VSS. The gate terminals of dummy transistors 1032 and 1034 are used to receive the lower supply voltage VSS to turn off dummy transistors 1032 and 1034.

[0410] In this non-limiting example, although the common drain / source terminals of n-type transistors 1012 and 1022 impose constraints on the electrical coupling relationship between the two drain / source terminals of n-type transistors 1012 and 1022 and a set of bit lines BLB[#]_0, BLB[#]_1, and BLB[#]_2, Figure 10A The combination of n-type transistors 1012 and 1022 can still represent up to [number] memory cells 1010 and 1020. The binary values ​​of (N=3) different information states. Thus, no dummy transistors are needed between n-type transistors 1012 and 1022, and the information states are not sacrificed or omitted, which further saves the area used to implement the memory device based on subarray 1000.

[0411] For example, Figure 10B Including those with various electrical coupling settings according to some embodiments. Figure 10A Schematic diagrams 1041 to 1049 show memory units (e.g., memory unit 1010 or memory unit 1020) in the memory. Given... Figure 2C In the example, memory cell 1010 or memory 1020 is arranged to have nine (9) different electrical coupling relationships with respect to a set of bit lines BLB[#]_0, BLB[#]_1, and BLB[#]_2 representing four (4) different candidate information states. Specifically, in Figure 10B In the diagrams, schematics 1041, 1045, and 1049 indicate three different electrical coupling settings corresponding to information state "0" (labeled "0_1", "0_2", and "0_3"); schematics 1042 and 1044 indicate two different electrical coupling settings corresponding to information state "a" (labeled "a_1" and "a_2"); schematics 1043 and 1047 indicate two different electrical coupling settings corresponding to information state "b" (labeled "b_1" and "b_2"); and schematics 1046 and 1048 indicate two different electrical coupling settings corresponding to information state "c" (labeled "c_1" and "c_2").

[0412] Therefore, in this non-limiting example, possible electrical coupling arrangements are listed in Table I below. In this table, column "Data (MC 1010)" corresponds to the binary data value stored by memory cell 1010, column "Data (MC 1020)" corresponds to the binary data value stored by memory cell 1020, and columns "Electrical Coupling (MC 1010)" and "Electrical Coupling (MC 1020)" correspond to the relationships associated with the corresponding binary data values ​​stored by memory cells 1010 and 1020, such as those related to... Figure 10B The possible combinations of electrical coupling settings described.

[0413] Table I

[0414]

[0415] Figure 11A This is a schematic diagram of a subarray 1100 comprising two memory cells 1110 and 1120 based on p-type transistors and associated with a set of bit lines BL[#]_0, BL[#]_1, and BL[#]_2, according to some embodiments. In this example, Figure 11A and Figure 11BThe "#" in the code corresponds to a number from 0 to (L-1). In this example, bit line BL[#]_2 is used to carry a higher supply voltage (VDD) and is represented as "BL[#]_2(VDD)". In some embodiments, subarray 1100 corresponds to variations based on subarray 1000, with modifications such as the type of switching transistors (e.g., from n-type transistors to p-type transistors and vice versa) and the polarity of the switching signal and supply voltage.

[0416] exist Figure 11A In this example, memory cell 1110 includes a p-type transistor 1112, and memory cell 1120 includes a p-type transistor 1122. In this example, p-type transistors 1112 and 1122 are based on a common drain / source terminal 1112a. The gate of p-type transistor 1112 is used to receive the word line signal WLB[n-1], and the gate of p-type transistor 1122 is used to receive the word line signal WLV[n]. Figure 11A In this example, subarray 1100 further includes two dummy transistors 1132 and 1134. In this instance, p-type transistor 1112 and dummy transistor 1132 are based on a common drain / source terminal 1112b, and p-type transistor 1122 and dummy transistor 1134 are based on a common drain / source terminal 1122b. Figure 11A In this configuration, the other drain / source terminal 1132b of dummy transistor 1132 and the other drain / source terminal 1134b of dummy transistor 1134 are used to receive a higher supply voltage VDD. The gate terminals of dummy transistors 1132 and 1134 are used to receive a higher supply voltage VDD to turn off dummy transistors 1132 and 1134.

[0417] In this non-restrictive instance, similar to Figure 10A and Figure 10B In the example, although the common drain / source terminals of p-type transistors 1112 and 1122 impose constraints on the electrical coupling relationship between the two drain / source terminals of p-type transistors 1112 and 1122 and a set of bit lines BL[#]_0, BL[#]_1, and BL[#]_2, Figure 11A The combination of p-type transistors 1112 and 1122 can still represent up to [number] memory cells 1110 and 1120. The binary values ​​of (N=3) different information states. Thus, no dummy transistors are needed between p-type transistors 1112 and 1122, and the information states are not sacrificed or omitted, which further saves the area used to implement the memory device based on subarray 1100.

[0418] For example, Figure 11BIncluding those with various electrical coupling settings according to some embodiments. Figure 11A Schematic diagrams 1141 to 1149 show memory units (e.g., memory unit 1110 or memory unit 1120) in the memory. Given... Figure 2C In the example, memory cell 1110 or memory 1120 is arranged to have nine (9) different electrical coupling relationships with respect to a set of bit lines BL[#]_0, BL[#]_1, and BL[#]_2 representing four (4) different candidate information states. Specifically, in Figure 11B In the diagrams, schematics 1141, 1145, and 1149 indicate three different electrical coupling settings corresponding to information state "0" (labeled "0_1", "0_2", and "0_3"); schematics 1142 and 1144 indicate two different electrical coupling settings corresponding to information state "a" (labeled "a_1" and "a_2"); schematics 1143 and 1147 indicate two different electrical coupling settings corresponding to information state "b" (labeled "b_1" and "b_2"); and schematics 1146 and 1148 indicate two different electrical coupling settings corresponding to information state "c" (labeled "c_1" and "c_2").

[0419] Therefore, in this non-limiting example, possible electrical coupling arrangements are listed in Table II below. In this table, column "Data (MC 1110)" corresponds to the binary data value stored by memory cell 1110, column "Data (MC 1120)" corresponds to the binary data value stored by memory cell 1120, and columns "Electrical Coupling (MC 1110)" and "Electrical Coupling (MC 1120)" correspond to the relationships associated with the corresponding binary data values ​​stored by memory cells 1110 and 1120, such as those related to... Figure 11B The possible combinations of electrical coupling settings described.

[0420] Table II

[0421]

[0422] Figure 12A This is a schematic block diagram of a memory device 1200 configured based on a second output circuitry system according to some embodiments. In some embodiments, the memory device 1200 corresponds to... Figure 3A The changes in the memory device 300, and also corresponding to the changes based on Figure 1 Implementation method of memory device 100 in Figure 2A Instances of memory cells in the memory. Therefore, with Figure 3A and Figure 1 The same or similar in Figure 12AThe components in the document are given the same reference code or component symbol, and their descriptions are simplified or omitted.

[0423] Compared to memory device 300, memory device 1200 includes an output circuit system 124B that replaces output circuit system 124A. In this non-limiting example, output circuit system 124B includes L readout circuit systems (in Figure 12A These are denoted as SA[0] to SA[L-1], and the readout circuitry is used to detect the voltage levels at these bit lines BL[0] to BL[L-1] and output the readout output signal S[#]_[0:R-1]. Here, Figure 12A The "#" in the code corresponds to a number from 0 to (L-1), and S[#]_[0:R-1] represents the readout output signal based on reading a set of bit lines BL[#]. Furthermore, the output circuit system 124B includes a decoder (in... Figure 12A The decoder (labeled "decoder") is used to receive the readout output signal S[#]_[0:R-1] and output decoded binary data O[0:P-1]. In some embodiments, each of these groups of bit lines includes N bit lines, and In some implementation schemes, ,in .

[0424] Figure 12B This is a schematic diagram of a portion (labeled "1200A (partial)") of a memory device 1200A according to some embodiments, which includes columns of memory cells 1210[0] to 1210[M-1] associated with a set of bit lines BLB[#]_0 to BLB[#]_N-1, and includes a readout circuitry system 1222 (represented as "SA[#]"). In some embodiments, the memory device 1200A is based on Figure 12A The memory device 1200 is implemented in which each of the memory cells 1210[0] to 1210[M-1] is based on a corresponding n-type transistor, as per the relevant information. Figures 5A to 5B The examples in [the text] are described similarly. In Figure 12B In this context, "#" corresponds to a number from 0 to (L-1).

[0425] and Figure 5A and Figure 5B Compared to the memory device 500 in the middle. Figure 12B The decoder is shared by multiple column memory cells and corresponding readout circuitry systems. Each readout circuitry system (e.g., readout circuitry system SA[#]) for a corresponding column of a memory cell associated with a set of N bit lines provides an output signal S[#]_[0:R-1], where .

[0426] Figure 12B This is a schematic diagram of a portion (labeled "1200B (partial)") of a memory device 1200B according to some embodiments, which includes columns of memory cells 1230[0] to 1230[M-1] associated with a set of bit lines BL[#]_0 to BL[#]_N-1, and includes a readout circuitry system 1242 (labeled "SA[#]"). In some embodiments, the memory device 1200B is based on Figure 12A The memory device 1200 is implemented in which each of the memory cells 1230[0] to 1230[M-1] is based on a corresponding p-type transistor, as per the relevant information. Figure 7 The examples in [the text] are described similarly. In Figure 12C In this context, "#" corresponds to a number from 0 to (L-1).

[0427] and Figure 7 Compared to the memory device 700 in the middle. Figure 12C The decoder is shared by multiple column memory cells and their corresponding readout circuitry systems. Each readout circuitry system (e.g., readout circuitry system SA[#]) for a corresponding column of a memory cell associated with a set of N bit lines provides an output signal S[#]_[0:R-1], where .

[0428] Figure 13 This is a flowchart of a method 1300 for detecting the information state of memory cells in a memory device according to some embodiments. In some embodiments, given that... Figures 8A to 12C Various configurations and / or changes in the instances, the memory device in method 1300 corresponds to Figure 3B Memory device 300 in Figure 5A Memory device 500 in Figure 6A The memory device 600 in the middle, or Figure 7 The memory device 700 is included. Method 1300 includes blocks 1310 to 1330.

[0429] At block 1310, in the pre-charge stage, the first bit line up to the (N-1)th bit line of a set of N bit lines arranged in association with the memory cells of the memory device are electrically coupled to a first power node carrying a first supply voltage, as based on the pre-charge signal PC before time T1. Figure 4A In the instances or Figure 5CAs illustrated in the examples. In some embodiments, N is an integer equal to or greater than 3. In some embodiments, as described in the various examples above, the Nth bit line of a set of N bit lines is used to carry a second supply voltage (e.g., BLB[#]_N-1 to VSS or BL[#]_N-1 to VDD). In some embodiments, as Figures 2A to 2D As described in the example, the memory cell includes a transistor, which includes a gate terminal and two drain / source terminals, and the electrical coupling between the two drain / source terminals and a set of N bit lines indicates the information state of the memory cell.

[0430] At block 1320, the word line signal is electrically coupled to the gate of the transistor to turn it on, as shown by the word line signal WL at time T2. Figure 4A Instances or Figure 5C The example is shown.

[0431] At block 1330, the electrical coupling relationship between the two drain / source terminals and a set of N bit lines is determined based on (N-1) readout stages. In some embodiments, block 1330 includes, during the first readout stage of the (N-1) readout stages, determining that one of the two drain / source terminals is electrically coupled to the Nth bit line based on the discharge state of the first bit line up to the (N-1)th bit line, and the other of the two drain / source terminals is electrically coupled to one of the first bit line up to the (N-1)th bit line, such as between time T2 and T3. Figure 4A Instances or Figure 5C The example is shown.

[0432] In some embodiments, block 1330 further includes performing the i-th read level out of (N-1) read levels for each index i ranging from 2 to (N-1), such as between time T3 and T4. Figure 4A In instances or between time TN and TN+1 Figure 5CThe example is illustrated. In some embodiments, the i-th read stage includes electrically coupling the (N-i+1)-th bit line to a second power node carrying a second supply voltage during the i-th read stage. In some embodiments, the i-th read stage further includes: during the i-th read stage, determining, based on the discharge state of the first bit line up to the (Ni)-th bit line, that one of the two drain / source terminals is electrically coupled to the (N-i+1)-th bit line and the other of the two drain / source terminals is electrically coupled to one of the first bit lines up to the (Ni)-th bit lines, or determining, based on the discharge state of the first bit line up to the (Ni)-th bit line and based on i being (N-1), that the two drain / source terminals are electrically coupled to the same bit line in a set of N bit lines. In some embodiments, method 1300 further includes converting the information state of the memory cell indicated by the detected electrical coupling relationship into binary data.

[0433] In some embodiments, the electrical coupling between the two drain / source terminals and a set of N bit lines is detected by a readout circuitry system based on (N-1) readout stages (e.g., ...). Figure 3C The readout circuit system 322 in Figure 5B The readout circuit system 522 in Figure 6B The readout circuit system 622, or Figures 8A to 8C (Example in the text) is executed. In some embodiments, the readout circuitry includes (N-1) precharge transistors electrically coupled between a first power node carrying a first supply voltage and a corresponding bit line in a corresponding group of N bit lines, and (N-2) discharge transistors electrically coupled between a second power node carrying a second supply voltage and a second bit line up to the (N-1)th bit line in a corresponding group of N bit lines, the Nth bit line in the corresponding group being used to carry the second supply voltage. In some embodiments, the readout circuitry further includes A unit metadata sampling device, for each index i ranging from 1 to (N-1), includes (Ni) unit metadata sampling devices, each unit metadata sampling device having a data input node electrically coupled to the i-th bit line of the corresponding group of N bit lines. In some embodiments, detecting the electrical coupling relationship between the two drain / source terminals and the group of N bit lines based on (N-1) read stages further includes: for each index i ranging from 1 to (N-1), during the i-th read stage of the (N-1) read stages, enabling the (Ni) unit metadata sampling devices having data input nodes electrically coupled to the first bit line up to the (Ni)-th bit line of the corresponding group of N bit lines to acquire (Ni) sampled data; and from The corresponding output node of the unit metadata sampling device obtains Data bits, the information state of memory units is based on Data bit indicator.

[0434] In some embodiments, during the precharge phase, electrically coupling the first bit line up to the (N-1)th bit line from a set of N bit lines to a first power node includes applying a precharge signal to (N-1) precharge transistors. In some embodiments, for each index i ranging from 2 to (N-1), electrically coupling the (N-i+1)th bit line to a second power node during the i-th read stage includes applying the (i-1)th discharge signal to the (N-i+1)th discharge transistor from the (N-2)th discharge transistors. In some embodiments, the readout circuitry further includes (N-1) holders electrically coupled between the first power node and the first bit line up to the (N-1)th bit line from a set of N bit lines. In some embodiments, detecting the electrical coupling between the two drain / source terminals and a set of N bit lines based on (N-1) read stages further includes: for each index i ranging from 2 to (N-1), during the i-th read stage, applying a (N-i+1)-th hold coupled to the (N-i+1)-th bit line based on the (i-1)-th discharge signal or a logic complement of the (i-1)-th discharge signal.

[0435] In some embodiments, Each of the unit metadata sampling devices corresponds to a flip-flop or latch. In some embodiments, detecting the electrical coupling between the two drain / source terminals and a set of N bit lines based on (N-1) read stages further includes: for each index i ranging from 1 to (N-1), during the i-th read stage, applying the i-th sampling clock signal to the clock or enable node of (Ni) unit metadata sampling devices, which are electrically coupled to the first bit line up to the (Ni)-th bit line in the set of N bit lines.

[0436] Figure 14 This is a block diagram of an IC manufacturing system 1400 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1400 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one element in a semiconductor integrated circuit layer.

[0437] exist Figure 14In this IC manufacturing system 1400, entities such as design room 1420, mask room 1430, and IC manufacturer / fab (fab) 1450 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC device 1460. The entities in system 1400 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 are owned by a single, larger company. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 coexist in shared facilities and use shared resources.

[0438] Design studio (or design team) 1420 generates IC design layout 1422 (e.g., a layout plan). IC design layout 1422 includes various geometric patterns designed for IC device 1460. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1460 to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 1422 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, metal wiring or vias for interlayer interconnects, and openings for bonding pads, as well as various material layers disposed on the semiconductor substrate. Design studio 1420 performs appropriate design procedures to form IC design layout 1422. Design procedures include one or more of the following: logic design, physical design, or placement and routing. IC design layout 1422 exists in one or more data files containing information about the geometric patterns. For example, IC design layout 1422 may be expressed in GDSII or DFII file format.

[0439] Mask chamber 1430 includes data preparation 1432 and mask fabrication 1444. Mask chamber 1430 uses an IC design layout 1422 to fabricate one or more masks 1445, which will be used to fabricate various layers of an IC device 1460 according to the IC design layout 1422. Mask chamber 1430 performs mask data preparation 1432, in which the IC design layout 1422 is converted into a representative data file (RDF). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 1445 or a semiconductor wafer 1453. The design layout 1422 is manipulated by mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1450. Figure 14 In this design, mask data preparation 1432 and mask manufacturing 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask manufacturing 1444 may be collectively referred to as mask data preparation.

[0440] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can be caused by diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 1422. In some embodiments, mask data preparation 1432 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0441] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that examines an IC design layout 1422 that has undergone a process in an OPC with a set of mask generation rules, which contain certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for photolithography effects during mask fabrication 1444, which may undo some modifications performed by the OPC to satisfy the mask generation rules.

[0442] In some embodiments, mask data preparation 1432 includes a lithography process checking (LPC) simulation process, which is performed by IC fab 1450 to manufacture IC device 1460. The LPC simulates this process based on IC design layout 1422 to produce a simulated manufactured device, such as IC device 1460. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as antenna image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device has been generated by the LPC, if the simulated device shape is not compact enough to meet design rules, OPC and / or MRC will be repeated to further refine the IC design layout 1422.

[0443] It should be understood that the above description of mask data preparation 1432 has been simplified for clarity. In some embodiments, data preparation 1432 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1422 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1422 during data preparation 1432 can be performed in various different sequences.

[0444] Following mask data preparation 1432 and during mask manufacturing 1444, mask 1445 or a group of masks 1445 is manufactured based on a modified IC design layout 1422. In some embodiments, mask manufacturing 1444 includes performing one or more lithography exposures based on IC design layout 1422. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to form a pattern on the mask (photomask or master photomask) 1445 based on the modified IC design layout 1422. Mask 1445 can be formed in various techniques. In some embodiments, mask 1445 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (such as ultraviolet (UV) beams) intended to expose image-sensitive material layers (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and emitted via the transparent areas. In one example, the binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1445 is formed using a phase shift mask technique. In the phase shift mask (PSM) version of mask 1445, various features in the pattern formed on the phase shift mask are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1444 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0445] IC fab 1450 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 1450 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) of various IC products, a second manufacturing facility for back-end manufacturing (back-end-of-line, BEOL) of interconnect and packaged IC products, and a third manufacturing facility for other services provided by the foundry company.

[0446] IC fab 1450 includes manufacturing tools 1452 for performing various manufacturing operations on semiconductor wafer 1453, such that IC device 1460 is manufactured according to a mask (e.g., mask 1445). In various embodiments, manufacturing tools 1452 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0447] IC fab 1450 uses a mask 1445 manufactured by mask chamber 1430 to fabricate IC device 1460. Therefore, IC fab 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, semiconductor wafer 1453 is fabricated by IC fab 1450 using mask 1445 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more lithography exposures at least indirectly based on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1453 further includes one or more of the following: various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent fabrication steps).

[0448] In some embodiments, a memory device includes a memory cell array comprising a plurality of memory cells arranged in columns and rows, a plurality of word lines arranged in association with corresponding columns of memory cells in the memory cell array, and a plurality of sets of N bit lines arranged in association with corresponding rows of memory cells in the memory cell array, where N is an integer equal to or greater than 3. Each memory cell in the memory cell array includes a transistor including a gate terminal and two drain / source terminals. The gate terminal is electrically coupled to a corresponding word line among the plurality of word lines, and the two drain / source terminals are electrically coupled to the same bit line or two bit lines in corresponding sets of N bit lines among the plurality of sets of N bit lines, and the electrical coupling relationship between the two drain / source terminals and the corresponding sets of N bit lines indicates... One of the candidate information states. Candidate information states include those of the N bit lines electrically coupled to the corresponding group. The two drain / source terminals of different parasite lines correspond to Candidate information states, wherein the candidate information states include one candidate information state corresponding to N different cases of two drain / source terminals of the same bit line electrically coupled to N bit lines in the corresponding group.

[0449] In some embodiments, each transistor in the plurality of memory cells corresponds to an n-type transistor, and each of the plurality of sets of N bit lines includes a bit line for carrying a lower supply voltage or a ground reference voltage.

[0450] In some embodiments, each transistor in the plurality of memory cells corresponds to a p-type transistor, and each of the plurality of sets of N bit lines includes a bit line for carrying a higher supply voltage.

[0451] In some embodiments, the plurality of memory cells include at least a first transistor of a first memory cell and a second transistor of a second memory cell, wherein the first transistor and the second transistor are based on a common drain / source structure.

[0452] In some embodiments, the memory device further includes: a plurality of readout circuitry systems arranged in association with corresponding groups of the plurality of groups of N bit lines, wherein each of the plurality of readout circuitry systems includes: (N-1) precharge transistors electrically coupled between a first power node carrying a first supply voltage and a corresponding bit line of the corresponding group of N bit lines; (N-2) discharge transistors electrically coupled between a second power node carrying a second supply voltage and a second bit line up to the (N-1)th bit line of the corresponding group of N bit lines, wherein an Nth bit line of the corresponding group of N bit lines is used to carry the second supply voltage; and The unit metadata sampling device includes (Ni) unit metadata sampling devices for each index i ranging from 1 to (N-1), each unit metadata sampling device having a data input node electrically coupled to the i-th bit line of the N bit lines of the corresponding group.

[0453] In some embodiments, the Each of the unit metadata sampling devices corresponds to a flip-flop or a latch.

[0454] In some embodiments, one of the readout circuit systems in the plurality of readout circuit systems is used to receive (N-1) sampled clock signals, and for each index i in the range from 1 to (N-1), applies an i-th sampled clock signal from the (N-1) sampled clock signals to the clock or enable node of (Ni) unit metadata sampling devices, the unit metadata sampling devices being electrically coupled to a first bit line to a (Ni)-th bit line among the N bit lines of the corresponding group.

[0455] In some embodiments, each of the plurality of readout circuit systems further includes (N-1) holders electrically coupled between a first bit line to a (N-1)th bit line in the N bit lines of the corresponding group at the first power node.

[0456] In some embodiments, the memory device further includes: a plurality of decoders, each of the plurality of decoders being electrically coupled to a corresponding readout circuit system in the plurality of readout circuit systems and configured to convert an output signal from the corresponding readout circuit system in the plurality of readout circuit systems into binary data.

[0457] In some embodiments, the memory device further includes: a decoder electrically coupled to the plurality of readout circuit systems and configured to convert output signals from the plurality of readout circuit systems into binary data.

[0458] In some embodiments, a method for detecting the information state of a memory cell in a memory device includes: in a precharge stage, electrically coupling the first bit line to the (N-1)th bit line of a set of N bit lines arranged in association with the memory cell of the memory device to a first power node carrying a first supply voltage, where N is an integer equal to or greater than 3, wherein the Nth bit line of this set of N bit lines is used to carry a second supply voltage. The memory cell includes a transistor, the transistor including a gate terminal and two drain / source terminals, and the electrical coupling relationship between the two drain / source terminals and the set of N bit lines indicates the information state of the memory cell. This method includes applying a word line signal to the gate terminal of the transistor to turn on the transistor, and detecting the electrical coupling relationship between the two drain / source terminals and the set of N bit lines based on (N-1) read stages. The (N-1) read stages include, during the first read stage of the (N-1) read stages, determining, based on the discharge state of the first bit line up to the (N-1) bit line, that one of the two drain / source terminals is electrically coupled to the Nth bit line, and the other of the two drain / source terminals is electrically coupled to one of the first bit line up to the (N-1) bit line. The (N-1) read stages include: for each index i ranging from 2 to (N-1), performing the i-th read stage of the (N-1) read stages, including electrically coupling the (N-i+1)-th bit line to a second power node carrying a second supply voltage during the i-th read stage; and during the i-th read stage, determining, based on the discharge state of the first bit line up to the (Ni)-th bit line, that one of the two drain / source terminals is electrically coupled to the (N-i+1)-th bit line and the other of the two drain / source terminals is electrically coupled to one of the first bit lines up to the (Ni)-th bit lines, or, based on the discharge state of the first bit line up to the (Ni)-th bit line and based on i being (N-1), determining that the two drain / source terminals are electrically coupled to the same bit line in a set of N bit lines.

[0459] In some embodiments, the method further includes converting the information state of the memory cell indicated by the detected electrical coupling relationship into binary data.

[0460] In some embodiments, the detection of the electrical coupling between the two drain / source terminals and the group of N bit lines based on the (N-1) readout stages is performed by a readout circuit system comprising: (N-1) precharge transistors electrically coupled between the first power node carrying the first supply voltage and a corresponding bit line in a corresponding group of N bit lines; (N-2) discharge transistors electrically coupled between the second power node carrying the second supply voltage and a second bit line up to the (N-1)th bit line in the corresponding group of N bit lines, wherein an Nth bit line in the corresponding group of N bit lines carries the second supply voltage; and A unit metadata sampling device, for each index i ranging from 1 to (N-1), includes (Ni) unit metadata sampling devices, each unit metadata sampling device having a data input node electrically coupled to the i-th bit line of the corresponding group of N bit lines, and detecting the electrical coupling relationship between the two drain / source terminals and the group of N bit lines based on the (N-1) read stages further includes: for each index i ranging from 1 to (N-1), during the i-th read stage in the (N-1) read stages, enabling the (Ni) unit metadata sampling devices having a data input node electrically coupled to a first bit line to a (Ni)-th bit line of the corresponding group of N bit lines to acquire (Ni) sampled data; and from the The corresponding output node of the unit metadata sampling device obtains Data bits, the information state of this memory cell is based on this Data bit indicator.

[0461] In some embodiments, during the precharge phase, electrically coupling the first bit line to the (N-1)th bit line of the N bit lines to the first power node includes applying a precharge signal to the (N-1)th precharge transistor, and for each index i ranging from 2 to (N-1), electrically coupling the (N-i+1)th bit line to the second power node during the i-th read stage includes applying a (i-1)th discharge signal to a (N-i+1)th discharge transistor of the (N-2)th discharge transistor.

[0462] In some embodiments, the readout circuitry further includes (N-1) holds electrically coupled between the first power node and a first bit line up to a (N-1)th bit line in the set of N bit lines, and detecting the electrical coupling between the two drain / source terminals and the set of N bit lines based on the (N-1) readout stages further includes: for each index i ranging from 2 to (N-1), during the i-th readout stage, applying a (N-i+1)th hold coupled to the (N-i+1)th bit line based on the (i-1)th discharge signal or a logic complement of the (i-1)th discharge signal.

[0463] In some embodiments, the Each of the unit metadata sampling devices corresponds to a flip-flop or a latch, and detecting the electrical coupling between the two drain / source terminals and the set of N bit lines based on the (N-1) read stages further includes: for each index i ranging from 1 to (N-1), during the i-th read stage, applying an i-th sampling clock signal to the clock or enable node of the (Ni) unit metadata sampling devices, which are electrically coupled to a first bit line to a (Ni)-th bit line in the set of N bit lines.

[0464] In some configurations, the semiconductor device includes N conductive lines configured as N bit lines, another conductive line configured as a word line, and a first memory cell including a first transistor. This first transistor includes a first gate terminal and two first drain / source terminals, where N is an integer equal to or greater than 3. The first gate terminal is electrically coupled to the word line. The two first drain / source terminals are electrically coupled to the same bit line among the N bit lines or between two bit lines, indicating a first information state of the first memory cell. This first information state is... One of the candidate information states. Candidate information states include those electrically coupled to N bit lines. The two drain / source terminals of different parasite lines correspond to A candidate information state, and a candidate information state corresponding to N different cases of the two drain / source terminals of the same bit line electrically coupled to N bit lines.

[0465] In some embodiments, the first transistor corresponds to an n-type transistor, and the N bit lines include a bit line for carrying a lower supply voltage or a ground reference voltage.

[0466] In some embodiments, the first transistor corresponds to a p-type transistor, and the N bit lines include a bit line for carrying a higher supply voltage.

[0467] In some embodiments, the semiconductor device further includes: a second memory cell including a second transistor, the second transistor including a second gate terminal and two second drain / source terminals, wherein one of the two first drain / source terminals of the first transistor and one of the two second drain / source terminals of the second transistor are based on a common drain / source structure.

[0468] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of one embodiment of this disclosure. Those skilled in the art should understand that one embodiment of this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of one embodiment of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of one embodiment of this disclosure.

Claims

1. A memory device, characterized in that, Include: A memory cell array comprising multiple memory cells arranged in columns and bars; Multiple word lines are arranged in association with corresponding columns of the multiple memory cells of the memory cell array; as well as Multiple groups of N bit lines are arranged in association with corresponding columns of the plurality of memory cells in the memory cell array, where N is an integer equal to or greater than 3. Each of the plurality of memory cells in the memory cell array comprises: A transistor includes a gate terminal and two drain / source terminals. The gate terminal is electrically coupled to a corresponding word line among the plurality of word lines. The two drain / source terminals are electrically coupled to an identical bit line or two bit lines in a corresponding group of N bit lines from the plurality of groups of N bit lines, and an electrical coupling relationship between the two drain / source terminals and the corresponding group of N bit lines indicates One of the candidate information states, and Should The candidate information state includes N bit lines electrically coupled to the corresponding group. The two drain / source terminals of different parasite lines correspond to Candidate information states, and the plurality of candidate information states include one candidate information state corresponding to N different cases of the two drain / source terminals of the same bit line electrically coupled to the N bit lines of the corresponding group.

2. The memory device as claimed in claim 1, characterized in that, in Each transistor in the plurality of memory cells corresponds to an n-type transistor, and Each of the multiple groups of N bit lines includes a bit line for carrying a lower supply voltage or a ground reference voltage.

3. The memory device as claimed in claim 1, characterized in that, in Each transistor in the plurality of memory cells corresponds to a p-type transistor, and Each of the multiple groups of N bit lines includes a bit line for carrying a higher supply voltage.

4. The memory device as claimed in claim 1, characterized in that, in The plurality of memory cells include at least a first transistor in a first memory cell and a second transistor in a second memory cell, and The first transistor and the second transistor are based on a common drain / source structure.

5. The memory device as claimed in claim 1, characterized in that, Further includes: Multiple readout circuit systems are arranged in association with corresponding groups of the multiple sets of N bit lines. Each of the plurality of readout circuit systems comprises: (N-1) precharged transistors are electrically coupled between a first power node carrying a first supply voltage and a corresponding bit line in a corresponding group of N bit lines; (N-2) discharge transistors are electrically coupled between a second power node carrying a second supply voltage and the second bit line to the (N-1)th bit line in the corresponding group of N bit lines, wherein the Nth bit line in the corresponding group is used to carry the second supply voltage. as well as The unit metadata sampling device includes (Ni) unit metadata sampling devices for each index i ranging from 1 to (N-1), each unit metadata sampling device having a data input node electrically coupled to the i-th bit line of the N bit lines of the corresponding group.

6. The memory device as claimed in claim 5, characterized in that, in One of the multiple readout circuit systems is used to receive (N-1) sampled clock signals, and For each index i ranging from 1 to (N-1), the i-th sampled clock signal of the (N-1) sampled clock signals is applied to the clock or enable node of the (Ni) unit metadata sampling device, which is electrically coupled to a first bit line to a (Ni)-th bit line of the N bit lines of the corresponding group.

7. The memory device as claimed in claim 5, characterized in that, in Each of the plurality of readout circuit systems further includes (N-1) holders electrically coupled between a first bit line to a (N-1)th bit line in the N bit lines of the corresponding group at the first power node.

8. The memory device as claimed in claim 5, characterized in that, Further includes: A decoder is electrically coupled to the plurality of readout circuit systems and is used to convert the output signals from the plurality of readout circuit systems into binary data.

9. A method for detecting the information state of a memory device, characterized in that, Include: In a precharge stage, a first bit line to a (N-1)th bit line from a set of N bit lines arranged in association with a memory cell of a memory device are electrically coupled to a first power node carrying a first supply voltage, where N is an integer equal to or greater than 3. The Nth bit line in this group of N bit lines is used to carry a second supply voltage. The memory cell includes a transistor. The transistor includes a gate terminal and two drain / source terminals, and An electrical coupling relationship between the two drain / source terminals and the set of N bit lines indicates an information state of the memory cell; A word signal is applied to the gate of the transistor to turn it on; as well as Detecting the electrical coupling between the two drain / source terminals and the set of N bit lines based on (N-1) readout stages includes: During a first read stage in the (N-1) read stages, based on a discharge state from the first bit line to the (N-1)th bit line, it is determined that one of the two drain / source terminals is electrically coupled to the Nth bit line, and the other of the two drain / source terminals is electrically coupled to one of the first bit line to the (N-1)th bit line; and For each index i ranging from 2 to (N-1), execute the i-th read level among the (N-1) read levels, including: During the i-th read stage, a (N-i+1)-th bit line is electrically coupled to a second power node carrying the second supply voltage; and During the i-th read stage, based on a discharge state of the first bit line to the (Ni)-th bit line, it is determined that one of the two drain / source terminals is electrically coupled to the (N-i+1)-th bit line and the other of the two drain / source terminals is electrically coupled to one of the first bit line to the (Ni)-th bit line; or based on the discharge state of the first bit line to the (Ni)-th bit line and based on i-system (N-1), it is determined that the two drain / source terminals are electrically coupled to an identical bit line in the group of N bit lines.

10. A semiconductor device, characterized in that, Include: N conductive lines are configured as N bit lines, where N is an integer equal to or greater than 3; Another conductive wire is configured as a single line; and A first memory cell includes a first transistor, the first transistor including a first gate terminal and two first drain / source terminals. in The first gate terminal is electrically coupled to the word line. The two first drain / source terminals are electrically coupled to one or two identical bit lines among the N bit lines, indicating a first information state of the first memory cell. This first information state is... One of the candidate information states, and Should Candidate information states include those electrically coupled to the N bit lines. The two first drain / source terminals of different parasite lines correspond to A candidate information state, and a candidate information state corresponding to N different cases of the two first drain / source terminals of the same bit line electrically coupled to the N bit lines.

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