Random access memory testing methods, apparatus, electronic devices, storage media and products

Abstract

This application discloses a random access memory (RAM) testing method, apparatus, electronic device, storage medium, and product. The RAM testing method includes: loading a test program into SRAM according to test instructions from a host computer, assuming successful DDR initialization; and running the test program to test the DDR. This technical solution, by loading the test program into SRAM, physically isolates the test program from the test space, avoiding the dependence of the test startup process on the normal operation of the DDR, and enables full-space testing of the DDR, thus improving test reliability.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a random access memory testing method, apparatus, electronic device, storage medium, and product. Background Technology

[0002] With the ever-increasing demands of modern electronic systems for memory capacity and performance, Double Data Rate Synchronous Dynamic Random Access Memory (DDR) has become a core component of computer systems. The reliability and stability of DDR memory directly affect the normal operation of the entire system; therefore, comprehensive testing of DDR is crucial in product manufacturing, factory testing, and fault diagnosis.

[0003] Currently, the mainstream DDR testing solutions mainly fall into two categories: The first category is the memtest86 testing tool based on Unified Extensible Firmware Interface (UEFI) firmware. memtest86 is a widely used open-source memory testing tool. Its working principle is to load the test code into DDR memory through the UEFI bootloader. This type of testing solution has the following limitations: The test program must rely on the UEFI firmware to boot, but the UEFI itself runs in DDR memory. When the DDR has physical faults (such as chip damage or short circuits) that prevent the UEFI from booting normally, the testing tool cannot run at all, forming a logical paradox of "to test DDR, you must first run DDR"; The memory space occupied by the UEFI firmware and the memtest86 program itself is shielded during the test, making it impossible to achieve a true full-space coverage test. The untested area may contain faulty cells; memtest86 uses a single-core or limited multi-core serial test mode, and it takes nearly 2 hours to complete a single full test of 16GB DDR4 memory, which seriously affects production efficiency. The second category is MemTester tools based on the Linux operating system. These testing solutions have the following limitations: they rely on the Linux operating system to start normally, and the test cannot be executed when a DDR failure causes a kernel panic or the root file system cannot be mounted; the physical address fragmentation corresponding to dynamic memory allocation (Malloc) is severe, making it impossible to achieve comprehensive testing of the contiguous physical address space, and it is easy to miss faults that interfere with each other in adjacent units; due to the limitations of the operating system's memory management, areas such as kernel space and reserved memory cannot be tested, and the actual coverage is usually less than 80% of the total capacity.

[0004] In summary, the main problem with the aforementioned DDR testing scheme lies in the spatial coupling contradiction between the execution unit and the test object. The test program must run within the DDR space, making it impossible to test the memory area occupied by the program itself, thus failing to achieve a complete test of the entire space. Furthermore, when a DDR failure causes the UEFI or operating system (OS) to fail to boot, the existing testing tools become completely ineffective. How to improve the reliability of DDR testing is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a random access memory (DDR) testing method, apparatus, electronic device, storage medium, and product to improve the reliability of DDR testing.

[0006] In a first aspect, embodiments of this application provide a random access memory (RAM) testing method, including:

[0007] Receive test commands from the host computer;

[0008] According to the test instructions, if the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) is successfully initialized, the test program is loaded into the Static Random-Access Memory (SRAM).

[0009] Run the test program to test the DDR.

[0010] Secondly, embodiments of this application also provide a random access memory testing apparatus, comprising:

[0011] The receiving module is used to receive test commands from the host computer.

[0012] The loading module is used to load the test program into the static random access memory (SRAM) according to the test instructions, provided that the DDR initialization is successful.

[0013] The test module is used to run the test program to test the DDR.

[0014] Thirdly, embodiments of this application provide an electronic device, including:

[0015] One or more processors;

[0016] Storage device for storing one or more programs;

[0017] When the one or more programs are executed by the one or more processors, the one or more processors implement the random access memory testing method as described in the first aspect.

[0018] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the random access memory testing method as described in the first aspect.

[0019] Fifthly, embodiments of this application also provide a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the random access memory testing method as described in any of the above embodiments.

[0020] This application provides a random access memory (RAM) testing method, apparatus, electronic device, storage medium, and product. The RAM testing method includes: receiving a test instruction from a host computer; loading a test program into SRAM according to the test instruction, assuming successful DDR initialization; and running the test program to test the DDR. This technical solution, by loading the test program into SRAM, physically isolates the test program from the test space, avoiding the dependence of the test startup process on the normal operation of the DDR, and enables full-space testing of the DDR, thus improving test reliability. Attached Figure Description

[0021] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0022] Figure 1 A flowchart of a random access memory testing method provided in this application embodiment;

[0023] Figure 2 A schematic diagram of a test system for random access memory provided in one embodiment;

[0024] Figure 3 A schematic diagram illustrating a testing process for a random access memory (RAM) according to one embodiment;

[0025] Figure 4 This is a schematic diagram of a random access memory testing device provided in an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0027] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present application, not the entire structure.

[0028] Before discussing the exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. The process can be terminated when its operation is complete, but may also have additional steps not included in the figures. The process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0029] It should be noted that the concepts of "first" and "second" mentioned in the embodiments of this application are only used to distinguish different devices, modules, units or other objects, and are not used to limit the order of functions performed by these devices, modules, units or other objects or their interdependencies.

[0030] It should also be noted that, unless otherwise specified, "multiple" in the embodiments of this application refers to at least two.

[0031] Furthermore, the embodiments and features described in this application may be combined with each other, unless otherwise specified.

[0032] The acquisition, storage, use, and processing of data in this application all comply with the relevant provisions of national laws and regulations.

[0033] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the relevant content of the solution.

[0034] Figure 1This is a flowchart illustrating a random access memory (RAM) testing method provided in an embodiment of this application. This embodiment is applicable to testing random access memory (DDR). Specifically, this RAM testing method can be executed by a RAM testing device, which can be implemented in software and / or hardware and integrated into an electronic device. Electronic devices include, but are not limited to, computers, servers, system-on-chips (SoCs), field-programmable gate arrays (FPGAs), or microcontroller units (MCUs), etc. Figure 1 As shown, the method specifically includes the following steps:

[0035] S110: Receive test commands from the host computer.

[0036] For example, the host computer sends a test command to the electronic device to initiate the test process. The test process may include test parameters for the DDR, such as test time, test space size, number of loops, divided test tasks or sub-tasks, number of CPU cores used to execute the test tasks or sub-tasks, and / or the test algorithm used. The electronic device then performs the test on the DDR accordingly.

[0037] S120. According to the test instructions, if the DDR initialization is successful, the test program is loaded into the SRAM.

[0038] For example, the test program could originally be stored in a non-volatile memory device such as flash memory. Upon receiving a test instruction and successfully initializing DDR, the test program can be moved from the flash memory or loaded into the SRAM for execution.

[0039] S130. Run the test program to test the DDR.

[0040] Figure 2 This is a schematic diagram of a test system for a random access memory (RAM) according to one embodiment. Figure 2As shown, the SOC stands for System-on-Chips. The Host PC serves as the terminal for test control and result analysis, providing a graphical configuration interface, issuing test commands to the SOC, and featuring real-time log monitoring and fault location capabilities. It can communicate with the SE and AP via a text log protocol, supports regular expression parsing, and enables dynamic parameter distribution and result visualization. The Secure Engine (SE) is the on-chip trusted execution environment. As the trusted control core, it is responsible for DDR initialization, test program loading, application processor (AP) core lifecycle management, and fault information relay. It has independent SRAM space and Flash access permissions, and is independent of DDR and OS. Test programs are loaded into the SOC's built-in SRAM. The application processor contains N CPU cores (typically 4-64 cores), which execute actual DDR test tasks under the control of the SE. Each CPU core has an independent SRAM stack space and a shared test parameter area. Each CPU core operates statelessly, only reading the shared SRAM parameter area. After the test is completed, it automatically enters a low-power Wait For Interrupt (WFI) state.

[0041] Figure 3 This is a schematic diagram illustrating a testing process for a random access memory (RAM) according to one embodiment. Figure 3 As shown, the testing process for random access memory mainly includes:

[0042] 1. The tester starts the test via the start button on the host computer;

[0043] 2. The host computer starts listening to the log information on the serial port;

[0044] 3. The tester will boot the board carrying the DDR under test, and then start the SE.

[0045] 4. When the host computer detects that the SE has started, it sends a test command to the SE for the DDR according to the user's configuration. The test command may include at least one of the following test parameters: the starting address of the DDR, the length, the test algorithm used, the number of CPU cores, and the CPU cores used for the test.

[0046] 5. After receiving the instruction, the SE parses and saves the test parameters to the shared memory area of ​​the on-chip SRAM.

[0047] 6. SE initializes DDR;

[0048] 7. The host computer checks whether there is an error in DDR initialization. If there is an error, it parses the incorrect channel number from the log, reports the error information, and exits the test process.

[0049] 8. If DDR initialization is successful, SE is responsible for moving the DDR test program from Flash to the first address of the on-chip SRAM, then initializing and starting AP. During the AP startup process, basic initialization of the CPU is performed, including MMU, interrupts, cache, exception vector table, multi-core stack space, Malloc space, inter-core shared memory and other multi-core operating environment.

[0050] 9. The AP retrieves the test parameter information from the shared memory area, assigns test tasks to each CPU core according to the test memory start address and length specified by the user, and then starts the multi-core test.

[0051] 10. If the AP multi-core test fails to start, report a startup timeout error; if the AP multi-core test starts successfully, continuously monitor the serial port log output during the test.

[0052] 11. During the test, if an error message is found, the error address will be resolved to a Channel number and the error will be reported; if a DDR fault is found, the error address, expected data, and actual data will be output through the log information.

[0053] 12. The host computer detects that the test has ended, finds no error messages, and reports that the test has passed.

[0054] This application provides a random access memory (RAM) testing method that loads a test program into SRAM and uses SRAM as the execution space for the test program. During the test, all CPU instruction fetching and stack operations are completed in SRAM, thereby physically isolating the execution body from the test object and achieving complete decoupling between the test program and the DDR test space. This fundamentally solves the contradiction between the program execution space and the test space, avoids the dependence of the test startup process on the normal operation of DDR, and enables full-space testing of DDR, thus improving the reliability of the test.

[0055] In one embodiment, the method further includes: dividing the DDR into at least one block and assigning each block to a corresponding central processing unit (CPU) core; step 130 may specifically be: running a test program through each CPU core to perform parallel testing on each block.

[0056] In this embodiment, a multi-core parallel scheduling mechanism can be used to intelligently divide the DDR memory into blocks and allocate each block to different CPU cores for parallel testing. Dividing the DDR into blocks can also be understood as dividing the DDR testing task into test subtasks. For example, the DDR can be intelligently divided into blocks based on the user-specified test space size, CPU core mask, and / or number of CPU cores. The DDR can be divided into x blocks, each allocated to N CPU cores, where x and N are positive integers. When x=N, there is a one-to-one relationship between each block and each CPU core. x can also be different from N; the allocation can ensure a balanced multi-core test load, thereby completing the test task under maximum pressure and in the shortest time. Furthermore, if there is only one block (x=1), any one of the y CPU cores can be used for testing, or the main core can be used directly without activating other CPU cores. Based on this, multi-core parallel testing can improve testing efficiency.

[0057] In one embodiment, assigning each block to a corresponding CPU core includes:

[0058] The base block size is determined based on the total size of the DDR test space and the number of CPU cores;

[0059] The alignment granularity is determined based on the cache line size and page size;

[0060] Based on the starting address, base block size, and alignment granularity of each CPU core, determine the test address and test length allocated to each CPU core.

[0061] For example, assuming the total test space size is L, the starting address is A_start, the number of available CPU cores is N (determined by the user-configured mask), and the number i of each CPU core ranges from 0 to N-1, then the initial test space allocation process for CPU core i includes:

[0062] Determine the size of the basic block S: S = L / N;

[0063] Determine the alignment granularity U: U = MAX(Cache_Line_Size, Page_Size), where Cache_Line_Size represents the cache line size and Page_Size represents the page size;

[0064] The starting address of CPU core i is: A_start + I × ROUND_UP(S, U), where ROUND_UP(Cache_Line_Size, Page_Size) means incrementing Cache_Line_Size upwards until it can satisfy the alignment of Page_Size (which is an integer multiple of Page_Size).

[0065] For the first N-1 CPU cores: the test length for CPU core i (i is less than N-1) is ROUND_UP(base block size, alignment granularity);

[0066] For the last CPU core: the test length of CPU core N-1 is L minus the sum of ROUND_UP (base block size, alignment granularity) for the first N-1 CPU cores, that is, the last core processes the remaining space other than the test space of the first N-1 CPU cores.

[0067] Based on this, the test space can be reasonably and evenly allocated while ensuring alignment, providing a reliable foundation for parallel testing.

[0068] In one embodiment, the SRAM is divided into the following functional areas:

[0069] Code segment (.text): Used to store test programs, approximately 100-200KB in size, 4-byte aligned;

[0070] The data segment (.data / .bss) is used to store global variables and static data structures defined in the test program, and its size is approximately 32KB.

[0071] Shared parameter area: Used to store test parameters and test results contained in test instructions. It can use atomic variables to achieve lock-free synchronization and is about 4KB in size.

[0072] Inter-core communication area: used to realize synchronization between CPU cores and the allocation of DDR blocks (i.e., task distribution), approximately 8KB in size;

[0073] Stack space: The AP core has a private stack space used to store information during function calls. Each CPU core is allocated independently, and the size is approximately 2KB per CPU core.

[0074] Heap space: Malloc heap space is used to store dynamic data structures for dynamic memory allocation, and its size is approximately 128KB.

[0075] In one embodiment, the multi-core test environment is initialized when the AP starts up, that is, before the test program is run through each CPU core, including at least one of the following:

[0076] 1) Memory Management Unit (MMU): This establishes a 1:1 mapping of SRAM space, maps the DDR test space to strongly-ordered or device attributes, and disables caching and write-combine mechanisms to ensure that test data is written directly to DDR without passing through the cache, thus preventing the cache from masking real faults.

[0077] 2) Setting up a separate exception vector in SRAM for locating and executing exception handlers can capture exceptions such as data abort and watchdog timeout restart, preventing test errors from causing system crashes;

[0078] 3) Wake up each CPU core based on event management instructions (such as Send Event (SEV) or WaitFor Event (WFE));

[0079] 4) Configure a spinlock to protect the shared parameter area in SRAM, thereby protecting critical access to the shared parameter area;

[0080] 5) Allocate the temporary buffers required by the test algorithm using a memory allocator (such as the lightweight malloc function).

[0081] Based on this, a stable and reliable testing environment is provided for DDR testing, thereby improving the reliability of the test.

[0082] In one embodiment, the test instruction includes a test algorithm specified by an algorithmic bitmask combination; the test algorithm includes at least one of the following:

[0083] The traversal-based fault detection algorithm (March C) can detect stuck-at faults, transition faults, and coupled faults, with a time complexity of O(n).

[0084] The checkerboard algorithm can detect interference between adjacent cells, with alternating modes of 0x55 and 0xAA.

[0085] The Walking 1 / 0 algorithm can detect address decoding faults, with a time complexity of O(n·log n).

[0086] Algorithms based on pseudo-random codes (such as pseudo-random binary sequences (PRBS)) can detect time-sensitive faults.

[0087] Based on the bit spread / flip algorithm, it can systematically test each individual bit and the influence between adjacent bits;

[0088] The Block Sequential algorithm can detect address decoder failures and bank collisions.

[0089] Based on this, by configuring the test algorithm library, test algorithms corresponding to various DDR fault models can be implemented. Users can specify the algorithm to be tested by combining algorithm bitmasks, thereby improving the comprehensiveness and flexibility of the test.

[0090] In one embodiment, the number of CPU cores is at least two, including a master core and at least one slave core; allocating each block to a corresponding CPU core includes: performing at least one round of allocation through the master core, in each round of allocation, allocating each block to a corresponding CPU core, and determining the target test algorithm to be used in this round of testing; running the test program through each CPU core includes: in each round of testing, testing the corresponding block through each CPU core according to the target test algorithm corresponding to this round of testing.

[0091] In this embodiment, a two-layer nested loop test architecture and fault triggering mechanism can be adopted. The outer loop can be scheduled and executed by the master core (such as Core 0). The loop granularity can be the number of algorithm rounds. In each round, the test tasks of each slave core can be reallocated. Work stealing and dynamic rebalancing can be considered. Different test algorithms can also be switched or combined (such as using the March C algorithm in the first round and the Checkerboard algorithm in the second round). The inner loop can be executed in parallel by slave cores (such as Core1, Core2...CoreN). The loop granularity can be a single test block. Read and write tests are performed according to the specified algorithm within the allocated task space.

[0092] Based on this, the traditional single-layer linear testing mode is deconstructed into a nested structure of "outer master core scheduling loop" and "inner slave core task loop". Through diverse loop combination strategies, complex address access patterns and timing pressures are generated, thereby effectively stimulating deep faults that are difficult to cover by traditional testing. The total testing intensity can be determined by the number of outer loops, the number of inner loops, and the algorithm complexity.

[0093] The random access memory testing method of this application has the following advantages:

[0094] The testing strategy is flexible: it provides a flexible parameter configuration interface, supporting dynamic configuration of test start address, length, algorithm combination mask, CPU core mask, inner loop count, and outer loop count, realizing multi-level testing capabilities from granular-level rapid screening to full-space in-depth stress testing. It can achieve rapid screening on the production line: using only the March C-algorithm, the test time is less than 5 minutes. It can also achieve in-depth R&D testing: with the full algorithm combination, the test time is about 16 minutes. It can also achieve fault reproduction: repeated testing of a specified address range to assist in signal integrity analysis.

[0095] 100% test reachability: Completely eliminates the boot dependency on DDR. Even in the event of complete DDR failure, SE can still boot from Flash and execute tests, solving the test blind spot problem in failure scenarios.

[0096] Achieve true / full space coverage: The test program runs in SRAM and does not occupy any DDR space. With the DDR controller configuration, it can achieve 100% coverage from physical address 0 to the maximum capacity, including the UEFI / OS area reserved in traditional solutions.

[0097] Testing efficiency can be improved by 5-10 times: In actual testing on a 4-core ARM Cortex-A720@1.8GHZ platform, the test time for 16GB DDR4-5500 memory was reduced from 120 minutes on memtest86 to 16 minutes. The efficiency improvement comes from maximizing the parallelism of multiple cores (N cores are tested in parallel).

[0098] It can be configured with multiple algorithm combinations and testing strategies, such as an algorithm masking mechanism: supporting bitwise combinations of various algorithms such as March C-, Checkerboard, Walking 1 / 0, PRBS, Block Sequential, and Bit Spread / Flip; a CPU core masking mechanism: supporting the specification of the CPU core used for DDR testing to maximize the utilization of hardware resources; and an inner and outer loop mechanism: the inner loop is the task loop within each CPU core, and the outer loop is the main core scheduling loop. The product of the two is the total number of loops. Through diverse loop combination strategies, complex address access patterns and timing pressures are generated, thereby effectively stimulating deep faults that are difficult to cover by traditional testing.

[0099] Figure 4 This is a schematic diagram of a random access memory testing device provided in an embodiment of this application. Figure 4 As shown, the random access memory testing apparatus provided in this embodiment includes:

[0100] The receiving module 210 is used to receive test commands from the host computer;

[0101] The loading module 220 is used to load the test program into the static random access memory (SRAM) according to the test instructions, provided that the double-rate synchronous dynamic random access memory (DDR) is successfully initialized.

[0102] Test module 230 is used to run the test program to test the DDR.

[0103] This device loads the test program into SRAM, physically isolating the test program from the test space, avoiding the dependence of the test startup process on the normal operation of DDR, and enabling full-space testing of DDR, thus improving the reliability of the test.

[0104] Based on any of the above embodiments, the device further includes: an allocation module, configured to divide the DDR into at least one block and allocate each block to a corresponding CPU core; the test module 230 is specifically configured to: run the test program through each of the CPU cores to perform parallel testing on each block.

[0105] Based on any of the above embodiments, the allocation module includes:

[0106] The size determination unit is used to determine the base block size based on the total size of the DDR test space and the number of CPU cores;

[0107] Alignment units are used to determine the alignment granularity based on cache line size and page size;

[0108] The allocation unit is used to determine the test address and test length allocated to each CPU core based on the starting address of each CPU core, the base block size, and the alignment granularity.

[0109] Based on any of the above embodiments, the SRAM is divided into the following functional areas:

[0110] Code segment: Used to store the test program;

[0111] Data segment: Used to store global variables and static data structures defined in the test program;

[0112] Shared parameter area: used to store the test parameters contained in the test instructions;

[0113] Inter-core communication area: used to realize synchronization between CPU cores and the allocation of DDR blocks;

[0114] Stack space: used to store information during function calls;

[0115] Heap space: Used to store dynamic data structures.

[0116] Based on any of the above embodiments, before running the test program through each of the CPU cores, the apparatus further includes: an initialization module, used for at least one of the following:

[0117] Map the DDR test space to a strong order attribute or device attribute, and disable the caching mechanism and write merging mechanism;

[0118] An exception vector is set in the SRAM for locating and executing the exception handler;

[0119] Each CPU core is woken up based on event management commands;

[0120] Configure a spinlock to protect the shared parameter region in the SRAM;

[0121] Allocate the temporary buffer required by the test algorithm using the memory allocator.

[0122] Based on any of the above embodiments, the test instruction includes a test algorithm specified by combining algorithmic bitmasks; the test algorithm includes at least one of the following: a fault detection algorithm based on traversal; a chessboard algorithm; a walk 1 / 0 algorithm; an algorithm based on pseudo-random codes; an algorithm based on bit spread / bit flip; and a block order algorithm.

[0123] Based on any of the above embodiments, the number of CPU cores is at least two, and the at least two CPU cores include one master core and at least one slave core;

[0124] The process of assigning each block to a corresponding CPU core includes:

[0125] At least one round of allocation is performed through the main core. In each round of allocation, each block is assigned to a corresponding CPU core, and the target test algorithm to be used in this round of testing is determined.

[0126] Running the test program via each of the CPU cores includes:

[0127] In each round of testing, each CPU core is used to test the corresponding blocks according to the target test calculation for that round.

[0128] The random access memory testing apparatus provided in this application can be used to execute the random access memory testing method provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0129] Figure 5A schematic diagram of an electronic device 10, which can be used to implement embodiments of this application, is shown. The electronic device 10 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 10 may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, user equipment, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0130] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0131] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks and wireless networks.

[0132] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above.

[0133] In some embodiments, the methods described above can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the methods of any of the embodiments described above by any other suitable means (e.g., by means of firmware).

[0134] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0135] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0136] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0137] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device 10, which includes: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device 10. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0138] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0139] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0140] This application also provides a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the random access memory testing method as described in any of the above embodiments.

[0141] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0142] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for testing random access memory, characterized in that, include: Receive test commands from the host computer; According to the test instructions, if the Double Rate Synchronous Dynamic Random Access Memory (DDR) is successfully initialized, the test program is loaded into the Static Random Access Memory (SRAM). Run the test program to test the DDR.

2. The method according to claim 1, characterized in that, Also includes: The DDR is divided into at least one block, and each block is assigned to a corresponding central processing unit (CPU) core; Running the test program to test the DDR includes: The test program is run by each of the CPU cores to perform parallel testing on each block.

3. The method according to claim 2, characterized in that, The process of assigning each block to a corresponding CPU core includes: The base block size is determined based on the total size of the DDR test space and the number of CPU cores; The alignment granularity is determined based on the cache line size and page size; Based on the starting address of each CPU core, the base block size, and the alignment granularity, the test address and test length allocated to each CPU core are determined.

4. The method according to claim 2, characterized in that, Before running the test program via each of the CPU cores, at least one of the following is also included: Map the DDR test space to a strong order attribute or device attribute, and disable the caching mechanism and write merging mechanism; An exception vector is set in the SRAM for locating and executing the exception handler; Each CPU core is woken up based on event management commands; Configure a spinlock to protect the shared parameter region in the SRAM; Allocate the temporary buffer required by the test algorithm using the memory allocator.

5. The method according to claim 1, characterized in that, The test instruction includes a test algorithm specified by combining algorithmic bitmasks; the test algorithm includes at least one of the following: a fault detection algorithm based on traversal; a chessboard algorithm; a move 1 / 0 algorithm; an algorithm based on pseudo-random codes; an algorithm based on bit spread / bit flip; and a block order algorithm.

6. The method according to claim 2, characterized in that, The number of CPU cores is at least two, and the at least two CPU cores include one master core and at least one slave core; The process of assigning each block to a corresponding CPU core includes: At least one round of allocation is performed through the main core. In each round of allocation, each block is assigned to a corresponding CPU core, and the target test algorithm to be used in this round of testing is determined. Running the test program via each of the CPU cores includes: In each round of testing, each CPU core is used to test the corresponding blocks according to the target test calculation for that round.

7. A random access memory testing device, characterized in that, include: The receiving module is used to receive test commands from the host computer. The loading module is used to load the test program into the static random access memory (SRAM) according to the test instructions, provided that the double-rate synchronous dynamic random access memory (DDR) is successfully initialized. The test module is used to run the test program to test the DDR.

8. An electronic device, characterized in that, include: At least one processor; A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the random access memory testing method as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the random access memory testing method as described in any one of claims 1-6.

10. A computer program product comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the random access memory testing method as described in any one of claims 1-6.

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