A verification circuit, memory, and electronic device

Abstract

This disclosure provides a verification circuit, a memory, and an electronic device. The verification circuit is configured to encode and calculate target data based on an initial verification result and a preset verification matrix to generate verification data, and then send the verification data to a storage array for storage. The preset verification matrix includes a first verification matrix and a second verification matrix. The first verification matrix includes n first elements arranged in a first order, and the second verification matrix includes n second elements arranged in a second order. Both the first and second elements are primitive elements in the Galois field. n is a positive integer. The primitive elements covered by the n first elements and the primitive elements covered by the n second elements are of the same type, but the first and second orders are different.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a verification circuit, memory, and electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is the main memory of a computer, and the reliability of its data is of paramount importance. Therefore, error checking and correction (ECC) mechanisms are often used to improve the correctness of storage.

[0003] However, the current circuit modules used to implement the ECC mechanism have a large area and require a lot of processing time, which affects the improvement of memory performance. Summary of the Invention

[0004] This disclosure provides a verification circuit, a memory, and an electronic device.

[0005] The technical solution of this disclosure embodiment is implemented as follows: In a first aspect, embodiments of this disclosure provide a verification circuit configured to encode target data based on an initial check code and a preset check matrix to generate check data, and send the check data to a storage array for storage; the preset check matrix includes a first check matrix and a second check matrix; the first check matrix includes n first elements arranged in a first order, and the second check matrix includes n second elements arranged in a second order, wherein the first elements and the second elements are primitive elements in the Galois field; n is a positive integer; the types of primitive elements covered by the n first elements and the types of primitive elements covered by the n second elements are the same, and the first order and the second order are different.

[0006] In some embodiments, the number of identical primitives covered in the n first elements is the same as the number of identical primitives covered in the n second elements.

[0007] In some embodiments, the primitive elements covered by the n first elements are exactly the same as the primitive elements covered by the n second elements, and the primitive element type of the i-th first element is the same as the primitive element type of the (n-m+i)-th second element, where i is a positive integer and i is less than or equal to m, n=2m+1, and m is an integer.

[0008] In some embodiments, the encoding polynomial corresponding to the preset check matrix is: The encoding polynomial is: .

[0009] In some embodiments, the first verification matrix The second verification matrix .

[0010] In some embodiments, the first verification matrix The second verification matrix .

[0011] In some embodiments, the verification circuit includes a first encoding circuit and a second encoding circuit; The first encoding circuit is specifically configured to perform encoding calculations on the initial check code and the target data based on the first check matrix to generate first check data; wherein, the first check data includes s-bit check bits; The second encoding circuit is specifically configured to perform encoding calculations on the initial check code and target data based on the second check matrix to generate second check data; wherein, the second check data includes s check bits; s is a positive integer; The first encoding circuit includes s first arithmetic circuits, each corresponding to one of the s-bit check bits of the first check data; the second encoding circuit includes s second arithmetic circuits, each corresponding to one of the s-bit check bits of the second check data.

[0012] In some embodiments, the structure of the first encoding circuit and the structure of the second encoding circuit are the same.

[0013] In some embodiments, the same XOR operation circuit is reused among the first arithmetic circuits corresponding to different check bits of the first check data. The first arithmetic circuits corresponding to different check bits of the second check data reuse the same XOR operation circuit.

[0014] In a second aspect, embodiments of this disclosure provide a memory that includes the verification circuit described in the first aspect.

[0015] Thirdly, embodiments of this disclosure provide an electronic device, which includes the memory described in the second aspect.

[0016] This disclosure provides a verification circuit, a memory, and an electronic device. For the verification circuit, since the first verification matrix and the second verification matrix include the same type of primitive elements, the calculation logic based on the first verification matrix and the calculation logic based on the second verification matrix are similar, and the amount of calculation is almost the same. Therefore, the calculation time of the two is very small, and no additional time is wasted. In addition, since the amount of calculation is similar, the current consumption and line load are relatively balanced, the requirement for driving force is not large, resulting in stable performance. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the verification circuit provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the calculation elements corresponding to the first verification matrix provided in this disclosure; Figure 3 This is a schematic diagram of the calculation elements corresponding to the second verification matrix provided in this embodiment of the disclosure; Figure 4 This is a schematic diagram of the verification circuit provided in an embodiment of this disclosure; Figure 5 This is a partial schematic diagram of the first encoding circuit provided in this embodiment of the disclosure; Figure 6 This is a flowchart illustrating a data verification method provided in this disclosure. Figure 7 This is a flowchart illustrating another data verification method provided in this disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0022] First, the nouns and terms used in the embodiments of this disclosure will be explained: Dynamic Random Access Memory (DRAM); Synchronous Dynamic Random Access Memory (SDRAM); Double Data Rate SDRAM (DDR); Low-power DDR (LPDDR); Column Access Strobe Latency (tAA); Reed-Solomon Code (RSCode).

[0023] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0024] First, the ECC mechanism involved in the embodiments of this disclosure will be explained.

[0025] The ECC mechanism refers to: using a preset verification matrix, calculating the target data during the data writing process to generate verification data, and storing the target data and verification data together in the storage array; during the data reading process, calculating the read data and the read verification data again, and verifying whether the "read data" has an error based on the calculation result.

[0026] In a common example, the ECC mechanism can be designed based on Reed-Solomon codes (RS codes for short). RS codes can be represented in the form Reed-Solomon(a,b), where b refers to the number of bytes the target data is divided into, and a refers to the total number of bytes generated after encoding. For example, if the original data is 136 bits long, and the parity data generated by the aforementioned preset parity matrix is ​​16 bits, then with 8 bits per byte, it can be represented as Reed-Solomon(19,17).

[0027] The predefined parity-check matrix for Reed-Solomon codes can be designed based on Galois fields, or simply finite fields. A finite field is a concept in abstract algebra, referring to a field containing a finite number of elements. It can be understood as a numerical system that defines specific elements and specific operational rules. Galois fields possess the concept of primitives. For a given Galois field, powers of its primitives can generate the entire multiplicative group. The multiplicative group refers to the group formed by multiplying the non-zero elements in the Galois field.

[0028] Galois has the following characteristics; (1) Fixed number of elements: The number of elements in a Galois field must be a power of some prime number p, denoted as GF(p). nFor example, the most commonly used GF(2) in computers 8 The field contains 256 elements.

[0029] (2) Operations are closed and self-consistent: In this domain, the result obtained after performing addition, subtraction, multiplication, or division (with the divisor not being 0) on any two elements is still in this domain.

[0030] (3) The operation rules in the domain are not the integer operations we are familiar with. For example, in GF(2 8 In the field, addition is performed as an XOR operation, i.e., 1+1=0.

[0031] In one embodiment of this disclosure, please refer to Figure 1 The diagram illustrates a connection schematic of a verification circuit 10 provided in this embodiment. This verification circuit 10 can be applied to a memory, which can be DRAM, such as DDR, LPDDR, etc., for example, DDR4 memory, DDR5 memory, DDR6 memory, LPDDR4 memory, LPDDR5 memory, or LPDDR6 memory, stacked memory, etc. The memory includes a storage array comprising multiple storage cells arranged in an array for storing data.

[0032] Please see Figure 1 In (a), the verification circuit 10 is configured to encode and calculate the target data based on the initial check code and the preset check matrix to generate check data, and send the check data to the storage array for storage.

[0033] Please see Figure 1 In (b) of the above, the verification circuit 10 is further configured to read from the storage array to generate read data and read verification data, and to verify the read data based on the read verification data to confirm whether an error occurred in the target data during storage. Here, the read data can be regarded as the result of reading the target data, and the read verification data can be regarded as the result of reading the verification data.

[0034] Here, the initial checksum is default data, such as all 0s or all 1s, depending on the preset checksum matrix type. In this embodiment, the initial checksum is all 0s.

[0035] In this way, the verification circuit 10 can confirm whether errors have occurred in the target data during storage, thereby improving the reliability of data storage.

[0036] In this embodiment, the encoding of written data and the decoding of read data are completed by reusing the same verification circuit 10, saving hardware circuit resources. From the perspective of circuit implementation, it is necessary to distinguish between the two working states of writing and reading. For example, a first data selection module and a second data selection module are introduced. The first input terminal of the first data selection module receives the initial verification code and the target data (please refer to...). Figure 1 In (a) of the first data selection module, the second input terminal receives the read verification data and the read target data (please refer to...). Figure 1 In (b) of the above, the output of the first data selection module is connected to the input of the verification circuit 10; The input terminal of the second data selection module is connected to the output terminal of the verification circuit 10, and the first output terminal of the second data selection module outputs verification data (please refer to...). Figure 1 (a) of the second data selection module outputs the verification result at the second output terminal (please refer to...). Figure 1 (a) in the middle.

[0037] Both the control terminals of the first and second data selection modules receive read / write status signals: (1) If the read / write status signal indicates a write operation, the first data selection module selects the first input terminal and the output terminal, and the second data selection module selects the input terminal and the first output terminal, i.e. Figure 1 The working state is shown in (a) above; (2) If the read / write status signal indicates a read operation, the second data selection module selects the second input terminal and the second output terminal, i.e. Figure 1 The working state is shown in (b) of the diagram.

[0038] Here, the first data selection module and the second data selection module can each be implemented by combining multiple data selectors (Mux).

[0039] In this embodiment of the disclosure, the preset parity check matrix includes a preset parity check matrix. It should be understood that each element of the preset parity check matrix can also be regarded as a matrix. In this embodiment of the disclosure, the preset parity check matrix is ​​designed based on the Galois field, that is, the elements in the preset parity check matrix (also referred to as the element matrix) are primitive elements in the selected Galois field.

[0040] In some embodiments, the preset parity check matrix includes a first parity check matrix H0 and a second parity check matrix H1; the first parity check matrix H0 includes n first elements arranged in a first order, and the second parity check matrix H1 includes n second elements arranged in a second order, wherein the first and second elements are primitive elements in the Galois field; n is a positive integer; The types of primitive elements covered by the n first elements are the same as the types of primitive elements covered by the n second elements, but the first order and the second order are different; it should be understood that the primitive elements themselves are also matrices.

[0041] This disclosure uses the data writing process (which can also be regarded as the encoding process) as an example to illustrate the preset verification matrix. The data reading process (which can also be regarded as the decoding process) can be referred to in the following description.

[0042] Specifically, during the data writing process, the initial checksum is all zeros.

[0043] It should be understood that in this embodiment, the verification data includes two bytes, represented as S0 and S1 respectively. Specifically, the verification circuit 10 is configured to, during the data writing process, calculate a portion of the target data based on the first verification matrix H0 to generate the first byte of verification data S0, and calculate a portion of the target data based on the second verification matrix H1 to generate the second byte of verification data S1.

[0044] In this embodiment of the disclosure, the number of identical primitives covered in the n first elements is the same as the number of identical primitives covered in the n second elements.

[0045] Thus, both the first parity check matrix H0 and the second parity check matrix H1 include the same type and the same number of primitive elements. Therefore, the calculation methods for parity data S0 and parity data S1 are basically similar. On the one hand, since the computational workload of the two is similar, the computation time of the two is very small, and there will be no extra computation time wasted due to the small computational workload of parity data S0 but the large computational workload of parity data S1. On the other hand, since the computational workload of the two is also similar, the current consumption and line load are relatively balanced, the requirements for driving force are not large, and the performance is stable.

[0046] In this scenario, the Galois field encoding polynomial (also known as the primitive polynomial) that can be used for the preset parity-check matrix is: Here, x is a position marker (also known as a placeholder), which is essentially an algebraic abstraction, not an unknown in the usual sense. It can be understood as a basis generator of binary polynomial representation.

[0047] In one embodiment, the primitive elements covered by the n first elements are exactly the same as the primitive elements covered by the n second elements, and the primitive element type of the i-th first element is the same as the primitive element type of the (n-m+i)-th second element, where i is a positive integer and i is less than or equal to m, n=2m+1, and m is an integer.

[0048] In this way, the primitive elements of the first parity check matrix H0 can be transformed by translation to obtain the second parity check matrix H1. Thus, the calculation logic of the first parity check matrix H0 and the calculation logic of the second parity check matrix H1 are the same, only the objects being calculated are different. Therefore, the design methods of the hardware calculation circuit based on the first parity check matrix H0 and the hardware calculation circuit based on the second parity check matrix H1 can be reused, bringing convenience in layout design.

[0049] In one specific embodiment, a specific error correction scenario is provided: the target data has a total of 136 bits, represented as D<135:0>, with 8 bits as one byte, for a total of 17 bytes; at this time, the first parity check matrix H0 and the second parity check matrix H1 each have 17 primitive elements.

[0050] It should be noted that, regarding The complete set of primitive elements contained herein is as follows: .

[0051] The specific expressions of the primitives mentioned above are public knowledge in this field, and will not be shown one by one in this embodiment.

[0052] It should be understood that the parity check matrix requires all columns to be linearly uncorrelated, while in the Galois field... In this system, every 255 primitive elements constitute one cycle, that is... Therefore, assuming the parity matrix... One of the columns appeared ,but Another column in the middle appears, and another column cannot have it. , where j is a positive integer.

[0053] In other words, if a column in the check matrix has a value of ,but It cannot appear in the matrix, that is You can only choose one of the two primitive elements.

[0054] Based on this, choose the simpler one. The primitive elements in the matrix are used to construct the first parity-check matrix H0 and the second parity-check matrix H1. In this embodiment, the selected primitive elements are: However, other primitive elements mentioned can also be selected to construct the first and second parity check matrices according to the aforementioned rules.

[0055] In one example of this error correction scenario, the first check matrix H0 and the second check matrix H1 are represented as shown in equations (1) and (2), respectively: ...(1) ...(2) For ease of explanation, the 17-byte target data D<135:0> is represented as E0~E16. The calculation method of the check data S0 is shown in Equation (3) below, and the calculation method of the check data S1 is shown in Equation (4) below.

[0056] …(3) …(4) In this way, each primitive specifies the calculation method for the corresponding byte in the target data. It should be understood that one byte of the target data has 8 bits, represented as b7~b0.

[0057] Please refer to Table 1 below, which shows the specific types of primitive elements involved. Based on Table 1 and formula (3), we can obtain the following... Figure 2 The diagram shows the calculation elements of the verification data S0_0~S0_7; based on Table 1 and formula (4), we can obtain the following: Figure 3 The diagram shows the calculation elements for the verification data S1_0~S1_7. Figure 2 and Figure 3 In this diagram, each row corresponds to one bit in the validation data, and each column corresponds to one bit in the target data. For example, b0 in E0 (hereinafter referred to as E0_b0) refers to the target data D. <0> In E0, b1 refers to D <1> ...b0 in E1 (hereinafter referred to as E1_b0) refers to the target data D. <8> ...b7 in E16 (hereinafter referred to as E16_b7) refers to the target data D. <135> . Figure 2 and Figure 3 The "1" in the text indicates that the bit data corresponding to that column is used in the calculation of the corresponding check data in that row. Figure 2 The "0" in the column indicates that the bit data corresponding to that column is not included in the calculation of the check data corresponding to that row.

[0058] Table 1

[0059] Therefore, the specific calculation method for the check data S0_0~S0_7 during the encoding process is as follows:

[0060] Therefore, a total of 27 data points in S0_7 are XORed.

[0061]

[0062] Therefore, a total of 28 data points in S0_6 are XORed.

[0063]

[0064] Therefore, a total of 24 data points in S0_5 are XORed.

[0065]

[0066] Therefore, a total of 25 data points in S0_4 are XORed.

[0067]

[0068] Therefore, a total of 26 data points in S0_3 are XORed.

[0069]

[0070] Therefore, a total of 25 data points in S0_2 are XORed.

[0071]

[0072] Therefore, a total of 26 data points in S0_1 are XORed.

[0073]

[0074] Therefore, a total of 25 data points in S0_0 are XORed.

[0075] The following is based on Figure 3 The specific calculation method for the verification data S1_0~S1_7 is shown:

[0076] Therefore, a total of 27 data points in S1_7 are XORed.

[0077]

[0078] Therefore, a total of 28 data points in S1_6 are XORed.

[0079]

[0080] Therefore, a total of 24 data points in S1_5 are XORed.

[0081]

[0082] Therefore, a total of 25 data points in S1_4 are XORed.

[0083]

[0084] Therefore, a total of 26 data points in S1_3 are XORed.

[0085]

[0086] Therefore, a total of 25 data points in S1_2 are XORed.

[0087]

[0088] Therefore, a total of 26 data points in S1_1 are XORed.

[0089]

[0090] Therefore, a total of 25 data points in S1_0 are XORed.

[0091] It should be understood that since the initial check code is 0, it is essentially placeholder data (see further explanation below) and does not affect the result of the check data. Therefore, the initial check code is omitted in formulas (5) to (20).

[0092] Here's a specific calculation example: Assume that in each byte of the target data D135~D0, bit b0 is "data 1" and all other bits are "data 0". That is, only E0_b0, E1_b0, E2_b0, E3_b0, E4_b0, E5_b0, E6_b0, E7_b0, E8_b0, E9_b0, E10_b0, E11_b0, E12_b0, E13_b0, E14_b0, E15_b0, and E16_b0 are "data 1", and the rest are "data 0". Then, after calculating according to the above formula: S0_7~S0_0 = 11101000; S1_7~S1_0 = 11101000.

[0093] In this way, the verification data S0, S1 and the 136-bit target data will all be stored in the storage unit.

[0094] The following describes the process of reading out the data and verifying it, which can also be regarded as the decoding process.

[0095] For the read data, the XOR calculation is performed according to the above formula, and the XOR calculation result is XORed with the read verification data to obtain the verification results PC0_7 and PC1_7.

[0096] The following is a detailed explanation: the read data is denoted as D135'~D0', the divided bytes are represented as E16'~E0', and the read check data is denoted as S0_7' and S1_7'.

[0097]

[0098] Here, ReS0_7' and S0_7 are calculated in the same way, the difference being that the former is calculated by reading data, while the latter is calculated by writing target data. In other words, for formula (21), the content in its parentheses is calculated in the same way as formula (5). At this time, formula (21) involves a total of 28 data XORed.

[0099]

[0100] Similarly, ReS0_6' is calculated in the same way as S0_6. In other words, for formula (22), the content in its parentheses has the same calculation logic as formula (6), except that one is for the data written and the other is for the data read. At this time, formula (22) involves a total of 29 data XORed.

[0101] akin: PC0_5=S0_5' ReS0_5'; Please refer to formula (7) for the calculation method of ReS0_5', and replace it with the read data accordingly; PC0_4=S0_4' ReS0_4'; Please refer to formula (8) for the calculation method of ReS0_4', and replace it with the read data accordingly; PC0_3=S0_3' ReS0_3'; Please refer to formula (9) for the calculation method of ReS0_3', and replace it with the read data accordingly; PC0_2=S0_2' ReS0_2'; Please refer to formula (10) for the calculation method of ReS0_2', and replace it with the read data accordingly; PC0_1=S0_1' ReS0_1'; Please refer to formula (11) for the calculation method of ReS0_1', and replace it with the read data accordingly; PC0_0=S0_0' ReS0_0'; ​​Please refer to formula (12) for the calculation method of ReS0_0', and replace it with the read data accordingly; PC1_7=S1_7' Please refer to formula (13) for the calculation method of ReS1_7' and ReS0_7', and replace them with the read data accordingly; PC1_6=S1_6' Please refer to formula (14) for the calculation method of ReS1_6' and ReS0_6', and replace them with the read data accordingly; PC1_5=S1_5' Please refer to formula (15) for the calculation method of ReS1_5' and ReS0_5', and replace them with the read data accordingly; PC1_4=S1_4' Please refer to formula (16) for the calculation method of ReS1_4' and ReS0_4', and replace them with the read data accordingly; PC1_3=S1_3' Please refer to formula (17) for the calculation method of ReS1_3' and ReS0_3', and replace them with the read data accordingly; PC1_2=S1_2' Please refer to formula (18) for the calculation method of ReS1_2' and ReS0_2', and replace them with the read data accordingly; PC1_1=S1_1' Please refer to formula (19) for the calculation method of ReS1_1' and ReS0_1', and replace them with the read data accordingly; PC1_0=S1_0' Please refer to formula (20) for the calculation method of ReS1_0' and ReS0_0', and replace them with the read data accordingly.

[0102] It should be noted that after the verification calculation, if both the target data and the verification data are error-free, PC0=PC1=00000000; If an error occurs when reading byte E0 of the data, then: ; E1~E8 are similar; If an error occurs in byte E9 of the read data, then: ; Similar to E10~E16.

[0103] Taking the aforementioned scenario as an example (assuming that the first bit of each byte in the target data D135~D0 is "data 1" and the other bits are "data 0", S0_7~S0_0=11101000; S1_7~S1_0=11101000), and assuming that the data E0_b2 is mistakenly changed to "data 1" during storage; then, after calculation according to the above formula: ReS0'_7~ReS0'_0=11101100, ReS0_7~ReS0'_7'=11100000; thus, PC0_7~PC0_0=00000100, PC1_7~PC1_0=00001000.

[0104] According to Table 1 The operation method =[PC0_6 PC0_7, PC0_5 PC0_7,PC4,PC0_3,PC0_2,PC0_1,PC0_0 PC0_7,PC0_7]=00001000= Therefore, it can be determined that there is an error in the read data byte E0.

[0105] Overall, the embodiments of this disclosure provide a verification algorithm in which the primitive elements of the first verification matrix H0 and the second verification matrix H1 are of the same type and have the same calculation logic, and have the characteristics of balanced calculation time and balanced load driving; at the same time, the first verification matrix H0 and the second verification matrix H1 also have the characteristic of overlapping after translation.

[0106] In another example of this disclosure, a hardware structure example of a verification calculation circuit is provided based on the aforementioned preset verification matrix.

[0107] Please see Figure 4 This illustrates a schematic diagram of the structure of a verification circuit 10 provided in an embodiment of this disclosure. For example... Figure 4 As shown, the verification circuit 10 includes a first encoding circuit 11 and a second encoding circuit 12; (1) During the data writing process: The first encoding circuit 11 is specifically configured to perform encoding calculations on the initial check code P0<7:0> and the target data D<135:0> based on the first check matrix H0, and generate the first check data S0_7~S0_0; The second encoding circuit 12 is specifically configured to perform encoding calculations on the initial check code P1<7:0> and the target data D<135:0> based on the second check matrix H1, and generate the second check data S1_7~S1_0.

[0108] In simple terms, in a write scenario, Figure 4 The input data OPD<135:0> refers to the aforementioned target data D<135:0> (divided into 8 bytes E0~E16), the output data ECC0<7:0> of the first encoding circuit 11 refers to the aforementioned first check data S0_7~S0_0; the output data ECC1<7:0> of the second encoding circuit 11 refers to the second check data S1_7~S1_0; the initial check code P0<7:0> / P1<7:0> is all 0 data.

[0109] (2) During the reading process: The first encoding circuit 11 is specifically configured to read out the verification data S0_7~S0_0' (i.e., based on the first verification matrix H0) and then encode the data. Figure 2 The P0<7:0> in the middle and the read data D<135:0>' are decoded and calculated to obtain the first verification result PC0_7~PC0_0; The second encoding circuit 12 is specifically configured to read out the verification data S1_7~S1_0' and the read out data D<135:0>' based on the second check matrix H1 (i.e. Figure 2 The P1<7:0> in the code is decoded and calculated to generate the second check data PC1_7~PC1_0.

[0110] Simply put, in a read-out scenario, Figure 4 The input data OPD<135:0> refers to the aforementioned read data D<135:0>' (divided into 8 bytes E0'~E16'), the output data ECC0<7:0> of the first encoding circuit 11 refers to the aforementioned first verification result PC0_7~PC0_0; the output data ECC1<7:0> of the second encoding circuit 11 refers to the second verification result PC1_7~PC1_0.

[0111] In this way, the first encoding circuit 11 and the second encoding circuit 12 undertake the encoding calculation in the writing process and the decoding calculation in the reading process. The writing process and the reading process can be completed using the same hardware circuit, saving hardware resources.

[0112] In this embodiment of the disclosure, since the primitive elements in the first parity check matrix H0 and the second parity check matrix H1 overlap after shifting, the calculation logic of the first encoding circuit 11 and the second encoding circuit 12 is the same, but the calculation objects are different. Therefore, the input data is input to the first encoding circuit 11 in the order of OPD<135:0>, and the input data is input to the second encoding circuit 12 in the order of OPD<63:0> / OPD<135:64>.

[0113] It should be noted that, according to the aforementioned formula, the calculations to be performed by the first encoding circuit are shown in Table 2, and the calculations to be performed by the second encoding circuit are shown in Table 3.

[0114] Table 2

[0115] Note: The "+1" corresponding to the number of elements indicates that there is still one port that receives the initial checksum input or reads the checksum data (i.e., P in the attached diagram). <7> or P <6> ) Table 3

[0116] As can be seen from Tables 2 and 3, the operation of any bit of check data involves at most 29 data points, while the 5-level XOR operation module supports XOR operations on at most "32" data points. Therefore, both the first encoding circuit 11 and the second encoding circuit 12 each employ a 5-level XOR operation module, which is cascaded sequentially. In contrast, related technologies may require a 6-level XOR operation module due to the more complex operation of check data. Therefore, the area of ​​the check circuit provided in this embodiment is significantly reduced, by approximately 15%, thus lowering the cost.

[0117] Furthermore, since the inputs of the first encoding circuit 11 and the second encoding circuit 12 are similar and the calculation logic is the same, the structures of the first encoding circuit 11 and the second encoding circuit 12 are the same. Here, the same structure means that: (1) all the circuit devices in both are of the same type; (2) the circuit connections in both are the same; therefore, both can reuse the same circuit layout, simplifying the design difficulty.

[0118] In some embodiments, see Figure 5 Taking the first encoding circuit 11 as an example, it mainly shows ECC0. <7> ECC0 <6> The hardware composition of the calculation part is similar for the remaining bits. For ease of correspondence with formulas (5) to (20), Figure 5 The specific object of the target data during the writing process is shown in parentheses. Additionally, during the writing process, P... <7> The preset low level is used; during the readout process, P <7> To read the verification data S0_7', the target data to be written is replaced with the corresponding read data (i.e., E0_b7 is replaced with E0_b7'...).

[0119] For details regarding its structure, please refer to [link / reference]. Figure 5 Each of the first encoding circuit 11 and the second encoding circuit 12 includes: The first-level XOR operation module is configured to receive multiple first data pairs, perform an XOR operation on each first data pair, and generate multiple first XOR data; wherein each first data pair contains 2 target data. The second-level XOR operation module is cascaded with the first-level XOR operation module and is configured to receive multiple second data pairs, perform an XOR operation on each second data pair, and generate multiple second XOR data; wherein each second data pair contains 2 first XOR data. The third-level XOR operation module is cascaded with the second-level XOR operation module and is configured to receive multiple third data pairs, perform an XOR operation on each third data pair, and generate multiple third XOR data; wherein each third data pair contains two second XOR data. The fourth-level XOR operation module is cascaded with the third-level XOR operation module and is configured to receive multiple third data pairs, perform an XOR operation on each third data pair, and generate multiple fourth XOR data; wherein each third data pair contains 2 third XOR data. The fifth-level XOR operation module is cascaded with the fourth-level XOR operation module and is configured to receive multiple fourth data pairs, perform an XOR operation on each fourth data pair, and generate verification data corresponding to the target data; wherein each fourth data pair contains two fourth XOR data.

[0120] like Figure 5As shown, each XOR operation module includes multiple XOR gates; in addition, each XOR operation module may also include several drivers, inverters, etc., thereby playing the role of driver enhancement and delay matching.

[0121] like Figure 5 The first verification data includes s parity bits, the second verification data includes s parity bits, and the first encoding circuit 11 includes s first arithmetic circuits, each corresponding one-to-one with the s parity bits of the first verification data. Figure 5 ECC0 is shown <7> The corresponding first operational circuit and ECC0 <6> The corresponding first operational circuit.

[0122] The second encoding circuit 12 includes s second operation circuits, which correspond one-to-one with the s-bit check bits of the second check data. These s second operation circuits are ultimately manifested as the aforementioned 5-level XOR module.

[0123] s is a positive integer. In the aforementioned scenario, s = 8, but this does not constitute a relevant restriction. In this embodiment of the disclosure, the first arithmetic circuits corresponding to different check bits of the first check data can reuse the same XOR operation circuit; the first arithmetic circuits corresponding to different check bits of the second check data can reuse the same XOR operation circuit, and the XOR operation circuit includes one or more of the aforementioned XOR gates.

[0124] Please see Figure 3 In the calculation of check data for different bits, some calculation parts may be the same. These parts can reuse the same physical devices without repeated configuration. For example, please refer to... Figure 3 The blue box indicates that each bit in the verification data S0_7, S0_6, S0_1, and S0_0 needs to be calculated as "E9_b7". E10_b6 E11_b5 E12_b5 E13_b4 E14_b3 E15_b2 E16_b1 (the XOR result is denoted as Share_a), then see... Figure 5 Only one set of XOR gates needs to be set up to calculate Share_a. All other calculations can directly use Share_a for subsequent calculations; there is no need to set up another set of XOR gates. Figure 5 The seven XOR gates in the middle dashed line do not need to be set; subsequent ECC0 will be handled accordingly. <1> and ECC0 <0> Similarly, by directly introducing Share_a, the part in the blue box alone can save 21 XOR gates, reducing the circuit area by about 15%. Figure 3The other color boxes in the text also exhibit similar reuse relationships.

[0125] After investigation, the first encoding circuit 11 and the second encoding circuit 12 require a total of 161×2=322 XOR gates, which is a relatively small number; this also brings a speed advantage.

[0126] It should be understood that the first parity check matrix H0 and the second parity check matrix H1 shown in formula (1) and formula (2) are only one example. The order of the primitive elements of the first parity check matrix H0 and the second parity check matrix H1 must follow the following conditions: (1) The primitive elements of the i-th first element and the i-th second element cannot be the same; (2) The sum of the superscripts of the primitive elements of the i-th first element and the i-th second element cannot be 255 (see the specific explanation above).

[0127] If the types of primitive elements selected remain unchanged and the aforementioned conditions are followed, the order of primitive elements in the first parity check matrix H0 and the second parity check matrix H1 can be interchanged, thus allowing for multiple expressions for the first parity check matrix H0 and the second parity check matrix H1.

[0128] For example, based on formulas (1) and (2), the n first elements and the n second elements are exactly the same, except that the order in H0 and H1 is reversed.

[0129] For example, the first parity check matrix H0 and the second parity check matrix H1 are represented as shown in equations (23) and (24) respectively: ……(twenty three) ……(twenty four) At this point, the first and second encoding circuits need to be redesigned based on the primitive elements in the first parity check matrix H0 and the second parity check matrix H1. Please refer to the foregoing content for an adaptive understanding. In addition, since the primitive elements in the first parity check matrix H0 and the second parity check matrix H1 also have the characteristic of overlapping after translation, they also have the advantages of balanced computation time and balanced driving force. The first and second encoding circuits still use a 5-level XOR gate structure to complete the calculation, and the structure is relatively simple.

[0130] In one related technique, error correction calculation is performed using the following first parity check matrix H0 and second parity check matrix H1: …………(25) (26) Here, the original element, for example The specific guiding meaning is publicly available and will not be illustrated in detail. However, since the primitives of H0 are relatively simple and can be completed by 5 XOR gates, but the primitives of the corresponding H1 are more complex and require at least 6 XOR gates to complete the calculation. Therefore, the relevant technical solutions have the following disadvantages: (1) The calculation process corresponding to H0 is faster and the calculation process corresponding to H1 is slower, thus slowing down the overall calculation time; (2) The calculation logic corresponding to H0 is relatively simple and the calculation logic corresponding to H1 is more complex, resulting in an imbalance in circuit layout and required driving capability; (3) The calculation circuits corresponding to H0 and H1 need to be designed separately, which increases the complexity of the design.

[0131] Simulation calculations show that, compared to formulas (25) and (26), the circuit processing time using the verification matrix of formulas (1) to (2) is reduced by about 20%.

[0132] In another embodiment of this disclosure, see [link to relevant documentation]. Figure 6 The diagram illustrates a flowchart of a data verification method provided in an embodiment of this disclosure. Figure 6 As shown, the process includes: S401: Based on the initial check code and the preset check matrix, the target data is encoded and calculated to generate check data; S402: Store the target data and its verification data; The preset check matrix includes a first check matrix and a second check matrix; the first check matrix includes n first elements arranged in a first order, and the second check matrix includes n second elements arranged in a second order. The first and second elements are primitive elements in the Galois field; n is a positive integer; the types of primitive elements covered by the n first elements and the types of primitive elements covered by the n second elements are the same, and the first and second orders are different.

[0133] In some embodiments, the number of identical primitives covered in the n first elements is the same as the number of identical primitives covered in the n second elements.

[0134] In some embodiments, the primitive elements covered by the n first elements are exactly the same as the primitive elements covered by the n second elements, and the primitive element type of the i-th first element is the same as the primitive element type of the (n-m+i)-th second element, where i is a positive integer and i is less than or equal to m, n=2m+1, and m is an integer.

[0135] In some embodiments, the encoding polynomial corresponding to the preset check matrix is: The encoding polynomial is: .

[0136] In some embodiments: First verification matrix ; Second verification matrix .

[0137] In other embodiments: First verification matrix ; Second verification matrix .

[0138] In another embodiment of this disclosure, see [link to relevant documentation]. Figure 7 This illustrates a flowchart of another data verification method provided in an embodiment of this disclosure. Figure 7 As shown, the process includes: S501: Read the target data and its corresponding verification data; S502: Verify the read data based on the verification data to confirm whether the target data has been erroneous during storage; The preset check matrix includes a first check matrix and a second check matrix; the first check matrix includes n first elements arranged in a first order, and the second check matrix includes n second elements arranged in a second order. The first and second elements are primitive elements in the Galois field; n is a positive integer; the types of primitive elements covered by the n first elements and the types of primitive elements covered by the n second elements are the same, and the first and second orders are different.

[0139] In some embodiments, the number of identical primitives covered in the n first elements is the same as the number of identical primitives covered in the n second elements.

[0140] In some embodiments, the primitive elements covered by the n first elements are exactly the same as the primitive elements covered by the n second elements, and the primitive element type of the i-th first element is the same as the primitive element type of the (n-m+i)-th second element, where i is a positive integer and i is less than or equal to m, n=2m+1, and m is an integer.

[0141] In some embodiments, the encoding polynomial corresponding to the preset check matrix is: The encoding polynomial is: .

[0142] In some embodiments: First verification matrix ; Second verification matrix .

[0143] In other embodiments: First verification matrix ; Second verification matrix .

[0144] In another embodiment of this disclosure, a memory is provided, which includes the verification circuit as described above. In a specific scenario, during data processing, the memory pre-fetches 256 bits of regular data (DQ) + 16 bits of system data (meta data) each time. Since the memory operates according to odd and even clock cycles, the verification circuit performs verification calculations on the target data of 128 bits of regular data (DQ) + 8 bits of system data (meta data) = 136 bits, thereby improving the accuracy of data processing.

[0145] In yet another embodiment of this disclosure, an electronic device is provided, which includes the memory as described above. Here, the electronic device may be a mobile phone, a computer, various smart devices, industrial equipment, etc.

[0146] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0147] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0148] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0149] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0151] The features disclosed in the several method or circuit embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or circuit embodiments.

[0152] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A verification circuit, characterized in that, The verification circuit is configured to encode and calculate the target data based on the initial check code and the preset check matrix to generate verification data, and then send the verification data to the storage array for storage. The preset verification matrix includes a first verification matrix and a second verification matrix; The first parity check matrix includes n first elements arranged in a first order, and the second parity check matrix includes n second elements arranged in a second order. Both the first and second elements are primitive elements in the Galois field; n is a positive integer. The types of primitive elements covered by the n first elements are the same as the types of primitive elements covered by the n second elements, and the first order and the second order are different.

2. The verification circuit according to claim 1, characterized in that, The number of identical primitives covered in the n first elements is the same as the number of identical primitives covered in the n second elements.

3. The verification circuit according to claim 1, characterized in that, The primitive elements covered by the n first elements are exactly the same as the primitive elements covered by the n second elements, and the primitive element type of the i-th first element is the same as the primitive element type of the (n-m+i)-th second element, where i is a positive integer and i is less than or equal to m, n=2m+1, and m is an integer.

4. The verification circuit according to claim 1, characterized in that, The encoding polynomial corresponding to the preset verification matrix is: The encoding polynomial is: .

5. The verification circuit according to claim 1, characterized in that, The first verification matrix ; The second verification matrix .

6. The verification circuit according to claim 1, characterized in that, The first verification matrix ; The second verification matrix .

7. The verification circuit according to any one of claims 1-5, characterized in that, The verification circuit includes a first encoding circuit and a second encoding circuit; The first encoding circuit is specifically configured to perform encoding calculations on the initial check code and the target data based on the first check matrix to generate first check data; wherein, the first check data includes s-bit check bits; The second encoding circuit is specifically configured to perform encoding calculations on the initial check code and the target data based on the second check matrix to generate second check data; wherein, the second check data includes s check bits; s is a positive integer; The first encoding circuit includes s first arithmetic circuits, each corresponding to one of the s-bit check bits of the first check data; the second encoding circuit includes s second arithmetic circuits, each corresponding to one of the s-bit check bits of the second check data.

8. The verification circuit according to claim 7, characterized in that, The structure of the first encoding circuit is the same as that of the second encoding circuit.

9. The verification circuit according to claim 7, characterized in that, The first arithmetic circuits corresponding to different check bits of the first check data reuse the same XOR operation circuit; The first arithmetic circuits corresponding to different check bits of the second check data reuse the same XOR operation circuit.

10. A memory, characterized in that, The memory includes a verification circuit as described in any one of claims 1-9.

11. An electronic device, characterized in that, The electronic device includes the memory as described in claim 10.

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