Synchronous Rectification Control Method and System

Abstract

This invention relates to the field of flyback converters, and particularly to a synchronous rectification method and system; the synchronous rectification control method is used to control the turn-on and turn-off of the secondary-side synchronous rectifier of a flyback converter, comprising the following steps: acquiring a first signal between the drain and source of the secondary-side synchronous rectifier; outputting a second signal from the first signal through a delay unit; acquiring a fall time length signal between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; and sending the first signal to a switch threshold detection unit, wherein the switch threshold detection unit compares the first signal with preset turn-on and turn-off thresholds of the secondary-side synchronous rectifier; this application avoids the erroneous turn-on of the secondary-side switch when the primary-side switch outputs a ZVS pulse drive signal, which could lead to excessive voltage stress on the power device and damage to the power device.

Description

Technical Field

[0001] This invention relates to the field of flyback converters, and particularly to a synchronous rectification control method and a synchronous rectification control system. Background Technology

[0002] Flyback converters dominate current small and medium power supply systems due to their simplified circuitry and control methods. By applying synchronous rectification (SR) control technology, replacing the secondary rectifier diodes of the flyback converter with power switching transistors can significantly reduce system conduction losses and improve converter efficiency. Currently, synchronous rectification control technology for flyback converters is relatively mature and widely used. With the continuous improvement of power electronics technology, traditional flyback converters have also evolved into more efficient topologies, including zero-voltage switching flyback converters (ZVS flyback) and asymmetric half-bridge (AHB) flyback converters, which will be collectively referred to below as new flyback converters. Figure 1 The circuit topology of an asymmetric half-bridge flyback converter is shown. These novel flyback converters reduce system switching losses and further improve converter efficiency by adding an auxiliary switch and a resonant device, utilizing the resonance principle to achieve zero-voltage turn-on of the main power transistor. Figure 2 As shown, in the novel flyback converter, the drop slopes of the secondary-side synchronous rectifier (SRC) during its normal turn-on phase (dt1 and dt2) are similar. Traditional slope detection and threshold detection schemes struggle to distinguish between dt1 and dt2, potentially leading to erroneous turn-on of the secondary-side SRC (QS), and failing to effectively avoid the risk of simultaneous primary and secondary-side conduction. To address the challenges posed by the novel flyback converter, synchronous rectification control technology urgently needs improvement. Summary of the Invention

[0003] This invention addresses the technical problem of erroneous activation of the secondary-side synchronous rectifier diode QS by providing a synchronous rectification control method and a synchronous rectification control system.

[0004] Firstly, a synchronous rectification control method is provided for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, comprising the following steps:

[0005] Obtain the first signal between the drain and source of the secondary-side synchronous rectifier; The first signal is delayed by a delay unit to output the second signal; Acquire the fall time length signal between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; The first signal is sent to the switch threshold detection unit, which compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier to obtain the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier. The fall time length signal, the on signal VGS_on and the off signal VGS_off of the secondary synchronous rectifier are output to the first logic control unit. The first logic control unit controls the secondary synchronous rectifier to turn on when the on signal VGS_on of the secondary synchronous rectifier is high and the duration of the fall time length signal is less than the duration of a preset third signal; and controls the secondary synchronous rectifier to turn off when the off signal VGS_off of the secondary synchronous rectifier is high.

[0006] Secondly, a synchronous rectification control method is also provided for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, comprising the following steps: Obtain the first signal between the drain and source of the secondary-side synchronous rectifier; The first signal is delayed by a delay unit to output the second signal; The voltage value of the energy storage capacitor C2 is obtained between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; the energy storage capacitor C2 is used to accumulate energy between the first time point and the second time point. The first signal is sent to the switch threshold detection unit, which compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier to obtain the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier. When the maximum voltage of the energy storage capacitor C2 is less than the specified voltage, and the turn-on signal VGS_on of the secondary synchronous rectifier is valid, the secondary synchronous rectifier is turned on. When the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value, and the first latch unit outputs a low level, the secondary synchronous rectifier is controlled to be turned off regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier is valid; the first latch unit is used to start outputting a low level signal when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value.

[0007] Preferably, the first signal outputting the second signal after passing through the delay unit includes: implementing the delay unit using a phase delay unit or a low-pass filter unit.

[0008] Preferably, obtaining the voltage value of the energy storage capacitor C2 between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal includes the following steps: The first signal is sent to the inverting input of comparator U1, and the second signal is sent to the non-inverting input of comparator U1; at the same time, the first signal is sent to the non-inverting input of comparator U2, and the first reference signal is sent to the inverting input of comparator U2. The output signal Vout1 of comparator U1 and the output signal Vout2 of comparator U2 are respectively sent to AND gate U5 to obtain the output signal Vout3 of AND gate U5; The constant current source I1 is turned on and off using the Vout3 signal, so that when the constant current source I1 is turned on, the energy storage capacitor C2 is charged until the amplitude of the first signal is less than the preset first reference signal; at the same time, the gate of the switching transistor Q1 connected in parallel with the energy storage capacitor C2 is controlled using the inverted signal of the Vout2 signal. The voltage value of the energy storage capacitor C2 is obtained when the amplitude of the first signal is less than the preset first reference signal.

[0009] Preferably, the first latch unit is used to start outputting a low-level signal when the voltage value of the energy storage capacitor C2 is greater than a specified voltage value, including the following steps: The voltage value of the energy storage capacitor C2 is compared with the specified voltage value through comparator U7 to output the Tdet signal; Invert the Tdet signal and input it simultaneously with the Vout2 signal into AND gate U9 to obtain the output Vout6 signal; The Vout6 signal is sent to the S terminal of latch U10, and the Tdet signal is sent to the R terminal of latch U10; when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value, latch U10 outputs a low-level signal.

[0010] Preferably, when the highest voltage value of the energy storage capacitor C2 is greater than a specified voltage value and the first latch unit outputs a low level, the secondary-side synchronous rectifier is controlled to be turned off regardless of whether the turn-on signal VGS_on of the secondary-side synchronous rectifier is valid, including the following steps: The output signal Vout7 of the latch U10 and the turn-on signal VGS_on of the secondary synchronous rectifier are simultaneously sent to the AND gate U11 to obtain the output signal Vout8 of the AND gate U11. The Vout8 signal is sent to the S terminal of latch U12, and the VGS_off signal of the secondary synchronous rectifier is sent to the R terminal of latch U12; the output terminal of latch U12 is used to output a signal to control the opening and closing of the secondary synchronous rectifier. Regardless of whether the turn-on signal VGS_on of the secondary-side synchronous rectifier is valid, the output of the latch U12 controls the secondary-side synchronous rectifier to turn off.

[0011] Thirdly, a synchronous rectification control system is also provided for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, including: Acquisition unit: used to acquire the first signal between the drain and source of the secondary-side synchronous rectifier; Delay unit: used to output the second signal after the first signal passes through the delay unit; Falling duration unit: used to acquire the falling time length signal between a first time point when the first signal starts to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; Threshold detection unit: used to send the first signal to the switch threshold detection unit, the switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier, and obtains the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier respectively; First logic control unit: This unit outputs the fall time length signal, the on signal VGS_on of the secondary-side synchronous rectifier, and the off signal VGS_off of the secondary-side synchronous rectifier to the first logic control unit. When the on signal VGS_on of the secondary-side synchronous rectifier is high and the duration of the fall time length signal is less than the duration of a preset third signal, the first logic control unit controls the secondary-side synchronous rectifier to turn on; when the off signal VGS_off of the secondary-side synchronous rectifier is high, the first logic control unit controls the secondary-side synchronous rectifier to turn off.

[0012] Fourthly, a synchronous rectification control system is also provided for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, including: Acquisition unit: used to acquire the first signal between the drain and source of the secondary-side synchronous rectifier; Delay unit: used to output the second signal after the first signal passes through the delay unit; Energy storage unit: used to acquire the voltage value of energy storage capacitor C2 between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; the energy storage capacitor C2 is used to accumulate energy between the first time point and the second time point; Threshold detection unit: used to send the first signal to the switch threshold detection unit, the switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier, and obtains the turn-on signal VGS_on and the turn-off signal VGS_off of the secondary synchronous rectifier respectively; The second logic control unit is used to control the secondary synchronous rectifier to turn on when the highest voltage value of the energy storage capacitor C2 is less than a specified voltage value and the turn-on signal VGS_on of the secondary synchronous rectifier is valid; and to control the secondary synchronous rectifier to turn off when the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value and the first latch unit outputs a low level, regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier is valid; the first latch unit is used to start outputting a low level signal when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value.

[0013] Preferably, the delay unit is implemented using a phase delay unit or a low-pass filter unit.

[0014] Fifthly, a chip is also provided for implementing any of the synchronous rectification control methods described above.

[0015] Beneficial effects: 1. The secondary-side synchronous rectifier is controlled to turn on or off by acquiring the voltage VDS_QS between the drain and source of the secondary-side synchronous rectifier and the fall time signal between the first time point and the second time point. The secondary-side synchronous rectifier will only be turned on when the fall time signal is less than a preset time length. This avoids the secondary-side synchronous rectifier being mistakenly turned on when the primary-side switching transistor outputs the ZVS pulse drive signal, which could lead to excessive voltage stress on the power device and damage to the power device. 2. The voltage VDS_QS between the drain and source of the secondary-side synchronous rectifier is obtained. The voltage amplitude of capacitor C2 between the first time point and the second time point is compared with a specified voltage value VSET2. The comparison output signal is used to control the turn-on or turn-off of the secondary-side rectifier. When the capacitor voltage amplitude is greater than the specified voltage value VSET2, the secondary-side rectifier is not turned on. This avoids the secondary-side synchronous rectifier being mistakenly turned on when the primary-side switching transistor outputs the ZVS pulse drive signal, which would cause the voltage stress of the power device to exceed the standard and thus damage the power device. 3. Applicable to traditional flyback converters as well as new flyback converters such as ZVS flyback and AHB flyback. Attached Figure Description

[0016] Figure 1 The circuit topology is for an asymmetric half-bridge (AHB) flyback converter; Figure 2 The timing diagram shows the key operating logic of the asymmetric half-bridge (AHB) flyback converter. Figure 3 A schematic diagram of a first embodiment of a synchronous rectification control method; Figure 4 This is a logic block diagram of a synchronous rectification control system; Figure 5 A timing diagram illustrating a first embodiment of a synchronous rectification control system; Figure 6 This is a schematic diagram of a first embodiment of a synchronous rectification control system; Figure 7 This is a schematic diagram of a second embodiment of a synchronous rectification control method; Figure 8 This is a schematic diagram of a second embodiment of a synchronous rectification control system; Figure 9 This is a schematic diagram of a third embodiment of a synchronous rectification control method; Figure 10 A timing diagram illustrating a second embodiment of a synchronous rectification control system; Figure 11 This is a schematic diagram of a fourth embodiment of a synchronous rectification control method; Figure 12 This is a schematic diagram of the fifth embodiment of a synchronous rectification control method; Figure 13 This is a schematic diagram of a third embodiment of a synchronous rectification control system; Figure 14 This is a schematic diagram of a fourth embodiment of a synchronous rectification control system; Figure 15 This is a schematic diagram of a fifth embodiment of a synchronous rectification control system.

[0017] Explanation of reference numerals in the attached figures: 1-First signal unit; 2-Second signal unit; 3-First fall time detection unit; 4-Switch threshold detection unit; 5-First logic control unit; 6-Second fall time detection unit; 7-First latch unit; 8-Second latch unit; 9-Second logic control unit; 10-Acquisition unit; 11-Delay unit; 12-Fall duration unit; 13-First threshold detection unit; 14-Energy storage unit; 15-Second threshold detection unit; 16-Voltage divider unit; 17-A synchronous rectification control system. Detailed Implementation

[0018] Terminology Explanation: ZVS: Zero Voltage Switching; is a soft-switching technology in the field of power electronics. Its core is to enable power switching devices (such as MOSFETs and IGBTs) to complete the turn-on operation when the voltage across them is zero or close to zero, thereby eliminating turn-on losses, improving efficiency and reducing EMI interference.

[0019] ZVS pulse: Essentially a pulse signal or control signal centered around zero-voltage switching technology. Its core is to perform switching action when the voltage of the switching device is zero, so as to solve the loss and interference problems caused by hard switching. It is widely used in power electronic equipment such as switching power supplies and high-frequency converters.

[0020] MOSFET: A voltage-controlled semiconductor device that uses the gate voltage to form a conductive channel on the semiconductor surface to control the current between the drain and source. It is one of the core basic components of modern electronic technology.

[0021] IGBT (Insulated Gate Bipolar Transistor) is a fully controllable voltage-driven power semiconductor device that combines the core advantages of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and BJT (Bipolar Junction Transistor), making it the mainstream switching device in the field of medium- and high-power power electronics.

[0022] Synchronous Rectifier (SR) is essentially a low on-resistance power MOSFET used to replace traditional rectifier diodes. It achieves high-efficiency rectification through precise timing control. Its core advantage is that it significantly reduces conduction losses and improves power conversion efficiency.

[0023] AHB: Asymmetrical Half-Bridge; Asymmetrical Half-Bridge Flyback Converter.

[0024] This invention addresses the technical problem of erroneous activation of the secondary-side synchronous rectifier diode QS by providing a synchronous rectification control method and a synchronous rectification control system.

[0025] Firstly, such as Figure 3 , Figure 4 , Figure 5 As shown, a synchronous rectification control method is provided for controlling the switching on and off of the secondary-side synchronous rectifier diode QS of a flyback converter, including the following steps: S101: Obtain the first signal between the drain and source of the secondary-side synchronous rectifier diode; in this technical solution, the voltage signal between the drain and source of the secondary-side synchronous rectifier diode MOSFET is obtained, which is the first signal VDS_QS. In the prior art, the first signal VDS_QS is also obtained, but the subsequent processing method is different. In this technical solution, the first signal between the drain and source of the secondary-side synchronous rectifier diode of the asymmetric half-bridge flyback converter is obtained.

[0026] S102: The first signal is delayed by a delay unit to output a second signal; the first signal VDS_QS is delayed to obtain the second signal VDS_Flt. In the prior art, the descent slope of the first signal VDS_QS is used for slope detection and threshold detection. This technical solution obtains the second signal VDS_Flt after delaying the first signal VDS_QS.

[0027] S103: Obtain the falling time length signal between the first time point when the first signal begins to be less than the second signal and the second time point when the first signal is less than the preset first reference signal VSET. In this technical solution, since the second signal VDS_Flt is obtained by delaying the first signal VDS_QS, the first signal VDS_QS and the second signal VDS_Flt have an intersection point on the time waveform. Therefore, when the first signal VDS_QS is falling, there will be a first time point when it is less than the second signal VDS_Flt. Subsequently, as the first signal VDS_QS continues to fall, there will be a second time point when the first signal VDS_QS is less than the preset first reference signal VSET. Obtain the duration between the first time point and the second time point, i.e., the falling time length signal Tdet.

[0028] S104: The first signal is sent to the switch threshold detection unit. The switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier to obtain the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier. S105: The fall time length signal, the on signal VGS_on and the off signal VGS_off of the secondary synchronous rectifier are output to the first logic control unit; the first logic control unit 5 controls the secondary synchronous rectifier to turn on when the on signal VGS_on of the secondary synchronous rectifier is high and the duration of the fall time length signal is less than the duration of the preset third signal; and controls the secondary synchronous rectifier to turn off when the off signal VGS_off of the secondary synchronous rectifier is high.

[0029] like Figure 4As shown, the first logic control unit 5 outputs VGS_en to control the on and off of the secondary-side synchronous rectifier tube.

[0030] like Figure 5 As shown, VDS_QS is the voltage signal between the drain and source of the secondary synchronous rectifier QS, i.e., the first signal. The dashed waveform is the filtered signal VDS_Flt, which lags slightly in phase with VDS_QS; VGS_QL is as follows... Figure 1 The primary power transistor shown.

[0031] At time t0, the secondary-side synchronous rectifier QS is turned off, and then the terminal voltage signal VDS_QS rises rapidly. After a certain phase lag, VDS_Flt tracks VDS_QS and remains basically equal until the secondary-side synchronous rectifier QS enters the freewheeling phase, and VDS_QS drops rapidly. like Figure 5 , Figure 6 As shown, at time t1, VDS_QS drops rapidly. Due to the filtering lag, VDS_Flt does not drop rapidly immediately. This results in the point at which the first signal VDS_QS is lower than the second signal VDS_Flt, i.e., the corresponding... Figure 5 Point A in the timer is then activated, meaning the Tdet signal goes high. The period from time t1 to t2 is the rapid drop phase of the first signal VDS_QS. At time t2, VDS_QS drops to the preset first reference signal VSET, corresponding to... Figure 5 At point B in the timer, the timer stops counting, and the Tdet signal is set low. The duration of the timing signal Tdet is compared with the duration of the set comparison signal Tset. If the duration of Tdet is lower than the preset third signal, then the duration of Tdet signal is less than the duration of Tset signal. In this case, the Tdet_en signal is set to high level. During the time intervals t2-t3, VDS_QS continuously decreases and crosses zero, and the body diode of the secondary synchronous rectifier QS turns on, entering the freewheeling stage; at time t3, VDS_QS is lower than the set turn-on threshold VON_TH, driving the turn-on signal VGS_on to a high level. At this time, both Tdet_en and VGS_on signals are high, enabling drive signal output, and signal VGS_en is set high. During the time intervals t3-t4, the secondary synchronous rectifier diode QS remains on. As the freewheeling current decreases, the terminal voltage of the secondary synchronous rectifier diode QS gradually decreases. At time t4, VDS_QS is higher than the set turn-off threshold VOFF_TH, driving the turn-off signal VGS_off to a high level, thus turning off the secondary synchronous rectifier diode QS. At time t5, after the drive signal transmission delay, the secondary synchronous rectifier QS is completely turned off, and then VDS_QS rises rapidly. At time t6, VDS_QS rapidly rises to exceed the set threshold VSET, and then the signal Tdet_en is set low and cleared to zero, starting a new round of detection; Between times t6 and t7, after the secondary-side synchronous rectifier diode QS is turned off, VDS_QS enters the oscillation phase under the influence of parasitic parameters. At time t7, VDS_QS again falls below VDS_Flt. This time point corresponds to... Figure 5 At point C in the timer, the timer starts counting again, and the Tdet signal goes high. During the oscillation phase from time t7 to t8, until time t8, under the ZVS Pulse drive of the primary-side switch QL, VDS_QS rapidly drops below VSET again, corresponding to... Figure 5 Point D in the timer is then turned off, and the Tdet signal is set low. At this time, the Tdet signal duration is significantly longer than the set Tset signal duration, so the Tdet_en signal will not be set high. During the oscillation phase, the time from point C to point D will be significantly longer than the time from point A to point B during the normal turn-on phase of the secondary rectifier tube. By setting a reasonable Tset time, the VDS_QS fast drop condition caused by ZVS Pulse can be distinguished from the normal turn-on condition. At time t9, VDS_QS drops to the turn-on threshold VON_TH again, driving the turn-on signal VGS_on to a high level. However, since the Tdet_en signal is low at this time, the drive signal will not be allowed to be output, thus avoiding the phenomenon of secondary synchronous rectifier QS being turned on twice within one switching cycle.

[0032] like Figure 6 The diagram shows a first embodiment of a synchronous rectification control system. It includes: a first signal unit 1, used to divide the voltage of the first signal, reducing its voltage to facilitate subsequent signal processing; and a second signal unit 2, used to delay the signal output by the first signal unit. In this embodiment, a low-pass filter is used for the delay. Other delay circuits can also be used. In this embodiment, the first fall time detection unit 3 uses two comparators U1 and U2, and a timer to detect the fall time and obtain the Tdet signal. The VGS_en signal output by the first logic control unit 5 is then output to the driving circuit to obtain the VGS signal that can drive the gate and source of the secondary-side synchronous rectifier diode QS.

[0033] Secondly, such as Figure 7 , Figure 8 , Figure 9As shown, a synchronous rectification control method is also provided for controlling the switching on and off of the secondary-side synchronous rectifier diode QS of a flyback converter, including the following steps: S201: Obtain the first signal between the drain and source of the secondary-side synchronous rectifier; S202: The first signal is delayed by the delay unit to output the second signal; S203: Obtain the voltage value of the energy storage capacitor C2 between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; the energy storage capacitor C2 is used to accumulate energy between the first time point and the second time point; this technical solution differs from the synchronous rectification control method provided in the first aspect in that it uses the energy accumulated in the energy storage capacitor C2, i.e., the amount of charge accumulated between the first time point and the second time point, to make subsequent judgments, instead of using the fall time length signal between the first time point when the first signal begins to be less than the second signal and the second time point when the first signal is less than the preset first reference signal VSET to make judgments. Figure 8 The diagram shown is a second embodiment of a synchronous rectification control system according to this technical solution. It illustrates the circuit topology of the synchronous rectification control system including the energy storage capacitor C2.

[0034] S204: The first signal is sent to the switch threshold detection unit. The switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier to obtain the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier, respectively. S205: When the highest voltage value of the energy storage capacitor C2 is less than the specified voltage value, and the turn-on signal VGS_on of the secondary synchronous rectifier is valid, control the secondary synchronous rectifier to turn on; S206: When the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value, and the first latch unit outputs a low level, the secondary synchronous rectifier is controlled to be turned off regardless of whether the on-state signal VGS_on of the secondary synchronous rectifier is valid. The first latch unit is used to start outputting a low-level signal when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value. In this technical solution, the first latch unit 7 includes an inverter U8, a NAND gate U9, and a latch U10; wherein, the latch U10 is a latch composed of NOR gates. When the latch U10 is composed of NOR gates, when the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value, the first latch unit 7 will definitely output a low level.

[0035] like Figure 8As shown, the first signal unit 1 is a sampling and processing circuit for the voltage signal VDS_QS at the QS terminal of the secondary synchronous rectifier diode. Here, only the simplest resistor voltage divider circuit is used as an example to convert the high voltage signal into a low voltage signal VDS_QS1 that can be processed by logic. The second signal unit 2 is a filtering circuit. After VDS_QS1 is filtered by resistor R3 and capacitor C1, a signal VDS_Flt with the same waveform as VDS_QS1 but with a phase lag is obtained. The first fall time detection unit 3 is a fall time detection circuit, including comparators U1 and U2, AND gate U5, NOT gate U6, current source I1, switch Q1, capacitor C2 and comparator U7; Among them, the sampling signal VDS_QS1 of the voltage signal at the QS terminal of the secondary synchronous rectifier is connected to the inverting input terminal and the non-inverting input terminal of comparators U1 and U2 respectively, and the filtered signal VDS_Flt is connected to the non-inverting input terminal of comparator U1. When comparator U1 outputs a high-level signal Vout1 and comparator U2 outputs a high-level signal Vout2, the output signal Vout3 of AND gate U5 outputs a high level, controlling current source I1 to charge capacitor C2, and the voltage VC2 on capacitor C2 increases linearly. The capacitor voltage VC2 and the set voltage threshold VSET2 are respectively input to the non-inverting input and the inverting input of the comparator U7. When the capacitor voltage VC2 exceeds the set voltage VSET2, the output signal Tdet of the NOT gate U6 becomes high. Meanwhile, when the output signal Vout2 of comparator U2 is low, it passes through NOT gate U6 to obtain a high-level signal Vout4, which controls switch Q1, causing the capacitor voltage VC2 to be cleared to zero.

[0036] The switch threshold detection unit 4 is a turn-on and turn-off threshold detection circuit for the secondary synchronous rectifier QS. Through comparators U3 and U4, the sampled signal VDS_QS1 is compared with the set turn-on threshold VON_TH and turn-off threshold VOFF_TH, respectively. When the turn-on or turn-off conditions are met, the output signals VGS_on and VGS_off of comparators U3 and U4 are set to high level and the signals are transmitted to the logic control module. The second logic control unit 9 is a logic control module, including NOT gate U8, AND gates U9 and U11, and RS latches U10 and U12; When the Tdet signal is low, it passes through the NOT gate U8 to obtain the high-level Vout5 signal. When the Vout2 signal is also high, the output signal Vout of the AND gate U9 is set to high, and the RS latch U10 is set to output high, that is, the Vout7 signal is output high. When both Vout7 and VGS_on signals are high, the output signal Vout8 of AND gate U11 is high, which controls RS latch U12 to set to a high level, i.e., VGS_en is high, allowing synchronous rectification drive output.

[0037] When the drive shutdown adjustment is met, i.e., VGS_off is high, the output of RS latch U12 is cleared and VGS_en is low, thus shutting down the secondary-side synchronous rectification drive.

[0038] Meanwhile, when the Tdet signal is high, that is, when the VDS_QS1 drop time exceeds the set threshold, the RS latch U10 outputs a low-level signal. In this state, the VGS_en signal remains low, and the secondary-side synchronous rectifier QS output drive is not allowed, which can effectively avoid the rectifier being turned on by mistake.

[0039] Preferably, the first signal outputting the second signal after passing through the delay unit includes: implementing the delay unit using a phase delay unit or a low-pass filter unit.

[0040] Preferred, such as Figure 9 As shown, obtaining the voltage value of the energy storage capacitor C2 between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal includes the following steps: S2031: The first signal is sent to the inverting input of comparator U1, and the second signal is sent to the non-inverting input of comparator U1; at the same time, the first signal is sent to the non-inverting input of comparator U2, and the first reference signal is sent to the inverting input of comparator U2. S2032: The output signal Vout1 of comparator U1 and the output signal Vout2 of comparator U2 are respectively sent to AND gate U5 to obtain the output signal Vout3 of AND gate U5; S2033: The constant current source I1 is turned on and off using the Vout3 signal, so that when the constant current source I1 is turned on, the energy storage capacitor C2 is charged until the amplitude of the first signal is less than the preset first reference signal; at the same time, the gate of the switching transistor Q1 connected in parallel with the energy storage capacitor C2 is controlled using the inverted signal of the Vout2 signal. S2034: Obtain the voltage value of the energy storage capacitor C2 when the amplitude of the first signal is less than the preset first reference signal.

[0041] Preferred, such as Figure 10 , Figure 11 As shown, the first latch unit is used to start outputting a low-level signal when the voltage value of the energy storage capacitor C2 is greater than a specified voltage value, including the following steps: S2064: The voltage value of the energy storage capacitor C2 is compared with the specified voltage value through comparator U7 to output the Tdet signal; S2065: Invert the Tdet signal and input it simultaneously with the Vout2 signal into AND gate U9 to obtain the output Vout6 signal; S2066: The Vout6 signal is sent to the S terminal of latch U10, and the Tdet signal is sent to the R terminal of latch U10; when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value, latch U10 outputs a low-level signal.

[0042] Preferred, such as Figure 10 , Figure 12 As shown, when the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value and the first latch unit outputs a low level, the secondary synchronous rectifier QS is controlled to be turned off regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier QS is valid. This includes the following steps: S2061: Simultaneously send the output signal Vout7 of the latch U10 and the turn-on signal VGS_on of the secondary synchronous rectifier to the AND gate U11 to obtain the output signal Vout8 of the AND gate U11; S2062: The Vout8 signal is sent to the S terminal of latch U12, and the VGS_off signal of the secondary synchronous rectifier is sent to the R terminal of latch U12; the output terminal of latch U12 is used to output a signal to control the opening and closing of the secondary synchronous rectifier. S2063: Regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier is valid, the output of the latch U12 controls the secondary synchronous rectifier to turn off.

[0043] like Figure 8 , Figure 10 As shown, at time t0, after the secondary synchronous rectifier QS is turned off, the voltage signal VDS_QS1 at the terminal of the secondary synchronous rectifier QS rises rapidly and begins to exceed the set threshold VSET. The signals Vout2, Vout5, Vout6 and Vout7 are set high. At time t1, after the upper transistor drive is turned off, the secondary-side synchronous rectification enters the demagnetizing stage, and VDS_QS1 drops rapidly. Simultaneously, due to the filtering lag, VDS_Flt does not drop immediately, resulting in VDS_QS1 falling below VDS_Flt. This time point corresponds to... Figure 10 Point A in the diagram; the Vout1 signal is set to a high level, controlling the Vout3 signal to also be set to a high level, the constant current source I2 charges the capacitor C2, and the capacitor voltage VC2 increases linearly.

[0044] At time t2, VDS_QS1 continues to drop below the set threshold VSET, i.e., the corresponding... Figure 10 At position B, the Vout2 signal output is low. After passing through NOT gate U6, the Vout4 signal becomes high. Then, switch Q1 is turned on, and the capacitor voltage VC2 is cleared to zero.

[0045] At time t3, VDS_QS1 continues to drop below the set threshold VON_TH, which satisfies the conditions for synchronous rectification to be turned on, and the VGS_on signal is set to a high level. At this time, since the Vout7 signal has been set to high level, VGS_en will also be set to high level, which means that synchronous rectification drive output is enabled; From time t3 to t5, the secondary synchronous rectifier tube remains on, and VDS_QS1 slowly increases as the excitation current gradually decreases. At time t4, VDS_QS1 exceeds the set threshold VON_TH again, and the VGS_on and Vout8 signals are set low. At time t5, VDS_QS1 rises above the set threshold VOFF_TH, the VGS_off signal goes high, the VGS_en signal goes low, and the synchronous rectification drive is turned off. It then enters an oscillation phase, with VDS_QS1 oscillating upwards, and VDS_QS1 exceeding VDS_Flt again.

[0046] At time t6, VDS_QS1 exceeds the set threshold VSET again, and the Vout2 and Vout6 signals are set high again. At time t7, VDS_QS1 and VDS_Flt become equal again during the oscillation phase, corresponding to... Figure 10 At position C, VDS_QS1 then falls below VDS_Flt, the Vout1 signal is set high again, and then the Vout3 signal is also set high again, controlling the current source I1 to charge the capacitor C2. At time t8, the capacitor voltage VC2 exceeds the set threshold VSET2, and the Tdet signal is set high; at the same time, the Vout5, Vout6, and Vout7 signals are set low. At time t9, VDS_QS1 and VDS_Flt are equal again, and VDS_QS1 begins to be higher than VDS_Flt. The Vout1 and Vout3 signals are set to low level. At this time, VDS_QS1 is still higher than the set threshold VSET, the Vout2 signal remains high, the capacitor C2 will not be cleared, and the VC2 signal remains unchanged. At time t10, VDS_QS1 and VDS_Flt are equal again, and VDS_QS1 begins to fall below VDS_Flt. The Vout1 and Vout3 signals are set to high level again, the control capacitor C2 is charged again, and the VC2 voltage continues to rise. At time t11, the original edge ZVS Pulse is activated, and then VDS_QS1 ends its oscillation phase and quickly goes offline; At time t12, VDS_QS1 drops below the set threshold VSET, Vout2 and Vout3 signals are set low, and Vout4 signal is set high, controlling Q1 to discharge capacitor C2 to zero; At the same time, the Tdet signal is set to low level and the Vout5 signal is set to high level; At time t13, VDS_QS1 continues to drop below the set threshold VON_TH, which means that the conditions for synchronous rectification to be turned on are met again, and the VGS_on signal is set to high level. At this time, the Vout7 signal is still low. Even if VGS_on is high, the VGS_en signal cannot be set to high, which means that the secondary synchronous rectifier tube output drive is not allowed. This step is the key to achieving the shielding effect against accidental activation.

[0047] At time t14, VDS_QS1 rises above VOFF_TH, satisfying the driver shutdown condition again, and VGS_off is set high; At time t15, VDS_QS1 exceeds the set threshold VSET again, Vout2 and Vout6 signals are set to high level, and Vout7 signal is set to high level again, and then a new cycle of detection begins.

[0048] Thirdly, such as Figure 13 As shown, a synchronous rectification control system 17 is also provided for controlling the switching on and off of the secondary-side synchronous rectifier diode QS of the flyback converter, including: Acquisition unit 10: used to acquire the first signal between the drain and source of the secondary-side synchronous rectifier; Delay unit 11: used to output the second signal after the first signal passes through the delay unit; Falling duration unit 12: used to acquire the falling time length signal between a first time point when the first signal starts to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; First threshold detection unit 13: used to transmit the first signal to the switch threshold detection unit, the switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier, and obtains the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier respectively; First logic control unit 5: This unit outputs the fall time length signal, the on signal VGS_on of the secondary-side synchronous rectifier, and the off signal VGS_off of the secondary-side synchronous rectifier to the first logic control unit. The first logic control unit controls the secondary-side synchronous rectifier to turn on when the on signal VGS_on of the secondary-side synchronous rectifier is high and the duration of the fall time length signal is less than the duration of a preset third signal; and controls the secondary-side synchronous rectifier to turn off when the off signal VGS_off of the secondary-side synchronous rectifier is high.

[0049] Fourthly, such as Figure 14 As shown, a synchronous rectification control system 17 is also provided for controlling the switching on and off of the secondary-side synchronous rectifier diode QS of the flyback converter, including: Acquisition unit 10: used to acquire the first signal between the drain and source of the secondary-side synchronous rectifier; Delay unit 11: used to output the second signal after the first signal passes through the delay unit; Energy storage unit 14: used to acquire the voltage value of energy storage capacitor C2 between a first time point when the first signal starts to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; the energy storage capacitor C2 is used to accumulate energy between the first time point and the second time point. Second threshold detection unit 15: used to transmit the first signal to the switch threshold detection unit, the switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier, and obtains the turn-on signal VGS_on and the turn-off signal VGS_off of the secondary synchronous rectifier respectively; The second logic control unit 9 is configured to: control the secondary synchronous rectifier QS to turn on when the highest voltage value of the energy storage capacitor C2 is less than a specified voltage value and the turn-on signal VGS_on of the secondary synchronous rectifier QS is valid; and control the secondary synchronous rectifier QS to turn off when the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value and the first latch unit outputs a low level, regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier QS is valid; the first latch unit is configured to start outputting a low level signal when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value.

[0050] Preferably, the delay unit is implemented using a phase delay unit or a low-pass filter unit.

[0051] Preferred, such as Figure 15 It also includes: a voltage divider unit 16: used to receive the first signal and output the first signal in a reduced voltage to the delay unit.

[0052] Fifthly, a chip is also provided for implementing any of the synchronous rectification control methods described above.

[0053] Beneficial effects: 1. The secondary-side synchronous rectifier is controlled to turn on or off by acquiring the voltage VDS_QS between the drain and source of the secondary-side synchronous rectifier and the fall time signal between the first time point and the second time point. The secondary-side synchronous rectifier will only be turned on when the fall time signal is less than a preset time length. This avoids the secondary-side synchronous rectifier being mistakenly turned on when the primary-side switching transistor outputs the ZVS pulse drive signal, which could lead to excessive voltage stress on the power device and damage to the power device. 2. The voltage VDS_QS between the drain and source of the secondary-side synchronous rectifier is obtained. The voltage amplitude of capacitor C2 between the first time point and the second time point is compared with a specified voltage value VSET2. The comparison output signal is used to control the turn-on or turn-off of the secondary-side rectifier. When the capacitor voltage amplitude is greater than the specified voltage value VSET2, the secondary-side rectifier will not be turned on. This avoids the secondary-side synchronous rectifier being mistakenly turned on when the primary-side switching transistor outputs the ZVS pulse drive signal, which would cause the voltage stress of the power device to exceed the standard and thus damage the power device. 3. Applicable to traditional flyback converters as well as new flyback converters such as ZVS flyback and AHB flyback.

[0054] Finally, it should be noted that any modification or equivalent substitution of some or all of the technical features based on the device structure and the technical solutions of the embodiments of the present invention, without departing from the corresponding technical solutions of the present invention, shall fall within the patent scope of the device structure and the embodiments of the present invention.

Claims

1. A synchronous rectification control method for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, characterized in that, Includes the following steps: Obtain the first signal between the drain and source of the secondary-side synchronous rectifier; The first signal is delayed by a delay unit to output the second signal; Acquire the fall time length signal between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; The first signal is sent to the switch threshold detection unit, which compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier to obtain the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier. The fall time length signal, the on signal VGS_on and the off signal VGS_off of the secondary synchronous rectifier are output to the first logic control unit. The first logic control unit controls the secondary synchronous rectifier to turn on when the on signal VGS_on of the secondary synchronous rectifier is high and the duration of the fall time length signal is less than the duration of a preset third signal; and controls the secondary synchronous rectifier to turn off when the off signal VGS_off of the secondary synchronous rectifier is high.

2. A synchronous rectification control method for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, characterized in that, Includes the following steps: Obtain the first signal between the drain and source of the secondary-side synchronous rectifier; The first signal is delayed by a delay unit to output the second signal; The voltage value of the energy storage capacitor C2 is obtained between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; the energy storage capacitor C2 is used to accumulate energy between the first time point and the second time point. The first signal is sent to the switch threshold detection unit, which compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier to obtain the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier. When the maximum voltage of the energy storage capacitor C2 is less than the specified voltage, and the turn-on signal VGS_on of the secondary synchronous rectifier is valid, the secondary synchronous rectifier is turned on. When the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value, and the first latch unit outputs a low level, the secondary synchronous rectifier is controlled to be turned off regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier is valid; the first latch unit is used to start outputting a low level signal when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value.

3. The synchronous rectification control method according to claim 2, characterized in that, The first signal outputting the second signal after passing through the delay unit includes: implementing the delay unit using a phase delay unit or a low-pass filter unit.

4. The synchronous rectification control method according to claim 2, characterized in that, The step of obtaining the voltage value of the energy storage capacitor C2 between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal includes the following steps: The first signal is sent to the inverting input of comparator U1, and the second signal is sent to the non-inverting input of comparator U1; at the same time, the first signal is sent to the non-inverting input of comparator U2, and the first reference signal is sent to the inverting input of comparator U2. The output signal Vout1 of comparator U1 and the output signal Vout2 of comparator U2 are respectively sent to AND gate U5 to obtain the output signal Vout3 of AND gate U5; The constant current source I1 is turned on and off using the Vout3 signal, so that when the constant current source I1 is turned on, the energy storage capacitor C2 is charged until the amplitude of the first signal is less than the preset first reference signal; at the same time, the gate of the switching transistor Q1 connected in parallel with the energy storage capacitor C2 is controlled using the inverted signal of the Vout2 signal. The voltage value of the energy storage capacitor C2 is obtained when the amplitude of the first signal is less than the preset first reference signal.

5. The synchronous rectification control method according to claim 4, characterized in that, The first latch unit is configured to start outputting a low-level signal when the voltage value of the energy storage capacitor C2 is greater than a specified voltage value, including the following steps: The voltage value of the energy storage capacitor C2 is compared with the specified voltage value through comparator U7 to output the Tdet signal; Invert the Tdet signal and input it simultaneously with the Vout2 signal into AND gate U9 to obtain the output Vout6 signal; The Vout6 signal is sent to the S terminal of latch U10, and the Tdet signal is sent to the R terminal of latch U10; when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value, latch U10 outputs a low-level signal.

6. The synchronous rectification control method according to claim 5, characterized in that, When the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value and the first latch unit outputs a low level, the secondary synchronous rectifier is controlled to be turned off regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier is valid. This includes the following steps: The output signal Vout7 of the latch U10 and the turn-on signal VGS_on of the secondary synchronous rectifier are simultaneously sent to the AND gate U11 to obtain the output signal Vout8 of the AND gate U11. The Vout8 signal is sent to the S terminal of latch U12, and the VGS_off signal of the secondary synchronous rectifier is sent to the R terminal of latch U12; the output terminal of latch U12 is used to output a signal to control the opening and closing of the secondary synchronous rectifier. Regardless of whether the turn-on signal VGS_on of the secondary-side synchronous rectifier is valid, the output of the latch U12 controls the secondary-side synchronous rectifier to turn off.

7. A synchronous rectification control system for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, characterized in that, include: Acquisition unit: used to acquire the first signal between the drain and source of the secondary-side synchronous rectifier; Delay unit: used to output the second signal after the first signal passes through the delay unit; Falling duration unit: used to acquire the falling time length signal between a first time point when the first signal starts to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; Threshold detection unit: used to send the first signal to the switch threshold detection unit, the switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier, and obtains the turn-on signal VGS_on and turn-off signal VGS_off of the secondary synchronous rectifier respectively; First logic control unit: This unit outputs the fall time length signal, the on signal VGS_on of the secondary-side synchronous rectifier, and the off signal VGS_off of the secondary-side synchronous rectifier to the first logic control unit. When the on signal VGS_on of the secondary-side synchronous rectifier is high and the duration of the fall time length signal is less than the duration of a preset third signal, the first logic control unit controls the secondary-side synchronous rectifier to turn on; when the off signal VGS_off of the secondary-side synchronous rectifier is high, the first logic control unit controls the secondary-side synchronous rectifier to turn off.

8. A synchronous rectification control system for controlling the switching on and off of the secondary-side synchronous rectifier diodes of a flyback converter, characterized in that, include: Acquisition unit: used to acquire the first signal between the drain and source of the secondary-side synchronous rectifier; Delay unit: used to output the second signal after the first signal passes through the delay unit; Energy storage unit: used to acquire the voltage value of energy storage capacitor C2 between a first time point when the first signal begins to be less than the second signal and a second time point when the first signal is less than a preset first reference signal; the energy storage capacitor C2 is used to accumulate energy between the first time point and the second time point; Threshold detection unit: used to send the first signal to the switch threshold detection unit, the switch threshold detection unit compares the first signal with the preset turn-on threshold and turn-off threshold of the secondary synchronous rectifier, and obtains the turn-on signal VGS_on and the turn-off signal VGS_off of the secondary synchronous rectifier respectively; The second logic control unit is used to control the secondary synchronous rectifier to turn on when the highest voltage value of the energy storage capacitor C2 is at a specified voltage value and the turn-on signal VGS_on of the secondary synchronous rectifier is valid; and to control the secondary synchronous rectifier to turn off when the highest voltage value of the energy storage capacitor C2 is greater than the specified voltage value and the first latch unit outputs a low level, regardless of whether the turn-on signal VGS_on of the secondary synchronous rectifier is valid; the first latch unit is used to start outputting a low level signal when the voltage value of the energy storage capacitor C2 is greater than the specified voltage value.

9. The synchronous rectification control system according to claim 8, characterized in that, The delay unit is implemented using a phase delay unit or a low-pass filter unit.

10. A chip, characterized in that, Used to implement any of the synchronous rectification control methods as described in claim 1 or 2.

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