Charge pump with adaptive periodic shift
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-04
- Publication Date
- 2026-08-14
Smart Images
Figure CN122577601A_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to semiconductor devices. More specifically, this disclosure relates to a charge pump having non-dissipative output voltage sensing. Background Technology
[0002] A charge pump power converter is a DC-DC converter that can convert an input voltage to a desired output voltage without using an inductor. Instead, it relies on capacitors as energy storage elements and switches to control the charge transfer process. A charge pump typically includes a controller, switches, and capacitors. The controller provides control signals (such as clock signals) to the switches, which alternately connect capacitors in series or parallel configurations. This alternating switching allows the capacitors to transfer and store charge, thereby effectively boosting or reversing the input voltage to produce the desired output voltage. Summary of the Invention
[0003] In one embodiment, a semiconductor device capable of adaptive periodic shifting is generally described. The semiconductor device may include a voltage sensing circuit configured to sense an output voltage from a charge pump. The output voltage may be equal to the steady-state voltage level of the charge pump. The semiconductor device may also include circuitry configured to output a signal indicating whether the sensed output voltage is within or outside a voltage window centered on the input voltage. The semiconductor device may further include a controller configured to adjust the period of a clock signal based on the signal output by the circuitry. The clock signal may drive the charge pump.
[0004] In one embodiment, a system capable of adaptive periodic shifting is generally described. The system may include a charge pump configured to convert an input voltage into an output voltage equal to the steady-state level of the charge pump. The system may also include a controller configured to generate a clock signal to drive the charge pump. The system may further include circuitry configured to sense the output voltage output by the charge pump. This circuitry may determine, based on the sensed output voltage, whether the output voltage is within or outside a voltage window centered on the input voltage. The circuitry may also adjust the period of the clock signal based on the determination that the output voltage is within or outside the voltage window.
[0005] In one embodiment, a method for implementing adaptive periodic shift is generally described. The method may include sensing an output voltage from a charge pump. The output voltage is equal to the steady-state voltage level of the charge pump. The method may further include determining, based on the sensed output voltage, whether the output voltage is within or outside a voltage window centered on the input voltage. The method may further include adjusting the period of a clock signal based on the determination of whether the output voltage is within or outside the voltage window. The clock signal drives the charge pump. Attached Figure Description
[0006] Figure 1 This is a diagram illustrating a system that can implement a charge pump with adaptive periodic shifting in one embodiment.
[0007] Figure 2 This is a diagram illustrating an implementation of a charge pump with adaptive periodic shifting in another embodiment.
[0008] Figure 3 This is a waveform diagram illustrating an implementation of a charge pump with adaptive periodic shift in another embodiment.
[0009] Figure 4 This is a flowchart illustrating the process of implementing a charge pump with adaptive periodic shift in the illustrated example embodiment. Detailed Implementation
[0010] In the following description, numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, are set forth in order to provide an understanding of various embodiments of this application. However, those skilled in the art will appreciate that various embodiments of this application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the application.
[0011] Figure 1 This is a diagram illustrating a system that can implement a charge pump with adaptive periodic shifting in one embodiment. Figure 1 The system 100 shown can be implemented by one or more semiconductor devices. The system 100 may include at least a controller 101, a charge pump power converter circuit 103 (hereinafter referred to as "charge pump 103"), a window detection circuit 105, a clock controller 107, a voltage sensing circuit 109, and a load 111.
[0012] Controller 101 may be, for example, a processor, microcontroller, central processing unit (CPU), field-programmable gate array (FPGA), state machine, or any other circuitry configured to control system 100 and operating system 100. Although described as a state machine in the illustrative embodiments, controller 101 is not limited to the state machines of these embodiments and may include any other circuitry configured to control and operate charge pump 103, window detection circuitry 105, and / or clock controller 107. Controller 101 may be configured to generate a clock signal CLK for controlling charge pump 103 and may be configured to receive a control signal 110 output by clock controller 107. As will be described in more detail below, controller 101 may be configured to adjust the clock period based on control signal 110.
[0013] Charge pump 103 may be, for example, a single-phase charge pump comprising four switching elements Q1, Q2, Q3, and Q4 (hereinafter referred to as "switch Q") in a half-bridge circuit configuration. In another embodiment, charge pump 103 may also be a multiphase charge pump. Charge pump 103 may include a high-side HS and a low-side LS, wherein the high-side may include switching elements Q1 and Q2, and the low-side LS may include switching elements Q3 and Q4. Switch Q may be, for example, a field-effect transistor (FET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Charge pump 103 may be configured to use a clock signal CLK to switch switch Q on and off to convert the input voltage Vin into a voltage to be output to load 111 at the voltage output pin Vout (or output voltage Vout). Load 111 may be, for example, but not limited to, a capacitive load C. load During operation, the output voltage Vout of charge pump 103 can be applied to capacitive load C. load Provide load current I load .
[0014] The charge pump 103 may include a decoupling capacitor Cdp. The decoupling capacitor Cdp may be connected in parallel with switches Q1 and Q2, and a second decoupling capacitor Cdp may be connected in parallel with switches Q3 and Q4. The decoupling capacitor Cdp can suppress or filter unwanted noise in the charge pump 103. Furthermore, the charge pump 103 may include a flying capacitor Cqp that can be connected between the HS switches Q1, Q2 and the LS switches Q3, Q4.
[0015] Voltage sensing circuit 109 may be a circuit including electrical components configured to measure or monitor voltage and / or current at a specific point in the system and provide this information to other components for control, monitoring, or protection purposes. For example, voltage sensing circuit 109 may be configured to use a sensing resistor or have a configuration with non-dissipative voltage sensing. Voltage sensing circuit 109 may be configured to perform non-dissipative voltage sensing by sensing and sampling voltage 108, which can be used to determine the output voltage Vout – Vsrc. Sampled voltage 108 may be provided to window detection circuitry for comparison. In such cases… Figure 1 In the example embodiment shown, the voltage sensing circuit 109 is configured to sense the voltage difference between Vout and Vsrc, therefore, the sampled voltage 108 is equal to Vout - Vsrc. The voltage sensing circuit 109 can also be configured to sense the voltage difference between Vout and Vsrc, therefore, the sampled voltage 108 can be equal to Vout - Vsrc.
[0016] Controller 101 can be configured to provide a clock signal CLK to the corresponding switches in charge pump 103. Controller 101 can generate the clock signal CLK to control switches Q. Because high-side HS switches Q1 and Q2 operate in a higher voltage domain, a level-shifted version of the clock signal CLK is provided. Therefore, low-side LS switches Q3 and Q4 are controlled based on the clock signal CLK, and switches Q1 and Q2 are controlled based on the level-shifted clock signal CLK. For example, when the clock signal CLK is HIGH, switch Q3 can be turned off and Q4 can be turned on, allowing the bottom of pump capacitor Cqp to be charged from Vin. Simultaneously, the level-shifted clock signal CLK causes switch Q1 to be turned off and Q2 to be turned on, allowing flying capacitor Qqp to be charged from Vsrc. Conversely, when the clock signal CLK is LOW, switch Q3 is turned on and switch Q4 is turned off, and the level-shifted clock signal CLK causes switch Q1 to be turned on and switch Q2 to be turned off, allowing the charge stored in flying capacitor Cqp to be transferred to Vout and load 111.
[0017] When the controller 101 starts the clock signal CLK, the charge pump 103 provides the load current I to the load 111. load The voltage across load 111 will increase until it reaches the steady-state voltage level of charge pump 103. This steady-state voltage level between Vout and Vsrc can, for example, be equal to the input voltage Vin or a predetermined voltage level depending on the application of system 100. The maximum output current that charge pump 103 can provide is inversely proportional to the period of the clock signal CLK. Therefore, increasing the clock frequency reduces the clock period, allowing charge pump 103 to transfer charge more frequently and deliver a higher maximum current to load 111. Conversely, a lower clock frequency results in a longer clock period, reducing the rate of charge transfer and thus reducing the maximum output current. This relationship introduces a trade-off between the clock period and the bias current of charge pump 103, which includes losses due to internal dissipation within the charge pump. Typically, a fast rise time for the output voltage Vout–Vsrc is desirable, such as for the fast turn-on of transistors or the fast rise time of data signals. However, a higher clock period results in a slower rise time for the output voltage, which can degrade system performance. On the other hand, when a low clock cycle is set to provide a faster rise time for the output voltage Vout-Vsrc, the bias current of the charge pump 103 does not decrease even after the output voltage has reached the steady-state voltage level of the charge pump 103. As a result, operating the charge pump 103 at a higher clock frequency allows for a higher output current, but also results in a consistently high bias current throughout the entire operating range.
[0018] System 100 includes a window detection circuit 105 configured to define an output voltage window. This window includes a threshold set above the charge pump steady-state voltage and a threshold set below the desired output voltage. Voltage sensing circuit 109 is configured to sense the output voltage Vout–Vsrc cycle-by-cycle or after skipping several clock cycles and provides a sampled voltage 108 to the window detection circuit 105. The window detection circuit 105 determines whether the sampled voltage 108 falls within the defined window and sends this information to the clock controller 107.
[0019] When charge pump 103 is initially enabled, clock signal CLK is set to its minimum period to rapidly increase the output voltage. After cycle-by-cycle or skipping many clock cycles of clock signal CLK, when the output voltage approaches the steady-state voltage level, sampled voltage 108 is compared with a threshold of a voltage window. If the output voltage Vout - Vsrc falls within the window, clock controller 107 provides control signal 110 to controller 101 to increase the period of clock signal CLK. This adjustment reduces the bias current of charge pump 103 while maintaining the steady-state voltage of charge pump 103. The feedback loop operates cycle-by-cycle or after skipping many clock cycles, thereby ensuring that the clock period of clock signal CLK dynamically adapts to the output voltage to optimize system performance.
[0020] Figure 2 This is a diagram illustrating an implementation of a charge pump with adaptive periodic shifting in another embodiment. Figure 2 The description can be found here. Figure 1 The components shown. In Figure 2 In the example embodiment shown, charge pump 103 may include switch Q5 connected in parallel with LS switch Q3. Charge pump 103 may also be configured to switch switch Q5 on and off using an inverted clock signal CLKN. The inverted clock signal CLKN may be the logical complement of clock signal CLK, i.e., the rising edge of clock signal CLK becomes the falling edge of inverted clock signal CLKN.
[0021] Controller 101 may include switch 211, which may be implemented as a transistor, such as an NMOS or PMOS transistor. Using switch 211, controller 101 can operate charge pump 103 in multiple modes. A signal SELECT may be generated by controller 101 in synchronization with a clock signal CLK to enable or disable operation of charge pump 103 and various operating modes. In one example embodiment, switch 211 is configured to switch between two modes. When signal SELECT enables operation of charge pump 103, switch 211 may be configured to reduce the voltage V at the drain terminal of switch 211. DD Connect to the input voltage node Vin, thereby converting the voltage V DD The input is supplied to the charge pump. When Vin equals VDD In the case of Vout-Vsrc, charge pump 103 can be configured to increase the output voltage Vout-Vsrc. Furthermore, the SELECT signal can control switch 211 to disconnect VDD from Vin and establish a connection between Vin and ground (GND). When Vin is equal to ground (GND), charge pump 103 can be configured to decrease the output voltage Vout-Vsrc.
[0022] When charge pump 103 begins operation, voltage sensing circuit 109 can sense and sample the output voltage Vout-Vsrc every clock cycle or after skipping many clock cycles. The sampled voltage 108 is provided to window detection circuit 105, which processes the voltage to determine if Vout-Vsrc is within an acceptable range. Window detection circuit 105 may include electrical components such as comparators 205 and 207, OR gate 209, and voltage sources 201 and 203. These components can be configured to define a voltage window centered on the input voltage Vin. Voltage source 201 is configured to provide an upper limit greater than Vin for the voltage window, while voltage source 203 provides a lower limit less than Vin. Depending on the specific application of the charge pump, the voltage window is predetermined and adjustable. The upper and lower limits do not need to be defined equally around Vin. For example, the upper limit may be 1% higher than the steady-state voltage of charge pump 103, while the lower limit may be 5% lower than the steady-state voltage of charge pump 103. In another example embodiment, the lower limit voltage can be 70mV, while the upper limit voltage can be 540mV. In an example embodiment where the steady-state voltage is equal to ground (GND), the upper limit voltage can be greater than ground (GND), while the lower limit voltage can be less than ground (GND).
[0023] Comparator 205 can be configured to receive an upper limit voltage from voltage source 201 at its inverting input and a sampled voltage 108 at its non-inverting input. This configuration allows comparator 205 to generate a signal indicating whether the sampled voltage 108 is below the upper limit of a voltage window. Comparator 207 can be configured to receive a lower limit voltage from voltage source 203 at its non-inverting input and a sampled voltage 108 at its inverting input. This configuration allows comparator 207 to generate a signal indicating whether the sampled voltage 108 is above the lower limit of a voltage window. The outputs of comparators 205 and 207 are fed to NOR gate 209. The NOR gate compares these outputs and generates a signal indicating whether the sampled voltage 108 is outside the defined voltage window. If the sampled voltage is greater than the upper limit (detected by comparator 205) or less than the lower limit (detected by comparator 207), the NOR gate output signal qp_OK is a logic LOW signal (or a binary 0 signal), indicating that the voltage is outside the range. If neither of the two conditions is true, it means that the sampled voltage is within the boundary of the voltage window, and the output signal qp_OK of the NOR gate is used as the logic HIGH signal (or binary 1 signal).
[0024] The signal qp_OK output by the window detection circuit 105 can be received by the clock controller 107. The clock controller 107 is configured to output a control signal 110 based on the signal qp_OK. The control signal 110 can be a 5-bit bus signal configured to instruct the controller 101 to increase or decrease the period of the clock signal CLK. For example, the control signal 110 can be a 5-bit binary signal equal to 00000, which represents the shortest period of the clock signal CLK. Conversely, the control signal 110 can be a 5-bit binary signal equal to 11111, which represents the longest period of the clock signal CLK, or the control signal 110 can be a value between 00000 and 11111.
[0025] Depending on the value of the qp_OK signal, the clock controller 107 can increment or decrement the counter and output the corresponding value as the control signal 110. For example, if the sampled voltage 108 is below the lower limit of the voltage window, the qp_OK signal received by the clock controller 107 will indicate a LOW signal. In response, the clock controller 107 decrements the counter value by 1, such as from 10001 to 10000, and outputs this updated control signal 110. This will instruct the controller 101 to slightly increase the clock frequency (equivalent to decreasing the period of CLK). If the control signal 110 is already 00000, it cannot be decremented further.
[0026] In the next clock cycle, clock controller 107 determines whether the sampled voltage 108 is now within the voltage window. If the signal remains outside the voltage window, clock controller 107 decrements the counter by 1 again, thus outputting a slightly higher frequency (shorter period) than the previous cycle. This process continues until the sampled voltage 108 falls within the voltage window, at which point the qp_OK signal changes to HIGH.
[0027] When the qp_OK indicator HIGH signal is received, clock controller 107 knows that the sampled voltage 108 is now within the window. It can then begin to decrease the clock frequency by counting the counter value, incrementally decreasing the frequency of CLK with each clock cycle or after skipping many clock cycles. If the counter value is 11111, it cannot increment further. The signal SELECT, input to controller 101, can also be provided to clock controller 107. Whenever the signal SELECT changes, it can reset the counter value of clock controller 107 to its lowest count of 00000, which corresponds to the shortest period of the clock signal CLK. This allows controller 101 to drive charge pump 103 at its highest frequency, even before the iterative process of gradually increasing the period has a chance to begin. This serves as a reset mechanism for clock controller 107.
[0028] The controller 101 can adjust the CLK period in several ways. For example, the period of the clock signal CLK can be increased / decreased linearly with each sensing cycle. In another example embodiment, the period of the clock signal CLK can be increased / decreased non-linearly with each sensing cycle. If the output voltage Vout-Vsrc remains within the output voltage window, the clock signal CLK period can continue to increase until the maximum period length of the clock signal CLK is reached. If the output voltage is detected to be outside the output voltage window, the clock signal CLK period will decrease.
[0029] Depending on the configuration of load 111, the output voltage characteristics can vary. For example, if the load is purely capacitive, the output voltage will asymptotically stabilize at the steady-state voltage of charge pump 103. If load 111 includes a non-capacitive load (e.g., with capacitor C), the output voltage characteristics will vary. load If a resistive load is connected in parallel, the output voltage will be adjusted near the lower limit of the voltage window.
[0030] Figure 3 This is a waveform diagram illustrating an implementation of a charge pump with adaptive periodic shift in another embodiment. Figure 3 The description can be found here. Figure 1 and Figure 2 The components shown. In Figure 3 The diagram illustrates three waveforms. Waveform 301 represents the output voltage Vout – Vsrc of charge pump 103, showing the voltage change (V) over time (t). Waveform 303 represents the frequency of the clock signal CLK, showing the frequency change (kHz) over time (t). Waveform 305 represents the bias current of the charge pump, showing the bias current change (mA) over time (t).
[0031] As described in the example embodiment above, when the SELECT signal enables the operation of charge pump 103, charge pump 103 operates at its maximum frequency. Waveform 303 illustrates this, where the waveform is initially at its maximum value. At its maximum frequency, the output voltage (waveform 301) begins to rise toward its steady-state voltage, as depicted by line 306. Lines 302 and 304 represent the upper and lower limits of the voltage window defined by window detection circuit 105, respectively. At time X, the output voltage Vout – Vsrc (waveform 301) crosses into the lower limit of the voltage window, as shown by waveform 301. At this time, clock controller 107 begins to instruct controller 101 to reduce the frequency of clock signal CLK, as illustrated by waveform 303, either cyclically or gradually after skipping many clock cycles, until the minimum frequency is reached. Due to the reduction in frequency, the current bias also begins to decrease, as illustrated by waveform 305 at time X.
[0032] Figure 4 This is a flowchart illustrating the process of implementing a charge pump with adaptive periodic shift in an illustrated example embodiment. Process 400 may include one or more operations, actions, or functions as illustrated by one or more of blocks 402, 404, and / or 406. Although illustrated as discrete blocks, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel, depending on the desired implementation.
[0033] Process 400 can be executed by a charge pump. Process 400 can begin at block 402, where the controller senses the output voltage from the charge pump. The output voltage is equal to the steady-state voltage level of the charge pump. The process can continue from block 402 to block 404. At block 404, based on the sensed output voltage, the controller can determine whether the output voltage is within or outside a voltage window centered on the input voltage. The process can continue from block 404 to block 406. At block 406, the controller can adjust the period of a clock signal, which drives the charge pump, based on the determination that the output voltage is within or outside the voltage window.
[0034] In another embodiment, the charge pump may increase the period of the clock signal when the signal indicates that the output voltage is within a voltage window. In another embodiment, the charge pump may decrease the period of the clock signal when the signal indicates that the output voltage is outside the voltage window. In yet another embodiment, the charge pump may periodically sense the output voltage and periodically adjust the period of the clock signal.
[0035] In another embodiment, the charge pump can also minimize the period of the clock signal when the operating mode of the charge pump changes. In another embodiment, the voltage window is defined by an upper threshold greater than the steady-state voltage level and a lower threshold less than the steady-state voltage level. In another embodiment, a first difference between the upper threshold and the steady-state voltage level, and a second difference between the lower threshold and the steady-state voltage level, are not equal.
[0036] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each box in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function(s). In some alternative implementations, the functions indicated in the boxes may occur in a different order than those noted in the figures. For example, depending on the functions involved, two boxes shown consecutively may actually be executed substantially simultaneously, or these boxes may sometimes be executed in reverse order. It should also be noted that each box in the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions. Example
[0037] Example 1: A semiconductor device comprising: a voltage sensing circuit configured to sense an output voltage from a charge pump, wherein the output voltage is equal to a steady-state voltage level of the charge pump; a circuit configured to output a signal indicating whether the sensed output voltage is within or outside a voltage window centered on an input voltage; and a controller configured to adjust the period of a clock signal based on the signal output by the circuit, wherein the clock signal drives the charge pump.
[0038] Example 2: The semiconductor device according to Example 1, wherein the controller is further configured to increase the period of the clock signal when the signal indicates that the output voltage is within the voltage window.
[0039] Example 3: A semiconductor device according to any one of Examples 1 to 2, wherein the controller is further configured to reduce the period of the clock signal when the signal indicates that the output voltage is outside the voltage window.
[0040] Example 4: A semiconductor device according to any one of Examples 1 to 3, wherein the voltage sensing circuit is configured to periodically sense the output voltage, and the controller is configured to periodically adjust the period of the clock signal.
[0041] Example 5: A semiconductor device according to any one of Examples 1 to 4, wherein the controller is configured to minimize the period of the clock signal when the operating mode of the charge pump changes.
[0042] Example 6: A semiconductor device according to any one of Examples 1 to 5, wherein the voltage window is defined by an upper threshold greater than the steady-state voltage level and a lower threshold less than the steady-state voltage level.
[0043] Example 7: A system comprising: a charge pump configured to convert an input voltage into an output voltage equal to a steady-state level of the charge pump; a controller configured to generate a clock signal to drive the charge pump; and circuitry configured to: sense the output voltage output by the charge pump; determine, based on the sensed output voltage, whether the output voltage is within or outside a voltage window centered on the input voltage; and adjust the period of the clock signal based on the determination that the output voltage is within or outside the voltage window.
[0044] Example 8: According to the system of Example 7, wherein the circuit is further configured to increase the period of the clock signal when the signal indicates that the output voltage is within the voltage window.
[0045] Example 9: A system according to any one of Examples 7 to 8, wherein the circuit is further configured to reduce the period of the clock signal when the signal indicates that the output voltage is outside the voltage window.
[0046] Example 10: A system according to any one of Examples 7 to 9, wherein the circuit is configured to: periodically sense the output voltage; and periodically adjust the period of the clock signal.
[0047] Example 11: A system according to any one of Examples 7 to 10, wherein: the controller is configured to generate a selection signal to control the operating mode of the charge pump; in a first operating mode, the charge pump increases the input voltage to reach the steady-state voltage level; and in a second operating mode, the charge pump decreases the input voltage to reach the steady-state voltage level.
[0048] Example 12: A system according to any one of Examples 7 to 11, wherein the circuit is configured to minimize the period of the clock signal when the operating mode of the charge pump changes.
[0049] Example 13: A system according to any one of Examples 7 to 12, wherein the voltage window is defined by an upper threshold greater than the steady-state voltage level and a lower threshold less than the steady-state voltage level.
[0050] Example 14: A method comprising: sensing an output voltage from a charge pump, wherein the output voltage is equal to a steady-state voltage level of the charge pump; determining, based on the sensed output voltage, whether the output voltage is within or outside a voltage window centered on an input voltage; and adjusting the period of a clock signal based on the determination that the output voltage is within or outside the voltage window, wherein the clock signal drives the charge pump.
[0051] Example 15: The method according to Example 14 further includes increasing the period of the clock signal when the signal indicates that the output voltage is within the voltage window.
[0052] Example 16: The method according to any one of Examples 14 to 15 further includes reducing the period of the clock signal when the signal indicates that the output voltage is outside the voltage window.
[0053] Example 17: The method according to any one of Examples 14 to 16 further includes periodically sensing the output voltage and periodically adjusting the period of the clock signal.
[0054] Example 18: The method according to any one of Examples 14 to 17, wherein when the operating mode of the charge pump changes, the method further includes minimizing the period of the clock signal.
[0055] Example 19: The method according to any one of Examples 14 to 18, wherein the voltage window is defined by an upper threshold greater than the steady-state voltage level and a lower threshold less than the steady-state voltage level.
[0056] Example 20: The method according to any one of Examples 14 to 19, wherein the first difference between the upper threshold and the steady-state voltage level and the second difference between the lower threshold and the steady-state voltage level are not equal.
[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that, when used in this specification, the term “comprises and / or comprising” specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0058] The corresponding structures, materials, actions, and equivalents of all components or steps plus functional elements (if any) in the following claims are intended to include any structures, materials, or actions for performing the function in combination with other claimed elements as specifically claimed. The disclosed embodiments of this disclosure have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of this disclosure, and to enable others skilled in the art to understand this disclosure with respect to various embodiments having various modifications suitable for the particular intended use.
Claims
1. A semiconductor device, comprising: A voltage sensing circuit is configured to sense an output voltage from a charge pump, wherein the output voltage is equal to the steady-state voltage level of the charge pump; The circuit is configured to output a signal indicating whether the sensed output voltage is within or outside a voltage window centered on the input voltage; as well as The controller is configured to adjust the period of a clock signal based on the signal output by the circuit, wherein the clock signal drives the charge pump.
2. The semiconductor device of claim 1, wherein the controller is further configured to: increase the period of the clock signal when the signal indicates that the output voltage is within the voltage window.
3. The semiconductor device of claim 1, wherein the controller is further configured to: reduce the period of the clock signal when the signal indicates that the output voltage is outside the voltage window.
4. The semiconductor device of claim 1, wherein the voltage sensing circuit is configured to periodically sense the output voltage, and the controller is configured to periodically adjust the period of the clock signal.
5. The semiconductor device of claim 1, wherein when the operating mode of the charge pump changes, the controller is configured to minimize the period of the clock signal.
6. The semiconductor device of claim 1, wherein the voltage window is defined by an upper threshold greater than the steady-state voltage level and a lower threshold less than the steady-state voltage level.
7. A system comprising: A charge pump is configured to convert an input voltage into an output voltage, the output voltage being equal to the steady-state level of the charge pump; The controller is configured to generate a clock signal to drive the charge pump; as well as The circuit is configured as follows: Sensing the output voltage output by the charge pump; Based on the sensed output voltage, determine whether the output voltage is within or outside a voltage window centered on the input voltage; as well as The period of the clock signal is adjusted based on the determination that the output voltage is within or outside the voltage window.
8. The system of claim 7, wherein the circuit is further configured to: increase the period of the clock signal when the signal indicates that the output voltage is within the voltage window.
9. The system of claim 7, wherein the circuit is further configured to: reduce the period of the clock signal when the signal indicates that the output voltage is outside the voltage window.
10. The system of claim 7, wherein the circuit is configured to: Periodically sense the output voltage; and The period of the clock signal is adjusted periodically.
11. The system according to claim 7, wherein: The controller is configured to generate a selection signal to control the operating mode of the charge pump; In the first operating mode, the charge pump increases the input voltage to achieve the steady-state voltage level; as well as In the second operating mode, the charge pump reduces the input voltage to achieve the steady-state voltage level.
12. The system of claim 7, wherein when the operating mode of the charge pump changes, the circuit is configured to minimize the period of the clock signal.
13. The system of claim 7, wherein the voltage window is defined by an upper threshold greater than the steady-state voltage level and a lower threshold less than the steady-state voltage level.
14. A method comprising: The output voltage from the charge pump is sensed, wherein the output voltage is equal to the steady-state voltage level of the charge pump; Based on the sensed output voltage, determine whether the output voltage is within or outside a voltage window centered on the input voltage; as well as The period of the clock signal, which drives the charge pump, is adjusted based on the determination that the output voltage is within or outside the voltage window.
15. The method of claim 14, further comprising: When the signal indicates that the output voltage is within the voltage window, the period of the clock signal is increased.
16. The method of claim 14, further comprising: When the signal indicates that the output voltage is outside the voltage window, the period of the clock signal is reduced.
17. The method of claim 14, further comprising: The output voltage is periodically sensed, and the period of the clock signal is periodically adjusted.
18. The method of claim 14, wherein when the operating mode of the charge pump changes, the method further comprises minimizing the period of the clock signal.
19. The method of claim 14, wherein the voltage window is defined by an upper threshold greater than the steady-state voltage level and a lower threshold less than the steady-state voltage level.
20. The method of claim 19, wherein the first difference between the upper threshold and the steady-state voltage level and the second difference between the lower threshold and the steady-state voltage level are not equal.