A solid-state transformer and its rectifier-side DC link voltage equalization control method and system

Abstract

This invention provides a solid-state transformer and its rectifier-side DC link voltage equalization control method and system, relating to the field of power electronic converters. The method includes the following steps: Step S1 signal acquisition; Step S2 total voltage summation and average value calculation; Step S3 voltage outer loop control; Step S4 current inner loop control; Step S5 feedforward compensation and control quantity generation for each module; Step S6 dynamic voltage equalization adjustment. This invention simultaneously achieves two objectives, eliminates the need for high-speed inter-module communication, exhibits fast dynamic response, strong robustness, and ease of expansion.

Description

Technical Field

[0001] This invention relates to the field of power electronic converters, and more specifically, to a solid-state transformer and a method and system for equalizing DC link voltage on its rectifier side. Background Technology

[0002] Traditional power distribution networks cannot flexibly integrate renewable energy generation and energy storage, nor can they meet the power consumption needs of smart microgrids. Distribution networks built around solid-state transformers (SSTs) possess exceptional renewable energy absorption capabilities. Renewable energy generation, such as wind and solar power, is intermittent and random; SSTs, through power electronic conversion technology, can rapidly adjust power flow and amplitude, smoothing out power fluctuations and enhancing the grid's ability to absorb renewable energy. SSTs can also be used to build smart microgrids. In industrial parks and remote areas, SSTs can enable interconnection between multiple microgrids and seamless switching between microgrids and the main grid, ensuring power supply reliability. Furthermore, against the backdrop of rapid development in artificial intelligence, computing power has become a core driving force for technological advancement. New-generation information technologies, represented by artificial intelligence, cloud computing, and the Internet of Things, are driving AI data centers to evolve from traditional "general computing" to "intelligent computing" and "supercomputing." The power required for computing racks is increasing, highlighting the limitations of traditional power supply architectures in terms of system efficiency, space utilization, and renewable energy integration. DC 800V power supply technology has emerged. 800V DC power supply systems, with solid-state transformers (SSTs) as key conversion devices, effectively reduce power transmission losses and copper usage by minimizing AC / DC conversion stages and increasing voltage levels. This improves the overall end-to-end operating efficiency of the system and significantly saves space, demonstrating excellent technical economy and voltage adaptability. Currently, to enable solid-state transformers to directly draw power from 10KV or 35KV grids, isolated solid-state transformers commonly employ three design approaches: first, using semiconductor devices in series; second, using a modular multilevel converter structure; and third, using a series input and parallel output or series input and series output configuration.

[0003] In existing solid-state transformer designs based on MMC and ISOP, the DC link voltage is uneven in MMC and ISOP applications due to the use of multi-chain series connection on the high-voltage side of the input, which affects the use of the transformer. Summary of the Invention

[0004] This invention aims to solve the problem of uneven DC link voltage in existing MMC and ISOP applications where multiple chains are connected in series on the high-voltage side of the input.

[0005] To address the aforementioned problems, this invention provides a DC link voltage equalization control method for the rectifier side of a solid-state transformer. This method is applied to the rectifier stage of any phase in the solid-state transformer. The phase comprises n power modules, each power module having an AC / DC rectifier stage, a DC / DC isolation stage, and a DC link capacitor connected between the AC / DC rectifier stage and the DC / DC isolation stage. The AC input terminals of the n power modules are connected in series to the AC power grid of that phase, and the DC output terminals of the n power modules are connected in parallel to serve as the low-voltage DC bus of that phase. The control method includes the following steps: Step S1: Signal acquisition. A voltage sensor is set inside each power module to acquire the voltage across the DC link capacitor in real time, and record it as the internal DC voltage Vdc1, Vdc2, ..., Vdcn; A voltage sensor and a current sensor are installed on the AC input side of this phase to collect the AC voltage signal Vin and the AC current signal Iin, respectively. Step S2: Total voltage summation and average value calculation. Sum the n internal DC voltages collected to obtain the actual value of the total DC link voltage of the phase, Vdc∑, that is: Vdc∑=Vdc1+Vdc2+...+Vdcn; At the same time, divide the actual value of the total voltage Vdc∑ by n to obtain the average voltage Vavg of the DC link of that phase, that is: Vavg=Vdc∑ / n; Step S3: Voltage outer loop control. Set the target value Vdc∑ref of the total DC link voltage for this phase. This target value is usually set according to the downstream load demand and the system rated voltage, and is equal to n times the rated DC voltage of a single module. Subtract the actual value Vdc∑ref from the target value to obtain the voltage error value. V, that is: V = Vdc∑ref - Vdc∑; Voltage error value V is fed into the first PI regulator for adjustment, and the voltage outer loop regulation output Uv_out is obtained; the voltage outer loop regulation output Uv_out is multiplied with the acquired input AC voltage signal Vin to generate the current reference signal Iref of the current inner loop, that is: Iref=Uv_out×Vin; Step S4: Inner loop control of the current, subtract the current reference signal Iref from the acquired input AC current signal Iin to obtain the current error value. I, that is: I = Iref - Iin; Current error value The current is fed into the second PI regulator for adjustment, resulting in the inner current loop regulation output Ui_out. Dividing the inner current loop regulation output Ui_out by the number of power modules n in that phase yields the basic regulation value. u, that is: u = Ui_out / n; Step S5: Feedforward compensation and control quantity generation for each module. For the i-th power module, i=1,...,n, calculate the DC voltage error value of this module. Vdci = Vavg - Vdci After Vdci is adjusted by the third PI regulator, the voltage compensation quantity Ucom_i is obtained, and then the final control quantity ui is calculated. u-Ucom_i or ui= u+Ucom_i, and use ui to generate the PWM control signal to drive the AC / DC rectifier stage switching transistor of this module; Step S6: Dynamic voltage equalization adjustment. Through the closed-loop control of steps 1 to 5 above, when the internal DC voltage Vdci of a certain power module deviates from the average value Vavg, the control logic automatically adjusts the PWM duty cycle of that module, so that the voltage of the module with a lower value rises and the voltage of the module with a higher value falls, thereby achieving dynamic balance of the DC link voltages Vdc1, Vdc2, ..., Vdcn of all modules, while ensuring that the input current Iin and the voltage Vin are in phase, thus achieving unity power factor control.

[0006] The present invention provides a DC link voltage equalization control method for the rectifier side of a solid-state transformer, which, compared with the prior art, has the following beneficial effects, but is not limited to: The invention achieves two objectives simultaneously: by using the cascaded structure of the outer voltage loop and the inner current loop, it ensures that the input current follows the voltage waveform, thus achieving unity power factor; at the same time, by using the independent voltage feedforward compensation loop of each module, it achieves dynamic balance of DC link voltage, and the two control objectives are decoupled from each other and do not interfere with each other.

[0007] This invention eliminates the need for high-speed inter-module communication: the voltage equalization control of each module relies solely on the globally calculated Vavg and the locally acquired Vdci, without requiring the transmission of real-time duty cycle or voltage error signals between modules. This greatly improves the system's reliability and anti-interference capability, and reduces hardware costs.

[0008] This invention features a fast dynamic response: when a module voltage deviates, the deviation not only acts directly through the local compensation loop, but also affects the global base regulation through changes in the total voltage and average value. u forms a dual-path adjustment system, accelerating the pressure equalization process.

[0009] The invention is highly robust: the control structure is insensitive to differences in module parameters, aging, temperature drift, etc., and can maintain good voltage equalization effect over a wide load range.

[0010] The invention is easily expandable: for any number of series modules n, only the division coefficient and the number of PWM channels need to be modified, and the algorithm structure does not need to be changed, thus exhibiting good scalability.

[0011] Furthermore, step S5 specifically includes: Step S51: Calculate the DC voltage error value of the module. Vdci, that is: Vdci = Vavg - Vdci; Step S52: ... Vdci is fed into the third PI regulator, that is, the independent PI regulator of each module is adjusted to obtain the voltage compensation amount Ucom_i of the module. Step S53: Calculate the final control quantity ui of this module, i.e.: ui = u-Ucom_i; Alternatively, based on polarity design, ui= u+Ucom_i, so that when Vdci is low, the PWM duty cycle can be increased to boost the voltage; this scheme uses ui= Taking u-Ucom_i as an example, the logic will be explained later; Step S54: The final control quantity ui is sent to the pulse width modulation (PWM) generator of the module and compared with the high-frequency carrier to generate a PWM control signal that drives the AC / DC rectifier stage switching transistor in the module.

[0012] Furthermore, in step S5, when the internal DC voltage Vdci of the i-th power module is too low, the specific adjustment process is as follows: Because Vdci is low, the actual value of the sum of DC link voltages in this phase, Vdc∑, is slightly lower than expected, thus causing a voltage error value. V increases slightly, and after passing through the first PI regulator and multiplication operation, the current reference signal Iref increases slightly, which in turn, after passing through the inner current loop, causes... u increases slightly; Meanwhile, due to the low Vdci, although the average value Vavg is also slightly low, the difference between Vavg and Vdci is... Vdci increases significantly, and the absolute value of the negative error increases. After Vdci is regulated by the third PI regulator, the absolute value of the output voltage compensation Ucom_i also increases accordingly; According to ui= The relationship between u and Ucom_i is such that increasing Ucom_i leads to a decrease in the final control variable ui. The reduction in ui causes the PWM modulation amplitude to decrease relative to the carrier wave, resulting in a decrease in the duty cycle of the AC / DC rectifier stage switching transistor of the module. Consequently, in the next switching cycle, the time for the input current to charge the DC link capacitor of the module increases relatively, and the internal DC voltage Vdci of the module rises until it recovers to the Vavg level.

[0013] Furthermore, in step S5, when the internal DC voltage Vdci of the i-th power module is too high, the specific adjustment process is as follows: Because Vdci is too high, the actual value of the sum of DC link voltages in this phase, Vdc∑, is slightly higher than expected, thus causing a voltage error value. As V decreases slightly, after passing through the first PI regulator and multiplication operation, the current reference signal Iref decreases slightly, and then, after passing through the inner current loop, it causes... u decreases slightly; Meanwhile, due to the high Vdci, the average value Vavg is also slightly higher, but the difference between Vavg and Vdci is... Vdci decreases significantly, the absolute value of the positive error decreases or becomes negative. After Vdci is regulated by the third PI regulator, the absolute value of the output voltage compensation Ucom_i will decrease accordingly or even reverse. According to ui= The relationship between u and Ucom_i is such that a decrease in Ucom_i leads to an increase in the final control variable ui. The increase in ui causes the PWM modulation amplitude to rise relative to the carrier wave, resulting in an increase in the duty cycle of the AC / DC rectifier stage switching transistor of the module. Consequently, in the next switching cycle, the time for the DC link capacitor of the module to release energy to the load or subsequent circuits increases relatively, and the DC voltage Vdci inside the module drops until it returns to the Vavg level.

[0014] Furthermore, in step S3, the target value Vdc∑ref of the outer voltage loop is equal to n times the rated DC voltage of a single module; during steady-state operation, the theoretical value of the DC link voltage of each module is Vdc∑ref / n, which is equal to the rated DC voltage of a single module.

[0015] Furthermore, in step S3, the current reference signal Iref is obtained by directly multiplying the output of the outer voltage loop with the instantaneous AC voltage Vin, so that the waveform of Iref is completely consistent with the waveform of Vin. Thus, under the tracking control of the inner current loop, the waveform of the actual input current Iin also strictly follows the waveform of Vin, achieving high power factor and low harmonic content.

[0016] Furthermore, the first PI controller, the second PI controller, and the third PI controller all adopt a discrete incremental PID algorithm or a positional PID algorithm, and the proportional coefficient and integral coefficient of each PI controller are independently tuned according to the system's dynamic response requirements and stability requirements.

[0017] Furthermore, the PWM control signal is generated using unipolar frequency doubling modulation or bipolar modulation, and the carrier frequency of the PWM control signal is not lower than 10kHz.

[0018] A rectifier-side control system for a solid-state transformer includes: The rectifier stage of any phase in a solid-state transformer contains n power modules with inputs connected in series and outputs connected in parallel; each power module has a voltage sensor inside for acquiring its own DC link voltage Vdci; and the AC input side of the phase has a voltage sensor for acquiring AC voltage Vin and a current sensor for acquiring AC current Iin. A digital controller executes the DC link voltage equalization control method to generate PWM drive signals for the AC / DC rectifier stages of each power module.

[0019] A solid-state transformer includes a main power circuit and a three-level control system; the input terminal of the main power circuit is connected to a medium- and high-voltage power grid, and the main power circuit is connected to the three-level control system. The main power circuit includes power module valve groups; the power module valve groups include A-phase power module valve group stacks, B-phase power module valve group stacks and C-phase power module valve group stacks, which are connected in parallel, and each phase power module valve group stack contains multiple power modules. The three-level control system includes a main controller, three phase controllers, and multiple module controllers. The main power circuit is signal-connected to the main controller. The three phase controllers are connected one-to-one with the valve groups of the A-phase power module, B-phase power module, and C-phase power module. The phase controllers are bidirectionally connected to the main controller via a pair of fiber optic interfaces. The phase controllers are bidirectionally connected to the phase controllers of the other two phases via two pairs of fiber optic interfaces. The phase controllers are connected to multiple module controllers of their respective phases via multiple pairs of fiber optic interfaces. The module controllers and power modules are signal-connected one-to-one. The rectifier stage of each phase controller adopts the aforementioned solid-state transformer rectifier-side control system and executes the aforementioned solid-state transformer rectifier-side DC link voltage equalization control method. Attached Figure Description

[0020] Figure 1 This is a flowchart of the DC link voltage equalization control method for the rectifier side of the solid-state transformer of the present invention. Figure 2This is a schematic diagram of the main power circuit of the DC link voltage equalization control method on the rectifier side of the solid-state transformer of the present invention; Figure 3 This is a schematic diagram of the main controller interface of the present invention; Figure 4 This is a schematic diagram of the phase controller interface of the present invention; Figure 5 This is a schematic diagram showing the connection of the module controller interface, drive adapter circuit, and module power circuit of the present invention. Figure 6 This is a schematic diagram illustrating the principle of the carrier horizontal phase-shifting SPWM modulation strategy in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram illustrating the working principle of the DC link voltage equalization control function on the rectifier side in Embodiment 1 of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings showing multiple embodiments according to this application. It should be understood that the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without creative effort will fall within the scope of protection of this application.

[0022] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the specification of this application is for the purpose of describing specific embodiments only and is not intended to limit this application; the terms "comprising," "including," "having," "containing," etc., in the specification, claims, and accompanying drawings of this application are open-ended terms. Therefore, "comprising," "including," or "having" refers to, for example, a method or apparatus having one or more steps or elements, but is not limited to having only these one or more elements. The terms "first," "second," etc., in the specification, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0023] In the description of this invention, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] It should be emphasized that when the term "comprising / including" is used in this specification, it is used to explicitly indicate the presence of the stated feature, integer, step, or component, but does not exclude the presence or addition of one or more other features, integers, steps, parts, or groups of features, integers, steps, or parts.

[0026] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, in this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0027] See Figures 1-7 This invention discloses a DC link voltage equalization control method for the rectifier side of a solid-state transformer, applied to the rectifier stage of any phase in the solid-state transformer. This phase includes n power modules, each power module having an AC / DC rectifier stage, a DC / DC isolation stage, and a DC link capacitor connected between the AC / DC rectifier stage and the DC / DC isolation stage. The AC input terminals of the n power modules are connected in series to the AC power grid of this phase, and the DC output terminals of the n power modules are connected in parallel to serve as the low-voltage DC bus of this phase. The control method includes the following steps: Step S1: Signal acquisition. A voltage sensor is set inside each power module to acquire the voltage across the DC link capacitor in real time, and record it as the internal DC voltage Vdc1, Vdc2, ..., Vdcn; A voltage sensor and a current sensor are installed on the AC input side of this phase to collect the AC voltage signal Vin and the AC current signal Iin, respectively. Step S2: Total voltage summation and average value calculation. Sum the n internal DC voltages collected to obtain the actual value of the total DC link voltage of the phase, Vdc∑, that is: Vdc∑=Vdc1+Vdc2+...+Vdcn; At the same time, divide the actual value of the total voltage Vdc∑ by n to obtain the average voltage Vavg of the DC link of that phase, that is: Vavg=Vdc∑ / n; Step S3: Voltage outer loop control. Set the target value Vdc∑ref of the total DC link voltage for this phase. This target value is usually set according to the downstream load demand and the system rated voltage, and is equal to n times the rated DC voltage of a single module. Subtract the actual value Vdc∑ref from the target value to obtain the voltage error value. V, that is: V = Vdc∑ref - Vdc∑; Voltage error value V is fed into the first PI regulator for adjustment, and the voltage outer loop regulation output Uv_out is obtained; the voltage outer loop regulation output Uv_out is multiplied with the acquired input AC voltage signal Vin to generate the current reference signal Iref of the current inner loop, that is: Iref=Uv_out×Vin; Step S4: Inner loop control of the current, subtract the current reference signal Iref from the acquired input AC current signal Iin to obtain the current error value. I, that is: I = Iref - Iin; Current error value The current is fed into the second PI regulator for adjustment, resulting in the inner current loop regulation output Ui_out. Dividing the inner current loop regulation output Ui_out by the number of power modules n in that phase yields the basic regulation value. u, that is: u = Ui_out / n; Step S5: Feedforward compensation and control quantity generation for each module. For the i-th power module, i=1,...,n, calculate the DC voltage error value of this module. Vdci = Vavg - Vdci After Vdci is adjusted by the third PI regulator, the voltage compensation quantity Ucom_i is obtained, and then the final control quantity ui is calculated. u-Ucom_i or ui= u+Ucom_i, and use ui to generate the PWM control signal to drive the AC / DC rectifier stage switching transistor of this module; Step S6: Dynamic voltage equalization adjustment. Through the closed-loop control of steps 1 to 5 above, when the internal DC voltage Vdci of a certain power module deviates from the average value Vavg, the control logic automatically adjusts the PWM duty cycle of that module, so that the voltage of the module with a lower value rises and the voltage of the module with a higher value falls, thereby achieving dynamic balance of the DC link voltages Vdc1, Vdc2, ..., Vdcn of all modules, while ensuring that the input current Iin and the voltage Vin are in phase, thus achieving unity power factor control.

[0028] In this invention, step S1 provides real-time and accurate physical quantity feedback for the entire control system, including the DC link voltage, AC input voltage, and AC input current of each power module.

[0029] Simultaneously, global phase current and phase voltage, as well as local voltage information for each module, are collected, laying the data foundation for hierarchical control. Each module's voltage sensor operates independently, eliminating the need for signal transmission between modules and avoiding communication delays and the risk of fault propagation. Data can be refreshed in each control cycle, supporting high-frequency dynamic adjustment.

[0030] Step S2 calculates the actual sum of the DC link voltages for that phase and the average DC link voltage for that phase, compressing the discrete voltage information from multiple modules into two key quantities: the total voltage used for power balancing and the average value used for voltage equalization reference. Only the voltages from each module need to be summed and averaged at the main controller; point-to-point communication between modules is not required.

[0031] Step S3 sets the total voltage, compares it with the actual total voltage, and multiplies the error by the given voltage after PI adjustment to generate the reference signal for the inner current loop. The outer loop ensures that the total voltage of the entire phase DC link tracks the given value, i.e., the entire phase power is balanced. The outer loop output, multiplied by the voltage, is directly used as the command for the inner current loop. The current loop only needs to be responsible for zero steady-state error tracking and does not need to generate an additional sinusoidal reference.

[0032] Step S4 compares the error, and after PI adjustment, divides it by the number of modules n to obtain the basic adjustment amount Δu. This achieves rapid input current tracking: the high bandwidth of the current inner loop allows for quick response to command changes and suppression of grid harmonics and dynamic disturbances. The current loop output is evenly distributed among the n modules, ensuring that each module bears the same power regulation responsibility macroscopically and preventing overload of some modules. The current inner loop can resist interference such as grid voltage distortion and load abrupt changes, maintaining the sinusoidal nature of the input current.

[0033] Step S5: Feedforward Compensation and Control Quantity Generation for Each Module The voltage error is calculated separately for each module, and the compensation amount is obtained after PI regulation. This compensation amount is then combined with the basic regulation amount to generate the final control amount for that module, which in turn generates a PWM signal.

[0034] Each module independently corrects its voltage deviation from the average value, with modules exhibiting larger deviations receiving greater compensation for rapid balancing. This system is responsible for local deviation correction; the two corrections are superimposed without mutual interference and do not require exchanging duty cycles or error signals with other modules. Even if a module exhibits significant deviations, such as signs of aging or impending damage, the compensation loop can maintain system stability and prevent cascading imbalances.

[0035] Step S6 uses closed-loop control to automatically correct voltage deviations in each module: fast dynamic response: deviation signals affect the same area simultaneously, forming dual-path regulation and accelerating the voltage equalization process.

[0036] The integral action of the PI regulator ensures that the voltage of each module is strictly equal to Vavg in steady state. It is insensitive to differences in module parameters, temperature drift, and load changes. It prevents individual modules from over-voltage from damaging the switching transistors and also prevents under-voltage from preventing power transfer.

[0037] The invention achieves two objectives simultaneously: by using the cascaded structure of the outer voltage loop and the inner current loop, it ensures that the input current follows the voltage waveform, thus achieving unity power factor; at the same time, by using the independent voltage feedforward compensation loop of each module, it achieves dynamic balance of DC link voltage, and the two control objectives are decoupled from each other and do not interfere with each other.

[0038] This invention eliminates the need for high-speed inter-module communication: the voltage equalization control of each module relies solely on the globally calculated Vavg and the locally acquired Vdci, without requiring the transmission of real-time duty cycle or voltage error signals between modules. This greatly improves the system's reliability and anti-interference capability, and reduces hardware costs.

[0039] This invention features a fast dynamic response: when a module voltage deviates, the deviation not only acts directly through the local compensation loop, but also affects the global base regulation through changes in the total voltage and average value. u forms a dual-path adjustment system, accelerating the pressure equalization process.

[0040] The invention is highly robust: the control structure is insensitive to differences in module parameters, aging, temperature drift, etc., and can maintain good voltage equalization effect over a wide load range.

[0041] The invention is easily expandable: for any number of series modules n, only the division coefficient and the number of PWM channels need to be modified, and the algorithm structure does not need to be changed, thus exhibiting good scalability.

[0042] Furthermore, step S5 specifically includes: Step S51: Calculate the DC voltage error value of the module. Vdci, that is: Vdci = Vavg - Vdci; Step S52: ... Vdci is fed into the third PI regulator, that is, the independent PI regulator of each module is adjusted to obtain the voltage compensation amount Ucom_i of the module. Step S53: Calculate the final control quantity ui of this module, i.e.: ui = u-Ucom_i; Alternatively, based on polarity design, ui= u+Ucom_i, so that when Vdci is low, the PWM duty cycle can be increased to boost the voltage; this scheme uses ui= Taking u-Ucom_i as an example, the logic will be explained later; Step S54: The final control quantity ui is sent to the pulse width modulation (PWM) generator of the module and compared with the high-frequency carrier to generate a PWM control signal that drives the AC / DC rectifier stage switching transistor in the module.

[0043] Step S51: Calculate DC voltage error Vdci compares the global average voltage with the local actual voltage to generate the voltage deviation signal for this module. This deviation reflects the degree and direction of the module's deviation from the overall phase average level. Each module only needs to know the globally broadcast Vavg and its own acquired Vdci to independently determine its own deviation. This provides a precise error input for subsequent PI regulation and avoids sign misinterpretation.

[0044] Step S52: The third PI adjustment obtains the compensation amount. Each module independently calculates the compensation amount based on its own deviation, without interfering with each other. Dynamic response is adjustable: By adjusting the PI parameters and integral coefficients, the voltage equalization response speed and stability of each module can be individually tuned. When a module experiences voltage drift due to temperature, aging, parameter differences, or other reasons, this loop can actively generate reverse compensation.

[0045] Step S53 calculates the final control quantity, decoupling global and local control: Δu is responsible for total power balance, i.e., outer loop demand, while Ucom_i is responsible for voltage equalization correction, i.e., local demand; the two are superimposed without conflict. Even if all modules receive the same Δu, the final ui will be different due to the different Ucom_i, thus achieving the voltage equalization effect of "same instruction, different output". Addition or subtraction is selected according to the system design to facilitate engineering debugging.

[0046] Step S54 generates a PWM control signal. The final control quantity is sent to the PWM generator and compared with a high-frequency carrier wave, such as a 20kHz triangular wave, to generate a PWM signal that drives the AC / DC rectifier stage of this module, such as the H-bridge switch. This signal is updated once per control cycle and immediately reflected in the PWM duty cycle of the next cycle, achieving cycle-by-cycle adjustment. Unipolar, bipolar, and unipolar frequency multiplication PWM strategies are supported. The PWM module inside the DSP or FPGA can directly perform the comparison output.

[0047] Step S5 of this invention, through the chain of "deviation calculation → PI compensation → superposition with global command → PWM output", decouples and integrates the global power demand and local voltage deviation, generating personalized but overall coordinated control signals for each module. It is the core execution link for realizing fast, zero steady-state error, and robust voltage equalization of the DC link in the multi-module ISOP structure.

[0048] Furthermore, in step S5, when the internal DC voltage Vdci of the i-th power module is too low, the specific adjustment process is as follows: Because Vdci is low, the actual value of the sum of DC link voltages in this phase, Vdc∑, is slightly lower than expected, thus causing a voltage error value. V increases slightly, and after passing through the first PI regulator and multiplication operation, the current reference signal Iref increases slightly, which in turn, after passing through the inner current loop, causes... u increases slightly; Meanwhile, due to the low Vdci, although the average value Vavg is also slightly low, the difference between Vavg and Vdci is... Vdci increases significantly, and the absolute value of the negative error increases. After Vdci is regulated by the third PI regulator, the absolute value of the output voltage compensation Ucom_i also increases accordingly; According to ui= The relationship between u and Ucom_i is such that increasing Ucom_i leads to a decrease in the final control variable ui. The reduction in ui causes the PWM modulation amplitude to decrease relative to the carrier wave, resulting in a decrease in the duty cycle of the AC / DC rectifier stage switching transistor of the module. Consequently, in the next switching cycle, the time for the input current to charge the DC link capacitor of the module increases relatively, and the internal DC voltage Vdci of the module rises until it recovers to the Vavg level.

[0049] This step clearly demonstrates that when the voltage of a certain module is low, the system works simultaneously through two parallel paths: the global path attempts to increase ui because the total voltage is low and more overall charging is needed, while the local path attempts to decrease ui because the voltage of this module is more severely low and requires more charging time.

[0050] Through complete dynamic signal flow analysis, this invention reveals how it utilizes the characteristics of "slow global total voltage response and fast local deviation response" to automatically identify modules with low voltage and prioritize compensation, thereby achieving fast and accurate voltage equalization while maintaining the overall phase power balance.

[0051] Furthermore, in step S5, when the internal DC voltage Vdci of the i-th power module is too high, the specific adjustment process is as follows: Because Vdci is too high, the actual value of the sum of DC link voltages in this phase, Vdc∑, is slightly higher than expected, thus causing a voltage error value. As V decreases slightly, after passing through the first PI regulator and multiplication operation, the current reference signal Iref decreases slightly, and then, after passing through the inner current loop, it causes... u decreases slightly; Meanwhile, due to the high Vdci, the average value Vavg is also slightly higher, but the difference between Vavg and Vdci is... Vdci decreases significantly, the absolute value of the positive error decreases or becomes negative. After Vdci is regulated by the third PI regulator, the absolute value of the output voltage compensation Ucom_i will decrease accordingly or even reverse. According to ui= The relationship between u and Ucom_i is such that a decrease in Ucom_i leads to an increase in the final control variable ui. The increase in ui causes the PWM modulation amplitude to rise relative to the carrier wave, resulting in an increase in the duty cycle of the AC / DC rectifier stage switching transistor of the module. Consequently, in the next switching cycle, the time for the DC link capacitor of the module to release energy to the load or subsequent circuits increases relatively, and the DC voltage Vdci inside the module drops until it returns to the Vavg level.

[0052] This step forms a strictly symmetrical but logically opposite complete description with the previous section on the low voltage situation. It details the automatic adjustment process of the control method of this invention when the DC voltage inside a certain power module is too high. This closed loop proves that the invention has symmetrical and effective adjustment capabilities for both high and low voltage situations, that is, the system is bidirectional and reversible, and will not have the unidirectional adjustment defects of "only rising and not falling" or "only falling and not rising". Without additional logical judgment, the integral action of the PI regulator will automatically complete this polarity conversion, reflecting the intelligence and simplicity of the control system. This symmetry proves that the control logic of this invention is inherently consistent, and there is no nonlinear problem of "asymmetric response to positive and negative deviations", ensuring the stability and predictability of the system across the entire operating range. Through a complete dynamic analysis symmetrical to the "low voltage situation", it proves that the invention has bidirectional, symmetrical, and automatic polarity switching adjustment capabilities for both high and low voltage deviations, reveals the intelligent compensation mechanism of Ucom_i that can "change from positive to negative", and verifies that the system can make the high voltage fall back to the average value level without steady-state error, thus forming a complete theoretical closed loop of the voltage equalization control of this invention together with the low voltage situation.

[0053] Furthermore, in step S3, the target value Vdc∑ref of the outer voltage loop is equal to n times the rated DC voltage of a single module; during steady-state operation, the theoretical value of the DC link voltage of each module is Vdc∑ref / n, which is equal to the rated DC voltage of a single module.

[0054] This step clarifies the basis for setting the target value Vdc∑ref of the outer voltage loop and the theoretical values ​​of each module's voltage during steady-state operation. The target value of the outer voltage loop is explicitly quantified as n times the rated voltage of a single module, thus establishing the control benchmark for the total phase voltage. From this, it is deduced that the voltage of each module is strictly equal to its rated value during steady-state operation, providing a unified physical anchor point for power factor correction, voltage equalization convergence analysis, and standardized system design.

[0055] Furthermore, in step S3, the current reference signal Iref is obtained by directly multiplying the output of the outer voltage loop with the instantaneous AC voltage Vin, so that the waveform of Iref is completely consistent with the waveform of Vin. Thus, under the tracking control of the inner current loop, the waveform of the actual input current Iin also strictly follows the waveform of Vin, achieving high power factor and low harmonic content.

[0056] This step clarifies the generation method of the current reference signal Iref and its decisive influence on the quality of the input current waveform. This invention achieves waveform consistency between the current reference signal and the grid voltage through a simple mathematical operation: "directly multiplying the outer voltage loop output by the instantaneous AC voltage." Furthermore, under the current inner loop tracking, it simultaneously achieves multiple objectives—unity power factor, low harmonic content, implicit grid voltage feedforward, and natural decoupling of the inner and outer loops—with minimal computational cost and hardware resources. Furthermore, the first PI controller, the second PI controller, and the third PI controller all adopt a discrete incremental PID algorithm or a positional PID algorithm, and the proportional coefficient and integral coefficient of each PI controller are independently tuned according to the system's dynamic response requirements and stability requirements.

[0057] In this invention, the abstract concept of "regulation via PI controller" is concretized into an incremental or positional PID algorithm that can be implemented in engineering. It also emphasizes that the three PI controllers, due to their different functional roles (i.e., external voltage protection total voltage, internal current protection waveform, and voltage equalization protection balance), must have their proportional and integral coefficients independently tuned. This ensures the optimal dynamic response of each loop while maintaining system stability.

[0058] Furthermore, the PWM control signal is generated using unipolar frequency doubling modulation or bipolar modulation, and the carrier frequency of the PWM control signal is not lower than 10kHz.

[0059] This invention converts the final control quantity ui generated in step S5 into an executable PWM signal. By explicitly stating that unipolar frequency multiplication or bipolar modulation can be used, and specifying that the carrier frequency is not lower than 10kHz, it provides a physical basis for high-bandwidth tracking of the current inner loop and fast response of the voltage equalization loop while ensuring low switching losses, low noise, and low current ripple. A rectifier-side control system for a solid-state transformer includes: The rectifier stage of any phase in a solid-state transformer contains n power modules with inputs connected in series and outputs connected in parallel; each power module has a voltage sensor inside for acquiring its own DC link voltage Vdci; and the AC input side of the phase has a voltage sensor for acquiring AC voltage Vin and a current sensor for acquiring AC current Iin. A digital controller executes the DC link voltage equalization control method described above to generate PWM drive signals for the AC / DC rectifier stages of each power module.

[0060] This invention translates the aforementioned control method from software algorithms into a hardware system. By defining a distributed sensor layout, namely, each module has a DC voltage sensor + each phase has an AC voltage / current sensor and a digital controller to execute all control algorithms, a complete sensing-computation-execution closed-loop hardware platform is constructed. This provides a concrete system architecture that can be implemented in engineering for the DC link voltage equalization control on the rectifier side of a solid-state transformer. This is the key bridge for this invention to move from theoretical methods to product implementation.

[0061] A solid-state transformer includes a main power circuit and a three-level control system; the input terminal of the main power circuit is connected to a medium- and high-voltage power grid, and the main power circuit is connected to the three-level control system. The main power circuit includes power module valve groups; the power module valve groups include A-phase power module valve group stacks, B-phase power module valve group stacks and C-phase power module valve group stacks, which are connected in parallel, and each phase power module valve group stack contains multiple power modules. The three-level control system includes a main controller, three phase controllers, and multiple module controllers. The main power circuit is signal-connected to the main controller. The three phase controllers are connected one-to-one with the valve groups of the A-phase power module, B-phase power module, and C-phase power module. The phase controllers are bidirectionally connected to the main controller via a pair of fiber optic interfaces. The phase controllers are bidirectionally connected to the phase controllers of the other two phases via two pairs of fiber optic interfaces. The phase controllers are connected to multiple module controllers of their respective phases via multiple pairs of fiber optic interfaces. The module controllers and power modules are signal-connected one-to-one. The rectifier stage of each phase controller adopts the above-mentioned rectifier-side control system and executes the above-mentioned DC link voltage equalization control method.

[0062] This invention integrates the above-mentioned control method and rectifier-side control system into a complete solid-state transformer product, forming a complete technical solution of "three-phase AC input → three-phase independent ISOP rectifier stage, i.e., each phase executes the voltage equalization control of this invention → high-frequency isolation stage → low-voltage DC output".

[0063] Example 1 uses a 10kV AC input, with 10 single-phase modules connected in series (n=10). The H-bridge circuit within each module is constructed from 1200V SiC MOSFETs. Specifically, the modulation frequency is 50Hz, the period is 20ms, and the amplitude remains constant at 1. A horizontal phase-shifted SPWM modulation strategy is employed, where the phase shift angle θ=2 between the 10 triangular carriers is sequentially shifted. Π / 10, carrier frequency 400Hz, period 2.5ms; during normal operation, the modulation principle and the H-bridge drive PWM in power module 1 and power module 2 are described in [link to documentation]. Figure 6 When the internal DC voltage of power module 1 is low, the DC link voltage equalization control function on the rectifier side comes into play. Through adjustment by the control system, the amplitude of carrier wave u1 is reduced, thereby increasing the PWM duty cycle of power module 1, ultimately increasing the internal DC voltage of power module 1. The principle is as follows: Figure 7 Conversely, when the internal DC voltage of power module 1 is too high, the DC link voltage equalization control function on the rectifier side comes into play. After adjustment by the control system, the amplitude of carrier u1 is increased, thereby reducing the PWM duty cycle of power module 1 and ultimately increasing the internal DC voltage of power module 1.

[0064] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. A method for equalizing DC link voltage control on the rectifier side of a solid-state transformer, characterized in that, This method applies to the rectifier stage of any phase in a solid-state transformer. The phase comprises n power modules, each with an AC / DC rectifier stage, a DC / DC isolation stage, and a DC link capacitor connecting the AC / DC rectifier stage and the DC / DC isolation stage. The AC input terminals of the n power modules are connected in series to the AC power grid of that phase, and the DC output terminals of the n power modules are connected in parallel to serve as the low-voltage DC bus of that phase. The control method includes the following steps: Step S1: Signal acquisition. A voltage sensor is set inside each power module to acquire the voltage across the DC link capacitor in real time, and record it as the internal DC voltage Vdc1, Vdc2, ..., Vdcn; A voltage sensor and a current sensor are installed on the AC input side of this phase to collect the AC voltage signal Vin and the AC current signal Iin, respectively. Step S2: Total voltage summation and average value calculation. Sum the n internal DC voltages collected to obtain the actual value of the total DC link voltage of the phase, Vdc∑, that is: Vdc∑=Vdc1+Vdc2+...+Vdcn; At the same time, divide the actual value of the total voltage Vdc∑ by n to obtain the average voltage Vavg of the DC link of that phase, that is: Vavg=Vdc∑ / n; Step S3: Voltage outer loop control. Set the target value Vdc∑ref of the total DC link voltage for this phase. This target value is usually set according to the downstream load demand and the system rated voltage, and is equal to n times the rated DC voltage of a single module. Subtract the actual value Vdc∑ref from the target value to obtain the voltage error value. V, that is: V = Vdc∑ref - Vdc∑; Voltage error value V is fed into the first PI regulator for adjustment, and the voltage outer loop regulation output Uv_out is obtained; the voltage outer loop regulation output Uv_out is multiplied with the acquired input AC voltage signal Vin to generate the current reference signal Iref of the current inner loop, that is: Iref=Uv_out×Vin; Step S4: Inner loop control of the current, subtract the current reference signal Iref from the acquired input AC current signal Iin to obtain the current error value. I, that is: I = Iref - Iin; Current error value The current is fed into the second PI regulator for adjustment, resulting in the inner current loop regulation output Ui_out. Dividing the inner current loop regulation output Ui_out by the number of power modules n in that phase yields the basic regulation value. u, that is: u = Ui_out / n; Step S5: Feedforward compensation and control quantity generation for each module. For the i-th power module, i=1,...,n, calculate the DC voltage error value of this module. Vdci = Vavg - Vdci After Vdci is adjusted by the third PI regulator, the voltage compensation quantity Ucom_i is obtained, and then the final control quantity ui is calculated. u-Ucom_i or ui= u+Ucom_i, and use ui to generate the PWM control signal to drive the AC / DC rectifier stage switching transistor of this module; Step S6: Dynamic voltage equalization adjustment. Through the closed-loop control of steps 1 to 5 above, when the internal DC voltage Vdci of a certain power module deviates from the average value Vavg, the control logic automatically adjusts the PWM duty cycle of that module, so that the voltage of the module with a lower value rises and the voltage of the module with a higher value falls, thereby achieving dynamic balance of the DC link voltages Vdc1, Vdc2, ..., Vdcn of all modules, while ensuring that the input current Iin and the voltage Vin are in phase, thus achieving unity power factor control.

2. The method for equalizing DC link voltage on the rectifier side of a solid-state transformer according to claim 1, characterized in that, Step S5 specifically involves: Step S51: Calculate the DC voltage error value of the module. Vdci, that is: Vdci = Vavg - Vdci; Step S52: ... Vdci is fed into the third PI regulator, that is, the independent PI regulator of each module is adjusted to obtain the voltage compensation amount Ucom_i of the module. Step S53: Calculate the final control quantity ui of this module, i.e.: ui = u-Ucom_i; Alternatively, based on polarity design, ui= u+Ucom_i, so that when Vdci is low, the PWM duty cycle can be increased to boost the voltage; this scheme uses ui= Taking u-Ucom_i as an example, the logic will be explained later; Step S54: The final control quantity ui is sent to the pulse width modulation (PWM) generator of the module and compared with the high-frequency carrier to generate a PWM control signal that drives the AC / DC rectifier stage switching transistor in the module.

3. The method for equalizing DC link voltage on the rectifier side of a solid-state transformer according to claim 2, characterized in that, In step S5, when the internal DC voltage Vdci of the i-th power module is too low, the specific adjustment process is as follows: Because Vdci is low, the actual value of the sum of DC link voltages in this phase, Vdc∑, is slightly lower than expected, thus causing a voltage error value. V increases slightly, and after passing through the first PI regulator and multiplication operation, the current reference signal Iref increases slightly, which in turn, after passing through the inner current loop, causes... u increases slightly; Meanwhile, due to the low Vdci, although the average value Vavg is also slightly low, the difference between Vavg and Vdci is... Vdci increases significantly, and the absolute value of the negative error increases. After Vdci is regulated by the third PI regulator, the absolute value of the output voltage compensation Ucom_i also increases accordingly; According to ui= The relationship between u and Ucom_i is such that increasing Ucom_i leads to a decrease in the final control variable ui. The reduction in ui causes the PWM modulation amplitude to decrease relative to the carrier wave, resulting in a decrease in the duty cycle of the AC / DC rectifier stage switching transistor of the module. Consequently, in the next switching cycle, the time for the input current to charge the DC link capacitor of the module increases relatively, and the internal DC voltage Vdci of the module rises until it recovers to the Vavg level.

4. The DC link voltage equalization control method for the rectifier side of a solid-state transformer according to claim 3, characterized in that, In step S5, when the internal DC voltage Vdci of the i-th power module is too high, the specific adjustment process is as follows: Because Vdci is too high, the actual value of the sum of DC link voltages in this phase, Vdc∑, is slightly higher than expected, thus causing a voltage error value. As V decreases slightly, after passing through the first PI regulator and multiplication operation, the current reference signal Iref decreases slightly, and then, after passing through the inner current loop, it causes... u decreases slightly; Meanwhile, due to the high Vdci, the average value Vavg is also slightly higher, but the difference between Vavg and Vdci is... Vdci decreases significantly, the absolute value of the positive error decreases or becomes negative. After Vdci is regulated by the third PI regulator, the absolute value of the output voltage compensation Ucom_i will decrease accordingly or even reverse. According to ui= The relationship between u and Ucom_i is such that a decrease in Ucom_i leads to an increase in the final control variable ui. The increase in ui causes the PWM modulation amplitude to rise relative to the carrier wave, resulting in an increase in the duty cycle of the AC / DC rectifier stage switching transistor of the module. Consequently, in the next switching cycle, the time for the DC link capacitor of the module to release energy to the load or subsequent circuits increases relatively, and the DC voltage Vdci inside the module drops until it returns to the Vavg level.

5. The method for equalizing DC link voltage control on the rectifier side of a solid-state transformer according to claim 1, characterized in that, In step S3, the target value Vdc∑ref of the outer voltage loop is equal to n times the rated DC voltage of a single module; during steady-state operation, the theoretical value of the DC link voltage of each module is Vdc∑ref / n, which is equal to the rated DC voltage of a single module.

6. The method for equalizing DC link voltage on the rectifier side of a solid-state transformer according to claim 5, characterized in that, In step S3, the current reference signal Iref is obtained by directly multiplying the output of the outer voltage loop with the instantaneous AC voltage Vin, so that the waveform of Iref is completely consistent with the waveform of Vin. Thus, under the tracking control of the inner current loop, the waveform of the actual input current Iin also strictly follows the waveform of Vin, achieving high power factor and low harmonic content.

7. The DC link voltage equalization control method for the rectifier side of a solid-state transformer according to claim 6, characterized in that, The first, second, and third PI controllers all employ discrete incremental PID algorithms or positional PID algorithms, and the proportional and integral coefficients of each PI controller are independently tuned according to the system's dynamic response and stability requirements.

8. The method for equalizing DC link voltage on the rectifier side of a solid-state transformer according to claim 7, characterized in that, The PWM control signal is generated using unipolar frequency doubling modulation or bipolar modulation, and the carrier frequency of the PWM control signal is not lower than 10kHz.

9. A rectifier-side control system for a solid-state transformer, characterized in that, include: The rectifier stage of any phase in a solid-state transformer contains n power modules with inputs connected in series and outputs connected in parallel; each power module has a voltage sensor inside for acquiring its own DC link voltage Vdci; and the AC input side of the phase has a voltage sensor for acquiring AC voltage Vin and a current sensor for acquiring AC current Iin. A digital controller executes the DC link equalization control method for the rectifier side of the solid-state transformer as described in any one of claims 1 to 8, generating PWM drive signals for the AC / DC rectifier stages of each power module.

10. A solid-state transformer, characterized in that, It includes a main power circuit and a three-level control system; the input terminal of the main power circuit is connected to the medium- and high-voltage power grid, and the main power circuit is connected to the three-level control system. The main power circuit includes power module valve groups; the power module valve groups include A-phase power module valve group stacks, B-phase power module valve group stacks and C-phase power module valve group stacks, which are connected in parallel, and each phase power module valve group stack contains multiple power modules. The three-level control system includes a main controller, three phase controllers, and multiple module controllers; the main power loop is connected to the main controller via signal; the three phase controllers are connected one-to-one with the A-phase power module valve group, the B-phase power module valve group, and the C-phase power module valve group; the phase controllers are bidirectionally connected to the main controller via a pair of optical fiber interfaces; the phase controllers are bidirectionally connected to the phase controllers of the other two phases via two pairs of optical fiber interfaces. The phase controller is connected to multiple module controllers of its phase through multiple pairs of optical fiber interfaces; the module controllers and power modules are connected in a one-to-one correspondence; wherein the rectifier stage of each phase controller adopts the rectifier-side control system of the solid-state transformer as described in claim 9, and executes the DC link equalization control method of the rectifier side of the solid-state transformer as described in any one of claims 1 to 8.

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