A unified modulation and capacitor voltage self-balancing method suitable for scalable hybrid cascaded H-bridge multilevel inverter

Abstract

This invention discloses a unified modulation and capacitor voltage self-balancing method applicable to scalable hybrid cascaded H-bridge multilevel inverters, belonging to the field of PWM technology for multilevel converters. The method includes: setting up a topology family based on a 1:1:3 basic building block; generating switching signals through a logical combination modulation strategy; during the positive half-cycle of the modulation wave, comparing the low-voltage unit modulation wave with four triangular carrier waves of the same frequency, phase, and amplitude to generate a first PWM signal controlling the switching transistors of each unit; during the negative half-cycle of the modulation wave, comparing the modulation wave with another four triangular carrier waves to generate a second PWM signal controlling the switching transistors of each unit; wherein, by switching between the two operating modes based on the capacitor voltage difference and the output current direction, the capacitor voltage is automatically balanced, thereby achieving high-quality output waveform without increasing control complexity.

Description

Technical Field

[0001] This invention belongs to the field of pulse width modulation technology for multilevel converters, specifically relating to a unified modulation and capacitor voltage self-balancing method applicable to scalable hybrid cascaded H-bridge (CHB) multilevel inverters. It can be widely used in medium- and high-voltage high-power power electronic equipment such as photovoltaic grid-connected power generation, energy storage systems, and power electronic transformers. Background Technology

[0002] Multilevel inverters have been widely used in medium- and high-voltage high-power conversion fields due to their significant advantages such as low output voltage stress, low electromagnetic interference, and high output power quality. Among various multilevel topologies, cascaded H-bridge inverters, with their high modularity and ease of expansion and maintenance, have gradually become the preferred solution in fields such as photovoltaic grid-connected power generation, energy storage technology, and power electronic transformers. However, with each additional cascaded unit in a traditional cascaded H-bridge inverter, a corresponding independent isolated DC power supply is required. As the number of cascaded units increases, the number of required DC sources also increases, significantly increasing system cost and size, as well as greatly increasing the complexity of DC-side wiring and raising the system failure rate.

[0003] To reduce the number of DC sources, replacing some independent DC sources with floating capacitors has become an effective technical approach. However, existing research on capacitor-based hybrid cascaded H-bridge inverters is mostly focused on specific topologies, lacking a systematic and scalable unified design methodology. In some schemes, the stability of the capacitor voltage relies on complex offline calculations of switching angles or online closed-loop control. As the number of cascaded units increases, the number of required control modes multiplies, leading to a significant increase in modulation complexity. Furthermore, some topologies employ complex transformations of the modulation wave to improve capacitor voltage utilization, increasing waveform distortion and control implementation difficulty, thus affecting the output power quality.

[0004] Therefore, there is an urgent need for a unified modulation method that can significantly reduce the number of DC sources while taking into account automatic capacitor voltage balancing, output waveform quality, modulation strategy scalability, and control implementation difficulty. Summary of the Invention

[0005] 1. Technical problem to be solved: To address the technical problems of existing hybrid cascaded H-bridge multilevel inverters, such as a large number of DC sources, high system cost, complex DC-side wiring, high complexity of capacitor voltage balancing strategy control, lack of scalability of modulation strategies, lack of precise basis for determining capacitor values, and difficulty in simultaneously achieving good output waveform quality, this invention proposes a unified modulation and capacitor voltage self-balancing method suitable for scalable hybrid cascaded H-bridge multilevel inverters. This method aims to achieve automatic capacitor voltage balancing through logic combination modulation and dual-mode switching strategies, significantly reducing the number of DC sources while maintaining excellent output waveform quality. It also provides a systematic and scalable topology design framework and a precise method for determining capacitor parameters.

[0006] 2. Technical Solution: To solve the above problems, the present invention adopts the following technical solution.

[0007] A unified modulation and capacitor voltage self-balancing method applicable to scalable hybrid cascaded H-bridge multilevel inverters is applied to an inverter topology family constructed by expanding a basic building block. The basic building block consists of a first low-voltage unit, a second low-voltage unit, and a high-voltage unit cascaded together. The first low-voltage unit is powered by a DC source with a rated voltage of E; the second low-voltage unit is powered by a capacitor instead of a DC source with a rated voltage of E; and the high-voltage unit is powered by a DC source with a rated voltage three times that of the low-voltage units. The method is characterized by the following steps: Four triangular carriers are set up, which have the same frequency, equal amplitude, and consistent phase, and are divided into a positive half-cycle carrier layer and a negative half-cycle carrier layer in the vertical direction. During the positive half-cycle of the modulation wave, the modulation wave of the low-voltage unit is compared with the carrier in the positive half-cycle carrier layer. A logic signal is generated based on the comparison result, and the first PWM signal for controlling the switching transistors of the first and second low-voltage units is generated through logic combination. At the same time, the instantaneous value of the original sinusoidal modulation wave is compared with the 2E step wave threshold to generate the base frequency signal for controlling the switching transistor of the high-voltage unit. During the negative half-cycle of the modulation wave, the modulation wave of the low-voltage unit is compared with the carrier in the negative half-cycle carrier layer. A logic signal is generated based on the comparison result, and a second PWM signal is generated to control the switching transistors of the first and second low-voltage units through logic combination. During this period, the base frequency signal of the high-voltage unit maintains or switches its current state based on the comparison result between the instantaneous value of the modulation wave and the threshold of the stepped wave. The capacitor voltage of the second low-voltage unit is automatically balanced by switching between two operating modes. The difference between the two operating modes is that the switching signals of the first low-voltage unit and the second low-voltage unit are exchanged, while the switching signal of the high-voltage unit remains unchanged. The mode switching is based on the difference between the real-time capacitor voltage and the rated voltage and the direction of the output current.

[0008] Preferably, the modulation wave of the low-voltage unit is obtained by piecewise linear transformation of the original sinusoidal modulation wave. Specifically, when the instantaneous value of the original modulation wave is greater than 2E, the modulation wave of the low-voltage unit is equal to the amplitude of the original modulation wave minus 3E; when the instantaneous value of the original modulation wave is less than or equal to -2E, the modulation wave of the low-voltage unit is equal to the amplitude of the original modulation wave plus 3E; and when the instantaneous value of the original modulation wave is between -2E and 2E, the modulation wave of the low-voltage unit is equal to 0. This transformation ensures that the low-voltage unit only participates in high-frequency modulation when a level difference needs to be supplemented, thereby effectively reducing switching losses.

[0009] Preferably, the specific switching rule for the two operating modes is as follows: define the capacitor voltage difference. Δuc = UcN - Uc ,in UcN This is the rated voltage of the capacitor. Uc The real-time voltage of the capacitor; when Δuc When > 0, the capacitor needs to be charged; when Δ uc When < 0, the capacitor needs to be discharged; Define the inverter output current io The positive direction is: the current flowing out from the positive terminal of the AC side of the inverter is positive; When Δ uc > 0: If the output current io > 0, switch to mode 2; if the output current io < 0, switch to mode 1; When Δ uc When <0: If the output current io > 0, switch to mode 1; if the output current io If the value is less than 0, switch to mode 2. This switching rule ensures that the capacitor voltage automatically tends to balance under various load conditions.

[0010] Preferably, when the inverter is expanded horizontally from a basic building block to a structure cascaded with one or more new high-voltage units, the new high-voltage units are powered by capacitors and their voltage levels are the same as those of the original high-voltage units in the basic building block. In mode 1, each new high-voltage unit corresponds one-to-one with an existing high-voltage unit, and their switching states are complementary. In mode 2, the switching signals of each pair of corresponding high-voltage units are exchanged to achieve automatic voltage balancing of all capacitor-powered high-voltage units.

[0011] Preferably, when the inverter is extended vertically from the basic building block, the number of units and the cascading order are exactly the same as the basic building block, except that the DC voltage of the high-voltage unit is increased to n times the voltage of the low-voltage unit, where n is an integer greater than or equal to 2; the base frequency switching signal generation rule of the high-voltage unit is updated to: when the original modulation wave is greater than 2E, the output is +nE; when the original modulation wave is less than -2E, the output is -nE; and when the original modulation wave is between -2E and 2E, the output is zero level; the logic combination modulation strategy and the dual-mode capacitor voltage self-balancing mechanism of the low-voltage unit remain unchanged.

[0012] Preferably, the unified modulation method controls the entire topology family through a parameterized recursive approach: the extended parameters include the high-voltage unit voltage multiple *n* and the horizontal extension level *m*. The original modulation wave is subjected to a piecewise linear transformation based on these extended parameters to obtain the low-voltage unit modulation wave. This low-voltage unit modulation wave is then fed into the logic combination modulation module of the low-voltage unit to generate a low-voltage unit switching signal. The original modulation wave is fed into the stepped wave comparison module of the high-voltage unit to generate a high-voltage unit switching signal. By updating the extended parameters *n* and *m*, switching signals suitable for different extended topologies can be generated. This unified modulation framework allows the entire topology family to share the same core modulation architecture, requiring only parameter configuration to adapt to any extension scheme.

[0013] Preferably, the method further includes a capacitor value determination step: The capacitor charging process is actively controlled via dual-mode switching, ensuring that the peak-to-peak value of the capacitor voltage ripple is entirely determined by the longest continuous discharge interval within one output cycle. Considering the engineering constraint that the peak-to-peak value of the capacitor voltage ripple does not exceed 10% of the rated voltage, the total discharge charge within this continuous discharge interval is calculated by integration. Based on the fundamental capacitor charging and discharging formula ΔQ=C·ΔU, the minimum capacitance value that meets the ripple requirements is determined. This design method provides a unified theoretical basis for parameter selection of all capacitors in the topology family.

[0014] 3. Beneficial effects: Compared with the prior art, the technical solution provided by this invention has the following advantages: (1) This invention achieves automatic equalization of capacitor voltage across the full modulation ratio range through logic combination modulation and dual-mode switching strategy. It eliminates the need for complex offline angle calculation or online closed-loop controller, making the control simple and reliable and significantly reducing the complexity of system control.

[0015] (2) The scalable topology family proposed in this invention can increase the number of output levels to 17 or even 21 levels through horizontal expansion, and can improve the output voltage gain through vertical expansion. All expansion schemes only require two DC sources. Compared with the traditional hybrid cascaded H-bridge inverter with the same number of output levels, the number of DC sources is reduced by more than 33%, which significantly reduces the system cost and the complexity of DC side wiring.

[0016] (3) The unified modulation framework of the present invention takes the basic building blocks as the core. It can adapt to any member of the entire topology family by only updating the parameters and the state lookup table. The modulation core architecture remains unchanged, and it has good scalability and versatility. It solves the problem that the control strategy needs to be redesigned for each additional cascaded unit in the traditional scheme.

[0017] (4) When the basic building block outputs an 11-level stepped wave with a modulation ratio of 0.9, the total harmonic distortion of the output voltage is 13.06%. After horizontal expansion to a 1:1:3:3 structure, it outputs a 17-level wave, and the total harmonic distortion is reduced to 7.82%. After composite expansion to a 1:1:4:4 structure, it outputs a 21-level wave, and the total harmonic distortion is further reduced to 6.19%. The output power quality is significantly improved, and the harmonic characteristics are excellent.

[0018] (5) The generalized capacitor design formula provided by the present invention can be uniformly applied to the parameter design of all capacitors in the topology family, providing a clear design basis for engineering applications and reducing the difficulty of system design.

[0019] It should be noted that the structures not described in this invention are not related to the design points and improvement directions of this invention, and are the same as or can be implemented using existing technologies, so they will not be elaborated here. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the topology of the basic building blocks, in which the low-voltage unit H1 is powered by DC source E, the low-voltage unit H2 is powered by a capacitor, and the high-voltage unit H3 is powered by DC source 3E. Figure 2 This is a schematic diagram of the capacitor cell's operating modes, where (a) is the charging / discharging mode when U2=1, (b) is the discharging / charging mode when U2=-1, and (c) and (d) are the bypass modes with the upper bridge arm and lower bridge arm conducting when U2=0, respectively. Figure 3 This is a schematic diagram of the circuit mode switching. Figure 4 This is a schematic diagram of the logic signal combination modulation principle; Figure 5 A schematic diagram illustrating the evolution and structure of a scalable hybrid cascaded H-bridge inverter family; Figure 6 The diagram shows a unified modulation framework, where (a) represents the modulation principle of the basic building block, (b) represents the modulation principle of horizontal expansion to 1:1:3:3, and (c) represents the modulation principle of vertical expansion to 1:1:4. Figure 7The following are the voltage waveforms of the capacitor at different operating stages, where (a) shows the rapid voltage build-up process of the capacitor and (b) shows the voltage ripple waveform of the capacitor during the steady-state adjustment stage (M=0.9). Figure 8 The output voltage waveform is plotted against the phase relationship of the load current, which is used to analyze the capacitor charging and discharging range and conduction angle. Figure 9 The results are from a dynamic simulation, where (a) represents the output voltage when the load switches from an inductive load to a purely resistive load (M=0.9). uo Output current io (a) The waveform of capacitor voltage uc, and (b) the output voltage when the modulation ratio M increases from 0.6 to 0.9. uo Output current io The dynamic response waveform of the capacitor voltage uc; Figure 10 The output voltage, current waveforms, and total harmonic distortion (THD) are shown in the following diagrams: (a) output level 7 when M=0.6, (b) output level 9 when M=0.7, (c) output level 9 when M=0.8, and (d) output level 11 when M=0.9, along with the corresponding harmonic spectrum distribution. Figure 11 The output voltage, current waveforms, and total harmonic distortion (THD) are analyzed for different extended topologies at M=0.9. Figure 12 The experimental waveforms of output voltage and current under different modulation ratios are shown, where (a) output level 7 when M=0.6, (b) output level 9 when M=0.7, (c) output level 9 when M=0.8, and (d) output level 11 when M=0.9. Figure 13 Output voltage of H2 unit uo 2. Experimental waveforms of capacitor voltage uc and capacitor current ic, where (a) is the dynamic establishment process of capacitor voltage, (b) is the steady-state operating waveform, and (c) is the independent output voltage waveform of each unit (H1, H2, H3); Figure 14 The diagram shows a comparative analysis of the switching power loss of the low-voltage unit, comparing the switching losses of units H1 and H2 under the modulation strategy proposed in this invention with those under the traditional hybrid modulation strategy. Detailed Implementation

[0021] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. The specific embodiments described are only for explaining the present invention and are not intended to limit the scope of protection of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0022] Example 1: Basic Building Block – Three-Unit Hybrid Cascaded H-Bridge Inverter This embodiment uses a basic building block consisting of three cascaded H-bridge units as an example to illustrate the implementation process of the present invention in detail.

[0023] 1. Circuit Topology Figure 1 The topology diagram of the basic building blocks is given. The main circuit consists of three cascaded H-bridge units H1, H2, and H3. H1 is the first low-voltage unit, powered by an independent DC source E on its DC side; H2 is the second low-voltage unit, powered by a capacitor C on its DC side with a rated voltage uc = E; H3 is the high-voltage unit, powered by an independent DC source 3E on its DC side. The AC output terminals of the three units are connected in series, and the total output voltage is output between the midpoint of the left arm of H1 and the midpoint of the right arm of H3.

[0024] Each H-bridge unit consists of four switching transistors Si1, Si2, Si3, and Si4, where i = 1, 2, and 3, corresponding to units H1, H2, and H3 respectively. Each switching transistor can be an IGBT connected in parallel with a freewheeling diode. The low-voltage unit can output -E, 0, and E voltage levels, while the high-voltage unit can output -3E, 0, and 3E voltage levels. Theoretically, cascading the three units can output 11 stepped waveforms ranging from -5E to 5E.

[0025] Inverter total output voltage uo The sum of the output voltages of each unit is expressed as: uo = uo 1 + uo 2 + uo 3 (1), Output current io It can be represented in sine form: io = Im sin(ωt-φ) (2), in Im ω is the output current amplitude, ω is the output voltage angular frequency, and φ is the output impedance angle. 2. Logic combination modulation strategy The modulation wave Vm is a sine wave with an amplitude of As and a frequency of fs. The modulation ratio M is defined as As / (5E), and its value ranges from 0 to 1. When M=0.9, As=4.5E, and the inverter can output a full-amplitude 11 level.

[0026] The low-voltage unit modulation wave Vm1 is obtained from the original sinusoidal modulation wave Vm through a piecewise linear transformation, and its expression is: When Vm > 2E, Vm1 = Vm - 3E; when Vm ≤ -2E, Vm1 = Vm + 3E. When -2E < Vm ≤ 2E, Vm1 = 0.

[0027] This transformation ensures that the low-voltage unit only participates in high-frequency modulation when the original modulation wave exceeds the ±2E range provided by the high-voltage unit, thereby effectively reducing the number of switching operations and losses of the low-voltage unit.

[0028] The carriers are set as four triangular carriers with the same frequency (carrier frequency fc = 3000Hz), phase, and amplitude (amplitude E). They are divided into two groups in the vertical direction: the positive half-cycle carrier layer includes the upper carrier Vtri2+ and the lower carrier Vtri1+, with amplitude ranges of [E, 2E] and [0,E], respectively; the negative half-cycle carrier layer includes the upper carrier Vtri2- and the lower carrier Vtri1-, with amplitude ranges of [-2E, -E] and [-E, 0], respectively.

[0029] Figure 4 This is a schematic diagram of the logic signal combination modulation principle. During the positive half-cycle of the modulation wave, the low-voltage unit modulation wave Vm1 is compared with the positive half-cycle carrier wave to generate three logic signals: Signal S1: When Vm1 > E, S1 = 1, otherwise S1 = 0; Signal P1: When Vm1 < Vtri2+, P1 = 1; otherwise, P1 = 0. Signal Q1: When Vm1 < Vtri1+, Q1 = 1, otherwise Q1 = 0.

[0030] The output state U1 of the first low-voltage unit H1 is directly determined by signal S1, i.e., U1 = S1. The output state U2 of the second low-voltage unit H2 is generated by a logical AND operation between signals P1 and Q1, i.e., U2 = P1·Q1. The values ​​of U1 and U2 can be 1, 0, or -1, corresponding to positive, zero, and negative output levels, respectively.

[0031] The switching signal of the high-voltage unit H3 is generated by fundamental frequency modulation, which is directly compared with the original modulation wave Vm and the stepped wave threshold ±2E: when Vm > 2E, H3 outputs +3E; when Vm < -2E, H3 outputs -3E; when -2E ≤ Vm ≤ 2E, H3 outputs 0. This unit operates at the fundamental frequency, with a low switching frequency and low switching loss.

[0032] During the negative half-cycle of the modulation wave, the corresponding logic combination rules are symmetrical to those of the positive half-cycle. The low-voltage unit modulation wave Vm1 is compared with the carrier in the negative half-cycle carrier layer, and the switching signals of each unit are generated through similar logic combination.

[0033] The upper and lower switches of the same bridge arm in each H-bridge unit adopt a complementary conduction mode, and an appropriate dead time is set to avoid shoot-through faults.

[0034] 3. Dual-mode capacitor voltage self-balancing principle Figure 2 This is a schematic diagram of the capacitor unit's operating mode. Taking the second low-voltage unit H2 as an example, the DC-side capacitor C of this unit provides voltage E. Based on the state of the output voltage U2 and the output current of H2... io The direction in which the capacitor is charged and discharged determines its state: When U2 = 1, switches S21 and S24 are turned on, and the capacitor is connected in series in the output circuit: If io < 0, current flows out from the positive terminal of the capacitor, and the capacitor charges; if io When the current is greater than 0, current flows into the positive terminal of the capacitor, and the capacitor discharges.

[0035] When U2 = -1, switches S22 and S23 are turned on, and the capacitor is connected in reverse series to the output circuit: if io > 0, current flowing out of the negative terminal of the capacitor is equivalent to charging the positive terminal, thus charging the capacitor; if io < 0, capacitor discharge.

[0036] When U2 = 0, the capacitor is bypassed and does not exchange energy with the output circuit, so the voltage remains unchanged.

[0037] To utilize the aforementioned charging and discharging characteristics to achieve automatic capacitor voltage balancing, this invention designs two operating modes. In Mode 1 and Mode 2, the output state of the high-voltage unit H3 remains completely identical, while the switching signals of the first low-voltage unit H1 and the second low-voltage unit H2 are exchanged. Figure 3 This is a schematic diagram illustrating the mode switching principle.

[0038] Define capacitor voltage difference Δuc = UcN - Uc ,in UcN This is the rated voltage of the capacitor. Uc This is the real-time voltage of the capacitor; When Δ uc When the value is > 0, it indicates that the actual voltage of the capacitor is lower than the rated voltage, and the capacitor needs to be charged. when Δuc When < 0, it indicates that the actual voltage of the capacitor is higher than the rated voltage, and the capacitor needs to be discharged. Define the inverter output current io The positive direction is: the current flowing out from the positive terminal of the AC side of the inverter is positive.

[0039] The mode switching rules are as follows: When the capacitor needs to be charged (Δ) uc When > 0): If the output current io > 0, switch to mode 2; if the output current io < 0, switch to mode 1; When the capacitor needs to discharge (Δ) uc When <0): If the output current is <0): io > 0, switch to mode 1; if the output current io <0, switch to mode 2.

[0040] Based on the above rules, regardless of the direction of the load current, the capacitor can be connected to the charging circuit when it needs to be charged and to the discharging circuit when it needs to be discharged, thereby achieving automatic voltage balancing across the entire modulation ratio range without the need for an additional closed-loop controller.

[0041] 4. Capacitor Parameter Design Figure 7 This is a voltage waveform diagram of the capacitor at different operating stages. Figure 7 (a) is the process by which the capacitor voltage rapidly builds up from zero to the rated value E when the system starts up. Figure 7 (b) is the capacitor voltage ripple waveform during steady-state operation. In steady state, the peak-to-peak value Vrpp of the capacitor voltage ripple occurs during the continuous discharge interval [t0, t3]. Figure 8 By analyzing the phase relationship between output voltage and current, and by examining the conduction angles θ1 to θ4 corresponding to each voltage level interval, the total charge during the discharge phase can be accurately calculated. Combined with the constraint of ripple limit Vrpp ≤ 10%E, the total discharge charge can be calculated through integration, leading to a unified design formula for the minimum required capacitance value, providing a theoretical basis for capacitor selection.

[0042] 5. Harmonic performance and simulation verification Using Matlab / S Im The U-Link simulation platform was used to verify this embodiment. The simulation parameters were set as follows: low-voltage DC source E = 50V, high-voltage DC source 3E = 150V, capacitor C = 4700μF, load resistance R = 25Ω, filter inductor L = 5.6mH, fundamental frequency fs = 50Hz, carrier frequency fc = 3000Hz.

[0043] Figure 10 The output voltage, current waveforms, and total harmonic distortion (THD) of the basic building block are shown in the graphs for different modulation ratios. As M increases from 0.6 to 0.9, the number of output levels increases from 7 to 11, the THD of the voltage improves from 18.36% to 13.06%, the current waveform maintains good sinusoidal characteristics, and the harmonics are mainly distributed near the carrier frequency.

[0044] Figure 9 The results are from dynamic performance simulation. Figure 9(a) Output voltage when the load changes from an inductive load (R = 50Ω, L = 5.6mH) to a purely resistive load (R = 50Ω, M = 0.9). uo Output current io The capacitor voltage uc waveform shows that the capacitor voltage remains stable even after a sudden change in load. Figure 9 (b) shows the dynamic response waveform when the modulation ratio M increases from 0.6 to 0.9. The output voltage, current and capacitor voltage can all respond quickly, which verifies the good dynamic performance of the method of the present invention.

[0045] 6. Experimental Verification An experimental platform based on basic building blocks was built for verification. The controller used an FPGA (Xilinx AX7010 series), the sampling module was AD7606, the current sensor was ACS712, and the voltage sensor was LV25P. The experimental parameters were set as follows: low-voltage DC source E = 24V, high-voltage DC source 3E = 72V, capacitor C = 4700μF, load resistance R = 25Ω, filter inductor L = 5.6mH, fundamental frequency fs = 50Hz, and carrier frequency fc = 3000Hz.

[0046] Figure 12 The experimental waveforms of output voltage and current under different modulation ratios are shown. When M = 0.6, the output level is 7; when M = 0.7 and 0.8, the output level is 9; and when M = 0.9, the output level is 11, verifying the effectiveness of the modulation strategy in controlling the number of output levels.

[0047] Figure 13 (a) is the dynamic establishment process of capacitor voltage. After startup, the capacitor voltage rises rapidly to 24V and remains stable. During this period, the output voltage u~o2~ of H2 unit increases smoothly, and the capacitor current i~c~ changes continuously. Figure 13 (b) is the steady-state operating waveform, with the capacitor voltage stable at 24V and the output current exhibiting a standard sine wave. Figure 13 (c) shows the independent output voltage waveforms of each unit (H1, H2, H3), all of which can stably output the desired voltage waveform.

[0048] Figure 14 A comparative analysis of the switching power loss of the low-voltage unit is presented. Compared with the traditional hybrid modulation strategy, the switching loss of the H1 unit (DC power supply) is lower under the strategy of this invention; although the switching loss of the H2 unit (capacitor power supply) is slightly increased, the total switching loss is lower than that of the traditional scheme within a certain modulation ratio range, thus balancing system efficiency and output waveform quality.

[0049] Example 2: Horizontally Extended Topology – 1:1:3:3 Quad-Unit Inverter To verify the horizontal scalability of this invention, the basic building block was extended to a structure containing four H-bridge units. For example... Figure 5 As shown, compared to the basic building block, a fourth unit H4 is added. This unit is a high-voltage unit, powered by a capacitor, with a rated voltage of 3E, the same as the voltage level of the H3 unit. This topology requires only two DC sources (E and 3E) and two capacitors to output a 17-level stepped waveform, reducing the number of DC sources by 50% compared to a traditional cascaded H-bridge inverter with the same output level.

[0050] Figure 6 (b) shows the unified modulation framework after horizontal expansion. In modulation mode 1, the switching states of H4 and H3 are complementary: when H3 outputs +3E, H4 outputs -3E or 0; when H3 outputs -3E, H4 outputs +3E or 0. In modulation mode 2, the switching signals of H4 and H3 are interchanged. This complementary design allows the two high-voltage capacitors to alternately charge and discharge during operation, achieving automatic voltage balancing without the need for additional control circuits.

[0051] When horizontally extended, the logic combination modulation strategy of low-voltage units H1 and H2 is exactly the same as in Example 1. Only the step wave comparison threshold and state lookup table of the high-voltage unit need to be updated, which fully reflects the uniformity and scalability of the modulation framework of the present invention.

[0052] Simulation results show that when the modulation ratio M = 0.9, the horizontal extended topology outputs a 17-level stepped wave, and the total harmonic distortion of the output voltage is reduced to 7.82%, which is significantly better than the basic building block.

[0053] Example 3: Vertically Extended Topology – 1:1:4 Three-Unit Inverter To verify the vertical scalability of this invention, the DC voltage of the high-voltage unit in the basic building block was increased from 3E to 4E, forming a 1:1:4 three-unit structure. For example... Figure 5 As shown, this topology requires only two DC sources (E and 4E) and one capacitor to output a 13-level stepped wave with an output voltage amplitude of up to 6E.

[0054] Figure 6 (c) shows the modulation frame after vertical expansion. The modulation rule of the high-voltage unit H3 is updated as follows: when Vm > 2E, the output is +4E; when Vm < -2E, the output is -4E; and the output is 0 in the remaining range. The logic combination modulation strategy and dual-mode capacitor voltage self-balancing mechanism of the low-voltage units H1 and H2 are completely consistent with those in Example 1; only the parameter n = 4 needs to be substituted into the control program.

[0055] Simulation results show that when the modulation ratio M = 0.9, the vertical extended topology outputs a 13-level stepped wave with a total harmonic distortion rate of 10.47%.

[0056] Example 4: Composite Extended Topology – 1:1:4:4 Quad-Unit Inverter Combining horizontal and vertical expansion paths, a composite expansion topology of 1:1:4:4 is formed. For example... Figure 5 As shown, this topology includes two low-voltage units (H1 is powered by DC source E, and H2 is powered by capacitor C1, both at voltage E) and two high-voltage units (H3 is powered by DC source 4E, and H4 is powered by capacitor C2, both at voltage 4E). This topology requires only two DC sources and two capacitors to output a 21-level stepped waveform.

[0057] In terms of modulation strategy, high-voltage units H4 and H3 inherit the horizontally extended complementary switching mode, while their voltage levels inherit the vertically extended parameterized modulation rule (n = 4). The logic combination modulation core of low-voltage units H1 and H2 is exactly the same as in Example 1.

[0058] Simulation results show that when the modulation ratio M = 0.9, the composite extended topology outputs a 21-level stepped wave, and the total harmonic distortion of the output voltage is further reduced to 6.19%, achieving optimal output performance.

[0059] Extending to general cases The unified modulation framework of this invention is applicable to any topology that is horizontally expanded from the basic building block to 1:1:3:...:3 (containing m high-voltage units), vertically expanded to 1:1:n (n≥2), or compositely expanded to 1:1:n:...:n (containing m high-voltage units, each with a voltage of nE). By processing the modulated wave through a parameterized recursive method, updating the state lookup table and the stepped wave comparison threshold, control of the new topology can be achieved by modifying only the parameters n and m, while the logic combination modulation core of the low-voltage unit and the dual-mode capacitor voltage self-balancing mechanism remain completely unchanged.

[0060] The structural and control details not described in this invention are not related to the design points and improvement directions of this invention, and can be implemented using existing technologies, so they will not be elaborated here.

[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A unified modulation and capacitor voltage self-balancing method applicable to scalable hybrid cascaded H-bridge multilevel inverters, applied to an inverter topology family constructed by expanding a basic building block, wherein the basic building block consists of a first low-voltage unit, a second low-voltage unit, and a high-voltage unit cascaded together, wherein the first low-voltage unit is powered by a DC source and has a rated voltage of E, the second low-voltage unit is powered by a capacitor instead of a DC source and has a rated voltage of E, and the high-voltage unit is powered by a DC source and its rated voltage is three times that of the low-voltage unit, characterized in that... Includes the following steps: Four triangular carriers are set up, which have the same frequency, equal amplitude, and consistent phase, and are divided into a positive half-cycle carrier layer and a negative half-cycle carrier layer in the vertical direction. During the positive half-cycle of the modulation wave, the modulation wave of the low-voltage unit is compared with the carrier in the positive half-cycle carrier layer, and a logic signal is generated based on the comparison result. The first PWM signal for controlling the switching transistors of the first and second low-voltage units is generated through logic combination. At the same time, the instantaneous value of the original sinusoidal modulation wave is compared with the 2E step wave threshold to generate the base frequency switching signal for controlling the switching transistors of the high-voltage unit. During the negative half-cycle of the modulation wave, the modulation wave of the low-voltage unit is compared with the carrier in the negative half-cycle carrier layer, and a logic signal is generated according to the comparison result. The second PWM signal controlling the switching transistors of the first low-voltage unit and the second low-voltage unit is generated through logic combination. During this period, the base frequency switching signal of the high-voltage unit maintains or switches the current state according to the comparison result between the instantaneous value of the modulation wave and the threshold of the stepped wave. The capacitor voltage of the second low-voltage unit is automatically balanced by switching between two operating modes. The difference between the two operating modes is that the switching signals of the first low-voltage unit and the second low-voltage unit are exchanged, while the base frequency switching signal of the high-voltage unit remains unchanged. The mode switching is based on the difference between the real-time capacitor voltage and the rated voltage and the direction of the output current. The specific switching rules for the two working modes are as follows: Define capacitor voltage difference Δuc = UcN - Uc ,in UcN This is the rated voltage of the capacitor. Uc The real-time voltage of the capacitor; when Δuc When > 0, the capacitor needs to be charged; when Δuc When < 0, the capacitor needs to be discharged; Define the inverter output current io The positive direction is: the current flowing out from the positive terminal of the AC side of the inverter is positive; When Δ uc > 0: If the output current io > 0, switch to mode 2; if the output current io < 0, switch to mode 1; When Δ uc When <0: If the output current io > 0, switch to mode 1; if the output current io < 0, switch to mode 2; When the inverter is expanded horizontally from the basic building block to a structure with one or more newly added high-voltage units cascaded, the newly added high-voltage units are powered by capacitors and their voltage levels are the same as those of the original high-voltage units in the basic building block. In mode 1, each newly added high-voltage unit corresponds one-to-one with an existing high-voltage unit, and their switching states are complementary. In mode 2, the base frequency switching signals of each pair of corresponding high-voltage units are exchanged to achieve automatic voltage balancing of all capacitor-powered high-voltage units.

2. The unified modulation and capacitor voltage self-balancing method according to claim 1, characterized in that, The modulation wave of the low-voltage unit is obtained by piecewise linear transformation of the original sinusoidal modulation wave. When the instantaneous value of the original modulation wave is greater than 2E, the modulation wave of the low-voltage unit is equal to the amplitude of the original modulation wave minus 3E; when the instantaneous value of the original modulation wave is less than or equal to -2E, the modulation wave of the low-voltage unit is equal to the amplitude of the original modulation wave plus 3E; when the instantaneous value of the original modulation wave is between -2E and 2E, the modulation wave of the low-voltage unit is equal to 0.

3. The unified modulation and capacitor voltage self-balancing method according to claim 1, characterized in that, When performing the horizontal expansion, only the stepped wave comparison threshold and state lookup table of the high-voltage unit need to be updated, while the logic combination modulation core of the low-voltage unit remains unchanged.

4. The unified modulation and capacitor voltage self-balancing method according to claim 1, characterized in that, When the inverter is expanded vertically from the basic building block, the number of units and the cascading order are exactly the same as the basic building block, except that the DC voltage of the high-voltage unit is increased to n times the voltage of the low-voltage unit, where n is an integer greater than or equal to 2; the base frequency switching signal generation rule of the high-voltage unit is updated to: when the original modulation wave is greater than 2E, the output is +nE; when the original modulation wave is less than -2E, the output is -nE; and when the original modulation wave is between -2E and 2E, the output is zero level; the logic combination modulation strategy and the dual-mode capacitor voltage self-balancing mechanism of the low-voltage unit remain unchanged.

5. The unified modulation and capacitor voltage self-balancing method according to claim 1, characterized in that, The unified modulation and capacitor voltage self-balancing method controls the entire topology family through parameterized recursion: the extended parameters include the high-voltage unit voltage multiple n and the horizontal extension level m. The original modulation wave is piecewise linearly transformed according to the extended parameters to obtain the low-voltage unit modulation wave. The low-voltage unit modulation wave is sent to the logic combination modulation module of the low-voltage unit to generate the low-voltage unit switching signal. The original modulation wave is sent to the stepped wave comparison module of the high-voltage unit to generate the high-voltage unit fundamental frequency switching signal. By updating the high-voltage unit voltage multiple n and the horizontal extension level m, switching signals suitable for different extended topologies can be generated.

6. The unified modulation and capacitor voltage self-balancing method according to claim 1, characterized in that, The method also includes a capacitor value determination step: by actively controlling the capacitor charging process through dual-mode switching, the peak value of the capacitor voltage ripple is completely determined by the longest continuous discharge interval within one output cycle. Combined with the engineering constraint that the peak value of the capacitor voltage ripple does not exceed 10% of the rated voltage, the total amount of capacitor discharge charge within the longest continuous discharge interval is calculated by integration. Based on the basic formula for capacitor charging and discharging, ΔQ=C·ΔU, the minimum capacitance value that meets the ripple requirement is determined.

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