An Adaptive Retiring Calibration All-Digital PLL Based on Overflow Detection

Abstract

This invention discloses an adaptive retiming calibration all-digital phase-locked loop (PLL) based on overflow detection, belonging to the field of integrated circuit technology. This invention utilizes the phase error overflow information output by the digital time converter to adaptively adjust the comparison threshold when the retiming compensation flag changes. This allows the retiming selector to correctly compensate for the inherent delay of the digital time converter, thereby eliminating resampling errors at the multi-mode divider output. This invention does not require interrupting the normal operation of the PLL and can significantly reduce in-band spurious emissions. This invention greatly reduces system design complexity and cost, giving it unique advantages in multi-band multi-protocol communication applications and high-performance radar applications.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to an adaptive retiming calibration all-digital phase-locked loop based on overflow detection. Specifically, it relates to an all-digital phase-locked loop architecture that can eliminate the resampling error problem of the multi-mode divider in the feedback path and significantly reduce in-band spurious emissions. Background Technology

[0002] As semiconductor technology advances to the nanoscale, the digitization of analog circuits has become a development trend. Against this backdrop, digital phase-locked loops (PLLs) have gradually become a research hotspot for on-chip integration due to their advantages in area, power consumption, and reliability. However, in fractional-division fully digital PLLs implemented using a digital time converter and a multi-mode divider, if the digital time converter used to compensate for the phase residual after integer division is placed before the multi-mode divider, a serious multi-mode divider resampling error problem will be introduced structurally. The underlying principle is as follows:

[0003] like Figure 1 As shown, for this all-digital phase-locked loop (PLL) structure, the output clock of the numerically controlled oscillator (CNC) is simultaneously fed into a digital time converter (DTC) and a multi-mode divider (MMD). The DTC phase-shifts the CNC oscillator clock, outputting a phase-shifted clock; the MMD divider divides the CNC oscillator output clock by an integer, outputting a divided clock. However, due to the inherent delay in the internal circuitry of the DTC caused by factors such as manufacturing process, voltage, and temperature, and the variable delay corresponding to the phase-shift control word, the sum of these two delays may exceed one CNC oscillator cycle. If the sum of the variable delay and inherent delay of the DTC is less than one CNC oscillator cycle, the ideal high-frequency phase-shifted clock for resampling arrives within one CNC oscillator cycle after the MMD divider completes its countdown, preventing sampling errors. If the sum of the variable delay and inherent delay of the DTC is greater than one CNC oscillator cycle, the ideal high-frequency phase-shifted clock for resampling arrives more than one CNC oscillator cycle after the MMD divider completes its countdown. Since the input signal of the multi-mode frequency divider is a phase-continuous signal, there is an additional sampling clock rising edge between the completion of the multi-mode frequency divider's countdown and the arrival of the ideal high-frequency phase-shifting clock rising edge used for resampling. For the circuit, this additional sampling clock rising edge is indistinguishable from the ideal sampling clock rising edge; it will only select the nearest arriving rising edge for sampling, resulting in incorrect sampling. In the case of incorrect sampling, there is a discrepancy between the actual phase and the ideal phase. The phase difference corresponds to a delay time of one numerically controlled oscillator cycle. This error often far exceeds the range of the phase comparator circuit, causing it to overflow and affecting the locking behavior of the all-digital phase-locked loop (PLL). Furthermore, since the control signal of the digital time converter often repeats within the cycle, the introduced phase error also exhibits repetitive characteristics within the cycle. This manifests as spurious noise in the output signal spectrum, worsening the spurious and phase noise performance of the all-digital PLL.

[0004] Current solutions include manually adjusting fixed delay values ​​and adding additional delay chains for front-end calibration. However, these methods are often sensitive to changes in process technology, voltage, temperature, and other factors, and require interrupting the normal operation of the fully digital phase-locked loop. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a fully digital phase-locked loop (PLL) with adaptive retiming calibration based on overflow detection. This PLL utilizes the phase error overflow information output by the phase comparator circuit as feedback to adaptively adjust the control word threshold of the digital time converter. This allows for the real-time generation of the correct retiming selection flag without external intervention or interruption of the PLL's normal operation, completely eliminating resampling errors in the clock feedback path.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A fully digital phase-locked loop (PLL) with adaptive retiming calibration based on overflow detection includes a phase comparator circuit, a digital loop filter, a digitally controlled oscillator (CNC), a digital time converter, and a multi-mode divider. These components are sequentially connected to form a closed loop. Frequency and phase synchronization are achieved through digital signal processing. The key feature is the addition of a retiming selector and a digital control module. The CNC oscillator output signal is modulated by the digital time converter to generate a phase-shifted clock, while the CNC oscillator output signal is simultaneously processed by the multi-mode divider to generate a divided clock based on the division ratio. The phase-shifting clock is used to resample the frequency-divided signal output by the multi-mode frequency divider; the digital control module is used to adaptively adjust the control word threshold of the digital time converter using the phase error overflow direction output by the phase comparison circuit, thereby generating the retiming compensation flag; the retiming selector is used to select a delayed clock, which is the output of the multi-mode frequency divider after synchronization and delayed by one or two numerically controlled oscillator cycles, as the feedback clock according to the retiming compensation flag; the feedback clock is compared with the reference clock in the phase comparison circuit, and the output result is used to adjust the frequency of the numerically controlled oscillator through a digital loop filter, thereby achieving phase locking in a closed loop.

[0008] Furthermore, the digital control module includes a frequency divider and phase shifter controller, an overflow detection module, a comparator, and an adaptive calibration module. The frequency control word is generated into a phase shifter control word after differential integral modulation and residual accumulation in the frequency divider and phase shifter controller. The overflow detection module is used to determine whether the phase error has reached positive or negative overflow at the rising edge of the retiming compensation flag. The adaptive calibration module is used to adjust the adaptive threshold according to the overflow direction. The adaptive calibration module outputs the adaptive threshold to the comparator for comparison with the phase shifter control word to update the retiming compensation flag.

[0009] Furthermore, the overflow detection module includes a rising edge detector, a phase error delay matching register, and an overflow detector. The rising edge detector consists of two flip-flops and is used to detect the moment when the retiming compensation flag jumps from 0 to 1 and outputs a single-cycle pulse. The phase error delay matching register is used to delay the current phase error by one and two cycles respectively to obtain the values ​​of the previous two cycles. When the single-cycle pulse is valid, the overflow detector is used to check whether the phase error of the current cycle and the previous two cycles is equal to a positive overflow value or a negative overflow value.

[0010] Furthermore, the adaptive calibration module includes a ramp counter and a clamping circuit. The ramp counter's initial value is set by an external preset initial value. Each clock cycle, if a positive overflow flag is valid, the counter increments by one; if a negative overflow flag is valid, the counter decrements by one; otherwise, it remains unchanged. The clamping circuit is used to limit the count value between a preset minimum value and a preset maximum value.

[0011] Furthermore, the retiming selector performs three-level synchronization on the frequency division clock in the phase-shifted clock domain, obtaining a first-level synchronization signal, a signal delayed by one beat, and a signal delayed by two beats, respectively. The signal delayed by one beat or delayed by two beats is selected as the feedback clock and sent to the phase comparison circuit.

[0012] Specifically, the all-digital phase-locked loop architecture of the present invention has the following beneficial effects:

[0013] This invention provides a novel all-digital phase-locked loop (PLL) scheme that adaptively eliminates resampling errors in multi-mode frequency dividers without external calibration. Utilizing the phase error overflow information output by the phase comparator circuit as the sole feedback, the calibration process runs entirely in the background, without interrupting the all-digital PLL locking, and can track environmental changes in real time. Compared to traditional fixed-delay compensation or interruptible calibration schemes, this invention significantly reduces system design complexity and cost, giving it unique advantages in multi-band, multi-protocol communication applications and high-performance radar applications. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a traditional all-digital phase-locked loop.

[0015] Figure 2 This is a structural diagram of the all-digital phase-locked loop architecture proposed in a specific embodiment of the present invention;

[0016] Figure 3 This is a structural diagram of the digital control module proposed in a specific embodiment of the present invention;

[0017] Figure 4 This is a timing diagram of a retiming selector proposed in a specific embodiment of the present invention;

[0018] Figure 5 This is a state transition diagram of a fully digital phase-locked loop proposed in a specific embodiment of the present invention;

[0019] Figure 6 The diagram shows the effect of the all-digital phase-locked loop retiming proposed in a specific embodiment of the present invention. Detailed Implementation

[0020] The structural diagram of the all-digital phase-locked loop architecture of this invention is shown below. Figure 2 As shown, it includes a phase comparator circuit, a digital loop filter, a numerically controlled oscillator (CNC), a digital time converter, a multi-mode frequency divider, a retiming selector, and a digital control module. The CNC oscillator output signal is phase-shifted by the digital time converter with reference to a phase-shift control word, outputting a phase-shifted clock. Simultaneously, the CNC oscillator output signal enters the multi-mode frequency divider, generating a divided clock based on the division ratio. The retiming selector performs three-level synchronization on the divided clock in the phase-shifted clock domain, obtaining a first-level synchronization signal, a signal delayed by one beat, and a signal delayed by two beats. The digital control module adaptively adjusts the digital time converter control word threshold using the phase error overflow direction output by the phase comparator circuit, thereby generating the retiming compensation flag and achieving adaptive selection of the retiming path. The retiming selector selects either a signal delayed by one beat or two beats as the feedback clock based on the retiming compensation flag and sends it to the phase comparator circuit. The phase comparator circuit simultaneously receives the reference clock and outputs the phase error. The phase error is filtered by the digital loop filter to generate an oscillator frequency control word, which is then sent to the digital control module to output the retiming compensation flag. Phase locking is achieved through a closed loop.

[0021] The digital control module includes a frequency division and phase shift controller, an adaptive calibration module, a comparator, and an overflow detection module, such as... Figure 3As shown. The frequency control word is generated by differential-integral modulation and residual accumulation in the frequency divider and phase shifter controller. The frequency divider and phase shifter controller internally implements comparison logic: when adaptive calibration is enabled, if the phase shifter control word is greater than the adaptive threshold, the retiming compensation flag is 1; otherwise, it is 0. The retiming compensation flag, after synchronization, controls the retiming selector: when the flag is 1, a path with a two-step delay is selected; when the flag is 0, a path with a one-step delay is selected. The overflow detection module determines whether the phase error has reached positive or negative overflow at the rising edge of the retiming compensation flag. The adaptive calibration module adjusts the adaptive threshold according to the overflow direction and outputs the adaptive threshold to the comparator. The comparator compares the phase shifter control word with the adaptive threshold to update the retiming compensation flag. During the retiming calibration process of the digital control module, the overflow detection module includes a rising edge detector, a phase error delay matching register, and an overflow detector. The rising edge detector consists of two flip-flops that detect the moment when the retiming compensation flag jumps from 0 to 1 and outputs a single-cycle pulse. Phase error delay matching delays the current phase error by one and two clock cycles respectively, obtaining the values ​​of the previous two cycles. When the single-cycle pulse is valid, the overflow detector checks whether the phase error of the current cycle and the previous two cycles equals a positive or negative overflow value. If a positive overflow exists, a positive overflow flag is output; if a negative overflow exists, a negative overflow flag is output. The adaptive calibration module includes a ramp counter and a clamping circuit. The ramp counter's initial value is set by an external preset value. Each clock cycle, it increments by one if the positive overflow flag is valid, decrements by one if the negative overflow flag is valid, and remains unchanged otherwise. The clamping circuit limits the count value to a preset minimum and maximum value. When the calibration enable signal is invalid, the calibration module directly outputs the preset initial value; otherwise, it outputs the clamped count value as the adaptive threshold. The overflow direction of the phase error output by the phase comparison circuit determines the direction of the adaptive threshold's increase or decrease, with positive overflow corresponding to an increase in the threshold and negative overflow corresponding to a decrease. The adaptive threshold is compared with the current phase shift control word to generate a retiming compensation flag. This flag is used to select the retiming path, thus eliminating resampling errors in the multi-mode divider.

[0022] This invention utilizes a digital control module based on overflow detection to adaptively adjust the comparison threshold, enabling the retiming selector to correctly compensate for the inherent delay of the digital time converter, thereby eliminating errors during resampling of the multi-mode divider output. The phase error overflow direction output from the phase comparator circuit is used as a feedback signal. The phase error is a signed number, with positive and negative overflow values ​​corresponding to the maximum range of the phase comparator circuit. When a retiming selection error occurs, the phase error quickly overflows, and the overflow direction indicates whether the adaptive threshold needs to be increased or decreased. This invention only needs to check for phase error overflow at each rising edge of the retiming compensation flag and adjust the threshold register according to the overflow direction. After several convergence steps, the retiming compensation flag accurately reflects whether an additional delay of one beat is needed, thus eliminating resampling errors in the multi-mode divider.

[0023] The timing sequence of the retiming selector of the present invention is as follows: Figure 4 As shown in the diagram, (a) represents the retiming timing of a multi-mode divider without retiming errors, where the sum of the variable delay and inherent delay corresponding to the phase-shift control word is less than one oscillator cycle; (b) represents the retiming timing of a multi-mode divider with retiming errors and after correction. When the sum of the variable delay and inherent delay corresponding to the phase-shift control word exceeds one oscillator cycle, an additional sampling clock rising edge exists between the completion of the multi-mode divider's countdown and the arrival of the ideal high-frequency phase-shift clock rising edge for resampling. For the circuit, this additional sampling clock rising edge is indistinguishable from the ideal sampling clock rising edge, and it will only select the nearest rising edge for sampling, resulting in incorrect sampling. In the case of incorrect sampling, there is a gap between the actual phase and the ideal phase. The phase difference corresponds to a delay time of one numerically controlled oscillator cycle. After correction, the multi-mode divider delays sampling by one cycle, effectively compensating for this. The phase difference. Due to the inherent delay of the digital time converter, when the sum of the variable delay corresponding to the phase shift control word and the inherent delay exceeds one oscillator cycle, the retiming compensation flag should be 1 to select a feedback clock delayed by two beats. The initial threshold may deviate from the optimal value. If the threshold is too high, it will cause positive overflow, and the adaptive calibration module will gradually lower the threshold; if the threshold is too low, it will cause negative overflow, and the adaptive calibration module will gradually raise the threshold. After several adjustments, the threshold converges to the optimal value, the phase error no longer overflows frequently, and the resampling error of the multi-mode divider is completely eliminated. When the process, voltage, and temperature change, the calibration module will continuously detect overflow events and fine-tune the threshold to achieve adaptive tracking.

[0024] The all-digital phase-locked loop of this invention includes five states: reset state, automatic frequency calibration state, coarse adjustment locking state, fine adjustment locking state, and ready state. For example... Figure 5As shown, after power-on in the reset state, it enters the automatic frequency calibration state after a fixed wait, executing a binary search algorithm to coarsely adjust the oscillator frequency. After calibration, it enters the coarse-adjustment locking state, which lasts for a configurable fixed time, or the coarse lock is determined by the average value output by the phase comparison circuit. During this time, the loop does not undergo retiming calibration. Afterward, the loop enters the fine-adjustment locking state, switching to fine-tuning coefficients, and the loop undergoes retiming calibration. The fine-adjustment locking state ends in two modes: a forced mode relying solely on a fixed-time counter timeout, or by enabling the lock detection circuit, outputting a lock signal when the absolute value of the phase error is continuously less than the lock threshold a specified number of times. The effect of the adaptive retiming calibration all-digital phase-locked loop based on overflow detection proposed in this invention is as follows: Figure 6 As shown in the diagram. (a) represents the behavior of the phase comparator output of the all-digital phase-locked loop (PLL) after adaptive retiming calibration. Without retiming calibration, within the expected locking range of the PLL, due to the inherent phase of the digital time converter, the output signal phase of the multi-mode divider experiences periodic abrupt changes after retiming. Since this phase disturbance exceeds the range of the digital time converter, the digital time converter output code overflows. When the PLL follows the phase abrupt change and relocks, the sum of the digital time converter output phase delay and the inherent phase is again less than... At this point, for the fully digital phase-locked loop after re-locking, an equivalent phase shift with opposite phase and the same amplitude is introduced, causing the time-to-digital converter output to overflow in reverse phase. This type of phase shift disturbance repeats, and its repetition period is related to the fractional division ratio. After re-timing calibration convergence and loop locking, the absolute value of the phase comparator output of the fully digital phase-locked loop remains within a relatively small range, which is equivalent to the reference clock and the output division clock being phase aligned, the re-timing error being calibrated, and there is no phase shift; (b) is the simulation result of the phase noise of the output clock without re-timing calibration. Due to the periodic repetitive overflow phenomenon of the time-to-digital converter output code, spurious signals appear in the phase noise spectrum of the output signal. Furthermore, because the output code disturbance is large, the corresponding numerically controlled oscillator frequency control signal disturbance is large, and a large amplitude periodic modulation signal is loaded on the phase of the equivalent output signal, resulting in extremely high spurious signals in the final phase noise spectrum, which seriously deteriorates the phase noise and spurious performance; (c) is the result after re-timing calibration convergence and loop locking, where it can be seen that the spurious signals introduced by the re-timing error are eliminated. Compared to traditional architectures with no calibration or fixed delay compensation, the multi-mode divider of this invention completely eliminates resampling errors and does not introduce additional spurious signals. The adaptive calibration technique of this invention requires very few digital gate circuits, and the calibration process runs in the background, without affecting the normal locking of the phase-locked loop, thus saving system hardware resources and time.

[0025] The above detailed implementation examples describe the all-digital phase-locked loop architecture based on overflow detection for adaptive retiming calibration of the present invention. Researchers and those skilled in the art can make non-substantial changes in form or content based on the above steps without departing from the scope of the present invention. Therefore, the present invention is not limited to the content disclosed in the above embodiments, and the scope of protection of the present invention should be determined by the claims.

Claims

1. A fully digital phase-locked loop (PLL) with adaptive retiming calibration based on overflow detection, comprising a phase comparator circuit, a digital loop filter, a digitally controlled oscillator, a digital time converter, and a multi-mode frequency divider, wherein the above devices are connected in sequence to form a closed loop, and frequency and phase synchronization is achieved through digital signal processing, characterized in that... A retiming selector and a digital control module are added, wherein: the output signal of the numerically controlled oscillator is modulated by a digital time converter to generate a phase-shifted clock; simultaneously, the output signal of the numerically controlled oscillator is processed by a multi-mode frequency divider to generate a divided clock according to the division ratio; the phase-shifted clock is used to resample the divided signal output by the multi-mode frequency divider; the digital control module is used to adaptively adjust the control word threshold of the digital time converter using the phase error overflow direction output by the phase comparison circuit, thereby generating the retiming compensation flag; the retiming selector is used to select, according to the retiming compensation flag, a delayed clock output by the multi-mode frequency divider that has been synchronized and delayed by one or two numerically controlled oscillator cycles as the feedback clock; the feedback clock is compared with the reference clock in the phase comparison circuit, and the output result is processed by a digital loop filter to adjust the frequency of the numerically controlled oscillator, achieving phase locking through a closed loop.

2. The all-digital phase-locked loop with adaptive retiming calibration based on overflow detection as described in claim 1, characterized in that, The digital control module includes a frequency divider and phase shifter controller, an overflow detection module, a comparator, and an adaptive calibration module. The frequency control word is generated into a phase shifter control word after differential integral modulation and residual accumulation in the frequency divider and phase shifter controller. The overflow detection module is used to determine whether the phase error has reached positive or negative overflow at the rising edge of the retiming compensation flag. The adaptive calibration module is used to adjust the adaptive threshold according to the overflow direction. The adaptive calibration module outputs the adaptive threshold to the comparator, which is used to compare with the phase shifter control word to update the retiming compensation flag.

3. The all-digital phase-locked loop with adaptive retiming calibration based on overflow detection as described in claim 2, characterized in that, The overflow detection module includes a rising edge detector, a phase error delay matching register, and an overflow detector. The rising edge detector consists of two flip-flops and is used to detect the moment when the retiming compensation flag jumps from 0 to 1 and outputs a single-cycle pulse. The phase error delay matching register is used to delay the current phase error by one and two cycles respectively to obtain the values ​​of the previous two cycles. When the single-cycle pulse is valid, the overflow detector is used to check whether the phase error of the current cycle and the previous two cycles is equal to a positive overflow value or a negative overflow value.

4. The all-digital phase-locked loop with adaptive retiming calibration based on overflow detection as described in claim 2, characterized in that, The adaptive calibration module includes a ramp counter and a clamping circuit. The ramp counter's initial value is set by an external preset initial value. It increments by one if a positive overflow flag is valid and decrements by one if a negative overflow flag is valid in each clock cycle; otherwise, it remains unchanged. The clamping circuit is used to limit the count value between a preset minimum value and a preset maximum value.

5. The all-digital phase-locked loop with adaptive retiming calibration based on overflow detection as described in claim 1, characterized in that, The retiming selector performs three-level synchronization on the frequency division clock in the phase-shifted clock domain, obtaining a first-level synchronization signal, a signal delayed by one beat, and a signal delayed by two beats respectively. The signal delayed by one beat or delayed by two beats is selected as the feedback clock and sent to the phase comparison circuit.

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