A communication method and apparatus

Abstract

This application provides a communication method and apparatus for improving LDPC encoding and decoding performance. The method includes processing a first region of a first LDPC matrix according to a first rule related to a first code rate or related to a first code length and the length of the information bits, encoding the information bits according to the matrix obtained after processing the first LDPC matrix (i.e., a second LDPC matrix), and transmitting the encoded result to obtain a codeword bit sequence. In this application, the first region includes a first set of columns of the first LDPC matrix, wherein the first set of columns consists of columns with column indices from 0 to X-1, or the first set of columns consists of the X columns with the largest column weight in the first LDPC matrix, or the first set of columns consists of the X columns corresponding to bits in the first LDPC matrix that participate in encoding, do not enter the circular buffer, and are not transmitted, where X is an integer less than or equal to the total number of columns in the first LDPC matrix.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication method and apparatus. Background Technology

[0002] Low-density parity-check (LDPC) codes are channel coding schemes that closely approximate the Shannon limit, offering advantages such as high performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the coding and decoding scheme for data channels in 5G communication. Mainstream LDPC codes employ a quasi-cyclic (QC) structure, which avoids poor structures such as short cycles and improves code distance by adjusting the shift of each block.

[0003] LDPC codes can be represented using a basis matrix. In practical LDPC encoding or decoding, a complete parity-check matrix can be obtained from the basis matrix, and encoding or decoding can then be performed based on this matrix. Currently, improving the performance of LDPC encoding and decoding is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a communication method and apparatus for improving LDPC encoding and decoding performance.

[0005] Firstly, embodiments of this application provide a communication method, which can be executed by a first communication device or a first equipment, or in other words, the method can be applied to a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to the first equipment itself, a component within the first equipment, or a logic module or software capable of implementing all or part of the first equipment. The first equipment can be a transmitting device and / or an encoding device. Specifically, the first equipment can be a terminal or a network device such as a base station. The components in this application may include, for example, at least one of a chip, a chip system, a processor, a transceiver, a processing unit, a transceiver unit, or other functional modules. Taking the first equipment as the executing entity as an example, the method includes: processing a first region of a first LDPC matrix according to a first rule, and encoding information bits according to the matrix obtained after processing the first LDPC matrix (i.e., a second LDPC matrix). A codeword bit sequence is obtained by transmitting the encoded data.

[0006] The first rule is related to the first code rate, or the first rule is related to the following parameters: the first code length and the length of the information bits; the first region includes the first set of columns of the first LDPC matrix, wherein the first set of columns is the column index of the first LDPC matrix from 0 to X-1, or the first set of columns is the X column with the largest column weight in the first LDPC matrix, or the first set of columns is the X column corresponding to the bits in the first LDPC matrix that participate in encoding, do not enter the circular buffer, and are not transmitted, where X is a positive integer less than or equal to the total number of columns of the first LDPC matrix.

[0007] Since the position of the punctured bits has a significant impact on encoding and decoding in low-complexity scenarios, this application improves the rationality of the LDPC matrix under different bitrates by modifying the punctured columns (i.e., the first column set mentioned above) of the LDPC matrix according to the bitrate. This results in better encoding performance under different bitrates and can bring significant gains to encoding and decoding performance.

[0008] Secondly, embodiments of this application provide a communication method, which can be executed by a second communication device or a second equipment, or in other words, the method can be applied to a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to the second equipment itself, a component within the second equipment, or a logic module or software capable of implementing all or part of the second equipment. The second equipment can be a receiving device and / or a decoding device. Specifically, the second equipment can be a terminal or a network device such as a base station. The components in this application may include, for example, at least one of a chip, a chip system, a processor, a transceiver, a processing unit, a transceiver unit, or other functional modules. Taking the second communication device as the executing entity as an example, the method includes: receiving first information, processing a first region of a first LDPC matrix according to a first rule, and decoding the received first information according to the matrix obtained after processing the first LDPC matrix (i.e., a second LDPC matrix).

[0009] The first rule is related to the first code rate, or the first rule is related to the following parameters: the first code length and the length of the information bits; the first region includes the first set of columns of the first LDPC matrix, wherein the first set of columns is the column index of the first LDPC matrix from 0 to X-1, or the first set of columns is the X column with the largest column weight in the first LDPC matrix, or the first set of columns is the X column corresponding to the bits in the first LDPC matrix that participate in encoding, do not enter the circular buffer, and are not transmitted, where X is a positive integer less than or equal to the total number of columns of the first LDPC matrix.

[0010] Since the position of the punctured bits has a significant impact on encoding and decoding in low-complexity scenarios, this application improves the rationality of the LDPC matrix under different bitrates by modifying the punctured columns (i.e., the first column set mentioned above) of the LDPC matrix according to the bitrate. This results in better encoding performance under different bitrates and can bring significant gains to encoding and decoding performance.

[0011] Regarding the first and second aspects mentioned above, the following design is proposed:

[0012] In one possible design, the first region of the first LDPC matrix is ​​processed according to a first rule, including modifying the positions and / or shift values ​​of 0 / 1 bits in the first region according to the first rule. This design can improve the rationality of the punctured bit positions at the current coding rate, thereby improving coding and decoding performance.

[0013] In one possible design, the positions and / or shift values ​​of 0 / 1 bits in the first region are modified according to a first rule, including: determining the row index i based on a first code rate, where i is a non-negative integer less than the total number of rows in the first LDPC matrix; and modifying the positions and / or shift values ​​of 0 / 1 bits in the row with row index i in the first region according to the first rule. This design can improve the rationality of the punctured bit positions under the current coding code rate, thereby improving coding and decoding performance.

[0014] In one possible design, determining the row index i based on the first bitrate includes: determining the row index i based on the bitrate range in which the first bitrate falls. This design helps reduce implementation complexity.

[0015] In one possible design, if the first bitrate is within the bitrate range Then the row index i is row-1, where a is the column number of the information column in the first LDPC matrix. This design improves encoding and decoding performance.

[0016] In one possible design, the positions and / or shift values ​​of 0 / 1 in the first region are modified according to a first rule, including: determining the row index i based on the first code length and the length of the information bits, where i is a non-negative integer less than the total number of rows in the first LDPC matrix; and modifying the positions and / or shift values ​​of 0 / 1 in the row with row index i in the first region according to the first rule. This design is beneficial for improving encoding and decoding performance.

[0017] In one possible design, row index i satisfies the following formula:

[0018]

[0019] Here, ceil() is the floor function, Zc is the smallest lift value in the set of lift values ​​that satisfy a*Zc≥K, a is the number of information columns in the first LDCP matrix, K is the length of the information bits, and N is the first code length. This design improves encoding and decoding performance.

[0020] In one possible design, the first rule includes: replacing the row with index i in the first LDPC matrix with the row with index i in the third matrix; wherein the third matrix has the same size as the first LDPC matrix, the positions and / or translation values ​​of 0 / 1 in the second region of the third matrix are different from those in the first region, the positions and translation values ​​of 0 / 1 in the third region of the third matrix are the same as those in the fourth region of the first LDPC matrix, the relative position of the second region in the third matrix is ​​the same as the relative position of the first region in the first LDPC matrix, the third region is the complement of the second region, and the fourth region is the complement of the first region. This design helps reduce implementation complexity.

[0021] In one possible design, the row with row index i in the first LDPC matrix is ​​replaced with the row with row index i in the third matrix. This includes: if the row with row index i does not belong to the first row set, then the row with row index i in the first LDPC matrix is ​​replaced with the row with row index i in the third matrix, where the first row set includes at least one row of the first LDPC matrix. This design is beneficial for improving encoding and decoding performance.

[0022] In one possible design, the first LDPC matrix is ​​BG1 of 5G, and the first row set includes at least one of the following rows: the row with row index 6 in the first LDPC matrix, or the row with row index 10 in the first LDPC matrix. This design is beneficial for improving encoding and decoding performance.

[0023] In one possible design, the positions of 1 in the third matrix include:

[0024] The row index is 0, and the column indexes are 0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, 23;

[0025] The row index is 1, and the column indexes are 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, 24;

[0026] The row index is 2, and the column indexes are 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0027] The row index is 3, and the column indexes are 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, 25;

[0028] The row index is 4, and the column indexes are 1 and 26.

[0029] The row index is 5, and the column indexes are 1, 3, 12, 16, 21, 22, and 27.

[0030] The row index is 6, and the column indexes are 0, 6, 10, 11, 13, 17, 18, 20, and 28.

[0031] The row index is 7, and the column indexes are 1, 4, 7, 8, 14, and 29.

[0032] The row index is 8, and the column indexes are 1, 3, 12, 16, 19, 21, 22, 24, and 30.

[0033] The row index is 9, and the column indexes are 1, 10, 11, 13, 17, 18, 20, and 31.

[0034] The row index is 10, and the column indexes are 1, 2, 4, 7, 8, 14, and 32.

[0035] The row index is 11, and the column indexes are 0, 12, 16, 21, 22, 23, and 33.

[0036] The row index is 12, and the column indexes are 1, 10, 11, 13, 18, and 34.

[0037] The row index is 13, and the column indexes are 0, 3, 7, 20, 23, and 35.

[0038] The row index is 14, and the column indexes are 0, 12, 15, 16, 17, 21, and 36.

[0039] The row index is 15, and the column indexes are 1, 10, 13, 18, 25, and 37.

[0040] In one possible design, the first rule includes deleting at least one 0 / 1 position from the row with row index i in the first region. This design improves encoding and decoding performance.

[0041] In one possible design, the first rule includes adding one or more 1 positions to the second row set of the first LDPC matrix. This design improves encoding and decoding performance.

[0042] In one possible design, the second row set includes the row with row index 4 and / or the row with row index 5 in the first LDPC matrix.

[0043] In one possible design, the first region is the region consisting of all rows of the first column set and the first LDPC matrix; or, the first region is the region consisting of the first column set and the row corresponding to the first code rate in the first LDPC matrix.

[0044] In one possible design, the row index (row) of the row corresponding to the first bit rate R satisfies the following formula:

[0045]

[0046] Where a is the number of information columns in the first LDPC matrix, and X is the number of columns included in the first column set.

[0047] In one possible design, the row index (row) of the row corresponding to the first bit rate R satisfies the following formula:

[0048]

[0049] Where Zc is the smallest lift value in the set of lift values ​​that satisfy a*Zc≥K, a is the number of columns of the information column of the first LDPC matrix, K is the length of the information bits, and N is the first code length.

[0050] Thirdly, a communication device is provided. The device can implement the method described in any possible implementation of any of the first or second aspects described above. The device possesses the functions of the first or second communication device described above. The device is, for example, a terminal device, a functional module within a terminal device, a network device, or a functional module within a network device, etc.

[0051] In one optional implementation, the device may include modules corresponding one-to-one with the methods / operations / steps / actions performed in any possible implementation of any of the first to second aspects. These modules may be hardware circuits, software, or a combination of hardware circuits and software. In another optional implementation, the device includes a processing unit (sometimes also called a processing module) and a communication unit (sometimes also called a transceiver module or communication module, etc.). The transceiver unit is capable of both sending and receiving functions. When the transceiver unit performs the sending function, it may be called a sending unit (sometimes also called a sending module); when the transceiver unit performs the receiving function, it may be called a receiving unit (sometimes also called a receiving module). The sending unit and the receiving unit may be the same functional module, referred to as the transceiver unit, which performs both sending and receiving functions; or, the sending unit and the receiving unit may be different functional modules, with the transceiver unit being a collective term for these functional modules.

[0052] For example, when the apparatus is used to perform the method described in any one of the first to second aspects, the apparatus may include a communication unit and a processing unit.

[0053] Fourthly, embodiments of this application also provide a communication device, including a processor for executing a computer program (or computer-executable instructions) stored in a memory, such that when the computer program (or computer-executable instructions) is executed, the device performs the method as described in any possible implementation of any of the first to second aspects.

[0054] In one possible implementation, the processor and memory are integrated together;

[0055] In another possible implementation, the memory is located outside the communication device.

[0056] The communication device also includes a communication interface for communicating with other devices, such as sending or receiving data and / or signals. For example, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0057] Fifthly, a computer-readable storage medium is provided for storing a computer program or instructions that, when executed, enable the implementation of the method described in any possible implementation of any of the first to second aspects, and the method shown in any possible implementation of the first aspect.

[0058] A sixth aspect provides a computer program product containing instructions that, when run on a computer, enables the method described in any possible implementation of any of the first to second aspects to be implemented.

[0059] In a seventh aspect, embodiments of this application also provide a communication device for performing the method described in any possible implementation of any of the first to second aspects described above.

[0060] Eighthly, a chip system is provided, comprising logic circuitry (or, as understood, a processor, which may include logic circuitry, etc.), and further comprising input / output interfaces. The input / output interfaces can be used to input messages or to output messages. The input / output interfaces can be the same interface, i.e., the same interface can implement both sending and receiving functions; or, the input / output interface includes an input interface and an output interface, the input interface being used to implement the receiving function, i.e., to receive messages; and the output interface being used to implement the sending function, i.e., to send messages. The logic circuitry can be used to perform operations other than the sending and receiving functions in any possible implementation of any of the first to second aspects described above; the logic circuitry can also be used to transmit messages to the input / output interfaces or to receive messages from other communication devices from the input / output interfaces. The chip system can be used to implement the methods described in any possible implementation of any of the first to second aspects described above. The chip system can be composed of chips or can include chips and other discrete devices.

[0061] Optionally, the chip system may also include a memory, which can be used to store instructions, and the logic circuits can call the instructions stored in the memory to implement the corresponding functions.

[0062] Ninth aspect, a communication method is provided, which may include the method implemented by a first communication device as shown in the first aspect and any possible implementation thereof, and the method implemented by a second communication device as shown in the second aspect and any possible implementation thereof.

[0063] A tenth aspect provides a communication system that may include a first communication device and a second communication device. The first communication device may be used to implement the method shown in the first aspect and any possible implementation thereof, and the second communication device may be used to implement the method shown in the second aspect and any possible implementation thereof.

[0064] The technical effects brought about by the third to tenth aspects above can be found in the descriptions of the beneficial effects of the corresponding solutions in the first and second aspects above, and will not be repeated here. Attached Figure Description

[0065] Figure 1(a) is an architecture diagram of a communication system used in an embodiment of this application;

[0066] Figure 1(b) is a schematic diagram of a network device in an embodiment of this application;

[0067] Figure 2 This is a schematic diagram of a 4×4 cyclic shift matrix in an embodiment of this application;

[0068] Figure 3This is an example diagram of a basis matrix in an embodiment of this application;

[0069] Figure 4 This is a schematic diagram of a verification matrix in an embodiment of this application;

[0070] Figure 5 This is a schematic diagram of a base matrix structure in an embodiment of this application;

[0071] Figure 6 This is a schematic diagram of a matrix region corresponding to different code rates in an embodiment of this application;

[0072] Figure 7 This is a schematic diagram illustrating one bit rate and system capacity in an embodiment of this application;

[0073] Figure 8 This is a flowchart illustrating a communication method according to an embodiment of this application;

[0074] Figure 9 This is a schematic diagram of the structure of a communication device according to an embodiment of this application;

[0075] Figure 10 This is a schematic diagram of the structure of a communication device according to an embodiment of this application. Detailed Implementation

[0076] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0077] Figure 1(a) is a schematic diagram of the architecture of the communication system applied in an embodiment of this application. The communication system 1000 shown in Figure 1(a) includes a wireless access network 100 and a core network 200. Optionally, the communication system 1000 also includes an Internet 300. The wireless access network 100 may include at least one network device (110a and 110b in Figure 1(a)) and at least one terminal device (120a-120j in Figure 1(a)). The terminal device is wirelessly connected to the network device, and the network device is wirelessly or wiredly connected to the core network. The core network device and the network device may be independent physical devices, or the functions of the core network device and the logical functions of the network device may be integrated on the same physical device, or a single physical device may integrate some of the functions of the core network device and some of the functions of the network device. Terminal devices and network devices may be interconnected via wired or wireless means. Figure 1(a) is just a schematic diagram. The communication system may also include other network devices, such as wireless relay devices and wireless backhaul devices, which are not shown in Figure 1(a).

[0078] Network equipment is an access device that enables terminal devices to access a communication system via wired or wireless means. Network equipment can be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a next-generation base station in a 6G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system; it can also be a module or unit that performs some of the functions of a base station, such as a central unit (CU), a distributed unit (DU), or a radio unit (RU). Network equipment can be a macro base station (110a in Figure 1(a)), a micro base station or an indoor station (110b in Figure 1(a)), a relay node, or a donor node, etc. The embodiments of this application do not limit the specific technology or specific equipment form used in the network equipment.

[0079] A terminal device is a device with wireless transceiver capabilities, capable of sending signals to or receiving signals from network devices. Terminal devices include, but are not limited to, terminal equipment, user equipment (UE), mobile stations, and mobile terminals. Terminal devices can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, and smart cities. Specifically, a terminal device can be a mobile phone, tablet computer, computer with wireless transceiver capabilities, wearable device, vehicle, aircraft, ship, robot, robotic arm, smart home device, etc. The embodiments of this application do not limit the specific technologies or device forms used in the terminal devices.

[0080] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can be deployed on aircraft, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0081] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1(a) can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 through 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device. That is, 110a and 120i communicate through a wireless air interface protocol. Of course, 110a and 120i can also communicate through a network device-to-network device interface protocol. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1(a) can be called communication devices with network device functions, and 120a-120j in Figure 1(a) can be called communication devices with terminal device functions.

[0082] Communication between network devices and terminal devices, between network devices, and between terminal devices can be conducted using licensed spectrum, unlicensed spectrum, or both simultaneously. Communication can be conducted using spectrum below 6 GHz, spectrum above 6 GHz, or both simultaneously. The embodiments of this application do not limit the spectrum resources used for wireless communication.

[0083] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes network device functions. This control subsystem, including network device functions, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. Similarly, the functions of the terminal device can be executed by modules (such as chips or modems) within the terminal device, or by a device that includes terminal device functions.

[0084] Figure 1(b) shows a schematic diagram of a network device. As shown in Figure 1(b), the network device includes at least one of the following: one or more CUs, one or more DUs, and one or more RUs. For clarity, only one CU, DU, and RU are shown in Figure 1(b). The CU is used to connect to the core network and one or more DUs. Optionally, the CU may have some of the core network's functions. The CU may include a CU-control plane (CP) and a CU-user plane (UP).

[0085] The CU and DU can be configured according to the protocol layer functions of the wireless network they implement: for example, the CU can be configured to implement the functions of the Packet Data Convergence Protocol (PDCP) layer and above (such as the Radio Resource Control (RRC) layer and / or the Service Data Adaptation Protocol (SDAP) layer); the DU can be configured to implement the functions of the protocol layers below the PDCP layer (such as the Radio Link Control (RLC) layer, the Medium Access Control (MAC) layer, and / or the Physical (PHY) layer). Alternatively, the CU can be configured to implement the functions of the protocol layers above the PDCP layer (such as the RRC and / or SDAP layers), and the DU can be configured to implement the functions of the protocol layers below the PDCP layer (such as the RLC, MAC, and / or PHY layers).

[0086] The above CU and DU configurations are merely examples; the functions of the CU and DU can be configured as needed. For instance, the CU or DU can be configured to have more protocol layer functions, or only some protocol layer processing functions. For example, some RLC layer functions and protocol layer functions above the RLC layer can be placed in the CU, while the remaining RLC layer functions and protocol layer functions below the RLC layer can be placed in the DU. Furthermore, the functions of the CU or DU can be divided according to service type or other system requirements, such as by latency. Functions that require low latency can be placed in the DU, while functions that do not require low latency can be placed in the CU.

[0087] DU and RU can cooperate to implement the functions of the PHY layer. A DU can be connected to one or more RUs. The functions of DU and RU can be configured in various ways depending on the design. For example, a DU can be configured to implement baseband functions, and an RU can be configured to implement mid-RF functions. Another example is that a DU can be configured to implement higher-level functions in the PHY layer, and an RU can be configured to implement lower-level functions in the PHY layer, or to implement both lower-level and RF functions. Higher-level functions in the physical layer can include a portion of the physical layer's functions that are closer to the MAC layer, while lower-level functions in the physical layer can include another portion of the physical layer's functions that are closer to the mid-RF side.

[0088] The CU and DU can be separate entities or included in the same network element, such as a baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN) system, CU can also be called O-CU (open CU), DU can be called O-DU, and RU can be called O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU units in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0089] To facilitate understanding of the content of this application, the nouns or terms involved in the embodiments of this application will be explained below.

[0090] I. Information Bit Sequence

[0091] An information bit sequence refers to a sequence of bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is 10101100101. Information bits can refer to the payload itself, or to the payload plus cyclic redundancy check (CRC) bits.

[0092] II. Code Length

[0093] Code length refers to the length of the bit sequence to be transmitted obtained by encoding the information bit sequence. It can be the length of the bit sequence to be transmitted corresponding to the modulated symbol. The code length is greater than or equal to the length of the information bit sequence.

[0094] III. Bitrate

[0095] The code rate is the ratio of the length of the information bit sequence to the code length. It can also be the ratio of the length of the information bit sequence to the length of the encoded bit sequence. For example, assuming the code length is N and the length of the information bit sequence is K, the code rate could be R = K / N.

[0096] The length, code length, and code rate of the information bit sequence can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the coding method, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme (MCS).

[0097] IV. LDPC Code

[0098] LDPC codes are a channel coding scheme very close to the Shannon limit, characterized by high performance and low complexity. They have been adopted by 3GPP as the coding and decoding scheme for 5G communication data channels. Mainstream LDPC codes have a quasi-cyclic (QC) structure, which avoids bad structures such as short cycles and improves code distance by setting the shift amount of each block.

[0099] LDPC codes can be represented using a basis matrix, where elements are either 0 or 1. Expanding the basis matrix by adding 1 elements results in a Zc*Zc cyclic shift matrix, and expanding by adding 0 elements results in a Zc*Zc zero matrix. This expansion yields a parity-check matrix, which can be used for encoding or decoding. Zc can be referred to as the lift factor, spread factor, spread value, spread coefficient, lifting size, etc. The basis matrix can be represented as H. BG BG is an abbreviation for basegraph. A basis matrix can also be represented by a basegraph, and the two have a corresponding relationship.

[0100] For example, if the element in the i-th row and j-th column of the basis matrix is ​​1 and corresponds to a shifting value (SV), it can be represented by P. i,j This represents the shift value corresponding to the i-th row and j-th column. A shift value can be used to calculate the corresponding number of cyclic shifts.

[0101] Taking Zc=4 as an example, the matrix obtained by cyclically shifting the 4*4 identity matrix to the right by 1, 2, 3, and 0 times respectively is as follows: Figure 2 As shown, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0102] The following example will illustrate this point. Figure 3 This is an example diagram of the basis matrix in an LDPC code. The basis matrix is ​​a 3x3 matrix, and it is assumed that Zc = 4, and P... 0,0 The corresponding right circular shift count is 1, P0,1 The corresponding right circular shift count is 2, P 1,0 The corresponding right circular shift count is 3, P 1,2 The corresponding right circular shift count is 3, P 2,2 The corresponding right circular shift is 1. Therefore, after expanding the base matrix, we can obtain the following: Figure 4 The verification matrix shown.

[0103] Table 1 shows the various values ​​of the lifting dimension (Zc).

[0104] Table 1

[0105]

[0106]

[0107] Referring to Table 1, the value of the lifting dimension Zc can be a j *2 kj Where j represents the j-th row in Table 1, j = 0, 1, 2, 3, 4, 5, 6, 7, a0, a1, a2, a3, a 4, a 5, a6 and a7 are 2, 3, 5, 7, 9, 11, 13, and 15 respectively. k j The value of traverses from 0 to max(k) j ), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, and 4, respectively.

[0108] For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7, so the value of Zc can be 2*2. 0 2*2 1 ,2*2 2 2*2 3 ,2*2 4 ,2*2 5 ,2*2 6 ,2*2 7 That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further.

[0109] In Table 1, each row of Zc corresponds to a set of SV. When constructing the parity check matrix, the size of Zc is first determined, then the set of SV corresponding to that Zc is determined, and then the parity check matrix is ​​constructed based on Zc and SV.

[0110] Table 2 below shows some examples of a set of SVs defined in the 3GPP 212 protocol.

[0111] Table 2

[0112]

[0113] Table 2 shows the basis matrix H. BG The translation values ​​SV corresponding to the elements with a value of 1 in row 0 i,j The set index i in Table 2 LS That is, the set index i in Table 1 LS Furthermore, the basis matrix H BG The cyclic shift value corresponding to each element with a value of 1 in row 0 can be obtained by taking the modulo of Zc using the corresponding translation value.

[0114] Table 2 only shows the translation values ​​corresponding to each element in row 0. In practice, it also includes the translation values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0115] Referring to Table 2, when Zc takes the values ​​2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BG The SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, then the basis matrix H... BG The cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the basis matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H... BG The elements in the 0th row that have a value of 0 correspond to a zero matrix of size 4*4.

[0116] Similarly, for other values ​​of Zc, there are corresponding translation values ​​and cyclic shift counts, as detailed in Table 2.

[0117] Similarly, for the basis matrix H BG The rows other than row 0 are also determined using a similar method to determine the corresponding Zc*Zc matrix.

[0118] In this embodiment, the lifting and translation operations of the LDPC code are described as follows: For a given lifting size Zc, from the basis matrix H BG Upgraded to the parity check matrix H, specifically, the basis matrix H BG t in i,j (where t) i,j =1) will be replaced with a Zc×Zc matrix I(P) i,j ), where I(P i,j ) is a cyclic shift of the identity matrix I of Zc×Zc by P i,j One (either left or right circular shift is possible) or circular shift P i,j A matrix of degree mod Zc, P i,j The translation value corresponding to the i-th row and j-th column; basis matrix H BG The zeros in H will be replaced with a Zc×Zc matrix of all zeros. It can be seen that the purpose of lifting is to improve the basis matrix H. BG To transform it into a larger parity check matrix H, the translation aims to shift each H... BG The identity matrix corresponding to the non-zero elements is cyclically shifted into a predefined matrix.

[0119] V. Basis Matrix of 5G LDPC Codes

[0120] The basis matrices of the 5G LDPC code include BG1 and BG2. BG1 is a 46x68 matrix, and BG2 is a 42x52 matrix. Both BG1 and BG2 have... Figure 5 The matrix structure is shown below. Region A corresponds to the high-bitrate information column, region B corresponds to the high-bitrate core verification column, region C is the zero matrix, region D is the incremental redundancy part of the base matrix and corresponds to the low-bitrate column, and region E is the incremental redundancy region and is an identity matrix. The base matrix takes values ​​of 0 or 1; a value of 0 represents an empty element, and a value of 1 represents an edge in the base graph, or the association between the verification and the variable.

[0121] To improve bitrate, LDPC encoding supports puncturing. For example, see [reference needed]. Figure 5 The first two columns of the matrices BG1 and BG2 are punched columns. In terms of matrix characteristics, the column weight of the punched column is relatively large. The column weight refers to the number of non-zero elements in a column. In terms of transmission characteristics, the bits corresponding to the punched column are not transmitted. The receiver does not need to pay attention to the received information of this part. Its log-likelihood ratio is set to 0 and it is recovered by decoding.

[0122] BG1 and BG2 are designed for the lowest bitrate. When different bitrates need to be supported, the upper left part of BG1 or BG2 can be used. Figure 6 This diagram illustrates the matrix regions corresponding to different bitrates. The matrix can be BG1 or BG2. Rows and columns of a high-bitrate region, as shown in the diagram, are selected from BG1 or BG2 to form the base matrix. The high-bitrate region can also be called the region corresponding to the highest bitrate. Taking BG1 as an example, the high-bitrate region of BG1 is a matrix region composed of region A and region B of BG1. Region A is a 4x22 matrix used to carry data information, and region B is a 4x4 matrix used to carry checksum information. When the first two columns are punched, the bitrate supported by the high-bitrate region is 22 / (22+4-2)=22 / 24≈0.917, and the bitrate of other regions is lower than that of the high-bitrate region.

[0123] When a high-bitrate region is selected from BG1 or BG2 as the base matrix, the resulting base matrix has the highest bitrate; therefore, it is also called the highest bitrate matrix. If more rows and columns than high-bitrate regions are selected from BG1 or BG2 to form the base matrix, the bitrate of this base matrix will be lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases. See also... Figure 6 The rows and columns of each dashed box region form a basis matrix. As the size of the dashed box region increases, the bit rate of the corresponding basis matrix gradually decreases.

[0124] VI. Spectral Efficiency

[0125] Spectral efficiency, also known as system capacity or bandwidth utilization, refers to the number of bits transmitted per unit time within a given bandwidth. The unit of spectral efficiency is, for example, bits per second per hertz (bit / s / Hz).

[0126] In this application, the communication parameters satisfying the first condition may further include a threshold value for spectral efficiency that is greater than or equal to the spectral efficiency. The threshold value for spectral efficiency may be a pre-configured or pre-defined value.

[0127] For example, the thresholds for spectral efficiency are 6 bit / s / Hz, 7 bit / s / Hz, 7.5 bit / s / Hz, or 8 bit / s / Hz, etc.

[0128] Currently, LDPC decoding performance is relatively poor. However, for some code rates, LDPC encoding and decoding has significant performance gain potential, for example... Figure 7 A schematic diagram showing the bit rate and system capacity is provided. Figure 7 In the graph, the horizontal axis represents the bitrate, and the vertical axis represents the distance from the capacity. Figure 7 It can be seen that there is a sudden change in the distance between the bitrate and the capacity, that is, at this bitrate, the rationality of the matrix design is low and the encoding and decoding performance is poor.

[0129] To address the aforementioned issues, this application provides corresponding solutions.

[0130] Figure 8 This is a flowchart illustrating a communication method provided in an embodiment of this application. The method is executed by a first device. Unless otherwise specified, the "first device" in this application may refer to the first device itself (e.g., a terminal device or a network device), a component within the first device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the first device.

[0131] In this application, the first device can be used as a transmitting device, and the second device can be used as a receiving device. For example, the first device can send information to the second device.

[0132] It should be noted that this application uses the example of sorting row and column indexes starting from 0 for illustration. In actual implementation, row and column indexes can also be sorted starting from 1, and no specific limitation is made here.

[0133] The method includes the following steps:

[0134] S901, the first device processes the first region of the first LDPC matrix according to the first rule to obtain the second LDPC matrix.

[0135] In this application, the first rule is related to the first code rate. In one exemplary description, the first code rate can also be described as the encoded code rate or the initial transmission code rate. Alternatively, the first rule is related to the following parameters: the first code length and the length of the information bits.

[0136] Optionally, the length of the information bits and the first code length can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or they can be obtained or calculated by the first and second devices. For example, the first and second devices can determine the first code length based on the encoding method, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme.

[0137] The first code rate can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or it can be obtained or calculated by the first and second devices. For example, the first and second devices can obtain the first code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the first code rate according to a modulation and coding scheme (MCS). Alternatively, the first code rate can also be determined based on the first code length and the length of the information bits. For example, assuming the first code length is N and the length of the information bits is K, the first code rate can be R = K / N.

[0138] From a column perspective, the first region in this application includes at least one column from the first column set of the first LDPC matrix. This first column set can be columns with column indices from 0 to X-1 in the first LDPC matrix. Alternatively, the first column set can be the X column in the first LDPC matrix with the largest column weight. Or, the first column set can be the X columns in the first LDPC matrix that include punctured bits (such as bits that participate in encoding, do not enter the circular buffer, and are not transmitted). Here, X is a positive integer greater than 0 and not greater than the total number of columns in the first LDPC matrix, for example, X = 1, 2, etc.

[0139] The weight of a column can be represented by the number of non-zero elements it contains, or by the number of non-zero elements contained in a portion of the rows corresponding to that column. For example, this portion of the rows could be the rows with indexes Y1 to Y2. Y1 is a non-negative integer less than the total number of rows in the first LDPC matrix, such as 1. Y2 is an integer greater than Y1 and less than the total number of rows in the first LDPC matrix.

[0140] In one example, from the perspective of columns, the first region consists of the set of the first columns of the first LDPC matrix. For instance, if the first column set includes the columns with column indices 0 and 1 of the first LDPC matrix, the first region consists of the columns with column indices 0 and 1 of the first LDPC matrix.

[0141] In another example, from a column perspective, the first region consists of a subset of columns from the first column set of the first LDPC matrix. For instance, if the first column set includes columns with column indices 0 and 1 of the first LDPC matrix, the first region consists of columns with column index 0 of the first LDPC matrix, or the first region consists of columns with column index 1 of the first LDPC matrix.

[0142] In another example, from a column perspective, the first region is composed of the second set of columns of the first LDPC matrix. This second set of columns includes the first set of columns as well as other columns not included in the first set. For instance, assuming the first set of columns includes columns with indices 0 and 1 of the first LDPC matrix, the second set of columns could include columns with indices 0 and 1 as well as columns with other indices of the first LDPC matrix. For example, the second set of columns could include columns with indices 0 to 2, or columns with indices 0 to 3, or columns with indices 0, 1, and 3, and so on. Assuming the second set of columns consists of columns with indices 0 to 2 of the first LDPC matrix, then the first region is composed of these indices.

[0143] In another example, from a column perspective, the first region is composed of the third column set of the first LDPC matrix. This third column set includes some columns from the first column set as well as other columns not included in the first column set. For instance, assuming the first column set includes columns with indexes 0 to 1 of the first LDPC matrix, the third column set could include columns with indices 0 and 2, or columns with indices 0, 2, and 3, or columns with indices 1 to 3, and so on. Assuming the third column set consists of columns with indices 1 to 3 of the first LDPC matrix, then the first region is composed of these indices.

[0144] The first region has been described above from the perspective of columns; the following section describes the first region from the perspective of rows.

[0145] Optionally, from a row perspective, the first region includes at least one row of the first LDPC matrix. For example, the first region includes all rows of the first LDPC matrix. Or, for another example, the first region includes the row in the first LDPC matrix corresponding to the first code rate.

[0146] For example, the row index (row) of the row corresponding to the first bit rate R can satisfy the following formula:

[0147]

[0148] Where a is the number of information columns in the first LDPC matrix.

[0149] Alternatively, the row index (row) of the row corresponding to the first bitrate R can satisfy the following formula:

[0150]

[0151] Where Zc is the lift value, which can be, for example, the smallest lift value in the set of lift values ​​that satisfy a*Zc≥K. a is the number of information columns in the first LDPC matrix. K is the length of the information bits. N is the first code length.

[0152] For example, the first LDPC matrix can be a base matrix, such as BG1 and BG2 in a 5G communication protocol. Alternatively, the first LDPC matrix can also be a parity check matrix.

[0153] The first rule will be explained in detail below.

[0154] S902, the first device encodes the information bits according to the second LDPC matrix to obtain a codeword bit sequence.

[0155] Understandably, the length of this codeword bit sequence is the first code length.

[0156] S903, the first device sends a codeword bit sequence. Correspondingly, the second device receives the first information.

[0157] The first piece of information can be the bit sequence after the codeword bit sequence has been transmitted through the channel.

[0158] S904, the second device processes the first region of the first LDPC matrix according to the first rule to obtain the second LDPC matrix.

[0159] The second device obtains the second LDPC matrix in the same way as the first device obtains the second LDPC matrix. For details, please refer to the relevant description on the first device side. Repeated parts will not be repeated.

[0160] S905, the second device decodes the first information according to the second LDPC matrix.

[0161] Since the position of the punctured bits has a significant impact on encoding and decoding in low-complexity scenarios, this application improves the rationality of the LDPC matrix under different bitrates by modifying the punctured columns (i.e., the first column set mentioned above) of the LDPC matrix according to the bitrate. This results in better encoding performance under different bitrates and can bring significant gains to encoding and decoding performance.

[0162] The first rule will now be explained.

[0163] One possible approach is to process the first region of the first LDPC matrix according to a first rule. Specifically, this could involve modifying the positions of 0 / 1 in the first region according to the first rule, and / or modifying the translation values ​​of 0 / 1 in the first region. For example, if the first LDPC matrix is ​​a parity check matrix, the first rule modifies the positions of 0 / 1 in the first region of the first LDPC matrix, for instance, modifying the position of 1 in the first region. If the first LDPC matrix is ​​a base matrix, such as BG1 and BG2 in a 5G communication protocol, the first rule modifies the positions of 0 / 1 and translation values ​​in the first region of the first LDPC matrix, for instance, modifying the position of 1 in the first region and modifying the corresponding translation values.

[0164] For example, modifications to the positions 0 / 1 in the first region can include at least one of the following: deletion, addition, movement, or remaining unchanged. Deleting a matrix element 0 can be understood as changing that matrix element to 1. Similarly, deleting a matrix element 1 can be understood as changing that matrix element from 1 to 0. Adding a matrix element 0 can be understood as changing a matrix element from 1 to 0. Similarly, adding a matrix element 1 can be understood as changing a matrix element from 0 to 1. Moving a matrix element 0 from position 1 to position 2 can be understood as changing the matrix element at position 1 from 0 to 1 and the matrix element at position 2 from 1 to 0. Similarly, moving a matrix element 1 from position 3 to position 4 can be understood as changing the matrix element at position 3 from 1 to 0 and the matrix element at position 4 from 0 to 1.

[0165] Alternatively, the modification of the 0 / 1 positions in the first region can also include: substitution based on the third matrix. Here, the third matrix has the same size as the first LDPC matrix. Compared to the first LDPC matrix, the positions of 0 / 1 in the corresponding regions of the first region of the third matrix are different from those in the first region of the first LDPC matrix, while the positions of 0 / 1 in the corresponding regions of the third matrix that are not in the first region are the same as those in the corresponding regions of the first LDPC matrix. For example, the positions of 0 / 1 in the first region of the first LDPC matrix are different from those in the second region of the third matrix, while the positions of 0 / 1 in the fourth region of the first LDPC matrix are the same as those in the third region of the third matrix. Here, the relative position of the second region in the third matrix is ​​the same as the relative position of the first region in the first LDPC matrix; that is, the second region is the region of the third matrix that is not in the first region. The third region is the complement of the second region; that is, the third region is the region of the third matrix that is not in the first region. The fourth region is the complement of the first region; that is, the region of the first LDPC matrix that is not in the first region.

[0166] Alternatively, the third matrix can be the same size as the first region, but the positions of 0 / 1 in the third matrix are different from the positions of 0 / 1 in the first region of the first LDPC matrix.

[0167] Optionally, if the first LDPC matrix is ​​a base matrix, and 0 / 1 in the first LDPC matrix also correspond to translation values, then 0 / 1 in the third matrix can also correspond to translation values. In this scheme, the translation values ​​of 0 / 1 at the same position in the second region and the first region can be the same. Furthermore, if a 1 position in the first LDPC matrix is ​​deleted after the replacement (i.e., the 1 at that position is replaced with a 0), the translation value at that position can be deleted accordingly. If a 1 position in the first LDPC matrix is ​​added after the replacement (i.e., the 0 at that position is replaced with a 1), the translation value at that position can be the translation value of the same position in the third matrix.

[0168] Modifications to the shifted values ​​of 0 / 1 in the first region can include at least one of the following: deletion, operation with a numerical value, etc. When operating on a shifted value of 0 / 1 with a numerical value, the numerical value can be related to the row index of the row containing the 0 / 1 and / or the column index of the column containing it. The above operations can include at least one of the following: addition, multiplication, subtraction, division, etc.

[0169] Furthermore, the above-mentioned processing of the first region of the first LDPC matrix according to the first rule can be to modify the i-th row of the first region, for example, to modify the position of 0 / 1 in the i-th row of the first region, and / or to modify the translation value of 0 / 1 in the i-th row of the first region.

[0170] For example, the value of i can be determined based on the first code rate, or the value of i can be determined based on the first code length and the length of the information bits. i is a non-negative integer less than the total number of rows in the first LDPC matrix.

[0171] Here we will introduce the two ways to determine i.

[0172] Method 1 The value of i is determined based on the first bit rate.

[0173] In one example, the first device and the second device determine the value of i based on the bitrate range in which the first bitrate is located.

[0174] For example, if the first bitrate is within the bitrate range Then the row index i is row-1, where a is the column number of the information column in the first LDPC matrix.

[0175] It should be noted that the above bitrate range can also be expressed as wait.

[0176] Method 2 The value of i is determined based on the first code length and the length of the information bits.

[0177] In one example, the first device and the second device can determine the first code rate based on the first code length and the length of the information bits, and determine the value of i based on the first code rate. The method for determining the first code rate based on the first code length and the length of the information bits can be found in the relevant description in S901, and the method for determining the value of i based on the first code rate can be found in the relevant description of determination method 1; repeated details will not be elaborated further.

[0178] In another example, the first and second devices can determine the value of i according to the following formula, or in other words, the value of i satisfies the following formula:

[0179]

[0180] Where ceil() is the floor function. Zc is the lift value, which can be the smallest lift value in the set of lift values ​​that satisfy a*Zc≥K. a is the number of information columns in the first LDCP matrix. K is the length of the information bits. N is the first code length.

[0181] In one implementation, the i-th row of the first region can be modified even if the row with row index i does not belong to the first row set. The first row set includes at least one row of the first LDPC matrix, for example, BG1 of the first base matrix 5G. The first row set may include at least one of the following rows: the row with row index 6 in the first LDPC matrix, or the row with row index 10 in the first LDPC matrix.

[0182] Optionally, the first rule may further include: adding one or more 1 positions to the second set of rows in the first LDPC matrix. For example, the second set of rows includes the row with row index 4 and / or the row with row index 5 in the first LDPC matrix.

[0183] For example, one or more positions of 1 in the second row set may include one or more positions shown in Table 3.

[0184] Table 3

[0185]

[0186]

[0187] To facilitate understanding of the scheme, the first rule will be explained below using BG1, where the first LDPC matrix is ​​of size 16*38, as an example.

[0188] Example 1: Suppose the first column set includes columns with column indices 0 to 1 of the first LDPC matrix, and the first region consists of the aforementioned first column set (i.e., columns with column indices 0 to 1 of the first LDPC matrix) and all rows of the first LDPC matrix. The first rule can be to modify the position of 0 / 1 in the row with column index i of the columns with column indices 0 to 1 of the first LDPC matrix.

[0189] The following description uses the implementation method corresponding to the above determination method 1 as an example. It can be understood that the implementation method corresponding to the above determination method 2 is similar, except that the method of determining the value of i is different.

[0190] The first rule can be specifically stated as follows: if the first bitrate R is within the bitrate range Then, the position of 0 / 1 in the row-th row (i.e., the row with row index i = row-1) of the first region is modified. For example, the element in the row-th row of the first column of the first LDPC matrix (i.e., the row with row index i = row-1) is deleted, that is, the 1 at that position is changed to 0. Optionally, if the position itself is 0, then the position does not need to be modified.

[0191] For example, if the first code rate R ∈ (22 / 24, 22 / 25), then the positions of 0 / 1 in the row with row index i of 4 in the first region are modified. For example, the element in the 5th row of the first column of the first LDPC matrix (i.e., the row with row index i of 4) is deleted, that is, the 1 at that position is changed to 0. If the first code rate R ∈ (22 / 25, 22 / 26), then the positions of 0 / 1 in the row with row index i of 5 in the first region are modified. For example, the element in the 6th row of the first column of the first LDPC matrix (i.e., the row with row index i of 5) is deleted, that is, the 1 at that position is changed to 0.

[0192] A concrete example is that, suppose the positions of 1 in the first LDPC matrix include:

[0193] The row index is 0, and the column indexes are: 0, 1, 2, 3, 5, 6, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22;

[0194] The row index is 1, and the column indexes are: 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23;

[0195] The row index is 2, and the column indexes are: 0, 1, 2, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0196] The row index is 3, and the column indexes are: 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 25;

[0197] The row index is 4, and the column indexes are 0, 1, and 26.

[0198] The row index is 5, and the column indexes are: 0, 1, 3, 12, 15, 20, 21, 22, 27;

[0199] The row index is 6, and the column indexes are: 0, 5, 10, 11, 13, 17, 18, 20, 28;

[0200] The row index is 7, and the column indexes are: 0, 1, 4, 7, 8, 14, 29;

[0201] The row index is 8, and the column indexes are: 0, 1, 3, 12, 15, 19, 20, 21, 22, 24, 30;

[0202] The row index is 9, and the column indexes are: 0, 1, 10, 11, 13, 17, 18, 20, 31;

[0203] The row index is 10, and the column indexes are: 1, 2, 4, 7, 8, 14, 32;

[0204] The row index is 11, and the column indexes are: 0, 12, 15, 20, 21, 22, 23, 33;

[0205] The row index is 12, and the column indexes are: 0, 1, 10, 11, 13, 18, 34;

[0206] The row index is 13, and the column indexes are: 0, 1, 3, 7, 20, 23, 35;

[0207] The row index is 14, and the column indexes are: 0, 1, 12, 15, 16, 17, 21, 36;

[0208] The row index is 15, and the column indexes are: 0, 1, 10, 13, 18, 25, 37;

[0209] As shown in Table 4.

[0210] Table 4

[0211]

[0212] If the first code rate R ∈ (22 / 24, 22 / 25), the positions of 0 / 1 in the first two columns and fifth row (i.e., the row with row index 4) of the first LDPC matrix can be modified to obtain the second LDPC matrix. For example, the positions of 1 in the second LDPC matrix include:

[0213] The row index is 0, and the column indexes are: 0, 1, 2, 3, 5, 6, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22;

[0214] The row index is 1, and the column indexes are: 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23;

[0215] The row index is 2, and the column indexes are: 0, 1, 2, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0216] The row index is 3, and the column indexes are: 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 25;

[0217] The row index is 4, and the column indexes are 1 and 26.

[0218] The row index is 5, and the column indexes are: 0, 1, 3, 12, 15, 20, 21, 22, 27;

[0219] The row index is 6, and the column indexes are: 0, 5, 10, 11, 13, 17, 18, 20, 28;

[0220] The row index is 7, and the column indexes are: 0, 1, 4, 7, 8, 14, 29;

[0221] The row index is 8, and the column indexes are: 0, 1, 3, 12, 15, 19, 20, 21, 22, 24, 30;

[0222] The row index is 9, and the column indexes are: 0, 1, 10, 11, 13, 17, 18, 20, 31;

[0223] The row index is 10, and the column indexes are: 1, 2, 4, 7, 8, 14, 32;

[0224] The row index is 11, and the column indexes are: 0, 12, 15, 20, 21, 22, 23, 33;

[0225] The row index is 12, and the column indexes are: 0, 1, 10, 11, 13, 18, 34;

[0226] The row index is 13, and the column indexes are: 0, 1, 3, 7, 20, 23, 35;

[0227] The row index is 14, and the column indexes are: 0, 1, 12, 15, 16, 17, 21, 36;

[0228] The row index is 15, and the column indexes are: 0, 1, 10, 13, 18, 25, 37;

[0229] As shown in Table 5.

[0230] Table 5

[0231]

[0232] If the first code rate R ∈ (22 / 25, 22 / 26), the positions of 0 / 1 in the first two columns and the 6th row (i.e., the row with row index 5) of the first LDPC matrix can be modified to obtain the second LDPC matrix. For example, the positions of 1 in the second LDPC matrix include:

[0233] The row index is 0, and the column indexes are: 0, 1, 2, 3, 5, 6, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22;

[0234] The row index is 1, and the column indexes are: 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23;

[0235] The row index is 2, and the column indexes are: 0, 1, 2, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0236] The row index is 3, and the column indexes are: 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 25;

[0237] The row index is 4, and the column indexes are 0, 1, and 26.

[0238] The row index is 5, and the column indices are: 1, 3, 12, 16, 21, 22, 27;

[0239] The row index is 6, and the column indexes are: 0, 5, 10, 11, 13, 17, 18, 20, 28;

[0240] The row index is 7, and the column indexes are: 0, 1, 4, 7, 8, 14, 29;

[0241] The row index is 8, and the column indexes are: 0, 1, 3, 12, 15, 19, 20, 21, 22, 24, 30;

[0242] The row index is 9, and the column indexes are: 0, 1, 10, 11, 13, 17, 18, 20, 31;

[0243] The row index is 10, and the column indexes are: 1, 2, 4, 7, 8, 14, 32;

[0244] The row index is 11, and the column indexes are: 0, 12, 15, 20, 21, 22, 23, 33;

[0245] The row index is 12, and the column indexes are: 0, 1, 10, 11, 13, 18, 34;

[0246] The row index is 13, and the column indexes are: 0, 1, 3, 7, 20, 23, 35;

[0247] The row index is 14, and the column indexes are: 0, 1, 12, 15, 16, 17, 21, 36;

[0248] The row index is 15, and the column indexes are: 0, 1, 10, 13, 18, 25, 37;

[0249] As shown in Table 6.

[0250] Table 6

[0251]

[0252] Optionally, the first rule also includes: adding 1 to one or more positions in the first LDPC matrix as described in Table 3.

[0253] For example, taking the determination method 1 mentioned above as an example, if the first bitrate R is within the bitrate range Then, the positions of 0 / 1 in the row with row index i = row-1 in the first region are modified. For example, if the first code rate R ∈ (22 / 24, 22 / 25), then the positions of 0 / 1 in the row with row index i = 4 in the first region are modified. If the first code rate R ∈ (22 / 25, 22 / 26), then the positions of 0 / 1 in the row with row index i = 5 in the first region are modified. The first rule also includes adding 1 to the 24th and 25th columns (column indices 23 and 24) of the 5th row (i.e., the row with index 4).

[0254] A concrete example is given below. Assume the first LDPC matrix is ​​as shown in Table 4. If the first code rate R ∈ (22 / 24, 22 / 25), the positions of 0 / 1 in the first two columns and fifth row (row index 4) of the first LDPC matrix can be modified as shown in Table 5. Furthermore, a 1 is added to the first LDPC matrix at the 24th and 25th columns (column indices 23 and 24) of the fifth row (row index 4) to obtain the second LDPC matrix. For example, the positions of 1 in the second LDPC matrix include:

[0255] The row index is 0, and the column indexes are: 0, 1, 2, 3, 5, 6, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22;

[0256] The row index is 1, and the column indexes are: 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23;

[0257] The row index is 2, and the column indexes are: 0, 1, 2, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0258] The row index is 3, and the column indexes are: 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 25;

[0259] The row index is 4, and the column indexes are: 1, 23, 24, 26;

[0260] The row index is 5, and the column indexes are: 0, 1, 3, 12, 15, 20, 21, 22, 27;

[0261] The row index is 6, and the column indexes are: 0, 5, 10, 11, 13, 17, 18, 20, 28;

[0262] The row index is 7, and the column indexes are: 0, 1, 4, 7, 8, 14, 29;

[0263] The row index is 8, and the column indexes are: 0, 1, 3, 12, 15, 19, 20, 21, 22, 24, 30;

[0264] The row index is 9, and the column indexes are: 0, 1, 10, 11, 13, 17, 18, 20, 31;

[0265] The row index is 10, and the column indexes are: 1, 2, 4, 7, 8, 14, 32;

[0266] The row index is 11, and the column indexes are: 0, 12, 15, 20, 21, 22, 23, 33;

[0267] The row index is 12, and the column indexes are: 0, 1, 10, 11, 13, 18, 34;

[0268] The row index is 13, and the column indexes are: 0, 1, 3, 7, 20, 23, 35;

[0269] The row index is 14, and the column indexes are: 0, 1, 12, 15, 16, 17, 21, 36;

[0270] The row index is 15, and the column indexes are: 0, 1, 10, 13, 18, 25, 37;

[0271] As shown in Table 7.

[0272] Table 7

[0273]

[0274] If the first code rate R ∈ (22 / 25, 22 / 26), the positions of 0 / 1 in the 6th row of the first 2 columns (i.e., the row with row index 5) of the first LDPC matrix can be modified according to the positions of 0 / 1 in the 6th row of the first 2 columns (i.e., the row with row index 5) in Table 6. Furthermore, a 1 is added to the first LDPC matrix at the 24th and 25th columns (i.e., columns with column indices 23 and 24) of the 5th row (i.e., the row with index 4), resulting in the second LDPC matrix. For example, the positions of 1 in the second LDPC matrix include:

[0275] The row index is 0, and the column indexes are: 0, 1, 2, 3, 5, 6, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22;

[0276] The row index is 1, and the column indexes are: 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23;

[0277] The row index is 2, and the column indexes are: 0, 1, 2, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0278] The row index is 3, and the column indexes are: 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 25;

[0279] The row index is 4, and the column indices are: 0, 1, 23, 24, 26;

[0280] The row index is 5, and the column indices are: 1, 3, 12, 16, 21, 22, 27;

[0281] The row index is 6, and the column indexes are: 0, 5, 10, 11, 13, 17, 18, 20, 28;

[0282] The row index is 7, and the column indexes are: 0, 1, 4, 7, 8, 14, 29;

[0283] The row index is 8, and the column indexes are: 0, 1, 3, 12, 15, 19, 20, 21, 22, 24, 30;

[0284] The row index is 9, and the column indexes are: 0, 1, 10, 11, 13, 17, 18, 20, 31;

[0285] The row index is 10, and the column indexes are: 1, 2, 4, 7, 8, 14, 32;

[0286] The row index is 11, and the column indexes are: 0, 12, 15, 20, 21, 22, 23, 33;

[0287] The row index is 12, and the column indexes are: 0, 1, 10, 11, 13, 18, 34;

[0288] The row index is 13, and the column indexes are: 0, 1, 3, 7, 20, 23, 35;

[0289] The row index is 14, and the column indexes are: 0, 1, 12, 15, 16, 17, 21, 36;

[0290] The row index is 15, and the column indexes are: 0, 1, 10, 13, 18, 25, 37;

[0291] As shown in Table 8.

[0292] Table 8

[0293]

[0294] Example 2: Assume the first column set includes columns with indexes 0 to 1 of the first LDPC matrix. The first region consists of the aforementioned first column set (i.e., columns with indexes 0 to 1 of the first LDPC matrix) and all rows of the first LDPC matrix. The first rule can be to modify the columns with indexes 0 to 1 of the first LDPC matrix based on the third matrix. The columns with indexes 0 to 1 of the third matrix differ from those of the columns with indexes 0 to 1 of the first LDPC matrix in at least one 0 / 1 position, and the columns with indexes 2 to 37 of the third matrix have the same 0 / 1 positions as the columns with indexes 2 to 37 of the first LDPC matrix.

[0295] The following description uses the implementation method corresponding to the above determination method 1 as an example. It can be understood that the implementation method corresponding to the above determination method 2 is similar, except that the method of determining the value of i is different.

[0296] The first rule can be specifically stated as follows: if the first bitrate R is within the bitrate range Then, the row-1 (row-1) of the first LDPC matrix is ​​replaced with the row-1 (row-1) of the third matrix. For example, if the first code rate R ∈ (22 / 24, 22 / 25), then the 5th row (row-4) of the first LDPC matrix is ​​replaced with the 5th row (row-4) of the third matrix. If the first code rate R ∈ (22 / 25, 22 / 26), then the 6th row (row-5) of the first LDPC matrix is ​​replaced with the 6th row (row-5) of the third matrix.

[0297] A concrete example is given by assuming the first LDPC matrix is ​​as shown in Table 4 above. The positions of 1s in the third matrix could include:

[0298] The row index is 0, and the column indexes are 0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, 23;

[0299] The row index is 1, and the column indexes are 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, 24;

[0300] The row index is 2, and the column indexes are 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0301] The row index is 3, and the column indexes are 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, 25;

[0302] The row index is 4, and the column indexes are 1 and 26.

[0303] The row index is 5, and the column indexes are 1, 3, 12, 16, 21, 22, and 27.

[0304] The row index is 6, and the column indexes are 0, 6, 10, 11, 13, 17, 18, 20, and 28.

[0305] The row index is 7, and the column indexes are 1, 4, 7, 8, 14, and 29.

[0306] The row index is 8, and the column indexes are 1, 3, 12, 16, 19, 21, 22, 24, and 30.

[0307] The row index is 9, and the column indexes are 1, 10, 11, 13, 17, 18, 20, and 31.

[0308] The row index is 10, and the column indexes are 1, 2, 4, 7, 8, 14, and 32.

[0309] The row index is 11, and the column indexes are 0, 12, 16, 21, 22, 23, and 33.

[0310] The row index is 12, and the column indexes are 1, 10, 11, 13, 18, and 34.

[0311] The row index is 13, and the column indexes are 0, 3, 7, 20, 23, and 35.

[0312] The row index is 14, and the column indexes are 0, 12, 15, 16, 17, 21, and 36.

[0313] The row index is 15, and the column indexes are 1, 10, 13, 18, 25, and 37.

[0314] As shown in Table 9.

[0315] Table 9

[0316]

[0317] It should be noted that the row indexes of each row in Table 9 or Table 10 below are merely examples, and this application does not limit the sorting of each row in Table 9 or Table 10 below.

[0318] If the first code rate R∈(22 / 24,22 / 25), the 5th row of the first LDPC matrix (i.e., the row with index 4) can be replaced with the 5th row of the third matrix (i.e., the row with index 4) to obtain the second LDPC matrix. The second LDPC matrix can be shown in Table 5 above.

[0319] If the first code rate R∈(22 / 25,22 / 26), the 6th row of the first LDPC matrix (i.e., the row with index 5) can be replaced with the 6th row of the third matrix (i.e., the row with index 5) to obtain the second LDPC matrix. The second LDPC matrix can be shown in Table 6 above.

[0320] Optionally, the first rule also includes adding 1 to one or more positions in the first LDPC matrix as described in Table 3. For example, adding 1 to the 24th and 25th columns (column indices 23 and 24) in row 5 (i.e., the row with index 4) could result in the following positions in the third matrix:

[0321] The row index is 0, and the column indexes are 0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, 23;

[0322] The row index is 1, and the column indexes are 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, 24;

[0323] The row index is 2, and the column indexes are 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25;

[0324] The row index is 3, and the column indexes are 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, 25;

[0325] The row index is 4, and the column indexes are 1, 23, 24, and 26.

[0326] The row index is 5, and the column indexes are 1, 3, 12, 16, 21, 22, and 27.

[0327] The row index is 6, and the column indexes are 0, 6, 10, 11, 13, 17, 18, 20, and 28.

[0328] The row index is 7, and the column indexes are 1, 4, 7, 8, 14, and 29.

[0329] The row index is 8, and the column indexes are 1, 3, 12, 16, 19, 21, 22, 24, and 30.

[0330] The row index is 9, and the column indexes are 1, 10, 11, 13, 17, 18, 20, and 31.

[0331] The row index is 10, and the column indexes are 1, 2, 4, 7, 8, 14, and 32.

[0332] The row index is 11, and the column indexes are 0, 12, 16, 21, 22, 23, and 33.

[0333] The row index is 12, and the column indexes are 1, 10, 11, 13, 18, and 34.

[0334] The row index is 13, and the column indexes are 0, 3, 7, 20, 23, and 35.

[0335] The row index is 14, and the column indexes are 0, 12, 15, 16, 17, 21, and 36.

[0336] The row index is 15, and the column indexes are 1, 10, 13, 18, 25, and 37.

[0337] As shown in Table 10.

[0338] Table 10

[0339]

[0340] For example, if the first code rate R∈(22 / 24,22 / 25), the 5th row of the first LDPC matrix (i.e., the row with row index 4) can be replaced with the 5th row of the third matrix (i.e., the row with row index 4). Furthermore, a 1 is added to the 24th and 25th columns (i.e., columns with column indices 23 and 24) of the 5th row (i.e., the row with index 4) of the first LDPC matrix to obtain the second LDPC matrix. For example, the second LDPC matrix can be as shown in Table 7 above.

[0341] If the first code rate R∈(22 / 25,22 / 26), the 6th row of the first LDPC matrix (i.e., the row with row index 5) can be replaced with the 6th row of the third matrix (i.e., the row with row index 5). Furthermore, a 1 is added to the 24th and 25th columns (i.e., columns with column indices 23 and 24) of the 5th row (i.e., the row with index 4) of the first LDPC matrix to obtain the second LDPC matrix. For example, the second LDPC matrix can be as shown in Table 8 above.

[0342] It should be noted that Tables 9 and 10 above are merely examples of the third matrix, and this application does not limit the size of the third matrix or the specific locations of the 0s and 1s included. For example, in a specific implementation, the size of the third matrix can be the same as that of the matrices shown in Tables 9 and 10, wherein some rows / columns of the matrices shown in Tables 9 and 10 are subsets of the third matrix, and the third matrix may also include rows / columns other than those in Tables 9 or 10. Alternatively, the size of the third matrix can also be larger than that of the matrices shown in Tables 9 and 10, wherein the matrices shown in Tables 9 and 10 are subsets of the third matrix, or some rows / columns of the matrices shown in Tables 9 and 10 are subsets of the third matrix.

[0343] Since the position of the punctured bits has a significant impact on encoding and decoding in low-complexity scenarios, this application improves the rationality of the LDPC matrix under different bitrates by modifying the punctured columns (i.e., the first column set mentioned above) of the LDPC matrix according to the bitrate. This results in better encoding performance under different bitrates and can bring significant gains to encoding and decoding performance.

[0344] It is understood that, in order to achieve the functions in the above embodiments, the device includes hardware structures and / or software modules corresponding to each function. Those skilled in the art should readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0345] Figure 9 and Figure 10This is a schematic diagram of the possible communication devices provided in the embodiments of this application. These communication devices can be used to implement the functions of the first device and / or the second device in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments. The first device and / or the second device can be referred to the description in the above method embodiments, and will not be repeated here. For example, the device can be used to implement... Figure 8 The function of the first device in the process shown, or its purpose in implementing... Figure 8 The function of the second device in the process shown.

[0346] Figure 9 The communication device 1600 shown includes a processing unit 1610 and a transceiver unit (or communication unit) 1620. The communication device 1600 is used to implement the functions of the first device and / or the second device in the above method embodiments. The transceiver unit may include a sending unit and a receiving unit, respectively used for sending and receiving.

[0347] by Figure 8 Taking the illustrated process as an example, the communication device 1600 can be used to implement... Figure 8 In the method embodiment shown, the first device functions as follows: specifically, the processing unit 1610 can be used to process a first region of the first LDPC matrix according to a first rule and to encode information bits according to the second LDPC matrix. For details, please refer to... Figure 8 The corresponding description of the process; the transceiver unit 1620 can be used to send the codeword bit sequence.

[0348] In one possible implementation, when processing unit 1610 processes the first region of the first LDPC matrix according to the first rule, it may specifically modify the positions and / or translation values ​​of 0 / 1 in the first region according to the first rule.

[0349] In one possible implementation, when the transceiver unit 1620 modifies the position and / or shift value of 0 / 1 in the first region according to the first rule, it can specifically determine the row index i according to the first code rate, where i is a non-negative integer less than the total number of rows of the first LDPC matrix; and modify the position and / or shift value of 0 / 1 in the row with row index i in the first region according to the first rule.

[0350] In one possible implementation, when the transceiver unit 1620 determines the row index i based on the first code rate, it can specifically determine the row index i based on the code rate range in which the first code rate is located.

[0351] In one possible implementation, when the transceiver unit 1620 modifies the position and / or shift value of 0 / 1 in the first region according to the first rule, it can specifically determine the row index i according to the first code length and the length of the information bit, where i is a non-negative integer less than the total number of rows of the first LDPC matrix; and modify the position and / or shift value of 0 / 1 in the row with row index i in the first region according to the first rule.

[0352] Communication device 1600 can also be used to achieve Figure 8 In the illustrated method embodiment, the second device functions as follows: specifically, the communication unit 1620 can be used to receive first information. The processing unit 1610 can be used to process a first region of the first LDPC matrix according to a first rule and to decode the first information according to the second LDPC matrix. For details, please refer to [link to relevant documentation]. Figure 8 The corresponding description of the process.

[0353] In one possible implementation, when processing unit 1610 processes the first region of the first LDPC matrix according to the first rule, it may specifically modify the positions and / or translation values ​​of 0 / 1 in the first region according to the first rule.

[0354] In one possible implementation, when the transceiver unit 1620 modifies the position and / or shift value of 0 / 1 in the first region according to the first rule, it can specifically determine the row index i according to the first code rate, where i is a non-negative integer less than the total number of rows of the first LDPC matrix; and modify the position and / or shift value of 0 / 1 in the row with row index i in the first region according to the first rule.

[0355] In one possible implementation, when the transceiver unit 1620 determines the row index i based on the first code rate, it can specifically determine the row index i based on the code rate range in which the first code rate is located.

[0356] In one possible implementation, when the transceiver unit 1620 modifies the position and / or shift value of 0 / 1 in the first region according to the first rule, it can specifically determine the row index i according to the first code length and the length of the information bit, where i is a non-negative integer less than the total number of rows of the first LDPC matrix; and modify the position and / or shift value of 0 / 1 in the row with row index i in the first region according to the first rule.

[0357] For a more detailed description of the processing unit 1610 and the transceiver unit 1620, please refer directly to the description of the process steps and their related features in the above method embodiments, which will not be repeated here.

[0358] Figure 9 The communication device 1700 shown includes a processor 1710 and an interface circuit 1720. The processor 1710 and the interface circuit 1720 are coupled to each other. It is understood that the interface circuit 1720 can be a transceiver or an input / output interface. Optionally, the communication device 1700 may also include a memory 1730 for storing instructions executed by the processor 1710, or storing input data required by the processor 1710 to execute instructions, or storing data generated after the processor 1710 executes instructions.

[0359] When the communication device 1700 is used to implement the above method embodiment, the processor 1710 is used to implement the function of the processing unit 1610, and the interface circuit 1720 is used to implement the function of the transceiver unit 1620.

[0360] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), microprocessors without interlocked piped stages architecture (MIPS), reduced instruction set computers (RISC) machines (ARM), network processors (NPs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0361] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disk, portable hard disk, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Furthermore, the ASIC can reside in a first communication device (or first device) or a second communication device (or second device). Alternatively, the processor and storage medium can exist as discrete components in the first communication device (or first device) or the second communication device (or second device).

[0362] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. A computer program is a set of instructions that directs each step of an action of an electronic computer or other device having a first communication device and / or a second communication device. It is typically written in a programming language and runs on a target architecture. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed, in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; or an optical medium, such as a digital video optical disc; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be volatile or non-volatile, or may include both types.

[0363] Based on the same technical concept, embodiments of this application also provide a computer-readable storage medium, including a program or instructions, which, when run on a computer, cause the methods in the above method embodiments to be executed.

[0364] Based on the same technical concept, embodiments of this application also provide a computer program product, including instructions that, when run on a computer, cause the methods in the above method embodiments to be executed.

[0365] Based on the same technical concept, embodiments of this application also provide a communication system, including a first device and a second device. Taking the system including a first device and a second device as an example, the first device can achieve... Figure 8 The method shown allows the second device to achieve... Figure 8 The method shown.

[0366] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, or optical storage) containing computer-usable program code.

[0367] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0368] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

Claims

1. A communication method, characterized in that, include: The first region of the first low-density parity-check LDPC matrix is ​​processed according to the first rule to obtain the second LDPC matrix. The first rule is related to the first code rate, or the first rule is related to the following parameters: the first code length and the length of the information bits. The first region includes the first set of columns of the first LDPC matrix. The first set of columns consists of columns with column indices from 0 to X-1 of the first LDPC matrix, or the first set of columns consists of the X column with the largest column weight in the first LDPC matrix, or the first set of columns consists of the X columns corresponding to the bits in the first LDPC matrix that participate in encoding, do not enter the circular buffer, and are not transmitted. X is a positive integer less than or equal to the total number of columns of the first LDPC matrix. The information bits are encoded according to the second LDPC matrix to obtain the codeword bit sequence; Send the codeword bit sequence.

2. A communication method, characterized in that, include: Receive the first message; The first region of the first low-density parity-check LDPC matrix is ​​processed according to the first rule to obtain the second LDPC matrix. The first rule is related to the first code rate, or the first rule is related to the following parameters: the first code length and the length of the information bits. The first region includes the first set of columns of the first LDPC matrix. The first set of columns consists of columns with column indices from 0 to X-1 of the first LDPC matrix, or the first set of columns consists of the X column with the largest column weight in the first LDPC matrix, or the first set of columns consists of the X columns corresponding to the bits in the first LDPC matrix that participate in encoding, do not enter the circular buffer, and are not transmitted. X is a positive integer less than or equal to the total number of columns of the first LDPC matrix. The first information is decoded based on the second LDPC matrix.

3. The method as described in claim 1 or 2, characterized in that, The processing of the first region of the first LDPC matrix according to the first rule includes: The positions and / or translation values ​​of 0 / 1 in the first region are modified according to the first rule.

4. The method as described in claim 3, characterized in that, The modification of the position and / or translation value of 0 / 1 in the first region according to the first rule includes: The row index i is determined based on the first code rate, where i is a non-negative integer less than the total number of rows in the first LDPC matrix; According to the first rule, the positions of 0 / 1 and / or shift values ​​in the row with row index i in the first region are modified.

5. The method as described in claim 4, characterized in that, Determining the row index i based on the first code rate includes: The row index i is determined based on the bitrate range in which the first bitrate is located.

6. The method as described in claim 5, characterized in that, If the first bitrate is within the bitrate range Then the row index i is row-1, where a is the number of columns of the information column of the first LDPC matrix.

7. The method as described in claim 3, characterized in that, The modification of the position and / or translation value of 0 / 1 in the first region according to the first rule includes: The row index i is determined based on the first code length and the length of the information bits, where i is a non-negative integer less than the total number of rows in the first LDPC matrix; According to the first rule, the positions of 0 / 1 and / or shift values ​​in the row with row index i in the first region are modified.

8. The method as described in claim 7, characterized in that, The row index i satisfies the following formula: Where ceil() is the floor function, Zc is the smallest lift value in the set of lift values ​​that satisfy a*Zc≥K, a is the number of columns of the information column of the first LDCP matrix, K is the length of the information bits, and N is the first code length.

9. The method according to any one of claims 4-8, characterized in that, The first rule includes: Replace the row with row index i in the first LDPC matrix with the row with row index i in the third matrix; The third matrix has the same size as the first LDPC matrix, the second region in the third matrix has different positions and / or translation values ​​of 0 / 1 compared to the first region, and the third region in the third matrix has the same positions and translation values ​​of 0 / 1 compared to the fourth region in the first LDPC matrix. The relative position of the second region in the third matrix is ​​the same as the relative position of the first region in the first LDPC matrix. The third region is the complement of the second region, and the fourth region is the complement of the first region.

10. The method as described in claim 9, characterized in that, The step of replacing the row with row index i in the first LDPC matrix with the row with row index i in the third matrix includes: If the row with row index i does not belong to the first row set, then the row with row index i in the first LDPC matrix is ​​replaced with the row with row index i in the third matrix, and the first row set includes at least one row of the first LDPC matrix.

11. The method as described in claim 10, characterized in that, The first LDPC matrix is ​​5GBG1, and the first row set includes at least one of the following rows: the row with row index 6 in the first LDPC matrix, or the row with row index 10 in the first LDPC matrix.

12. The method as described in claim 11, characterized in that, The positions of 1 in the third matrix include: The row index is 0, and the column indexes are 0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, 23; The row index is 1, and the column indexes are 0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, 24; The row index is 2, and the column indexes are 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, 25; The row index is 3, and the column indexes are 0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, 25; The row index is 4, and the column indexes are 1 and 26. The row index is 5, and the column indexes are 1, 3, 12, 16, 21, 22, and 27. The row index is 6, and the column indexes are 0, 6, 10, 11, 13, 17, 18, 20, and 28. The row index is 7, and the column indexes are 1, 4, 7, 8, 14, and 29. The row index is 8, and the column indexes are 1, 3, 12, 16, 19, 21, 22, 24, and 30. The row index is 9, and the column indexes are 1, 10, 11, 13, 17, 18, 20, and 31. The row index is 10, and the column indexes are 1, 2, 4, 7, 8, 14, and 32. The row index is 11, and the column indexes are 0, 12, 16, 21, 22, 23, and 33. The row index is 12, and the column indexes are 1, 10, 11, 13, 18, and 34. The row index is 13, and the column indexes are 0, 3, 7, 20, 23, and 35. The row index is 14, and the column indexes are 0, 12, 15, 16, 17, 21, and 36. The row index is 15, and the column indexes are 1, 10, 13, 18, 25, and 37.

13. The method according to any one of claims 4-8, characterized in that, The first rule includes: Delete at least one 0 / 1 position in the row with row index i in the first region.

14. The method according to any one of claims 4-13, characterized in that, The first rule includes: Add one or more 1 positions to the second row set of the first LDPC matrix.

15. The method as described in claim 14, characterized in that, The second row set includes the row with row index 4 and / or the row with row index 5 in the first LDPC matrix.

16. The method according to any one of claims 1-15, characterized in that, The first region is the region consisting of all rows of the first column set and the first LDPC matrix; Alternatively, the first region may be a region consisting of the first set of columns and the row corresponding to the first code rate in the first LDPC matrix.

17. The method as described in claim 16, characterized in that, The row index (row) of the row corresponding to the first bit rate R satisfies the following formula: Wherein, a is the number of information columns in the first LDPC matrix, and X is the number of columns included in the first column set; Alternatively, the row index (row) of the row corresponding to the first bit rate R satisfies the following formula: Wherein, Zc is the smallest lift value in the set of lift values ​​that satisfy a*Zc≥K, a is the number of information columns in the first LDPC matrix, K is the length of the information bits, and N is the first code length.

18. A communication device, characterized in that, It includes a module for performing the method as described in any one of claims 1, 3-17, or includes a module for performing the method as described in any one of claims 2-17.

19. A communication device, characterized in that, The communication device includes at least one processor, the at least one processor being configured to cause the method as described in any one of claims 1, 3-17 to be executed by the communication device, or the at least one processor being configured to cause the communication device to execute the method as described in any one of claims 2-17.

20. A chip or chip system, characterized in that, The chip or chip system includes: At least one processor and an interface, the at least one processor being configured to call and execute instructions from the interface, wherein when the at least one processor executes the instructions, the method as claimed in any one of claims 1, 3-17 is executed, or the method as claimed in any one of claims 2-17 is executed.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program that, when run on a computer, causes the method as described in any one of claims 1, 3-17 to be performed, or causes the method as described in any one of claims 2-17 to be performed.

22. A computer program product, characterized in that, The computer program product includes a computer program that, when run on a computer, causes the method as described in any one of claims 1, 3-17 to be performed, or causes the method as described in any one of claims 2-17 to be performed.

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