A bandwidth zero-IF receiver circuit and correction method with parameters adaptive to gain.

Abstract

This invention provides a bandwidth zero-IF receiver circuit and correction method with parameters adaptive to gain. The circuit includes: a main signal path comprising a first branch, a second branch, a DC offset correction module, and a mirror rejection correction module. The radio frequency signal is received by an antenna, amplified, and then fed into the first and second branches respectively. The first and second branches generate two parallel baseband signals through a quadrature mixer to generate an interface signal that meets the board-level transmission requirements based on the two baseband signals. The DC offset correction module and the mirror rejection correction module are both connected to the first and second branches. A detection signal path is used to detect gain information in the main signal path. A control feedback path is used to dynamically adjust the gains of various parameters in the main signal path according to the gain information. This invention effectively reduces DC offset and mirror rejection performance, greatly expanding the application scenarios of on-chip zero-IF receivers.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a bandwidth zero intermediate frequency receiver circuit and correction method with parameters that adapt to gain. Background Technology

[0002] With the rapid development of information technology and mobile communication networks, decentralization has become a common network deployment evolution approach to increase the system capacity of cellular networks. This involves replacing traditional macro base stations with densely deployed micro base stations, thereby effectively improving the spatial utilization of the spectrum. In the practical application of micro base station solutions, extremely stringent requirements are placed on the size, weight, and power consumption of base station equipment. To meet the design requirements of small size, low weight, and low power consumption, micro base stations are increasingly adopting a zero-IF transceiver architecture.

[0003] In a zero-IF receiver implemented on a single integrated circuit chip, the radio frequency signal is amplified by a low-noise amplifier and then directly down-converted to baseband via a mixer. However, due to limitations in semiconductor manufacturing processes and the non-ideal characteristics of circuit devices, zero-IF receivers face severe problems of direct current offset (DC offset) and image interference. DC offset can occupy the dynamic range of the analog-to-digital converter and even lead to link saturation; while the image signal introduced by the mismatch in amplitude and phase between the I-channel (in-phase) and Q-channel (quadrature) signals severely degrades the signal-to-noise ratio (SNR) of the received signal. Furthermore, DC offset also changes with gain. Summary of the Invention

[0004] This invention provides a bandwidth zero-IF receiver circuit and correction method with parameters that adapt to gain, in order to solve the technical problems of poor DC offset and image rejection performance in existing zero-IF receivers within a large signal bandwidth and high gain dynamic range, as well as the slow correction speed caused by the inability of correction parameters to dynamically match the gain.

[0005] This invention provides a bandwidth zero-IF receiver circuit with parameters that adapt to gain, the circuit comprising: The main signal path includes a first branch, a second branch, a DC offset correction module, and a mirror rejection correction module. The radio frequency signal is received by the antenna and amplified before being transmitted to the first branch and the second branch respectively. The first branch and the second branch generate two parallel baseband signals through an orthogonal mixer to generate an interface signal that meets the board-level transmission requirements based on the two baseband signals. The DC offset correction module and the mirror rejection correction module are both connected to the first branch and the second branch. A detection signal path is used to detect gain information in the main signal path; and, A control feedback path is used to dynamically adjust the gains of various components of the main signal path based on the gain information. The DC offset correction module and the image suppression correction module determine the corresponding DC offset correction code and image suppression correction code according to the gain information, respectively, so as to reduce the DC offset of the main signal path and suppress the image signal according to the DC offset correction code and the image suppression correction code.

[0006] In one embodiment of the present invention, the first branch includes a first mixer, a first analog baseband signal link, and a first digital baseband signal link cascaded in sequence; the second branch includes a second mixer, a second analog baseband signal link, and a second digital baseband signal link cascaded in sequence, wherein the first mixer and the second mixer constitute the quadrature mixer.

[0007] In one embodiment of the present invention, the circuit structure of the first analog baseband signal link and the second analog baseband signal link are the same. The first analog baseband signal link includes a transimpedance amplifier, a low-pass filter, an analog-to-digital converter, and a correction digital-to-analog converter cascaded at the input of the transimpedance amplifier in sequence. The correction digital-to-analog converter is used to convert the DC offset correction code corresponding to the radio frequency signal into an analog signal and add it to the link. The low-pass filter receives the image rejection correction code corresponding to the radio frequency signal to filter out the corresponding image signal.

[0008] In one embodiment of the present invention, the first digital baseband signal link includes a first filter chain, a delay unit, a first digital gain unit and a first digital adder cascaded in sequence. The first digital adder adds the DC offset correction code corresponding to the radio frequency signal to the link to reduce the DC offset introduced by the radio frequency signal.

[0009] In one embodiment of the present invention, the second digital baseband signal link includes a second filter chain, a mirror rejection filter, a second digital gain unit, and a second digital adder cascaded in sequence. The second digital adder adds a DC offset correction code corresponding to the radio frequency signal to the link to reduce the DC offset introduced by the radio frequency signal. The mirror rejection filter receives the mirror rejection correction code corresponding to the radio frequency signal to filter out the mirror signal corresponding to the radio frequency signal.

[0010] In one embodiment of the present invention, the image suppression filter is used to perform filtering based on the phase mismatch information and amplitude mismatch information contained in the image suppression correction code.

[0011] In one embodiment of the present invention, multiple detection points are provided on two branches of the main signal path, and detection signals are obtained from each detection point through the detection signal path. The detection points are respectively set on the analog baseband signal link and the digital baseband signal link of each branch, and each detection point can detect one or more outputs.

[0012] In one embodiment of the present invention, the circuit includes a reset state, a calibration state, an idle state, and / or a radio frequency operating state.

[0013] In one embodiment of the present invention, when the circuit is in the calibration state, it performs DC offset and image rejection calibration by traversing all gain values ​​and stores the calibration results in a lookup table. When the circuit is in the RF operating state, it can look up the corresponding DC offset value and image rejection value according to the gain value of the current link to complete the corresponding calibration.

[0014] The present invention also provides a correction method for a bandwidth zero-IF receiver circuit with parameters that adapt to gain, comprising: switching the bandwidth zero-IF receiver circuit to RF operating state and obtaining the current gain value; retrieving the corresponding DC offset value and image rejection value from a lookup table according to the current gain value to correct the DC offset and image rejection in the RF operating state, thereby obtaining a correction result; wherein the correction result is used to characterize the correspondence between the gain value and the DC offset value and the image rejection value, and the correction result is obtained by traversing all gain values ​​in the correction state to perform DC offset and image rejection correction.

[0015] The beneficial effects of this invention are as follows: This invention proposes a bandwidth zero-IF receiver circuit and correction method with parameters that adapt to gain. By introducing gain-related DC offset correction and image rejection correction into the analog baseband signal path and digital baseband signal path of the zero-IF receiver, and through joint correction at the RF end (analog domain) and the baseband end (digital domain), large signal offset is canceled at the physical layer and fine compensation is performed at the digital layer. This effectively improves the technical defects of traditional zero-IF receivers, such as large DC offset and poor image rejection performance in wide bandwidth and high gain dynamic change scenarios, and improves the overall quality of the received signal. In a large signal bandwidth and high gain range, it effectively reduces DC offset and image rejection performance, greatly expanding the application scenarios of on-chip zero-IF receivers. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1 This is a schematic diagram of the circuit architecture of a bandwidth zero-IF receiver circuit with parameters that adapt to gain, provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the circuit architecture of an analog baseband signal processing link provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit architecture of a digital baseband signal processing link for channel I in one embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit architecture of the Q-channel digital baseband signal processing link in one embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit principle of a mirror rejection filter in one embodiment of the present invention; Figure 6 This is a flowchart illustrating a correction method for a bandwidth zero-IF receiver circuit with parameters that adapt to gain, according to an embodiment of the present invention. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0021] This application provides a broadband zero-IF receiver circuit with parameters that adapt to gain. It is mainly used in the field of radio frequency transceiver integrated circuit design and aims to solve the technical problems of poor DC offset and image rejection in existing zero-IF receivers within a large signal bandwidth and high gain dynamic range, and slow correction speed caused by the inability of correction parameters to dynamically match the gain.

[0022] The inventors discovered that a common approach to increasing cellular network capacity is decentralization, replacing traditional macro base stations with micro base stations to improve spectrum utilization. However, micro base station solutions place higher demands on base station size, weight, and power consumption. To address the issues of small size, low weight, and low power consumption, micro base stations are increasingly adopting zero-IF transceiver architectures. However, in monolithically implemented zero-IF receivers, due to process limitations, the receiver's DC offset and image rejection performance is poor. Therefore, a new zero-IF receiver architecture is needed to improve DC offset and image rejection performance. Traditional zero-IF receiver architectures use a single correction method, improving DC offset and image rejection performance only within a narrow, fixed-gain range. As signal bandwidth increases and gain dynamically changes, the performance of traditional zero-IF receiver architectures deteriorates, failing to meet the requirements of modern wireless communication systems and significantly limiting the application scenarios of zero-IF receivers.

[0023] In view of the problems existing in the prior art, the present invention provides a broadband zero-IF receiver circuit and correction method with parameters adaptive to gain. The technical solution of the present invention will be described in detail below with reference to specific embodiments.

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of the circuit architecture of a broadband zero-IF receiver in one embodiment of the present invention. The architecture of this embodiment includes a low-noise amplifier (LNA), a mixer, an analog baseband signal link, a digital baseband signal link, an interface circuit, an enable state machine (ENSM), an automatic gain control circuit (AGC controller), a DC offset correction module (including RF DC offset correction and BB DC offset correction), and a mirror rejection correction module (including RF QEC (Radio Frequency Quadrature Error Correction) and BB QEC (Baseband Quadrature Error Correction)).

[0025] The proposed broadband receiver circuit architecture is functionally divided into four parts: signal receiving link, gain control, received signal performance optimization algorithm, and state control. The signal receiving link implements wireless signal reception and amplification within the chip; the gain control section adjusts the receiving link gain in real time based on a set threshold and the power of the received wireless signal; the received signal performance optimization algorithm detects the quality of the received signal and processes it to improve the quality of the received signal. The receiver state machine control circuit divides the receiver's operation into several defined states, providing logic control signals to other modules according to different states, thereby controlling the receiver to achieve high-quality signal reception.

[0026] In one embodiment, Figure 1 The wideband zero-IF receiver circuit shown includes a main signal path, a detection signal path, and a control feedback path. The main signal path includes a first branch, a second branch, a DC offset correction module, and a mirror rejection correction module. The radio frequency signal is received by the antenna, amplified, and then fed into the first and second branches respectively. The first and second branches generate two parallel baseband signals through a quadrature mixer to generate an interface signal that meets the board-level transmission requirements based on the two baseband signals. The DC offset correction module and the mirror rejection correction module are both connected to the first and second branches. The detection signal path is used to detect the gain information in the main signal path. The control feedback path is used to dynamically adjust the gain of each component of the main signal path according to the gain information. The DC offset correction module and the mirror rejection correction module determine the corresponding DC offset correction code and mirror rejection correction code according to the gain information, so as to reduce the DC offset of the main signal path and suppress the mirror signal.

[0027] In one embodiment, the first branch includes a first mixer, a first analog baseband signal link, and a first digital baseband signal link cascaded in sequence. The second branch includes a second mixer, a second analog baseband signal link, and a second digital baseband signal link cascaded in sequence, wherein the first mixer and the second mixer constitute the quadrature mixer. In the main signal path: the radio frequency (RF) signal after passing through the antenna enters the receiver, and is then amplified by a low-noise amplifier (LNA); then it passes through an I / Q mixer, realizing the conversion from RF to baseband analog signal. After the I / Q mixer, the RF signal is transformed from a single RF signal into two orthogonal baseband analog signals (i.e., the aforementioned baseband signals). Due to varying degrees of non-ideal factors during integrated circuit implementation, the I / Q signals are not strictly orthogonal, causing a mismatch between the I and Q signals, introducing a mirror signal into the received signal. The I / Q analog baseband signals are processed by their respective analog baseband signal chains before being fed into the digital baseband signal chain. After passing through the digital baseband signal chain, the signals are sent to the interface circuit (IO interface). After being shaped by the interface circuit, an interface signal (IO signal) suitable for board-level transmission is generated and sent to the receiver chip. In the proposed receiver circuit, the I / Q analog baseband signal chains are implemented identically; however, the I and Q channels require different implementation methods for the digital baseband signal chains.

[0028] In one embodiment, on the detection signal path: a portion of the detection signal provides gain information to the gain control module; a portion of the detection signal provides signal quality information to the performance optimization algorithms (DC offset correction algorithm, image rejection correction algorithm). Multiple detection points are set on the two branches of the main signal path. Detection signals are obtained from each of these detection points through the detection signal path. These detection points are respectively set on the analog baseband signal link and digital baseband signal link of each branch, and each detection point can detect one or more outputs. The detection signal path draws detection signals from the analog baseband signal link and digital baseband signal link corresponding to the two branches of the main signal path. These detection signals include information such as signal amplitude, power, DC component, I / Q signal amplitude mismatch, and phase mismatch. The control feedback path receives these detection signals and outputs gain control signals (such as INA gain, mixer gain, analog gain, digital gain) to the main signal path to achieve dynamic adjustment of the gain of each stage of the circuit. Specifically, the broadband zero-IF receiver circuit has one or more detection points to provide gain information for the receiving link. The first gain detection point is located in the analog baseband signal link. This point outputs a detection signal, analog det, which provides gain information before the ADC (Analog-to-Digital Converter). The second gain detection point is located in the digital baseband signal link. This point outputs a detection signal, digital det, which provides gain information after the ADC. Both the analog det and digital det detection signals are fed into the feedback control path. The feedback control path is based on an automatic gain control algorithm, controlling the gain of the receiving link according to the different states of the analog det and digital det. The analog and digital baseband signal links are implemented differently, and the analog det and digital det detection signals can have multiple outputs. When the signal link is implemented in multiple stages, the output signals of analog det and digital det can be output by each stage, or multiple stages can output a single signal. The detection points used for the performance optimization algorithm are derived from the I-channel and Q-channel digital baseband signal links, respectively, and are designated I_sig_BB and Q_sig_BB. The I / Q detection signals carry information about the DC offset and I / Q mismatch of the received signal. These two signals are sent to the signal quality enhancement circuit, where algorithms improve the DC offset and image rejection parameters of the received signal. The signal quality enhancement circuit incorporates a DC offset correction algorithm and an image rejection correction algorithm, corresponding to the DC offset correction module and the image rejection correction module, respectively. These two algorithms improve the DC offset and image rejection parameters of the received signal.DC offset correction algorithms include radio frequency (RF) DC offset correction (RF DCOC) and baseband DC offset correction (BB DCOC). The RF DC offset correction algorithm reduces the DC value originating from the radio frequency component; the baseband DC offset correction algorithm reduces the DC value originating from the baseband component. These two DC offset correction algorithms together reduce the overall DC offset of the received signal.

[0029] The RF DC offset correction algorithm inputs control codewords ICODE_RF_DCOC and QCODE_RF_DCOC to the I / Q analog baseband signal processing links based on the detected signal DC offset value. These control codewords control the corresponding analog execution units (such as correction DACs (Digital-to-Analog Converters)) to correct the DC value introduced by the RF section. To improve the correction speed during normal receiver operation, the proposed circuit structure utilizes a look-up table (LUT) to store different ICODE_RF_DCOC and QCODE_RF_DCOC values. These values ​​correspond to different link gains. Before the receiver circuit receives the useful signal, the RF DC offset correction algorithm iterates through all possible gains, corrects the links, obtains the ICODE_RF_DCOC and QCODE_RF_DCOC values ​​corresponding to each gain, and stores these values ​​in the look-up table. The address of the look-up table is the index of each gain, and the content corresponding to each address in the look-up table is the DC offset correction codeword. When the receiving circuit is in normal operating mode under the control of the ENSM (Enable State Machine), the circuit uses the current link gain to look up the LUT (Local Underlying Transmission Unit) and obtains the ICODE_RF_DCOC and QCODE_RF_DCOC values ​​that match the current link gain. The baseband DC offset correction algorithm inputs the control codes ICODE_BB_DCOC and QCODE_BB_DCOC to the I / Q digital baseband signal processing links respectively, based on the detected signal DC offset value. The baseband digital signal processing circuit adds these control codes to the corresponding received signal, thereby correcting the offset value introduced by the baseband section.

[0030] In one embodiment, the image rejection correction algorithm includes a radio frequency (RF) image rejection correction algorithm (RF QEC) and a baseband image rejection correction algorithm (BB QEC). The RF QEC reduces image signals caused by the radio frequency portion of the received RF signal; the BB QEC reduces image signals caused by the baseband portion of the RF signal.

[0031] The RF image suppression correction algorithm inputs control codes ICODE_RF_QEC and QCODE_RF_QEC into the I / Q analog baseband signal processing links based on the detected image signal. These control codes control the corresponding analog execution units (e.g., the capacitor array of the baseband filter) to correct the image signal introduced by RF section mismatch. To improve the correction speed during normal receiver operation, the proposed circuit structure uses a lookup table (LUT) to store different ICODE_RF_QEC and QCODE_RF_QEC values. These values ​​correspond to different link gains. Before the receiver circuit receives the useful signal, the RF image suppression correction algorithm iterates through all possible gains, corrects the links, obtains the ICODE_RF_QEC and QCODE_RF_QEC values ​​corresponding to each gain, and stores these values ​​in the lookup table. The address of the lookup table is the index of each gain, and the content corresponding to each address is the image suppression correction codeword. When the receiving circuit is in normal operating mode under ENSM control, it uses the current link gain to find the LUT (Local Underlying Transmission Unit) and obtains the ICODE_RF_QEC and QCODE_RF_QEC values ​​that match the current link gain. The baseband image rejection correction algorithm inputs the control codewords ICODE_BB_QEC and QCODE_BB_QEC into the I / Q digital baseband signal processing links respectively, based on the detected image signal. The I / Q baseband digital signal processing circuits process ICODE_BB_QEC and QCODE_BB_QEC separately, thereby reducing the image signal in the received signal caused by the mismatch in the baseband processing circuit.

[0032] In one embodiment, the feedback control path includes: a portion of the control signals acting on the main signal path gain control module to control the gain of the main signal path; and a portion of the control signals acting on the main signal path algorithm correction module to improve the quality of the received signal. The feedback control path includes an Automatic Gain Control (AGC) controller. Based on the detected signal power and / or amplitude, and in conjunction with a gain control algorithm, the AGC controller controls the gain of corresponding units in the receiving link through gain control signals, thereby dynamically adjusting the receiving link gain. The gain control signals include: LNA gain, mixer gain, analog gain, and digital gain. These control signals respectively control the gain of the low-noise amplifier, mixer, analog baseband signal link, and digital baseband signal link. Depending on the circuit implementation, only one or more of these signals may be needed. Depending on the implementation of the analog and digital baseband signal links, the analog gain and digital gain signals can be multiple signals. When the analog baseband signal link is implemented in a multi-stage cascaded manner, the analog gain can be multiple signals to control the gain of one or more stages; when the digital baseband signal link is implemented in a multi-stage cascaded manner, the digital gain can be multiple signals to control the gain of one or more stages.

[0033] In one embodiment, the DC offset correction module includes an RF DC offset correction unit and a baseband digital DC offset correction unit. The image rejection correction unit includes an RF image rejection correction unit and a baseband image rejection correction unit. A lookup table is used to store DC offset correction codes and image rejection correction codes corresponding to different link gains. When the circuit is in the correction state, it performs DC offset and image rejection correction by traversing all gain values ​​and stores the correction results in the lookup table. When the circuit is in the RF operating state, it retrieves the corresponding DC offset correction code and image rejection correction code based on the current link gain value to complete the corresponding correction. Specifically, the receiver's ENSM is configured with a correction state and an RF operating state. In the correction state, the ENSM controls the receiver to traverse all gain values ​​to perform DC offset and image rejection correction and stores the generated DC offset correction code and image rejection correction code along with the corresponding gain index in the lookup table. In the RF operating state, the ENSM uses the current link gain as an index to search the lookup table, directly retrieves and outputs the corresponding DC offset correction code and image rejection correction code. This mechanism eliminates the need for recalculation during normal RF operation, enabling rapid DC offset correction and image rejection correction, and significantly improving correction speed.

[0034] In other embodiments, the receiver's operating states may also include a reset state and an idle state to improve the receiver's power consumption and logic control throughout its entire lifecycle.

[0035] In one embodiment, by introducing gain-related DC offset correction and image rejection correction circuits and algorithms into the analog baseband signal link and the digital baseband signal link, and combining them with a lookup table mechanism, adaptive adjustment of parameters with gain is achieved. This lookup table-based adaptive closed-loop architecture avoids the problem of algorithm re-convergence during gain switching in traditional schemes, and achieves fast DC offset correction and image rejection correction. It effectively improves the technical defects of traditional zero-IF receivers in wideband, high-gain dynamic change scenarios, such as large DC offset and poor image rejection performance.

[0036] like Figure 2 As shown, in some embodiments, the circuit structure of the first analog baseband signal link and the second analog baseband signal link is the same. The first analog baseband signal link includes a transimpedance amplifier (TIA), a low-pass filter (LPF), an analog-to-digital converter (RXADC), and a correction digital-to-analog converter (DCOC DAC) cascaded at the input of the transimpedance amplifier. The correction DCOC DAC is used to convert the DC offset control codeword corresponding to the radio frequency signal into an analog signal and add it to the link. The low-pass filter (LPF) receives the image rejection correction code corresponding to the radio frequency signal to filter out the corresponding image signal. Specifically, the radio frequency DC offset control codeword (i.e., DC offset correction code) output by the DC offset correction module is input to the DC offset correction digital-to-analog converter, and the DC offset value brought by the radio frequency section is canceled by the current or voltage output by the converter. The RF image suppression control codeword (i.e. image suppression correction code) output by the image suppression correction module is input to the low-pass filter LPF, which controls the capacitor array inside it. By changing the amplitude and phase frequency characteristics of the I / Q channels, it corrects the amplitude mismatch and phase mismatch caused by I / Q imbalance, thereby reducing the image signal component at the physical layer.

[0037] In one embodiment, a peak detector is connected to the output of a low-pass filter (LPF) to output an analog detection signal (analog det) to the control feedback path. When the analog baseband signal link is implemented in a multi-stage cascaded manner, the analog gain includes a transimpedance amplifier gain control signal (TIA_gain) and a low-pass filter gain control signal (LPF_gain), which control the transimpedance amplifier (TIA) and the low-pass filter (LPF) respectively, achieving multi-stage fine-grained gain control of the analog baseband.

[0038] like Figure 3 As shown, in some embodiments, the first digital baseband signal link includes a first filter chain Filter Chain 1, a delay unit Delay, a first digital gain unit DIG Gain 1, a first digital adder, and a second filter chain Filter Chain 2, cascaded in sequence. The first digital adder adds the DC offset correction code corresponding to the baseband signal to the link to reduce the DC offset introduced by the baseband signal. Specifically, the I-channel control codeword ICODE_BB_DCOC output by the baseband digital DC offset correction unit is input to the first digital adder and algebraically added to the signal after gain adjustment, thereby accurately compensating for the residual DC offset introduced by the baseband portion. A peak detector and a power measurement detector are located at both the input and output of the first filter chain Filter Chain 1. The peak detector detects the amplitude value of the received signal and outputs signals digital_det1 and digital_det2. These two signals are sent to the automatic gain control module for use by the automatic gain control algorithm. The gain control signal digital gain generated by the automatic gain control module serves as an input to the first digital gain unit DIG Gain 1, controlling the gain of the received signal. In implementation, the digital gain can be in logarithmic or linear domain form. The control codeword ICODE_BB_DCOC generated from the DC offset correction module is used as an input to the adder to correct the DC offset value in the I-channel received signal.

[0039] like Figure 4 As shown, in some embodiments, the second digital baseband signal link includes a third filter chain 3, a QEC filter, a second digital gain unit (DIG Gain 2), a second digital adder, and a fourth filter chain 4, cascaded in sequence. The second digital adder adds the DC offset correction code corresponding to the baseband signal to the link to reduce the DC offset introduced by the baseband signal. The image rejection filter receives the image rejection correction code corresponding to the baseband signal to filter out the corresponding image signal. Specifically, the Q-channel control codeword QCODE_BB_DCOC (i.e., the DC offset correction code) output by the baseband digital DC offset correction unit is input to the second digital adder. The control signal QCODE_BB_QEC (i.e., the image rejection correction code) output by the baseband image rejection correction unit is input to the image rejection filter to correct the image rejection of the received signal.

[0040] In one embodiment, the second digital baseband signal link consists of a third filter chain 3, a mirror correction filter (QEC filter), a second digital gain unit (DIG Gain 2), a second digital adder, a peak detector, a power measurement detector, and a fourth filter chain 4. The digital signal output from the RX ADC is sent to the third filter chain 3. The third filter chain 3 has a peak detector and a power measurement detector at both its input and output. The peak detector detects the amplitude of the received signal and outputs signals digital_det3 and digital_det4, which are sent to the automatic gain control module for use by the automatic gain control algorithm. The gain control signal digital gain generated by the automatic gain control module serves as an input to the second digital gain unit, controlling the gain of the received signal. In implementation, digital gain can be in logarithmic or linear domain form. The control codeword QCODE_BB_DCOC generated from the DC offset correction module serves as an input to the second digital adder, correcting the DC offset value in the Q-channel received signal. The control signal QCODE_BB_QEC output from the image rejection correction module serves as the control signal for the image correction filter QEC, thereby correcting the image rejection of the received signal. In the circuit implementation, QCODE_BB_DCOC contains amplitude mismatch and phase mismatch information of the IQ received signals.

[0041] like Figure 5 As shown, in some embodiments, the image rejection filter (QEC filter) includes a phase mismatch compensation unit and an amplitude mismatch compensation unit. The control signal output by the baseband image rejection correction unit contains phase mismatch information. and amplitude mismatch information The phase mismatch compensation unit utilizes... Phase rotation compensation is performed on the signal, and the amplitude mismatch compensation unit utilizes... Amplitude scaling compensation is applied to the signal. By separating phase mismatch and amplitude mismatch and mathematically compensating for them separately, this structure achieves precise correction of I / Q imbalance, significantly improving the image rejection ratio.

[0042] In some embodiments, the gain control signal "digital gain" received by the first and second digital gain units is in logarithmic or linear domain form. When the digital baseband signal link is implemented in a multi-stage cascaded manner, the gain control signal "digital gain" includes multiple sub-signals, each controlling the gain of a specific stage. Furthermore, the second and fourth filter chains are configured to be reduced or bypassed according to bandwidth requirements to flexibly adapt to different communication scenarios.

[0043] Please see Figure 6 In one embodiment, this application also provides a correction method applied to a bandwidth zero-IF receiver circuit whose parameters adapt to gain, comprising: Step S600: Switch the broadband zero-IF receiver circuit to RF operating mode and obtain the current gain value; Step S610: Retrieve the corresponding DC offset value and image rejection value from the lookup table according to the current gain value, so as to correct the DC offset and image rejection under the RF operating state and obtain the correction result.

[0044] In one embodiment, the correction result is used to characterize the correspondence between the gain value, DC offset value, and image rejection value. The correction result is obtained by traversing all gain values ​​under the correction state to perform DC offset and image rejection correction. Gain information and signal quality information of the receiving link are obtained through the detection signal path; the link gain of the main signal path is dynamically adjusted by the automatic gain control module based on the gain information; the DC offset correction unit and image rejection correction unit are controlled by the ENSM to perform calibration operations according to the current operating state; during normal calibration operations, a pre-generated lookup table is searched using the current link gain as an index to obtain the matching DC offset correction code and image rejection correction code, and the DC offset correction code and image rejection correction code are used to jointly correct the analog baseband signal link and the digital baseband signal link, respectively. The specific execution process of this method has been described in detail in the aforementioned circuit embodiments and will not be repeated here.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bandwidth zero-IF receiver circuit with parameters adaptive to gain, characterized in that, The circuit includes: The main signal path includes a first branch, a second branch, a DC offset correction module, and a mirror rejection correction module. The radio frequency signal is received by the antenna and amplified before being transmitted to the first branch and the second branch respectively. The first branch and the second branch generate two parallel baseband signals through an orthogonal mixer to generate an interface signal that meets the board-level transmission requirements based on the two baseband signals. The DC offset correction module and the mirror rejection correction module are both connected to the first branch and the second branch. A detection signal path is used to detect gain information in the main signal path; and, A control feedback path is used to dynamically adjust the gains of various components of the main signal path based on the gain information. The DC offset correction module and the image suppression correction module determine the corresponding DC offset correction code and image suppression correction code according to the gain information, respectively, so as to reduce the DC offset of the main signal path and suppress the image signal according to the DC offset correction code and the image suppression correction code.

2. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 1, characterized in that, The first branch includes a first mixer, a first analog baseband signal link, and a first digital baseband signal link cascaded in sequence; the second branch includes a second mixer, a second analog baseband signal link, and a second digital baseband signal link cascaded in sequence, wherein the first mixer and the second mixer constitute the quadrature mixer.

3. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 2, characterized in that, The first analog baseband signal link has the same circuit structure as the second analog baseband signal link. The first analog baseband signal link includes a transimpedance amplifier, a low-pass filter, an analog-to-digital converter, and a correction digital-to-analog converter cascaded at the input of the transimpedance amplifier. The correction digital-to-analog converter is used to convert the DC offset correction code corresponding to the radio frequency signal into an analog signal and add it to the link. The low-pass filter receives the image rejection correction code corresponding to the radio frequency signal to filter out the corresponding image signal.

4. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 3, characterized in that, The first digital baseband signal link includes a first filter chain, a delay unit, a first digital gain unit, and a first digital adder cascaded in sequence. The first digital adder adds the DC offset correction code corresponding to the radio frequency signal to the link to reduce the DC offset introduced by the radio frequency signal.

5. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 4, characterized in that, The second digital baseband signal link includes a second filter chain, a mirror rejection filter, a second digital gain unit, and a second digital adder cascaded in sequence. The second digital adder adds the DC offset correction code corresponding to the radio frequency signal to the link to reduce the DC offset introduced by the radio frequency signal. The mirror rejection filter receives the mirror rejection correction code corresponding to the radio frequency signal to filter out the mirror signal corresponding to the radio frequency signal.

6. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 5, characterized in that, The image suppression filter is used to filter based on the phase mismatch information and amplitude mismatch information contained in the image suppression correction code.

7. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 5, characterized in that, Multiple detection points are set on the two branches of the main signal path. Detection signals are obtained from each detection point through the detection signal path. The detection points are respectively set on the analog baseband signal link and the digital baseband signal link of each branch. Each detection point can detect one or more outputs.

8. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 5, characterized in that, The circuit includes a reset state, a calibration state, an idle state, and / or an RF operating state.

9. The bandwidth zero-IF receiver circuit with parameters adaptive to gain according to claim 8, characterized in that, When the circuit is in the calibration state, it performs DC offset and image rejection correction by traversing all gain values ​​and stores the correction results in a lookup table. When the circuit is in the RF operating state, it can look up the corresponding DC offset and image rejection values ​​according to the gain value of the current link to complete the corresponding correction.

10. A correction method for a bandwidth zero-IF receiver circuit with parameters adaptive to gain as described in any one of claims 1-9, characterized in that, include: Switch the broadband zero-IF receiver circuit to RF operating mode and obtain the current gain value; The DC offset value and image rejection value are retrieved from the lookup table based on the current gain value to correct the DC offset and image rejection under RF operating conditions, and the correction result is obtained. The correction result is used to characterize the correspondence between the gain value, the DC offset value, and the image rejection value, and the correction result is obtained by traversing all gain values ​​in the correction state to perform DC offset and image rejection correction.

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