A Fast Privacy Magnification Method Based on Number Theory Transformation QKD

Abstract

This invention discloses a fast privacy amplification method for QKD based on number theory transformations. It reshapes the initial key vector and the Toeplitz matrix generation vector into a first matrix and a second matrix with the same number of rows and columns based on row and column decomposition. NTT operations are then performed on the corresponding column vectors of both matrices. Each data point is multiplied by its corresponding row and column rotation factor. The corresponding row vectors are traversed, and a radix-r butterfly operation unit is called to perform a butterfly operation once, followed by dot multiplication and modular reduction. A radix-r butterfly operation unit is called to perform a butterfly operation on the row vectors in the modular reduction result matrix, and then an INTT operation is performed on each column vector in the butterfly operation result matrix. The final key is then obtained by recombining the results. This invention uses finite-field integer NTT operations to avoid floating-point errors. Through radix-r butterfly unit reuse and matrix-parallel architecture, it achieves high-throughput privacy amplification with low hardware resource consumption while ensuring absolute computational accuracy, meeting the real-time processing requirements of high-speed QKD systems.

Description

Technical Field

[0001] This invention relates to the intersection of quantum key distribution (QKD) and cryptography, and in particular to a fast privacy amplification method for QKD based on number theory transformation (NTT), which is applicable to high-speed QKD systems based on FPGA hardware acceleration platforms. Background Technology

[0002] In a QKD system, legitimate communicating parties obtain an initial key of the same length as the original key through steps such as quantum state transmission, basis vector comparison, and error negotiation. However, this initial key may contain residual eavesdropping information. To eliminate information that potential eavesdroppers might obtain, the initial key must be purified through privacy amplification. The core of privacy amplification lies in hash function operations, which aim to use its one-wayness and collision resistance to destroy the information association between potential eavesdroppers and the initial key.

[0003] Toeplitz matrix multiplication is the most common implementation of hash functions in privacy amplification. However, directly multiplying the Toeplitz matrix with the initial key vector has a computational complexity of O(n^2). 2 ), where n is the length of the initial key vector. To meet security requirements, the length n of the initial key vector for privacy amplification processing typically needs to be n ≥ 10. 6 The order of magnitude is O(n). 2 The computational speed under these conditions is extremely low, which cannot match the real-time processing requirements of GHz-level high-speed QKD systems.

[0004] Currently, the industry commonly uses Fast Fourier Transform (FFT) to optimize Toeplitz matrix multiplication. The process involves: constructing an initial key vector and a Toeplitz matrix generation vector; padding both vectors with zeros to a specified length; performing FFT operations on the expanded vectors to obtain frequency domain vectors; performing an IFFT operation on the dot product of the two frequency domain vectors back to the time domain; and truncating the first n elements of the result to obtain the final key. This method utilizes the convolution theorem to transform time-domain circular convolution into frequency-domain dot product, thereby reducing the computational complexity to O(nlogn). However, the optimization method using FFT operations has the following inherent drawbacks in QKD privacy amplification applications: Precision loss issue: FFT operations are based on complex floating-point operations, which have rounding and truncation errors. However, QKD system key operations require absolute precision. Any tiny error may cause the keys of legitimate communicating parties to be inconsistent, thus compromising the availability of QKD system.

[0005] High hardware resource consumption: Complex floating-point operations require distinguishing between the real and imaginary parts. When implementing large-scale FFT operations on hardware acceleration platforms such as FPGAs, a large number of multipliers, registers and on-chip storage resources are required, making it difficult to balance high throughput and low resource consumption, which limits the engineering deployment capability of high-speed QKD systems.

[0006] Therefore, how to achieve a privacy amplification hardware acceleration solution with low resource consumption and high throughput while ensuring absolute computational accuracy is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a fast privacy amplification method for QKD based on number theory transformation, which can achieve high throughput privacy amplification with low hardware resource consumption while ensuring absolute accuracy of computation, and meet the real-time processing requirements of high-speed QKD systems.

[0008] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a fast privacy amplification method based on number theory transformation using QKD, comprising the following steps: Obtain the initial key vector and the Toeplitz matrix generation vector, both of which have the same length; The initial key vector and the Toeplitz matrix generation vector are respectively converted into a first matrix and a second matrix with the same number of rows R and columns C; where R is a predetermined number of NTT operation points, NTT represents number-theoretical transformation, the NTT operation uses a radix-r butterfly operation unit as the basic operation granularity, and each level of operation is completed by reusing the radix-r butterfly operation unit, R=r q r is a positive integer power of 2 and r≥4, q is a positive integer, and C=r; For the corresponding column vectors in the first matrix and the second matrix, perform NTT operation respectively to obtain the corresponding first frequency domain column vector and second frequency domain column vector, resulting in a total of C first frequency domain column vectors and C second frequency domain column vectors, thereby forming a first frequency domain matrix and a second frequency domain matrix; For each data point in the first frequency domain matrix and the second frequency domain matrix, multiply it by the row and column rotation factors corresponding to the row and column indices of that data point; Traverse the corresponding row vectors in the first and second frequency domain matrices after multiplying rows and columns by rotation factors, and call the radix-r butterfly operation unit in the NTT operation to perform a butterfly operation once to obtain the corresponding first and second frequency domain row vectors; perform a dot product operation on the first and second frequency domain row vectors, and perform a modular reduction operation on the dot product result vector to obtain the modular reduction result vector; after traversing all row vectors, form the modular reduction result matrix; Traverse each row vector in the modular reduction result matrix, call the basis-r butterfly operation unit in the INTT operation to perform a butterfly operation once, and obtain the corresponding butterfly operation result vector; after traversing all row vectors, form a butterfly operation result matrix; for each column vector in the butterfly operation result matrix, perform the INTT operation to obtain the corresponding privacy amplification time-domain output vector, and obtain a total of C privacy amplification time-domain output vectors; where INTT represents the number-theoretical inverse transform; The C privacy-enhanced time-domain output vectors are reassembled in order into a long vector, thereby obtaining the final privacy-enhanced key.

[0009] R=65536, r=16, q=4, C=16.

[0010] The NTT operation employs a DIF divide-and-conquer strategy; the NTT operation comprises a total of log r R = 4 levels of operation. In each level of operation, R / r = 4096 butterfly operations are performed by reusing the radix-16 butterfly operation unit.

[0011] The NTT operation adopts a ping-pong read-write storage architecture, including: The first and second memory arrays each contain 16 simple dual-port RAMs arranged in parallel. Each of the aforementioned simple dual-port RAMs has a depth of 4096 and a bit width of 28 bits; The first storage array and the second storage array alternate between read and write states between each level of operation, used to store the results of the previous level of operation and for the next level of operation to read.

[0012] The NTT operation employs a hierarchical dynamic interval read / write strategy, including: Initial write before the first level of operation: Divide the input data of 65536 points into 16 consecutive data blocks in sequence, each data block containing 4096 data; Store the 16 data blocks in sequence into the 16 simple dual-port RAMs of the memory array currently in the write state, with the 4096 data in each data block stored sequentially at addresses 0 to 4095 of the same simple dual-port RAM; During each level of computation, the following read and write operations are performed: Read operation: In the current level operation, data is read in parallel from 16 simple dual-port RAMs of the memory array currently in read state through a unified RAM address space. During the k-th read, one piece of data is read from the same address k-1 of each of the 16 simple dual-port RAMs, and the data is concatenated into 16 parallel data streams and sent to the base-16 butterfly operation unit for one butterfly operation. The unified RAM address space is {0,1,2,…,4095}, and the value of k ranges from 1 to 4096, representing the order of butterfly operations in the current level operation. Write operation: After the current level operation, the 16 parallel calculation results output by the base-16 butterfly operation unit are written into the 16 simple dual-port RAMs of the memory array that are currently in the write state, according to the preset address step size corresponding to the current level operation and the preset write control mode.

[0013] The process of writing to the 16 simple dual-port RAMs of the memory array currently in a write state according to a preset write control mode includes: After the first-level operation, the first write control mode is adopted: taking 256 consecutive butterfly operations as a write unit, all 16 parallel calculation results of each of the 256 consecutive butterfly operations are written into the same simple dual-port RAM, and then switched to the next simple dual-port RAM in sequence until the addresses of all 16 simple dual-port RAMs are filled; wherein, the 16 parallel calculation results of each of the d1×(p-1)+1 to d1×p butterfly operations are all written into the p-th simple dual-port RAM, where d1 represents the preset address step size corresponding to the first-level operation, d1=256, p=1,2,…,16; in each simple dual-port RAM, the 16 parallel calculation results written to the simple dual-port RAM for the t-th time are written to the address (t-1)+s×d1 according to d1, where t represents the local write order in the simple dual-port RAM, t=1,2,…,256, s=0,1,...,15; After the second-level operation, a second write control mode is adopted: the unified RAM address space is divided into 16 address segments, each segment being 256 units long, with segment numbers u1=0,1,…,15 corresponding to a starting address of u1×256; a write cycle consists of 256 consecutive butterfly operations, each cycle containing 16 consecutive write blocks, each block consisting of 16 consecutive butterfly operations; in the v1-th write cycle, corresponding to the address segment with write sequence number u1=v1-1, for any p=1,2,…,16, the segment from 256×u1+d2×(p-1)+1 to 256× The 16-way parallel computation results of each of the u1+d2×p butterfly operations are all written into the address segment with the sequence number u1 in the p-th simple dual-port RAM, where v1=1,2,…,16, d2 represents the preset address step size corresponding to the second-level operation, d2=16; in each consecutive write block corresponding to the p-th simple dual-port RAM, the 16-way parallel computation result of the b-th butterfly operation is written into the address u1×256+(b-1)+s×d2 of the p-th simple dual-port RAM according to d2, where b represents the operation order in the consecutive write block, b=1,2,…,16, s=0,1,…,15; After the third-level operation, a third write control mode is adopted: the unified RAM address space is divided into 256 address segments, each segment being 16 units long, with segment numbers u2=0,1,…,255 corresponding to a starting address of u2×16; a write cycle consists of 16 consecutive butterfly operations, each cycle containing 16 consecutive write blocks, each block consisting of one butterfly operation; in the v2th write cycle, the corresponding write segment with write number u2=v2-1 is used to write the 16th ×... The 16-way parallel computation result of u2+d3×p butterfly operations is written to the address segment with the sequence number u2 in the p-th simple dual-port RAM, where v2=1,2,…,256, d3 represents the preset address step size corresponding to the third-level operation, and d3=1; in each consecutive write block corresponding to the p-th simple dual-port RAM, the 16-way parallel computation result of one butterfly operation is written to the address u2×16+s×d3 of the p-th simple dual-port RAM according to d3, where s=0,1,…,15.

[0014] The INTT operation reuses the same radix-16 butterfly operation unit, the same ping-pong read-write storage architecture, and the same hierarchical dynamic interval read-write strategy as the NTT operation. The NTT rotation factor required by the NTT operation is switched to the INTT rotation factor required by the INTT operation, and an inverse multiplication operation is added.

[0015] The corresponding NTT twitch factor set is dynamically called according to the current level of operation to determine the NTT twitch factor required to perform the NTT operation. The NTT twitch factor is pre-stored in the on-chip read-only memory after symmetry optimization, and the total storage amount is only 32. The NTT twitch factor required for the INTT operation is the multiplicative inverse of the NTT twitch factor required for the NTT operation.

[0016] The set of NTT twitch factors corresponding to the first-level operation is There are a total of 8 NTT twitch factors; The set of NTT twitch factors corresponding to the second-level operation is There are a total of 8 NTT twitch factors; The set of NTT twitch factors corresponding to the third-level operation is as follows: There are a total of 8 NTT twitch factors; The set of NTT twitch factors corresponding to the fourth-level operation is as follows: There are a total of 8 NTT twitch factors.

[0017] The specific process of performing NTT operations on the corresponding column vectors in the first matrix and the second matrix is ​​as follows: 1) Combine the corresponding column vectors in the first matrix and the second matrix to form a pair of column data, resulting in a total of C pairs of column data; 2) Select at least G pairs of column data sequentially from C pairs of column data, and input the selected G pairs of column data into G independent processing channels to perform NTT operations in parallel. Here, G is greater than or equal to 1. Each independent processing channel includes two parallel NTT operations, which are used to perform NTT operations on the two column vectors in the input pair of column data at the same time, to obtain the corresponding first frequency domain column vector and second frequency domain column vector respectively. 3) Repeat step 2) until column C has finished processing the data.

[0018] Compared with the prior art, the advantages of the present invention are as follows: The initial key vector and the Toeplitz matrix generation vector are converted into a first matrix and a second matrix with the same number of rows and columns, respectively. The corresponding column vectors are selected from the first matrix and the second matrix and NTT operation is performed simultaneously. The number of data points contained in the column vector is consistent with the number of NTT operation points. This reduces the cache capacity and simplifies the control.

[0019] When performing NTT operations, it has good scalability, which can process multiple pairs of column vectors in parallel at the same time, or process all column vectors in parallel at the same time. By flexibly adjusting the number of column vector pairs processed in parallel, the overall throughput of privacy amplification can be improved to varying degrees.

[0020] By replacing FFT operations with NTT operations, which are based on integer field operations and do not require distinguishing between real and imaginary parts, the core operations only include integer multiplication and modular operations. This avoids the inherent rounding and truncation errors of FFT from the root, perfectly matching the "zero error" requirement of QKD system for key consistency. It ensures the accuracy of large-scale privacy amplification data processing, guarantees that the keys of legitimate communication parties are completely consistent and the privacy amplification effect is stable, and solves the technical problem that the FFT scheme may destroy the availability of QKD system due to precision loss.

[0021] NTT is based on integer field operations, resulting in a more streamlined core operation unit. Only basic operation units such as integer multipliers are needed to complete the core transformation. Compared to FFT, which requires separate deployment of real and imaginary part operation and storage units and occupies a large number of multipliers and on-chip storage resources, the NTT operation of this invention significantly improves resource utilization when implemented on an FPGA platform. When all corresponding column vectors in the first and second matrices are processed in parallel, high throughput is achieved while ensuring low resource consumption, solving the technical problem of FFT schemes struggling to balance high throughput and low resource consumption on FPGAs.

[0022] Meanwhile, NTT, as an implementation of fast transform, shares the same O(nlogn) computational complexity as FFT, meeting the real-time processing requirements of long key strings. Compared to the FFT scheme, the innovation of this invention lies in: while maintaining the advantage of O(nlogn) computational complexity, it completely eliminates the precision loss of FFT through integer field operations, and significantly reduces FPGA resource consumption through simplified integer operation units, achieving high-precision, low-resource-consumption QKD fast privacy amplification. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating the overall implementation of the method of the present invention; Figure 2 A schematic diagram of the data addresses involved in 4096 butterfly operations in each stage of a 65536-point NTT operation; Figure 3 This is a schematic diagram showing the data distribution (represented in data address form) within 16 simple dual-port RAMs of a memory array in the write state before the first-level operation. Figure 4 This is a schematic diagram showing the data distribution (represented in data address form) within 16 simple dual-port RAMs of a memory array in the write state before the second-level operation. Figure 5 A schematic diagram showing the data distribution (represented in data address form) within 16 simple dual-port RAMs of a memory array in write mode before the third-level operation; Figure 6 This is a schematic diagram showing the data distribution (represented in data address form) within 16 simple dual-port RAMs of a memory array in write mode before the fourth-level operation. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0025] This embodiment provides a fast privacy amplification method for QKD based on number theory transformation, suitable for implementing the privacy amplification stage of a high-speed QKD system on an FPGA platform. For example... Figure 1 As shown, the QKD fast privacy amplification method includes the following steps: S1. Obtain the initial key vector and the Toeplitz matrix generation vector, both of which have the same length, L. The Toeplitz matrix generation vector is constructed from the Toeplitz matrix, and both the initial key vector and the Toeplitz matrix generation vector have been padded with zeros and extended to the specified length L.

[0026] S2. Based on the idea of ​​row and column decomposition, the initial key vector and the Toeplitz matrix generation vector are respectively converted into a first matrix and a second matrix with the same number of rows R and columns C; where R is the predetermined number of NTT operation points, NTT (Number Theoretic Transform) represents number-theoretic transformation, and NTT operation uses radix-r butterfly operation units as the basic operation granularity, and completes each level of operation by reusing radix-r butterfly operation units, R=r q r is a positive integer power of 2 and r≥4, q is a positive integer, and C=r.

[0027] As a concrete example, the length L=2 of the initial key vector and the Toeplitz matrix-generated vector. 20 When R=65536 and C=16, the first and second matrices are represented as follows: , where a0 is the least significant bit of the vector.

[0028] As a specific example, r takes the value 16 and q takes the value 4.

[0029] S3. Perform NTT operation on the corresponding column vectors in the first matrix and the second matrix respectively to obtain the corresponding first frequency domain column vectors and second frequency domain column vectors, resulting in a total of C first frequency domain column vectors and C second frequency domain column vectors, thus forming the first frequency domain matrix and the second frequency domain matrix.

[0030] In this embodiment, the specific process of performing NTT operations on the corresponding column vectors in the first and second matrices is as follows: 1) Combine the corresponding column vectors in the first and second matrices to form a pair of column data, resulting in a total of C pairs of column data; 2) Select at least G pairs of column data sequentially from C pairs of column data, and input the selected G pairs of column data into G independent processing channels to perform NTT operations in parallel. Here, G is greater than or equal to 1. Each independent processing channel includes two parallel NTT operations, which are used to perform NTT operations on the two column vectors in the input pair of column data at the same time, to obtain the corresponding first frequency domain column vector and second frequency domain column vector respectively. 3) Repeat step 2) until column C has finished processing the data.

[0031] In actual processing, C=16 independent processing channels can be selected to process in parallel simultaneously, maximizing the overall throughput of privacy amplification.

[0032] In this embodiment, the 65536-point NTT operation employs a DIF (Decimation-In-Frequency) divide-and-conquer strategy. In the first stage of the 65536-point NTT operation, the DIF divide-and-conquer strategy extracts data at 4096-point address intervals; in the second stage, it extracts data at 256-point address intervals; in the third stage, it extracts data at 16-point address intervals; and in the fourth stage, it extracts data at 1-point address intervals. Designed for a 65536-point operation scale, it comprises four stages (log... r R=4) Iterative operation (see...) Figure 2 In each stage of operation, radix-16 butterfly operation units are reused to perform R / r = 4096 butterfly operations, and the 65536-point operation scale is precisely adapted to the typical key length of QKD privacy amplification (n≥10). 6 (Scale), which solves the problem of extremely slow operation speed of traditional methods in long key scenarios. The four-level iterative operation is perfectly matched with the radix-16 granularity to achieve optimal computational efficiency. The 4096 butterfly operations per level are perfectly matched with 16 parallel data channels to ensure that the radix-16 butterfly operation unit operates at full load.

[0033] The 65536-point NTT operation employs a DIF divide-and-conquer strategy with a radix-16 butterfly arithmetic unit as the basic operation granularity. By reusing the radix-16 butterfly arithmetic unit to complete each stage of the operation, the number of iterations in the 65536-point NTT is reduced from 16 stages in radix-2 to 4 stages, significantly reducing computational latency. Reusing the radix-16 butterfly arithmetic unit also significantly reduces hardware resource consumption. The DIF divide-and-conquer strategy facilitates pipelined implementation, further improving throughput.

[0034] This invention applies NTT to large-scale privacy amplification in QKD. Using a divide-and-conquer iterative principle, a low-point 16-point NTT is used as the core computational unit. A hierarchical iterative reuse architecture completes high-point 65536-point NTT computations, effectively solving the problem that conventional point-count NTT designs cannot adapt to large-scale privacy amplification. The radix-16 butterfly computation unit serves as the basic computational granularity, requiring only 4096 butterfly operations per level to complete the transformation. Compared to directly using a radix-2 design, this significantly reduces implementation complexity while maintaining the same computational accuracy, enabling efficient application of NTT in QKD systems with n≥10^2 ... 6 Processing long key strings on the order of magnitude.

[0035] In this embodiment, the NTT operation adopts a ping-pong read-write storage architecture, including a first storage array (Ping_Ram) and a second storage array (Pang_Ram). Each storage array contains 16 parallel-arranged simple dual-port RAMs, each with a depth of 4096 and a bit width of 28 bits. The first and second storage arrays alternate between read and write states between different operation levels, used to store the results of the previous operation and for the next operation to read. A ping-pong read / write storage architecture consisting of a first storage array and a second storage array is adopted. Each storage array contains 16 simple dual-port RAMs arranged in parallel with a depth of 4096. The first and second storage arrays alternate between read and write states between each level of operation to realize ping-pong operation, hide data read / write latency, and achieve pipelined computation and data transmission. Each storage array contains 16 simple dual-port RAMs arranged in parallel, supporting 16-way parallel data reading from the radix-16 butterfly operation unit. Each simple dual-port RAM has a depth of 4096, which is exactly matched with 65536 points / 16, with no waste of storage resources, thus solving the problem of high storage resource consumption when implementing FFT on FPGA.

[0036] Due to the physical limitations of simple dual-port RAM, multiple data cannot be read from the same simple dual-port RAM at the same time. Therefore, in order to meet the requirement of 16 data parallel inputs of the radix-16 butterfly arithmetic unit, NTT arithmetic adopts a hierarchical dynamic interval read / write strategy.

[0037] In this embodiment, the NTT operation employs a hierarchical dynamic interval read / write strategy, including: Initial write before the first-level operation: Before performing the first-level operation, the input data of length 65536 points (i.e., the column vectors in the first or second matrix) is divided into 16 consecutive data blocks, each containing 4096 data points. These 16 data blocks are then sequentially stored into the 16 simple dual-port RAMs of the memory array currently in write mode. The 4096 data points of each data block are stored sequentially at addresses 0 to 4095 of the same simple dual-port RAM. Figure 3 As shown, specifically: the first data block (global address 0-4095) is stored in the first simple dual-port RAM at addresses 0 to 4095, the second data block (global address 4096-8191) is stored in the second simple dual-port RAM at addresses 0 to 4095, and so on, until the 16th data block (global address 61440-65535) is stored in the 16th simple dual-port RAM at addresses 0 to 4095.

[0038] During each level of computation, the following read and write operations are performed: Read operation: In the current level operation, data is read in parallel from 16 simple dual-port RAMs of the memory array currently in read state through a unified RAM address space. During the k-th read, one data is read from the same address k-1 of each of the 16 simple dual-port RAMs, and the data is concatenated into 16 parallel data streams and sent to the radix-16 butterfly operation unit for one butterfly operation. The unified RAM address space is {0,1,2,…,4095}, and the value of k ranges from 1 to 4096, which represents the order of the butterfly operations in the current level operation.

[0039] Write operation: After the current level operation, the 16 parallel computation results output by the radix-16 butterfly arithmetic unit are written to the 16 simple dual-port RAMs of the memory array currently in write state according to the preset address step size corresponding to the current level operation number and the following preset write control mode: After the first level of operation, the first write control mode is adopted: such as Figure 4 As shown, each of the 256 consecutive butterfly operations is considered a write unit. The 16-way parallel computation results of each of the 256 consecutive butterfly operations are all written into the same simple dual-port RAM, and then switched to the next simple dual-port RAM in sequence until the addresses of all 16 simple dual-port RAMs are filled. Specifically, the 16-way parallel computation results of each of the d1×(p-1)+1 to d1×p butterfly operations are all written into the p-th simple dual-port RAM, where d1 represents the preset address step size corresponding to the first-level operation, d1=256, p=1,2,…,16. In each simple dual-port RAM, the 16-way parallel computation result written to the simple dual-port RAM for the t-th time is written to the address (t-1)+s×d1 according to d1, where t represents the local write order in the simple dual-port RAM, t=1,2,…,256, s=0,1,...,15.

[0040] After the second-level operation, the second write control mode is used: such as Figure 5As shown, the unified RAM address space is divided into 16 address segments, each with a length of 256. The address segment numbers u1=0,1,…,15 correspond to the starting address u1×256. A write cycle consists of 256 consecutive butterfly operations, and each write cycle contains 16 consecutive write blocks, each consisting of 16 consecutive butterfly operations. In the v1-th write cycle, the address segment with the write sequence number u1=v1-1 is written. For any p=1,2,…,16, the butterfly operations from the 256×u1+d2×(p-1)+1 to the 256×u1+d2×p-th butterfly operations are performed. The 16-way parallel computation results of each butterfly operation are all written into the address segment with the sequence number u1 in the p-th simple dual-port RAM, where v1=1,2,…,16, and d2 represents the preset address step size corresponding to the second-level operation, d2=16; in each consecutive write block corresponding to the p-th simple dual-port RAM, the 16-way parallel computation results of the b-th butterfly operation are written into the address u1×256+(b-1)+s×d2 of the p-th simple dual-port RAM according to d2, where b represents the operation order in the consecutive write block, b=1,2,…,16, s=0,1,…,15; After the third-level operation, the third write control mode is adopted: such as Figure 6 As shown, the unified RAM address space is divided into 256 address segments, each segment being 16 bytes long. The segment numbers u2 = 0, 1, ..., 255 correspond to a starting address of u2 × 16. A write cycle consists of 16 consecutive butterfly operations, each cycle containing 16 consecutive write blocks, each block consisting of one butterfly operation. In the v2th write cycle, the address segment with write number u2 = v2 - 1 is written, and the 16 × u2 + d3 × p butterfly operation is performed. The 16-way parallel computation result of the butterfly operation is written to the address segment with the sequence number u2 in the p-th simple dual-port RAM, where v2=1,2,…,256, and d3 represents the preset address step size corresponding to the third-level operation, d3=1; in each consecutive write block corresponding to the p-th simple dual-port RAM, the 16-way parallel computation result of one butterfly operation is written to the address u2×16+s×d3 of the p-th simple dual-port RAM according to d3, where s=0,1,…,15.

[0041] The specific reading and writing steps are as follows: Reading during the first level of operation: By simply reading one piece of data in parallel from 16 simple dual-port RAMs in the read state of the memory array (such as the first memory array) according to a unified RAM address, the 16 parallel input data required for one radix-16 butterfly operation can be directly obtained. The first read operation involves parallelly reading data stored at RAM address 0 from the 16 simple dual-port RAMs in the read state of the memory array. Specifically, this involves reading 16 data points with addresses 0, 4096, 8192, ..., 61440, to perform the first butterfly operation. The second read operation involves parallelly reading data stored at RAM address 1 from the 16 simple dual-port RAMs in the read state of the memory array. Specifically, this involves reading 16 data points with addresses 1, 4097, 8193, ..., 61441, to perform the second butterfly operation. This process continues until the 4096th read operation, where the 4096th read operation involves parallelly reading data stored at RAM address 4095 from the 16 simple dual-port RAMs in the read state of the memory array. Specifically, this involves reading 16 data points with addresses 4095, 8191, ..., 65535, to perform the 4096th butterfly operation.

[0042] Write during the first level of operation (i.e., write before the second level of operation): The second storage array is in write state. To ensure that the next level of operation can use the same 16-way parallel data retrieval logic without additional address concatenation or waiting, the first write control mode is adopted. The calculation result of the first level operation needs to be written to the corresponding simple dual-port RAM of the second storage array at 256-point intervals. After one simple dual-port RAM is filled, the operation count register is switched to the next one. After each butterfly operation is completed, the operation count register is incremented by 1. When it is accumulated to 4096, and all the calculation results of the first level operation are stably written to the second storage array, the operation jumps to the second level operation.

[0043] In the first butterfly operation, the data involved in the operation are data with addresses 0, 4096, 8192, ..., 61440, and the addresses of the 16 parallel computation results are also 0, 4096, 8192, ..., 61440, which are written to addresses 0, 256, 512, ..., 3840 of the first simple dual-port RAM. In the second butterfly operation, the data involved in the operation are data with addresses 1, 4097, 8193, ..., 61441, and the 16 parallel computation results are written to addresses 1, 257, 513, ..., 3841 of the first simple dual-port RAM. And so on. In the 256th butterfly operation, the data involved in the operation are data with addresses 255, 4351, 8447, ..., 61695, and the 16 parallel computation results are written to addresses 255, 511, 767, ..., 4095 of the first simple dual-port RAM.

[0044] In the 257th butterfly operation, the data involved in the operation are data with addresses 256, 4352, ..., 61696. The 16 parallel calculation results are written to addresses 0, 256, 512, ..., 3840 of the second simple dual-port RAM, respectively. Similarly, in the 512th butterfly operation, the data involved in the operation are data with addresses 511, 4607, ..., 61951. The 16 parallel calculation results are written to addresses 255, 511, 767, ..., 4095 of the second simple dual-port RAM, respectively.

[0045] And so on. In the 3841st butterfly operation, the data involved in the operation are data with addresses 3840, 7936, ..., 65280, and the 16 parallel computing results are written to addresses 0, 256, 512, ..., 3840 of the 16th simple dual-port RAM, respectively. Similarly, in the 4096th butterfly operation, the data involved in the operation are data with addresses 4095, 8191, ..., 65535, and the 16 parallel computing results are written to addresses 255, 511, 767, ..., 4095 of the 16th simple dual-port RAM, respectively.

[0046] During the second-level operation, the first storage array changes from a read state to a write state, and the second storage array changes from a write state to a read state. The first read operation involves parallelly reading data stored at RAM address 0 from the 16 simple dual-port RAMs in the read state of the memory array. This includes 16 data points with addresses 0, 256, 512, ..., 3840, performing the first butterfly operation. The second read operation involves parallelly reading data stored at RAM address 1 from the 16 simple dual-port RAMs in the read state of the memory array. This includes 16 data points with addresses 1, 257, 513, ..., 3841, performing the second butterfly operation. This process continues until the 4096th read operation, where the 4096th read operation involves parallelly reading data stored at RAM address 4095 from the 16 simple dual-port RAMs in the read state of the memory array. This includes 16 data points with addresses 61695, 61951, 62207, ..., 65535, performing the 4096th butterfly operation.

[0047] The second-level operation (i.e., the write before the third-level operation) involves the following steps: The first butterfly operation uses data at addresses 0, 256, 512, ..., 3840, and the resulting 16-way parallel computation results are also written to addresses 0, 256, 512, ..., 3840, respectively, and are written to addresses 0, 16, 32, ..., 240 of the first simple dual-port RAM. The second butterfly operation uses data at addresses 1, 257, 513, ..., 3841, and the resulting 16-way parallel computation results are written to addresses 1, 17, 33, ..., 241 of the first simple dual-port RAM. Similarly, the 16th butterfly operation uses data at addresses 15, 271, 527, ..., 3855, and the resulting 16-way parallel computation results are written to addresses 15, 31, 47, ..., 255 of the first simple dual-port RAM.

[0048] The 17th butterfly operation involved data at addresses 16, 272, 528, ..., 3856, and the 16 parallel computation results were written to addresses 0, 16, 32, ..., 240 of the second simple dual-port RAM. Similarly, the 32nd butterfly operation involved data at addresses 31, 287, 543, ..., 3871, and the 16 parallel computation results were written to addresses 15, 31, 47, ..., 255 of the second simple dual-port RAM.

[0049] And so on. In the 241st butterfly operation, the data involved are at addresses 240, 496, 752, ..., 4080. The 16 parallel calculation results are written to addresses 0, 16, 32, ..., 240 of the 16th simple dual-port RAM. Similarly, in the 256th butterfly operation, the data involved are at addresses 255, 511, 767, ..., 4095. The 16 parallel calculation results are written to addresses 15, 31, 47, ..., 255 of the 16th simple dual-port RAM.

[0050] At this point, the first 255 addresses of the 16 simple dual-port RAMs are filled, and this writing method is repeated 16 times.

[0051] The third-level operation involves reading data in parallel from 16 simple dual-port RAMs in the read state, specifically data stored at RAM address 0 (addresses 0, 16, 32, ..., 240) to perform the first butterfly operation. The second read involves reading data stored at RAM address 1 in parallel from 16 simple dual-port RAMs in the read state, specifically data stored at RAM address 1 (addresses 1, 17, 33, ..., 241) to perform the second butterfly operation. This process continues until the 4096th read, which involves reading data stored at RAM address 4095 in parallel from 16 simple dual-port RAMs in the read state, specifically data stored at RAM addresses 65295, 65311, ..., 65535, to perform the 4096th butterfly operation.

[0052] The third-level operation (i.e., the write before the fourth-level operation) involves the following steps: The first butterfly operation uses data at addresses 0, 16, 32, ..., 240, and the resulting 16-way parallel computation results are also written to addresses 0, 16, 32, ..., 240, respectively, and are written to addresses 0, 1, 2, ..., 15 of the first simple dual-port RAM. The second butterfly operation uses data at addresses 1, 17, 33, ..., 241, and the resulting 16-way parallel computation results are written to addresses 0, 1, 2, ..., 15 of the second simple dual-port RAM. This process continues until the 16th butterfly operation uses data at addresses 15, 31, 47, ..., 255, and the resulting 16-way parallel computation results are written to addresses 0, 1, 2, ..., 15 of the 16th simple dual-port RAM.

[0053] The 17th butterfly operation uses data with addresses 16, 32, 48, ..., 256. The 16 parallel computation results are written to addresses 16, 17, ..., 31 of the first simple dual-port RAM. Similarly, the 32nd butterfly operation uses data with addresses 31, 47, 62, ..., 271. The 16 parallel computation results are written to addresses 16, 17, ..., 31 of the 16th simple dual-port RAM.

[0054] Based on the above writing method, the third-level operation and writing are completed after the last 16 addresses of each simple dual-port RAM are filled.

[0055] The fourth-level operation involves reading data in parallel from the 16 simple dual-port RAMs in the read state, specifically data stored at RAM address 0 (addresses 0, 1, 2, ..., 15) to perform the first butterfly operation. The second read involves reading data stored at RAM address 1 in parallel from the 16 simple dual-port RAMs in the read state, specifically data stored at RAM address 16 (addresses 16, 17, 18, ..., 31) to perform the second butterfly operation. This process continues until the 4096th read, which involves reading data stored at RAM address 4095 in parallel from the 16 simple dual-port RAMs in the read state, specifically data stored at RAM addresses 65520, 65521, ..., 65535 to perform the 4096th butterfly operation.

[0056] The essence of the aforementioned hierarchical dynamic interval read / write strategy is to achieve data rearrangement through progressively refined data block partitioning: Before the first level of operation: each simple dual-port RAM is treated as a single block, storing 4096 consecutive data entries; after the first level of operation: each simple dual-port RAM is divided into 16 regions, each with a length of 256, storing 256 data entries; after the second level of operation: each simple dual-port RAM is further divided into 256 regions, each with a length of 16, storing 16 data entries; after the third level of operation: each simple dual-port RAM is divided into 4096 regions, each with a length of 1, meaning one data entry is stored per address. Through this progressively refined region partitioning, coupled with different write steps at each level (256, 16, 1), the data distribution after each level of operation precisely meets the parallel read requirements of the next level of operation, thus completely resolving the hardware contradiction between the 16-way parallel input requirement of the radix-16 butterfly arithmetic unit and the read / write capability of a single-port RAM.

[0057] Hardware control and scheduling of NTT transform: In this embodiment, the 65536-point NTT core adopts a design combining a single-radix-16 butterfly arithmetic unit and four-level iterative multiplexing. A four-level STAGE state machine controls the radix-16 butterfly arithmetic unit to perform each level of operation in a time-sharing manner, with each level executing 4096 butterfly operations. Two sets of 16 simple dual-port RAMs are used for data relay between levels, and ping-pong read / write control is used to store the results of the previous level's operation and retrieve the data for the next level's operation. Each independent processing channel contains two identical 65536-point NTT cores, used to perform NTT forward transforms on the corresponding column vectors in the first and second matrices, respectively.

[0058] S4. For each data in the first frequency domain matrix and the second frequency domain matrix, multiply it by the row and column rotation factors corresponding to the row index and column index of the data to achieve inter-column frequency domain association.

[0059] S5. Traverse the corresponding row vectors in the first and second frequency domain matrices after multiplying by the row and column rotation factors, and call the radix-r butterfly operation unit in the NTT operation to perform a butterfly operation to obtain the corresponding first and second frequency domain row vectors; perform a dot product operation on the first and second frequency domain row vectors, and perform a modular reduction operation on the dot product result vector to obtain the modular reduction result vector; after traversing all row vectors, form the modular reduction result matrix.

[0060] In this embodiment, since the corresponding row vectors in the first and second frequency domain matrices after multiplying by the row and column rotation factors both include 16 data points, a butterfly operation can be performed once by the radix-16 butterfly operation unit used in the NTT operation. Therefore, the radix-16 butterfly operation unit is directly called. If C is not equal to 16, then the corresponding radix-r butterfly operation unit needs to be redesigned.

[0061] In this embodiment, a single butterfly operation of the radix-16 butterfly unit can only output 16 outputs (i.e., the first and second frequency domain row vectors), while the system is configured with 32 parallel multipliers for dot multiplication. The 32 multipliers are divided into two groups and operate in a time-division multiplexing manner: in the first time period, the first group of 16 multipliers is used to process the current pair of first and second frequency domain row vectors, and in the second time period, the second group of 16 multipliers is used to process the next pair of first and second frequency domain row vectors. By having the two groups of multipliers work alternately in a time-division multiplexing manner, the 16 outputs of the radix-16 butterfly unit are precisely matched, and all 32 multiplier resources are fully utilized, significantly improving hardware utilization while ensuring processing speed.

[0062] In this embodiment, the system is configured with 32 parallel Barrett reduction modules. Each Barrett reduction module is optimized for the prime number 167772161, performing fast modular reduction on the 56-bit multiplication result to avoid data overflow and ensure that the result is confined to the finite field GF(167772161), i.e., (0~167772160). The modular reduction operation converts division into multiplication and shift operations, avoiding the use of a divider, making it suitable for hardware implementation and solving the problem of high resource consumption in FFT complex floating-point operations.

[0063] S6. Traverse each row vector in the modular reduction result matrix, call the basis-r butterfly operation unit in the INTT operation to perform a butterfly operation once, and obtain the corresponding butterfly operation result vector; after traversing all row vectors, form the butterfly operation result matrix; for each column vector in the butterfly operation result matrix, perform the INTT operation to obtain the corresponding privacy amplification time domain output vector, and obtain a total of C privacy amplification time domain output vectors; where INTT (Inverse Number Theoretic Transform) represents the inverse number theory transform.

[0064] In this embodiment, the INTT operation and the NTT operation reuse the same radix-16 butterfly operation unit, the same ping-pong read-write storage architecture, and the same hierarchical dynamic interval read-write strategy. This reuse design reduces hardware resource consumption by nearly 50%. It only requires switching the NTT twitch factor required for the NTT operation to the INTT twitch factor required for the INTT operation, and adding the inverse multiplication operation. The control logic is simple, and it maintains the same high throughput capability as NTT, further solving the problem of high hardware resource consumption.

[0065] a) Twist factor switching: During INTT operations, the pre-stored INTT twist factor (the finite field inverse of the original NTT twist factor) is called. The calling of the NTT twist factor and the INTT twist factor can be achieved by switching the mode control signal.

[0066] b) Post-output processing: After the fourth level of the INTT operation is completed, an inverse multiplication operation is added, that is, the result of the butterfly operation is multiplied by R. -1 mod a, where R = 65536, a = 167772161, R -1 Let R be the multiplicative inverse of R in the finite field GF(a), and mod denotes the modulo operation.

[0067] In this embodiment, INTT operation is performed on each column vector in the butterfly operation result matrix. In specific operations, the same processing method as NTT operation can be used, that is, multiple column vectors are processed in parallel.

[0068] S7. Reassemble the C privacy-enhanced time-domain output vectors into a long vector in order to obtain the final privacy-enhanced key.

[0069] Compared to the conventional 65536-point NTT operation, which has limitations such as large NTT rotation factor storage, poor reusability, and complex control logic, as shown in Table 1, the radix-16 butterfly operation unit design adopted in this invention optimizes the symmetry of the four sets of NTT rotation factors (16 in each set) required for the four-level iterative operation to a total storage of only 32, which are pre-stored in the small ROM (read-only memory) on the FPGA chip. All butterfly operations at the same level reuse the same set of NTT rotation factors, and only simple switching is required between levels.

[0070] Table 1. NTT twiddle factors required for each stage of NTT operation (totaling 65,536 points).

[0071] In this embodiment, the NTT twitch factor set corresponding to the current level of operation is dynamically called to determine the NTT twitch factor required for performing the NTT operation; the NTT twitch factor required for the INTT operation is the multiplicative inverse of the NTT twitch factor required for the NTT operation. Specifically: the NTT twitch factor set corresponding to the first level operation is... There are a total of 8 NTT twitch factors; the set of NTT twitch factors corresponding to the second-level operation is... There are a total of 8 NTT twitch factors; the set of NTT twitch factors corresponding to the third-level operation is... There are a total of 8 NTT twitch factors; the set of NTT twitch factors corresponding to the fourth-level operation is... There are a total of 8 NTT twitch factors.

[0072] After symmetry optimization, the total storage requirement for NTT twiddle factors is only 32, saving 50% of storage resources compared to the original 64 factors (4 levels × 16). NTT twiddle factors are pre-stored in on-chip ROM, resulting in low access latency. The corresponding NTT twiddle factor set is dynamically called based on the current operation level, enabling reuse within the same level and switching between levels. The control logic is simple, solving the problem of requiring large storage resources for FFT complex number operations. The twiddle factor step size (4096→256→16→1) corresponds to the write step size (256→16→1) of the hierarchical dynamic interval read / write strategy, reflecting the consistency of the overall design.

[0073] This invention designs an efficient 65536-point NTT operation, which includes a rotation factor storage strategy, an efficient intermediate result reading and writing strategy, and a radix-16 butterfly operation unit reuse strategy. It realizes the combination of fast number theory transformation and QKD large-scale privacy amplification, achieving a high-precision, low-computational-resource-consumption QKD fast privacy amplification effect.

[0074] At a clock frequency of 156.25MHz, a single independent 65536-point NTT operation requires 573601 clock cycles. By instantiating multiple independent processing channels, the parallel computing advantages of the FPGA can be fully utilized. The number of module instantiations can be flexibly adjusted according to the actual hardware resources. Sixteen 65536-point NTT operations are set for the first matrix and the second matrix respectively, and 65536th radix-16 butterfly operation units are called respectively, achieving a data processing rate of 110.3Mbps.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fast privacy amplification method based on number-theory transform using QKD, characterized in that, Includes the following steps: Obtain the initial key vector and the Toeplitz matrix generation vector, both of which have the same length; The initial key vector and the Toeplitz matrix generation vector are respectively converted into a first matrix and a second matrix with the same number of rows R and columns C; where R is a predetermined number of NTT operation points, NTT represents number-theoretical transformation, the NTT operation uses a radix-r butterfly operation unit as the basic operation granularity, and each level of operation is completed by reusing the radix-r butterfly operation unit, R=r q r is a positive integer power of 2 and r≥4, q is a positive integer, and C=r; For the corresponding column vectors in the first matrix and the second matrix, perform NTT operation respectively to obtain the corresponding first frequency domain column vector and second frequency domain column vector, resulting in a total of C first frequency domain column vectors and C second frequency domain column vectors, thereby forming a first frequency domain matrix and a second frequency domain matrix; For each data point in the first frequency domain matrix and the second frequency domain matrix, multiply it by the row and column rotation factors corresponding to the row and column indices of that data point; Traverse the corresponding row vectors in the first and second frequency domain matrices after multiplying by the row and column rotation factors, and call the radix-r butterfly operation unit in the NTT operation to perform a butterfly operation once to obtain the corresponding first and second frequency domain row vectors; perform a dot product operation on the first and second frequency domain row vectors, and perform a modular reduction operation on the dot product result vector to obtain the modular reduction result vector; after traversing all row vectors, form the modular reduction result matrix; Traverse each row vector in the modular reduction result matrix, call the basis-r butterfly operation unit in the INTT operation to perform a butterfly operation once, and obtain the corresponding butterfly operation result vector; after traversing all row vectors, form a butterfly operation result matrix; for each column vector in the butterfly operation result matrix, perform the INTT operation to obtain the corresponding privacy amplification time-domain output vector, and obtain a total of C privacy amplification time-domain output vectors; where INTT represents the number-theoretical inverse transform; The C privacy-enhanced time-domain output vectors are reassembled in order into a long vector, thereby obtaining the final privacy-enhanced key.

2. The QKD fast privacy amplification method based on number theory transformation according to claim 1, characterized in that, R=65536, r=16, q=4, C=16.

3. The QKD fast privacy amplification method based on number theory transformation according to claim 2, characterized in that, The NTT operation employs a DIF divide-and-conquer strategy; the NTT operation comprises a total of log r R = 4 levels of operation. In each level of operation, R / r = 4096 butterfly operations are performed by reusing the radix-16 butterfly operation unit.

4. The QKD fast privacy amplification method based on number theory transformation according to claim 3, characterized in that, The NTT operation adopts a ping-pong read-write storage architecture, including: The first and second memory arrays each contain 16 simple dual-port RAMs arranged in parallel. Each of the aforementioned simple dual-port RAMs has a depth of 4096 and a bit width of 28 bits; The first storage array and the second storage array alternate between read and write states between each level of operation, used to store the results of the previous level of operation and for the next level of operation to read.

5. The QKD fast privacy amplification method based on number theory transformation according to claim 4, characterized in that, The NTT operation employs a hierarchical dynamic interval read / write strategy, including: Initial write before the first level of operation: Divide the input data of 65536 points into 16 consecutive data blocks in sequence, each data block containing 4096 data; Store the 16 data blocks in sequence into the 16 simple dual-port RAMs of the memory array currently in the write state, with the 4096 data in each data block stored sequentially at addresses 0 to 4095 of the same simple dual-port RAM; During each level of computation, the following read and write operations are performed: Read operation: In the current level operation, data is read in parallel from 16 simple dual-port RAMs of the memory array currently in read state through a unified RAM address space. During the k-th read, one piece of data is read from the same address k-1 of each of the 16 simple dual-port RAMs, and the data is concatenated into 16 parallel data streams and sent to the base-16 butterfly operation unit for one butterfly operation. The unified RAM address space is {0,1,2,…,4095}, and the value of k ranges from 1 to 4096, representing the order of butterfly operations in the current level operation. Write operation: After the current level operation, the 16 parallel calculation results output by the base-16 butterfly operation unit are written into the 16 simple dual-port RAMs of the memory array that are currently in the write state, according to the preset address step size corresponding to the current level operation and the preset write control mode.

6. The QKD fast privacy amplification method based on number theory transformation according to claim 5, characterized in that, The process of writing to the 16 simple dual-port RAMs of the memory array currently in a write state according to a preset write control mode includes: After the first-level operation, the first write control mode is adopted: taking 256 consecutive butterfly operations as a write unit, all 16 parallel calculation results of each of the 256 consecutive butterfly operations are written into the same simple dual-port RAM, and then switched to the next simple dual-port RAM in sequence until the addresses of all 16 simple dual-port RAMs are filled; wherein, the 16 parallel calculation results of each of the d1×(p-1)+1 to d1×p butterfly operations are all written into the p-th simple dual-port RAM, where d1 represents the preset address step size corresponding to the first-level operation, d1=256, p=1,2,…,16; in each simple dual-port RAM, the 16 parallel calculation results written to the simple dual-port RAM for the t-th time are written to the address (t-1)+s×d1 according to d1, where t represents the local write order in the simple dual-port RAM, t=1,2,…,256, s=0,1,...,15; After the second-level operation, a second write control mode is adopted: the unified RAM address space is divided into 16 address segments, each segment being 256 units long, with segment numbers u1=0,1,…,15 corresponding to a starting address of u1×256; a write cycle consists of 256 consecutive butterfly operations, each cycle containing 16 consecutive write blocks, each block consisting of 16 consecutive butterfly operations; in the v1-th write cycle, corresponding to the address segment with write sequence number u1=v1-1, for any p=1,2,…,16, the segment from 256×u1+d2×(p-1)+1 to 256× The 16-way parallel computation results of each of the u1+d2×p butterfly operations are all written into the address segment with the sequence number u1 in the p-th simple dual-port RAM, where v1=1,2,…,16, d2 represents the preset address step size corresponding to the second-level operation, d2=16; in each consecutive write block corresponding to the p-th simple dual-port RAM, the 16-way parallel computation result of the b-th butterfly operation is written into the address u1×256+(b-1)+s×d2 of the p-th simple dual-port RAM according to d2, where b represents the operation order in the consecutive write block, b=1,2,…,16, s=0,1,…,15; After the third-level operation, a third write control mode is adopted: the unified RAM address space is divided into 256 address segments, each segment being 16 units long, with segment numbers u2=0,1,…,255 corresponding to a starting address of u2×16; a write cycle consists of 16 consecutive butterfly operations, each cycle containing 16 consecutive write blocks, each block consisting of one butterfly operation; in the v2th write cycle, the corresponding write segment with write number u2=v2-1 is used to write the 16th ×... The 16-way parallel computation result of u2+d3×p butterfly operations is written to the address segment with the sequence number u2 in the p-th simple dual-port RAM, where v2=1,2,…,256, d3 represents the preset address step size corresponding to the third-level operation, and d3=1; in each consecutive write block corresponding to the p-th simple dual-port RAM, the 16-way parallel computation result of one butterfly operation is written to the address u2×16+s×d3 of the p-th simple dual-port RAM according to d3, where s=0,1,…,15.

7. A fast privacy amplification method based on number theory transformation using QKD according to claim 5 or 6, characterized in that, The INTT operation reuses the same radix-16 butterfly operation unit, the same ping-pong read-write storage architecture, and the same hierarchical dynamic interval read-write strategy as the NTT operation. The NTT rotation factor required by the NTT operation is switched to the INTT rotation factor required by the INTT operation, and an inverse multiplication operation is added.

8. The QKD fast privacy amplification method based on number theory transformation according to claim 7, characterized in that, The corresponding NTT twitch factor set is dynamically called according to the current level of operation to determine the NTT twitch factor required to perform the NTT operation. The NTT twitch factor is pre-stored in the on-chip read-only memory after symmetry optimization, and the total storage amount is only 32. The NTT twitch factor required for the INTT operation is the multiplicative inverse of the NTT twitch factor required for the NTT operation.

9. The QKD fast privacy amplification method based on number theory transformation according to claim 8, characterized in that, The set of NTT twitch factors corresponding to the first-level operation is There are a total of 8 NTT twitch factors; The set of NTT twitch factors corresponding to the second-level operation is There are a total of 8 NTT twitch factors; The set of NTT twitch factors corresponding to the third-level operation is as follows: There are a total of 8 NTT twitch factors; The set of NTT twitch factors corresponding to the fourth-level operation is as follows: There are a total of 8 NTT twitch factors.

10. The QKD fast privacy amplification method based on number theory transformation according to claim 1, characterized in that, The specific process of performing NTT operations on the corresponding column vectors in the first matrix and the second matrix is ​​as follows: 1) Combine the corresponding column vectors in the first matrix and the second matrix to form a pair of column data, resulting in a total of C pairs of column data; 2) Select at least G pairs of column data sequentially from C pairs of column data, and input the selected G pairs of column data into G independent processing channels to perform NTT operations in parallel. Here, G is greater than or equal to 1. Each independent processing channel includes two parallel NTT operations, which are used to perform NTT operations on the two column vectors in the input pair of column data at the same time, to obtain the corresponding first frequency domain column vector and second frequency domain column vector respectively. 3) Repeat step 2) until column C has finished processing the data.

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