A Communication Encryption Method and System Based on Triple Clock-Controlled Stop-and-Go Stream Cipher

Abstract

This invention belongs to the field of communication encryption, and particularly relates to a communication encryption method and system based on triple clock-controlled stop-go stream cipher. The method includes: generating a 32-bit encryption key using random positive integer tokens; deriving three seeds through three asymmetric bit transformations and initializing them with multiple rounds of linear feedback; generating three linear feedback shift registers with different tap configurations; the triple clock-controlled stop-go mechanism selectively drives register updates based on the carry bit state, and its output is XORed to generate a key stream; protocol data is serialized into a big-endian byte stream via a custom binary protocol stack and then XORed byte-by-byte with the key stream for in-place encryption; the receiver synchronously generates the key stream for decryption and deserialization to recover the protocol data, achieving zero-round-trip latency instantaneous encrypted communication.

Description

Technical Field

[0001] This invention belongs to the field of communication encryption, and particularly relates to a communication encryption method and system based on triple clock-controlled stop-and-go stream cipher. Background Technology

[0002] Existing game communication encryption schemes generally suffer from technical deficiencies related to real-time performance, integration, and resistance to analysis. While standard TLS / HTTPS schemes provide a mature secure channel, the two round-trip times (2-RTT) introduced during the handshake process can cause significant latency jitter in high-concurrency real-time scenarios such as mobile device disconnection and reconnection, severely impacting the player experience. Schemes employing common symmetric encryption algorithms such as AES and RC4 require additional data encapsulation and parsing, as their encryption process is independent of the game's custom binary serialization protocol. This not only increases processing overhead but also results in ciphertext data streams that still retain pattern characteristics recognizable by standard cryptanalysis tools. Schemes relying solely on plaintext communication or WebSockets lack encryption protection entirely, making their protocol formats highly susceptible to interception and tampering. Furthermore, in the field of security authentication, the quantum group signature method based on quantum short-key cryptography disclosed in Chinese patent CN115174066B achieves group signatures through quantum key distribution, quantum one-time pad encryption, and quantum walk teleportation. Although it offers high security, this scheme heavily relies on quantum hardware devices and complex quantum state preparation and transmission processes, resulting in extremely high system complexity. This makes it unsuitable for low-overhead, low-latency game communication scenarios on consumer mobile terminals. In summary, existing technologies lack a game communication encryption scheme that can be deeply integrated with custom binary protocols, achieving a closed-loop encryption and serialization system at the protocol level, while simultaneously satisfying zero round-trip time (0-RTT), minimal packet overhead, resistance to replay attacks, and difficulty in protocol reverse engineering. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes a communication encryption method and system based on triple-clocked stop-and-go stream cipher, comprising: generating a random positive integer token and extracting bits from it to form a 32-bit encryption key; performing three asymmetric bit transformations on the encryption key to generate a first seed, a second seed, and a third seed respectively; generating initial states of three linear feedback shift registers with different tap configurations after multiple rounds of linear feedback shift initialization; selectively driving some or all of the linear feedback shift registers to update their states based on the carry bit states of the three linear feedback shift registers through a triple-clocked stop-and-go mechanism, and performing an XOR operation on the current state values ​​output by each register to generate a key stream; serializing the protocol data to be transmitted into a big-endian binary byte stream through a custom binary protocol stack, performing byte-by-byte in-situ XOR encryption using the key stream to generate ciphertext data and sending it; the receiver using the same encryption key and clock configuration as the sender, generating a synchronization key stream for in-situ XOR decryption, recovering the binary byte stream and deserializing it into protocol data. This invention achieves real-time encrypted communication with zero round-trip latency, deeply integrates encryption with the protocol stack, has strong resistance to protocol reverse analysis, and has minimal packet overhead.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] Communication encryption methods based on triple clock-controlled stop-and-go stream ciphers include:

[0006] Generate a random positive integer token, extract bits at preset positions from the token, and combine them into a 32-bit encryption key;

[0007] The encryption key is subjected to three asymmetric bit transformations to generate a first seed, a second seed, and a third seed, respectively. Using the first seed, the second seed, and the third seed, multiple rounds of linear feedback shift initialization are performed to generate the initial states of a first linear feedback shift register, a second linear feedback shift register, and a third linear feedback shift register with different tap configurations.

[0008] Through a triple clock-controlled stop mechanism, based on the carry bit states of the first, second, and third linear feedback shift registers, some or all of the linear feedback shift registers are selectively driven to update their states, and the current state values ​​output by each linear feedback shift register are XORed to generate a key stream.

[0009] The protocol data to be transmitted is serialized into a big-endian binary byte stream using a custom binary protocol stack;

[0010] Using the key stream, the binary byte stream is subjected to byte-by-byte in-situ XOR encryption to generate ciphertext data, which is then sent to the receiver.

[0011] The receiver uses the same encryption key and clock control configuration as the sender to generate a key stream synchronized with the sender. It performs byte-by-byte in-situ XOR decryption on the received ciphertext data to recover the binary byte stream, and then deserializes the binary byte stream into protocol data through the custom binary protocol stack.

[0012] Specifically, it is combined into a 32-bit encryption key, including:

[0013] Generate a random positive integer token, extract the first preset bit segment from the token, and determine its corresponding integer value as the reference offset;

[0014] The extraction start position is obtained by performing a modulo operation between the reference offset and a preset base.

[0015] Starting from the extraction start position in the token, continuously extract bits of a second preset length along a preset direction to form a candidate key fragment;

[0016] Extract the remaining bits from the token that did not participate in generating the candidate key fragment and did not participate in generating the reference offset, select bits of a third preset length from them, and combine them into an obfuscation mask;

[0017] The candidate key fragment is XORed with the obfuscation mask to obtain a 32-bit encryption key.

[0018] Specifically, the encryption key undergoes three asymmetric bit transformations, including:

[0019] Extract a preset bit segment from the random positive integer token that was not used to generate the encryption key, and determine its corresponding integer value as the transformation adjustment factor;

[0020] The transformation adjustment factor is XORed with a first preset constant to obtain a first dynamic mask; the transformation adjustment factor is then cyclically shifted left by a first preset number of bits to obtain a second dynamic mask.

[0021] After cyclically shifting the transformation adjustment factor to the right by a second preset number of bits, a third dynamic mask is obtained;

[0022] The encryption key is XORed with the first dynamic mask. The XOR result is then processed by linear feedback, and the result is XORed with the third dynamic mask to obtain the first seed.

[0023] Specifically, performing three asymmetric bit transformations on the encryption key further includes:

[0024] The first seed is subjected to parity bit swapping, the swapping result is inverted after linear feedback processing, and then the inverted result is XORed with the first dynamic mask to obtain the second seed.

[0025] The second seed is subjected to half-byte swapping. The swapping result is then processed by linear feedback, and the processing result is XORed with the second dynamic mask to obtain the third seed.

[0026] Specifically, generating the keystream includes:

[0027] Extract the third preset bit segment from the random positive integer token that was not used to generate the encryption key, the reference offset, or the transformation adjustment factor, and determine its corresponding integer value as the clock control adjustment factor;

[0028] The clock control adjustment factor is XORed with the second preset constant to obtain the clock control mask; the clock control adjustment factor is then cyclically shifted left by a third preset number of bits to obtain the clock control disturbance factor.

[0029] In each clock cycle, the first clock sampling bit located at the highest bit in the current carry bit and corresponding current state value of the first linear feedback shift register, the second clock sampling bit located at the highest bit in the current carry bit and corresponding current state value of the second linear feedback shift register, and the third clock sampling bit located at the highest bit in the current carry bit and corresponding current state value of the third linear feedback shift register are respectively acquired.

[0030] Specifically, generating the keystream also includes:

[0031] The first clock control determination bit is obtained by performing an XOR operation between the current carry bit of the first linear feedback shift register and the first clock control sampling bit; the second clock control determination bit is obtained by performing an XOR operation between the current carry bit of the second linear feedback shift register and the second clock control sampling bit; and the third clock control determination bit is obtained by performing an XOR operation between the current carry bit of the third linear feedback shift register and the third clock control sampling bit.

[0032] The first clock control decision bit, the second clock control decision bit, and the third clock control decision bit are concatenated from the high bit to the low bit to form a three-bit binary number, which is used as the clock control selection code;

[0033] The clock selection code is XORed with the lowest three bits of the clock mask to obtain the clock drive code.

[0034] Specifically, generating the keystream also includes:

[0035] Based on the value of the clock control drive code, determine the combination of linear feedback shift registers that are driven to update the state in the current clock cycle;

[0036] The intermediate key is obtained by XORing the current state values ​​of the clock-driven linear feedback shift registers and the current state values ​​of the non-clock-driven linear feedback shift registers.

[0037] The intermediate key word is XORed with the clock perturbation factor to generate a 32-bit key word, which is then filled into the key stream buffer.

[0038] Specifically, the combination of linear feedback shift registers driven to perform state updates within the current clock cycle is determined, including:

[0039] When the clock control drive code is 000 or 111, the first linear feedback shift register, the second linear feedback shift register, and the third linear feedback shift register are all driven to perform a linear feedback shift operation once. When the clock control drive code is 001, 010, 100, 110, 101, or 011, only the clock drives the two linear feedback shift registers corresponding to the bits that are 1 in the clock control drive code to perform a linear feedback shift operation once, while the other linear feedback shift register keeps its current state value unchanged.

[0040] A communication encryption system based on triple clock-controlled stop-and-go stream cipher includes:

[0041] The token generation module is configured to: generate a random positive integer token, extract bits at preset positions from the token, and combine them into a 32-bit encryption key;

[0042] The initialization module is configured to: perform three asymmetric bit transformations on the encryption key to generate a first seed, a second seed, and a third seed respectively; and use the first seed, the second seed, and the third seed to generate the initial states of a first linear feedback shift register, a second linear feedback shift register, and a third linear feedback shift register with different tap configurations through multiple rounds of linear feedback shift initialization.

[0043] The key stream generation module is configured to: selectively drive some or all of the linear feedback shift registers to update their states based on the carry bit states of the first, second, and third linear feedback shift registers using a triple clock-controlled stop mechanism, and perform an XOR operation on the current state values ​​output by each linear feedback shift register to generate a key stream.

[0044] Specifically, the communication encryption system also includes:

[0045] The serialization module is configured to serialize the protocol data to be transmitted into a big-endian binary byte stream using a custom binary protocol stack.

[0046] The encryption module is configured to: use the key stream to perform byte-by-byte in-situ XOR encryption on the binary byte stream, generate ciphertext data, and send it to the receiver;

[0047] The synchronous decryption module is configured such that: the receiver uses the same encryption key and clock control configuration as the sender to generate a key stream synchronized with the sender, performs byte-by-byte in-situ XOR decryption on the received ciphertext data to recover the binary byte stream, and then deserializes the binary byte stream into protocol data through the custom binary protocol stack.

[0048] Compared with the prior art, the beneficial effects of the present invention are:

[0049] This invention effectively solves the technical defects of existing communication encryption schemes in terms of real-time performance, integration, and anti-analysis capabilities by deeply integrating random token derivation, triple asymmetric bit transformation, and triple clock-controlled stop mechanism. First, the encryption key is generated by dynamically offsetting and XORing the random positive integer token with a confusion mask. Combined with the transformation adjustment factor in the token, three asymmetric bit transformations and multiple rounds of linear feedback initialization are performed, so that the seed and the initial state of the register change dynamically and unpredictably for each session. This eliminates the reproducibility of the key from the root and gives the scheme the ability to resist replay attacks and reverse engineering of the protocol. Secondly, the triple clock-controlled stop mechanism generates clock-driven codes in real time based on the carry and sample bits of each register, selectively driving register updates irregularly. This results in a keystream with high-order nonlinearity and long-period characteristics, and its output does not carry any fixed pattern characteristics of standard encryption algorithms, making it impossible for cheating programs or cryptanalysis tools to identify the encryption logic through the ciphertext. Furthermore, the encryption process directly operates on the big-endian byte stream serialized by a custom binary protocol stack, achieving an integrated closed loop of encryption and protocol serialization. No additional data encapsulation and parsing are required, greatly reducing processing overhead and packet size. Finally, the receiver can synchronously generate a keystream based on a consistent encryption key and clock configuration, without any handshake negotiation, truly achieving zero-round-trip latency instant encrypted communication, which is particularly suitable for real-time interactive scenarios such as games that are highly sensitive to latency. Attached Figure Description

[0050] Figure 1 This is a flowchart of the communication encryption method based on triple clock-controlled stop-and-go stream cipher of the present invention;

[0051] Figure 2 The flowchart shows how to assemble a 32-bit encryption key for this invention.

[0052] Figure 3 This is a block diagram of the communication encryption system based on triple clock-controlled stop-and-go stream cipher of the present invention. Detailed Implementation

[0053] Example 1

[0054] Please see Figure 1 The present invention provides an embodiment of a communication encryption method based on a triple clock-controlled stop-and-go stream cipher, applied to secure communication between a game client and a server, comprising the following steps:

[0055] S1. After the server and client establish a connection, a random positive integer token is generated. Bits at a preset position are extracted from the token and combined to form a 32-bit encryption key. In this embodiment, extracting bits at a preset position from the token essentially means that the communicating parties have pre-agreed a set of deterministic operation rules to dynamically determine the extraction starting point based on the token's own value, rather than pointing to an absolutely fixed physical coordinate. This rule first extracts an integer value from the pre-specified high bit segment of the random positive integer token as a base offset, and then performs a modulo operation on this offset with a preset fixed base to obtain an extraction starting position that slides within that base. This design allows the key fragment extraction starting point of each session to be dynamically adjusted according to the change of the high bit value of the token generated in each session. Logically, it fully realizes the technical connotation of preset position extraction, ensuring that the sending and receiving parties can accurately and synchronously extract positions based on the same token and the same set of agreed rules, while eliminating the risk of key predictability caused by fixed position extraction.

[0056] S2. Perform three asymmetric bit transformations on the encryption key to generate a first seed, a second seed, and a third seed respectively; using the first seed, the second seed, and the third seed, perform multiple rounds of linear feedback shift initialization to generate the initial states of a first linear feedback shift register, a second linear feedback shift register, and a third linear feedback shift register with different tap configurations respectively.

[0057] It should be further explained that one implementation method of this embodiment, which involves multiple rounds of linear feedback shift initialization, is as follows:

[0058] The first seed is used as the initial value and input to the first linear feedback shift register. 2048 rounds of linear feedback shift operation are performed to obtain the initial state of the first linear feedback shift register. The first linear feedback shift register is configured with a first feedforward step size and a first feedback step size.

[0059] In this embodiment, using a specific 32-bit seed value as an example, the process of performing one round of linear feedback shift operation is as follows:

[0060] Assuming the current state value of the first linear feedback shift register is 0x89ABCDEF (hexadecimal representation), a single linear feedback shift operation is now performed:

[0061] First, extract the values ​​of bits 31, 6, 4, 2, and 1 from this state value—bit 31 is 1 (most significant bit), bit 6 is 1, bit 4 is 1, bit 2 is 1, and bit 1 is 1.

[0062] Perform an XOR operation between the above five bits and the state value itself, i.e., 1^1^1^1^1^1 = 1 (the state value itself is XORed, i.e., the highest bit is 1).

[0063] Perform a bitwise AND operation between the XOR result 0 and 0x00000001 to obtain the feedback bit 0;

[0064] Shift the feedback bit 0 left by 31 bits to the most significant bit position to get 0x00000000;

[0065] Shift the original state value 0x89ABCDEF one bit to the right to get 0x44D5E6F7;

[0066] Perform a bitwise OR operation between the left-shifted feedback bit and the right-shifted state value, i.e., 0x00000000|0x44D5E6F7=0x44D5E6F7. This is the new state value of the register after completing one round of linear feedback shift operation.

[0067] This operation was repeated 2048 times, which not only stirred and diffused the initial seed value bit by bit, but also generated an initial state that was not statistically significantly related to the original seed.

[0068] The second seed is used as the initial value and input to the second linear feedback shift register. 2048 rounds of linear feedback shift operation are performed to obtain the initial state of the second linear feedback shift register. The second linear feedback shift register is configured with a second feedforward step size and a second feedback step size.

[0069] The third seed is used as the initial value and input to the third linear feedback shift register. 2048 rounds of linear feedback shift operation are performed to obtain the initial state of the third linear feedback shift register. The third linear feedback shift register is configured with a third feedforward step size and a third feedback step size.

[0070] In this embodiment, the second and third seeds perform 2048 rounds of linear feedback shift operations. Refer to the specific operation of the first seed, which will not be repeated here.

[0071] The first feedforward step size is different from the first feedback step size, the second feedforward step size is different from the second feedback step size, and the third feedforward step size is different from the third feedback step size, so that the first linear feedback shift register, the second linear feedback shift register and the third linear feedback shift register have different tap configurations. The specific parameters of the corresponding feedforward step size (dis1) and feedback step size (dis2) are shown in Table 1.

[0072] Table 1. Tap configuration of the three LFSRs

[0073] 0 55 24 1 57 7 2 58 19

[0074] S3. Through the triple clock-controlled stop mechanism, based on the carry bit states of the first linear feedback shift register, the second linear feedback shift register, and the third linear feedback shift register, some or all of the linear feedback shift registers are selectively driven to update their states, and the current state values ​​output by each linear feedback shift register are XORed to generate a key stream.

[0075] S4. Serialize the protocol data to be transmitted into a big-endian binary byte stream using a custom binary protocol stack;

[0076] S5. Using the key stream, perform byte-by-byte in-situ XOR encryption on the binary byte stream to generate ciphertext data and send it to the receiver;

[0077] S6. The receiver uses the same encryption key and clock control configuration as the sender to generate a key stream synchronized with the sender, performs byte-by-byte in-situ XOR decryption on the received ciphertext data, recovers the binary byte stream, and then deserializes the binary byte stream into protocol data through the custom binary protocol stack.

[0078] As a concrete example, suppose in a massively multiplayer online role-playing game, player A is using a skill to attack a monster in an open-world map. At this moment, the game client needs to send the protocol data "Skill ID=205, Target Monster ID=1734, Skill Coordinates (x=342, y=567)" to the server. In traditional solutions, if standard TLS / HTTPS encryption is used, the client needs to complete certificate verification and handshake negotiation with the server, which takes at least two round-trip times. In scenarios with mobile network jitter, players will clearly perceive stuttering delays in skill release. If AES symmetric encryption is used, although the encryption itself has lower computational overhead, the encryption module is independent of the game's own binary serialization protocol. It is necessary to first serialize the protocol data into a byte stream and then call a separate encryption library for secondary encapsulation. The processing flow is fragmented, and the encrypted ciphertext data stream still has characteristic patterns that can be identified by protocol analysis tools such as Wireshark. Cheat program developers can reverse engineer the client program to locate the AES S-box or key expansion function, and then crack the encryption logic. If plaintext WebSocket transmission is used directly, cheat program tools can directly intercept and parse the skill ID, target ID, and coordinates, thereby writing third-party malicious reverse engineering and illegal cheat scripts, which seriously disrupts the game balance. Using the method in this embodiment, when the client establishes a connection with the server, it dynamically generates a 32-bit encryption key using a 63-bit random positive integer token, and completes the initialization of three linear feedback shift registers and the pre-filling of the keystream buffer pool, achieving zero round-trip latency throughout. The moment the player presses the skill key, the client directly serializes the aforementioned protocol data into a compact big-endian byte stream using a custom binary protocol stack. It then immediately retrieves an equal-length keystream from the 4096-byte keystream buffer pool, performs in-situ XOR encryption on the byte stream, generates ciphertext data packets, and sends them. Even if cheating tools intercept packets at the network layer between the client and server, the ciphertext does not carry any magic words or signature patterns from standard encryption algorithms, and the keystream state of the stream cipher dynamically changes with each communication context. Therefore, attackers cannot perform protocol format analysis or replay attacks on the intercepted ciphertext. After receiving the ciphertext, the server uses the same synchronously generated key stream to perform in-situ XOR decryption, and then deserializes it through the same set of custom binary protocol stacks to restore the skill ID, target ID and coordinates. This drives the server's combat logic to complete the damage calculation and broadcast it to nearby players. The entire process, from the moment the skill is pressed to the server's response, involves only a byte-by-byte XOR operation as overhead for encryption and serialization, with no additional memory allocation. Players are completely unaware of any encryption delay.

[0079] Example 2

[0080] Please see Figure 2 It should be further explained that this embodiment combines a 32-bit encryption key, including:

[0081] S101. Generate a random positive integer token, extract the first preset bit segment from the token, and determine its corresponding integer value as the reference offset; In this embodiment, the random positive integer token is generated by the server through a cryptographically secure random number generator after the connection is established, and its bit width is 63 bits to ensure sufficient entropy source; The first preset bit segment is the high 5 bits of the token, which, after being converted into an integer, has a value range of 0 to 31 natural numbers, thereby providing a dynamic reference within the range of 0 to 31 for the subsequent extraction starting position.

[0082] S102. Perform a modulo operation between the reference offset and the preset base to obtain the extraction start position. In this embodiment, the preset base is set to 32, which is the target bit width of the encryption key. The modulo operation ensures that the extraction start position is always constrained between the 0th and 31st bits of the token. For example, if the reference offset is 13, then 13 mod 32 = 13, and the extraction start position is determined to be the 13th bit of the token, that is, the key fragment is continuously extracted from this bit along the preset direction.

[0083] S103. Starting from the extraction start position in the token, continuously extract bits of a second preset length along a preset direction to form a candidate key fragment. In this embodiment, the preset direction is to continuously extract towards the lower bits, and the second preset length is 32 bits. For example, if the extraction start position is the 13th bit, then the 13th to the 44th bits of the token, a total of 32 bits, are extracted to form a candidate key fragment, ensuring that the fragment covers a complete 32-bit key width. In this embodiment, the second preset length is set to 32 bits because the target bit width of the encryption key is explicitly designed to be 32 bits. Therefore, after dynamically locating the extraction start point from the token, exactly 32 bits must be continuously extracted to form a complete candidate key fragment, so as to directly cover the entire bit width required by the encryption key. For a 63-bit random positive integer token, extracting 32 bits continuously from the starting position towards the lower bit direction can make full use of the sufficient entropy source provided by the token, ensuring that the candidate key fragment strictly matches the final 32-bit encryption key in length. This avoids both insufficient bit width leading to a loss of key strength and bit width overflow causing a waste of token bit resources or extraction exceeding the limit, thus achieving a precise balance between deterministic rules and randomness.

[0084] S104. Extract the remaining bits from the token that did not participate in generating the candidate key fragment and the reference offset, and select bits of a third preset length from them to form a confusion mask. In this embodiment, the remaining bits are all bits in the token except for the first preset bit segment and the bit segment occupied by the candidate key fragment, and the third preset length is 32 bits. 32 bits are continuously selected from the remaining bits in a preset offset direction to form a confusion mask. This confusion mask introduces an additional source of randomness independent of the candidate key fragment. In this embodiment, the third preset length is set to 32 bits because the purpose of the confusion mask is to perform a bitwise XOR operation with the candidate key fragment to generate the final encryption key. The XOR operation requires that the bit widths of the two operands be strictly equal for bitwise execution. Therefore, when selecting the confusion mask from the remaining bit segments in the token that did not participate in generating the candidate key fragment and the reference offset, 32 bits with the exact same bit width as the candidate key fragment must be extracted. With a 63-bit random positive integer token architecture, after subtracting the bit width extracted from the occupied base offset and the bit width extracted from the candidate key fragment from the total bit width of the token, the remaining bit segment has enough capacity to provide exactly 32 bits of obfuscation mask material. This ensures the mathematical rigor of the XOR operation and makes full use of the independent entropy sources in the token that have not yet been mined. As a result, the final generated encryption key combines the randomness of two non-overlapping bit segments in the token, eliminating the linear predictability of a single-source key fragment. In this embodiment, when generating candidate key fragments, the preset direction is set to continuously extract from the extraction start position towards the lower bit direction to meet the requirement that the key fragment completely covers a 32-bit width. For the extraction of the obfuscation mask, the preset offset direction is determined by another set of direction rules agreed upon by the communicating parties based on the specific position and continuous available length of the remaining bit segment in the 63-bit random positive integer token. The purpose is to extract from the independent bit region in the token that has not yet been mined, along the direction that is most conducive to ensuring that the obfuscation mask and the candidate key fragment do not overlap and that their entropy sources are fully isolated. In the specific scenario of the embodiment, the candidate key fragment has occupied 32 consecutive bits in the token from the extraction start position towards the lower bit direction, and the remaining bit segment is distributed in the high bit area and low bit area of ​​the token. At this time, the preset offset direction is agreed to start from one end of the remaining bit segment and continuously select 32 bits towards the other end to ensure that the selected obfuscation mask and the candidate key fragment have no intersection in the token, thereby maximizing the randomness and unpredictability of the final encryption key.

[0085] S105. Perform an XOR operation between the candidate key fragment and the obfuscation mask to obtain a 32-bit encryption key. In this embodiment, the XOR operation is performed bit by bit between the candidate key fragment and the obfuscation mask, so that the final generated encryption key integrates the random characteristics of the two independent bit segments in the token, eliminates the key predictability caused by fixed position extraction, and makes full use of all available bit entropy values ​​of the token.

[0086] As a concrete example, taking the scenario of player A releasing a skill in a massively multiplayer online role-playing game as an example, the generation process of the 32-bit encryption key in this embodiment is as follows: When player A's mobile client connects to the game server for the first time, the server generates a 63-bit random positive integer token using a cryptographically secure random number generator. Assume the hexadecimal representation of this token is 0x3F2A8B1C9D4E6F07. First, the high 5 bits of this token are extracted as the first preset bit segment, i.e., 01111, and converted to the integer value 15, which is determined as the base offset. Then, the base offset 15 is moduloed by the preset base 32, i.e., 15 mod 32 = 15, resulting in the extraction starting position being the 15th bit. Next, starting from the 15th bit of the 63-bit token, 32 bits are continuously extracted towards the lower bits, i.e., all bits from the 15th to the 46th bit are extracted and combined to form a candidate key fragment, assuming this fragment is 0xA8B1C9D4. At this point, excluding the high 5 bits and the extracted 32-bit candidate key fragment, the remaining 26 bits in the token, along with the empty lower bits, constitute the remaining bit set. From this remaining bit set, 32 bits are continuously selected in a preset offset direction to form a confusion mask, assuming this confusion mask is 0xE4D2C3B1. Finally, the candidate key fragment 0xA8B1C9D4 is XORed bit-by-bit with the confusion mask 0xE4D2C3B1 to obtain the 32-bit encryption key 0x4C730A65. The generation of this encryption key incorporates the randomness of two non-overlapping bit segments in the token. Even if an attacker intercepts the token at the network layer, the starting position and the final encryption key are unpredictable because the reference offset for each connection dynamically changes with the high 5 bits of the token. This effectively eliminates the security risk of direct key reproduction under traditional fixed-position extraction methods and fully utilizes all available bit entropy values ​​of the 63-bit token.

[0087] It should be further explained that this embodiment performs three asymmetric bit transformations on the encryption key, including:

[0088] S201. Extract the preset bit segment from the random positive integer token that is not used to generate the encryption key, and determine its corresponding integer value as the transformation adjustment factor. In this embodiment, the preset bit segment is another specified bit segment in the 63-bit random positive integer token, excluding the bit segment used to generate the encryption key and the bit segment used to generate the reference offset. The position of this bit segment in the token is predetermined, and its corresponding integer value is used as the transformation adjustment factor, so that the subsequent three asymmetric bit transformations are dynamically bound to the token of this communication, ensuring that the transformation adjustment factor corresponding to each connection is different.

[0089] S202. Perform an XOR operation between the transformation adjustment factor and a first preset constant to obtain a first dynamic mask; cyclically shift the transformation adjustment factor left by a first preset number of bits to obtain a second dynamic mask; cyclically shift the transformation adjustment factor right by a second preset number of bits to obtain a third dynamic mask. In this embodiment, the first preset constant is GENIUS_NUMBER, and the first and second preset number of bits are 7 bits and 11 bits respectively. Through three different transformation operations—XOR constant, cyclic left shift, and cyclic right shift—three distinct dynamic masks are derived from the same transformation adjustment factor, providing independent dynamic obfuscation parameters for the subsequent three asymmetric bit transformations. In this embodiment, the first preset number of bits (7 bits) and the second preset number of bits (11 bits) are set based on the fact that the design goal of the three asymmetric bit transformations is to generate three statistically independent and non-derivative seeds. When deriving three dynamic masks from the same transformation adjustment factor, it is necessary to ensure that there is no simple linear correlation or cyclic symmetry between the masks to prevent attackers from deducing the transformation adjustment factor by analyzing the algebraic relationship between the masks. Choosing 7 and 11 bits, two coprime odd values, as the cyclic shift bits, combined with an XOR constant operation, allows the first, second, and third dynamic masks to exhibit significant structural differences in bit distribution. Even if the transformation adjustment factor fluctuates only within a small range, the mask values ​​generated after cyclic shifting with different bit numbers will be sufficiently diffused in terms of Hamming weight and bit pattern, eliminating the correlation between masks. Simultaneously, the values ​​of 7 and 11 bits balance computational efficiency and diffusion effect; they avoid insufficient high-low bit confusion due to too small a shift bit, and also avoid wasting computational resources due to too large a shift bit. In the implementation scenario of a 63-bit random positive integer token, this ensures that each of the three seeds receives independent and unpredictable dynamic confusion protection on the cascaded generation path.

[0090] S203. Perform the first asymmetric bit transformation: XOR the encryption key with the first dynamic mask, process the XOR result through linear feedback, and then XOR the result with the third dynamic mask to obtain the first seed. In this embodiment, the linear feedback process uses the same linear feedback function as the aforementioned linear feedback shift register, i.e., linearity(key)=((((key>>31)^(key>>6)^(key>>4)^(key>>2)^(key>>1)^key)&0x00000001)<<31)|(key>>1). Through the initial confusion of the encryption key and the first dynamic mask, the diffusion and agitation of the linear feedback function, and the secondary confusion of the third dynamic mask, the first seed is generated. The first seed has been significantly separated from the original encryption key in terms of statistical characteristics. In this embodiment, the expression linearity(key)=((((key>>31)^(key>>6)^(key>>4)^(key>>2)^(key>>1)^key)&0x00000001)<<31)|(key>>1) defines a round of state update function for the linear feedback shift register; where key represents the current 32-bit state value of the register, >> is the logical right shift operator, key>>31 extracts the most significant bit of the current state value, and key>>6, key>>4, key>>2, and key>>1 extract the most significant bit of the current state value respectively. 6. The values ​​of bits 4, 2, and 1; ^ is the bitwise XOR operator, which performs an XOR operation on the most significant bit with the four tap bits mentioned above to obtain a feedback bit; & is the bitwise AND operator, &0x00000001 retains the least significant bit of the XOR result and masks the remaining high bits, ensuring that the feedback bit is only 0 or 1; << is the logical left shift operator, <<31 shifts the feedback bit to the most significant bit position; | is the bitwise OR operator, key>>1 shifts the original state value one bit to the right and performs a bitwise OR operation with the feedback bit shifted to the most significant bit, thereby completing the alternation of the register state and generating an updated 32-bit state value. This function, through specific tap configuration and linear feedback mechanism, enables the register state to achieve non-linear diffusion and churning under each clock cycle, and is the core operation unit for constructing the initial state of three linear feedback shift registers and generating the key stream.

[0091] S204. Perform the second asymmetric bit transformation: swap the odd and even bits of the first seed, invert the swap result after linear feedback processing, and then XOR the inverted result with the first dynamic mask to obtain the second seed. In this embodiment, the odd and even bit swap is to swap the odd and even bits of the 32-bit first seed in pairs. After the bit arrangement is shuffled by the odd and even swap, the second seed is generated by sequentially passing through linear feedback diffusion, bit-by-bit inversion and flipping, and XORing with the first dynamic mask. The generation of the second seed takes the first seed as input, establishing a cascaded dependency relationship between the three transformations, so that the local information of any transformation result cannot be used independently.

[0092] S205. Perform the third asymmetric bit transformation: perform half-byte swap on the second seed, process the swap result through linear feedback, and then XOR the processing result with the second dynamic mask to obtain the third seed. In this embodiment, the half-byte swap is to cross-exchange the half-bytes within the high 16 bits and low 16 bits of the 32-bit second seed. After recombining the bit structure through half-byte swap, the third seed is generated by sequentially passing through linear feedback diffusion and XORing with the second dynamic mask. The generation of the third seed takes the second seed as input. Thus, a chain-cascaded generation path is formed between the first seed, the second seed, and the third seed. With the different dynamic masks introduced by each seed, the statistical correlation between seeds that may be caused by the derivation of the same key is completely eliminated. This ensures that even if an attacker knows the encryption key and the fixed transformation rules, they will not be able to reproduce the correct three seeds because they cannot know the transformation adjustment factor bound to the current communication token.

[0093] As a concrete example, taking the scenario of player A releasing a skill in a massively multiplayer online role-playing game as an example, the complete process of performing three asymmetric bit transformations on the encryption key in this embodiment is as follows:

[0094] After the server completes the generation of the encryption key 0x4C730A65, it extracts a preset bit segment that was not involved in the generation of the encryption key from the same 63-bit random positive integer token. Assuming that the preset bit segment is the 46th to 41st bits of the token, a total of 6 bits, its binary representation is 101101. It is converted into a decimal integer, which yields the value 45. This value 45 is determined as the transformation adjustment factor for this communication. Next, the transformation adjustment factor 45 is XORed with the first preset constant GENIUS_NUMBER (assumed to be 0x9E3779B9) to obtain the first dynamic mask 0x9E3779DC; the transformation adjustment factor 45 is cyclically shifted left by 7 bits, i.e. 45<<7|45>>(32-7), and the second dynamic mask 0x00001680 is obtained by calculation; the transformation adjustment factor 45 is cyclically shifted right by 11 bits, i.e. 45>>11|45<<(32-11), and the third dynamic mask 0x00168000 is obtained by calculation. Then, the first asymmetric bit transformation is performed: the encryption key 0x4C730A65 is XORed with the first dynamic mask 0x9E3779DC to obtain 0xD24473B9. This result is input into the linear feedback function linearity(key)=((((key>>31)^(key>>6)^(key>>4)^(key>>2)^(key>>1)^key)&0x00000001)<<31)|(key>>1) for processing. The processing result is then XORed with the third dynamic mask 0x00168000 to obtain the first seed seed0. Subsequently, a second asymmetric bit transformation is performed: all odd-numbered bits of the first seed seed0 are swapped with their even-numbered bits in pairs, completing the odd-even bit swap. The swap result is then input into the same linear feedback function as described above for processing. Each bit of the processed result is inverted, and then XORed with the first dynamic mask 0x9E3779DC to obtain the second seed seed1. Finally, a third asymmetric bit transformation is performed: the high 16 bits and low 16 bits of the second seed seed1 are each divided into four nibbles. The nibbles within the high 16 bits and the nibbles within the low 16 bits are rearranged according to a preset cross-correspondence relationship, completing the nibble reassembly. The reassembly result is input into the linear feedback function for processing, and then XORed with the second dynamic mask 0x00001680 to obtain the third seed seed2. At this point, the first, second, and third seeds are generated.In this example, since the transformation adjustment factor 45 originates from a specific bit segment of a unique 63-bit random positive integer token for each connection, even if an attacker completely masters the fixed operation rules of the three asymmetric bit transformations and the tap configuration of the linear feedback function through reverse engineering, they cannot derive the correct first, second, and third dynamic masks because they cannot obtain the actual value of the preset bit segment in the current communication token. Consequently, they cannot reproduce the first, second, and third seeds. At the same time, the generation paths of the three seeds present a chain-cascaded structure, that is, the second seed depends on the first seed, and the third seed depends on the second seed. Furthermore, each introduces a different dynamic mask, which completely eliminates the statistical correlation between seeds that may be caused by the derivation of the same source key, ensuring the forward security and session independence of the seed generation process.

[0095] Example 3

[0096] It should be further explained that the key stream generation in this embodiment includes:

[0097] S301. Extract the third preset bit segment from the random positive integer token that was not used to generate the encryption key, the base offset, or the transformation adjustment factor, and determine its corresponding integer value as the clock control adjustment factor. In this embodiment, the aforementioned 63-bit token 0x3F2A8B1C9D4E6F07 is continued, and its binary representation is 01111110010101010001011110010011101010011100010111001011100010111000111000111000111000111000111000111000111000111. Among them, the encryption key generation stage has occupied bits 62 to 58 (5 bits in total) of the token as the base offset, and bits 15 to 46 (32 bits in total) and some remaining bits as the source of candidate key fragments and obfuscation masks; the transformation adjustment factor generation stage has occupied bits 46 to 41 (6 bits in total) of the token. The 33rd to 28th bits of the token are extracted as the third preset bit segment. These 6 bits are 110011. Converting them to a decimal integer gives 51. This value 51 is determined as the clock control adjustment factor for this communication.

[0098] S302. Perform an XOR operation between the clock control adjustment factor and the second preset constant to obtain the clock control mask; cyclically shift the clock control adjustment factor left by a third preset number of bits to obtain the clock control disturbance factor; in this embodiment, the second preset constant is 0x6D2A4F81, whose binary representation is 01101101001010100100111110000001. The 32-bit binary representation of the clock control adjustment factor 51 is 000000000000000000000000000110011. Perform a bitwise XOR operation between the two, that is:

[0099] 00000000000000000000000000110011

[0100] 01010100100111110110010, resulting in the clock mask 0x6D2A4FB2.

[0101] The third preset bit length is 5 bits. The clock control adjustment factor 51 is cyclically shifted left by 5 bits, i.e., (51<<5)|(51>>(32-5))=(51×32)|0=1632, which is represented in hexadecimal as 0x00000660. This is determined as the clock control perturbation factor. In this embodiment, the second preset constant is set to 0x6D2A4F81 because the generation of the clock control mask requires XORing the clock control adjustment factor with a fixed constant with good random characteristics. This ensures that even if the clock control adjustment factor exhibits regular or low-entropy values ​​in continuous sessions, the XORed clock control mask can still fully diffuse and present an unpredictable bit distribution pattern. The selection of this constant follows the principle of avoiding weak mask states in cryptography. The ratio of 0s and 1s in its binary representation is roughly balanced. The bit sequence is designed so that after being XORed with the clock control adjustment factor with only 6 effective bits, it can effectively spread local small-range disturbances to all bits of the 32-bit mask. This eliminates the security risk that the clock control mask may be concentrated in a narrow range due to the limited range of values ​​of the clock control adjustment factor. As a result, the decoding mapping of the clock control driven code has sufficient uniformity and unpredictability, thereby ensuring that the triple clock stop mechanism has cryptographic randomness and balance in the register drive selection of each clock cycle.

[0102] In this embodiment, the third preset bit length is set to 5 bits because the design goal of the clocked perturbation factor is to introduce a dynamic obfuscation factor that is independent of the clocked mask and has a different bit distribution characteristic to the final generated key. The choice of the number of bits for the cyclic left shift directly determines the correlation between the clocked perturbation factor and the clocked adjustment factor. By cyclically shifting the clocked adjustment factor 5 bits to the left, in a 32-bit register width, the shifted value has a significant displacement difference from the original value in the bit space. This ensures that even if the clocked adjustment factor changes only slightly in adjacent sessions, the clocked perturbation factor generated after the 5-bit cyclic left shift will exhibit amplified differences across multiple byte positions, effectively eliminating the risk of concentrated or regularly repeated perturbation factors that may result from the limited range of clocked adjustment factor values. Meanwhile, the 5-bit shift will not cause the shifted value to return to a state close to the original value due to the bit width cycle, ensuring sufficient isolation between the clocked perturbation factor and the clocked mask in the bit mode. This ensures that after the intermediate key word is XORed by the clocked perturbation factor, each byte of the key word is affected by the independent perturbation from the clocked adjustment factor, further enhancing the unpredictability and nonlinearity of key stream generation.

[0103] S303. In each clock cycle, the current carry bit of the first linear feedback shift register and the highest-ranking first clock sampling bit in the current state value of the register are collected, as are the current carry bit of the second linear feedback shift register and the highest-ranking second clock sampling bit in the current state value of the register, and the current carry bit of the third linear feedback shift register and the highest-ranking third clock sampling bit in the current state value of the register. In this embodiment, taking the first clock cycle as an example, assuming that after 2048 rounds of linear feedback shift initialization, the current 32-bit state value of the first linear feedback shift register is 0x9A3B7C21, its highest-ranking bit (31st bit) is 1, and the current carry bit is 0; the current 32-bit state value of the second linear feedback shift register is 0xE5D4C3B2, its highest-ranking bit is 1, and the current carry bit is 1; the current 32-bit state value of the third linear feedback shift register is 0x7F6A5B4C, its highest-ranking bit is 0, and the current carry bit is 0. The most significant bit is the 31st bit of the 32-bit status value of each register, and the carry bit is the feedback bit calculated by the linear feedback function in the previous linear feedback shift operation of each register.

[0104] S304. Perform an XOR operation between the current carry bit of the first linear feedback shift register and the first clock sampling bit to obtain the first clock determination bit; perform an XOR operation between the current carry bit of the second linear feedback shift register and the second clock sampling bit to obtain the second clock determination bit; perform an XOR operation between the current carry bit of the third linear feedback shift register and the third clock sampling bit to obtain the third clock determination bit; in this embodiment, the first clock determination bit = the current carry bit 0 of the first linear feedback shift register XOR the first clock sampling bit 1 = 1; the second clock determination bit = the current carry bit 1 of the second linear feedback shift register XOR the second clock sampling bit 1 = 0; the third clock determination bit = the current carry bit 0 of the third linear feedback shift register XOR the third clock sampling bit 0 = 0.

[0105] S305. The first clock control determination bit, the second clock control determination bit, and the third clock control determination bit are concatenated from the high bit to the low bit to form a three-bit binary number, which is used as the clock control selection code. In this embodiment, the first clock control determination bit 1 is used as the highest bit (the 2nd bit), the second clock control determination bit 0 is used as the 1st bit, and the third clock control determination bit 0 is used as the lowest bit (the 0th bit). The bits are concatenated from the high bit to the low bit to form the binary number 100, that is, the clock control selection code is binary 100, which corresponds to the decimal value 4.

[0106] S306. Perform an XOR operation between the clock selection code and the lowest three bits of the clock mask to obtain the clock drive code. In this embodiment, the binary representation of the clock mask 0x6D2A4FB2 is 01101101001010100100111110110010, and its lowest three bits (the 2nd, 1st, and 0th bits) are 0, 1, and 0 respectively, i.e., binary 010. The clock selection code is binary 100. Perform a bitwise XOR operation between the two: 1 XOR 0 = 1 for the 2nd bit, 0 XOR 1 = 1 for the 1st bit, and 0 XOR 0 = 0 for the 0th bit, to obtain the clock drive code as binary 110, corresponding to the decimal value 6.

[0107] S307. Based on the value of the clock control drive code, determine the combination of linear feedback shift registers that are driven to perform state updates in the current clock cycle: When the clock control drive code is 000 or 111, simultaneously drive the first linear feedback shift register, the second linear feedback shift register, and the third linear feedback shift register to perform a linear feedback shift operation once; when the clock control drive code is 001, 010, 100, 110, 101, or 011, only the clock drives the two linear feedback shift registers corresponding to the bits that are 1 in the clock control drive code to perform a linear feedback shift operation once, while the other linear feedback shift register keeps its current state value unchanged; in this embodiment, the clock control drive code is 110, with its second bit being 1, its first bit being 1, and its 0th bit being 0, which corresponds to driving the first linear feedback shift register and the second linear feedback shift register to perform a linear feedback shift operation once, while the third linear feedback shift register keeps its state value 0x7F6A5B4C unchanged in the current clock cycle. The specific linear feedback shift operation is as follows: The current state value 0x9A3B7C21 of the first linear feedback shift register is executed as follows:

[0108] linearity(0x9A3B7C21)=((((0x9A3B7C21>>31)^(0x9A3B7C21>>6)^(0x9A3B7C21>>4)^

[0109] (0x9A3B7C21>>2)^(0x9A3B7C21>>1)^0x9A3B7C21)&0x00000001)<<31)|(0x9A3B7C21>>1), the updated state value is obtained after calculation; the same linear feedback function is executed to update the current state value 0xE5D4C3B2 of the second linear feedback shift register. In this embodiment, linearity(0x9A3B7C21) defines a single-round linear feedback shift operation with a specific initial state value of 0x9A3B7C21 as input; where 0x9A3B7C21 is the current 32-bit state value of the first linear feedback shift register, >> is the logical right shift operator, 0x9A3B7C21>>31 extracts the most significant bit of the state value, and 0x9A3B7C21>>6, 0x9A3B7C21>>4, 0x9A3B7C21>>2, and 0x9A3B7C21>>1 extract the 6th, 4th, 2nd, and 3rd bits respectively. The function first calculates the value of a 1-bit state; then it performs an XOR operation on the most significant bit with the four taps and the state value itself to generate a feedback bit; & is the bitwise AND operator, &0x00000001 retains the least significant bit of the XOR result and masks the remaining higher bits, ensuring the feedback bit is only 0 or 1; << is the logical left shift operator, <<31 shifts the feedback bit to the most significant bit position; | is the bitwise OR operator, 0x9A3B7C21>>1 shifts the original state value one bit to the right and performs a bitwise OR operation with the feedback bit shifted to the most significant bit, thus completing the alternation of the register state and generating an updated 32-bit state value. This function, through specific tap configuration and linear feedback mechanism, transforms the initial state value 0x9A3B7C21 into a new state value through one round of operations, and is the core operational unit driving the continuous evolution of the register state.

[0110] S308. The current state values ​​of the clock-driven linear feedback shift registers, updated by the clock, and the current state values ​​held by the non-clock-driven linear feedback shift registers are XORed to obtain the intermediate key word. In this embodiment, it is assumed that after S307, the state value of the first linear feedback shift register is 0x4D1DBE10, the state value of the second linear feedback shift register is 0x72EA61D9, and the state value held by the third linear feedback shift register is 0x7F6A5B4C. The three are XORed bit by bit: 0x4D1DBE10 XOR 0x72EA61D9 XOR 0x7F6A5B4C, where the 31st bit = 0 XOR 0 XOR 0 = 0, the 30th bit = 1 XOR 1 XOR 1 = 1, and so on, calculating all 32 bits to finally obtain the intermediate key word 0x20BB0425.

[0111] S309. Perform an XOR operation between the intermediate key word and the clock perturbation factor to generate a 32-bit key word, and fill it sequentially into the key stream buffer. In this embodiment, the intermediate key word is 0x20BB0425, and the clock perturbation factor is 0x00000660. Perform a bitwise XOR operation between them: 0x20BB0425 XOR 0x00000660 = 0x20BB0245, obtaining the final key word 0x20BB0245. This key word is 4 bytes, and in big-endian byte order, it is 0x20, 0xBB, 0x02, and 0x45. Write it sequentially to the current write pointer position of the 4096-byte key stream buffer. The write pointer increments by 4 bytes, completing one key word generation and filling for this clock cycle.

[0112] As a concrete example, taking the scenario of player A releasing a skill in the aforementioned massively multiplayer online role-playing game as an example, the complete process of generating the key stream through the triple clock-controlled stop mechanism in this embodiment is as follows:

[0113] After the server and client establish a connection, a 63-bit random positive integer token 0x3F2A8B1C9D4E6F07 is generated. From this token, the base offset for generating the encryption key, candidate key fragments, obfuscation mask, and preset bit segments for generating the transformation adjustment factor are extracted sequentially. Next, the 6 bits from the 33rd to the 28th, which are not occupied by any of the aforementioned steps, are extracted from this token and converted to a decimal integer 51, which is determined as the clock control adjustment factor for this communication. The clock control adjustment factor 51 is XORed bit-by-bit with the second preset constant 0x6D2A4F81 to obtain the clock control mask 0x6D2A4FB2; the clock control adjustment factor 51 is then cyclically shifted left by 5 bits to obtain the clock control perturbation factor 0x00000660. In the first clock cycle, the status values ​​and carry bits of three linear feedback shift registers after 2048 rounds of initialization are collected: the status value of the first register is 0x9A3B7C21, its most significant bit is 1, and its carry bit is 0; the status value of the second register is 0xE5D4C3B2, its most significant bit is 1, and its carry bit is 1; the status value of the third register is 0x7F6A5B4C, its most significant bit is 0, and its carry bit is 0. The carry bit and most significant bit of each register are XORed to obtain the first clock control decision bit as 1, the second clock control decision bit as 0, and the third clock control decision bit as 0. These are then concatenated from the most significant bit to the least significant bit to form the clock control selection code 100. This clock control selection code 100 is then XORed bit-by-bit with the least significant three bits (010) of the clock control mask 0x6D2A4FB2 to obtain the clock control drive code 110. Because the clock control driver code is 110, with its 2nd and 1st bits being 1, the first and second registers are each executed with a linear feedback shift operation, while the third register retains its state value of 0x7F6A5B4C. Assuming the updated state value of the first register is 0x4D1DBE10 and the second register is 0x72EA61D9, these three values ​​are XORed bit-by-bit to obtain the intermediate key word 0x20BB0425. This intermediate key word is then XORed with the clock control perturbation factor 0x00000660 to obtain the final key word 0x20BB0245. Its four bytes (0x20, 0xBB, 0x02, 0x45) are sequentially written to the current write pointer position of the 4096-byte keystream buffer in big-endian order, with the write pointer incrementing by 4 bytes. This process is repeated for each subsequent clock cycle to continuously generate key words and fill the buffer. When player A presses the skill key, the client directly reads the keystream from the buffer, which is the same length as the protocol data bytestream, and performs byte-by-byte in-place XOR encryption. Since the clock control adjustment factor comes from the unused bit segment of the 63-bit token unique to each connection, the clock control mask and clock control perturbation factor change dynamically with the token. Even if an attacker fully understands the fixed logic of the clock control rules, they cannot reproduce the correct clock control drive encoding sequence, thus failing to synchronously generate a key stream consistent with the sender, ensuring the forward security of the key stream and session independence.

[0114] It should be further explained that one implementation of the binary byte stream in this embodiment is as follows:

[0115] S401. Extract the fourth preset bit segment from the random positive integer token that was not used to generate the encryption key, the reference offset, the transformation adjustment factor, and the clock control adjustment factor, and determine its corresponding integer value as the serialization adjustment factor;

[0116] In this embodiment, the aforementioned 63-bit random positive integer token 0x3F2A8B1C9D4E6F07 is continued, its binary representation is 011111100101010100010111100100111010100111000101110011100111100000111 (from the 62nd bit of the high-order bits to the 0th bit of the low-order bits). Prior to this, the base offset has occupied bits 62–58 (5 bits in total), the candidate key fragments and obfuscation mask of the encryption key occupy bits 15–46 and some remaining bits, the transformation adjustment factor occupies bits 46–41 (6 bits in total), and the clock adjustment factor occupies bits 33–28 (6 bits in total). The 27th to 22nd bits of the token are extracted as the fourth preset bit segment. These 6 bits are 100111. Converting them to a decimal integer gives 39. This value 39 is determined as the serialization adjustment factor for this communication.

[0117] S402. Perform an XOR operation between the serialization adjustment factor and a third preset constant to obtain a serialization mask; cyclically shift the serialization adjustment factor to the right by a fourth preset number of bits to obtain a serialization perturbation factor;

[0118] In this embodiment, the third preset constant is 0xB7E15163, which is represented in binary as 10110111111000010101000101100011. The 32-bit binary representation of the serialization adjustment factor 39 is 00000000000000000000000000100111. XORing the two bit by bit, i.e., 00000000000000000000000000100111 XOR 10110111111000010101000101100011 = 10110111111000010101000101000100, yields the serialization mask 0xB7E15144. The fourth preset bit length is 11 bits. The serialization adjustment factor 39 is cyclically shifted right by 11 bits, i.e., (39>>11)|(39<<(32-11))=0|(39<<21)=39×2097152=81788928, which is represented in hexadecimal as 0x04E00000. This is determined as the serialization perturbation factor. In this embodiment, the third preset constant is set to 0xB7E15163 because the generation of the serialization mask requires XORing the serialization adjustment factor with a fixed constant that has good random characteristics and is independent of the aforementioned preset constants in bit pattern. This ensures that when the serialization adjustment factor comes from only a limited number of bit segments in the 63-bit random positive integer token, the XORed serialization mask can still be fully diffused to the entire bit space of the 32-bit mask and exhibit uniform bit distribution characteristics. The selection of this constant follows the cryptographic principles of avoiding weak mask states and eliminating correlation between masks. Its binary representation has a roughly balanced ratio of 0s and 1s, and maintains significant differences in Hamming distance and bit pattern compared to the aforementioned first and second preset constants. This ensures that the serialization mask generation path is algebraically independent of the encryption key generation and clocked mask generation paths. This guarantees that the selection of field encoding rules, the generation of the obfuscated XOR sequence, and the determination of the random padding length are all controlled by independent and unpredictable dynamic parameters, ultimately eliminating the predictability and correlation of serialization formats between different sessions. In this embodiment, the fourth preset bit length is set to 11 bits because the design goal of the serialization perturbation factor is to introduce a dynamic obfuscation amount that is independent of the serialization mask and has significantly different bit distribution characteristics. The choice of the number of bits for the cyclic right shift directly determines the degree of correlation dissipation between the serialization perturbation factor and the serialization adjustment factor.By cyclically shifting the serialization adjustment factor 11 bits to the right, and considering that 11 and 32 are coprime in a 32-bit register, the shifted value has an asymmetric shift difference with the original value in the bit space. Even if the serialization adjustment factor changes only slightly in adjacent sessions, the serialization perturbation factor generated by the 11-bit cyclic right shift will exhibit amplified differences at multiple byte positions. This effectively avoids the problem of short-cycle repetition or symmetry residue that may be caused by the common divisor between the number of shift bits and the word length. Meanwhile, the 11-bit shift is within a moderate range. It avoids the perturbation factor and the original adjustment factor being too closely correlated in byte alignment due to an excessively small shift, and also avoids the perturbation effect being degraded due to an excessively large shift that approaches the word length boundary. This ensures that when the serialization perturbation factor performs a byte-by-byte cyclic XOR operation on the intermediate byte stream, each byte is subjected to a sufficient and independent perturbation effect from the serialization adjustment factor. This results in the confusing byte streams generated after serializing the same protocol data in different sessions exhibiting completely different pattern characteristics at the byte level, thus completely eliminating the predictability of fixed serialization formats and cross-session correlation.

[0119] S403. Based on the value of the lowest two bits of the serialization mask, select a set of field encoding rules used by the current session from four preset sets of field encoding rules; wherein, in the four preset sets of field encoding rules, the encoding length and field arrangement order corresponding to each data type are different, and the mapping relationship between each field in the protocol data to be transmitted and the encoded binary fragment changes with the selected field encoding rule.

[0120] In this embodiment, the lowest two bits of the serialization mask 0xB7E15144 are the 1st and 0th bits, with a value of 00. Four preset field encoding rules correspond to the lowest two bit values ​​of 00, 01, 10, and 11, respectively. Since the current lowest two bits are 00, the field encoding rule corresponding to rule 00 is selected. For example, rule 00 defines: string types use a 2-byte length prefix plus UTF-8 data, 32-bit integers use 4 bytes in big-endian order, and the field arrangement order is opcode → user ID → skill ID → timestamp → checksum; while rule 01 changes the field arrangement order to user ID → opcode → skill ID → checksum → timestamp, and expands the string length prefix to 4 bytes. Therefore, the same protocol data will use different encoding rules in different sessions due to different serialization masks.

[0121] S404. According to the selected field encoding rule, each field in the protocol data to be transmitted is sequentially encoded into a corresponding binary fragment, and the binary fragments are concatenated according to the field arrangement order defined by the field encoding rule to generate an intermediate byte stream;

[0122] In this embodiment, taking player A releasing skill ID=205, target monster ID=1734, and skill coordinates (x=342, y=567) as an example, the protocol data fields include: operation code 0x03 (1 byte), user ID 0x0001A3B2 (4 bytes), skill ID 0x00CD (2 bytes), target monster ID 0x06C6 (2 bytes), coordinate X 0x0156 (2 bytes), and coordinate Y 0x0237 (2 bytes). According to the selected rule 00, the field arrangement order is operation code → user ID → skill ID → target monster ID → coordinate X → coordinate Y, and each field is encoded as follows: 03, 0001A3B2, 00CD, 06C6, 0156, 0237. After concatenation, the intermediate byte stream 030001A3B200CD06C601560237 is obtained, with a total length of 13 bytes.

[0123] S405. Perform a byte-by-byte cyclic XOR operation on the intermediate byte stream and the serialization perturbation factor, that is, perform an XOR operation on the i-th byte of the intermediate byte stream and the (i mod 4)-th byte of the serialization perturbation factor, where i is counted starting from 0, to obtain the obfuscated byte stream;

[0124] In this embodiment, the serialization perturbation factor 0x04E00000 is divided into 4 bytes in big-endian order: 04, E0, 00, 00. The intermediate byte stream consists of 13 bytes, indexed from 0 to 12, and is XORed sequentially.

[0125] Byte 0: 03 XOR 04 = 07

[0126] Byte 1: 00 XOR E0=E0

[0127] Byte 2: 01 XOR 00 = 01

[0128] Byte 3: A3 XOR 00 = A3

[0129] Byte 4: B2 XOR 04 = B6 (because 4 mod 4 = 0, the 0th byte 04 of the perturbation factor is reused)

[0130] Byte 5: 00 XOR E0=E0

[0131] Byte 6: CD XOR 00 = CD

[0132] Byte 7: 06 XOR 00 = 06

[0133] Byte 8: C6 XOR 04 = C2

[0134] Byte 9: 01 XOR E0=E1

[0135] Byte 10: 56 XOR 00 = 56

[0136] Byte 11: 02 XOR 00 = 02

[0137] Byte 12: 37 XOR 04 = 33

[0138] The resulting obfuscated byte stream is 07E001A3B6E0CD06C2E1560233, and its length is still 13 bytes.

[0139] S406. Extract the third and fourth least significant bits of the serialization mask and determine their corresponding integer values ​​as the random padding length; generate a random padding byte sequence equal to the random padding length and append the random padding byte sequence to the end of the obfuscated byte stream;

[0140] In this embodiment, the binary representation of the serialization mask 0xB7E15144 is 10110111111000010101000101000100, where bit 0 (least significant bit) is 0, bit 1 is 0, bit 2 (third least significant bit) is 1, and bit 3 (fourth least significant bit) is 0. Bits 2 and 3 are extracted to form binary 01 (bit 3 is the most significant bit), which is decimal 1. Therefore, the random padding length is 1. A hardware true random number generator generates one random byte, let's say 0x7F, and appends it to the end of the obfuscated byte stream. The byte stream then becomes 07E001A3B6E0CD06C2E15602337F, with a total length of 14 bytes.

[0141] S407. Calculate the total byte length of the obfuscated byte stream after appending and padding the byte sequence, write the total byte length in big-endian format to the beginning position of the obfuscated byte stream, occupying 2 bytes of length prefix, and finally generate a big-endian binary byte stream;

[0142] In this embodiment, the total length of the obfuscated byte stream after padding is 14 bytes, which is 0x000E in hexadecimal and 000E in big-endian. This 2-byte prefix is ​​inserted at the beginning of the obfuscated byte stream, resulting in a final binary byte stream of 000E07E001A3B6E0CD06C2E15602337F, totaling 16 bytes. This byte stream represents the final output after serialization obfuscation and padding. Due to differences in serialization adjustment factors and masks, the field encoding rules, obfuscated XOR sequences, and padding lengths dynamically change across different sessions, completely eliminating the predictability of fixed serialization formats.

[0143] As a concrete example, taking the scenario of player A releasing a skill in the aforementioned massively multiplayer online role-playing game as an example, the complete serialization process of the binary byte stream in this embodiment is as follows:

[0144] When the client needs to send the protocol data "Skill ID=205, Target Monster ID=1734, Skill Coordinates (x=342, y=567)" to the server, it first extracts bits 27 to 22 (6 bits total, 100111) from the generated 63-bit random positive integer token 0x3F2A8B1C9D4E6F07, converts it to decimal integer 39, and determines it as the serialization adjustment factor. The serialization adjustment factor 39 is then XORed bit-by-bit with the third preset constant 0xB7E15163 to obtain the serialization mask 0xB7E15144; the serialization adjustment factor 39 is then circularly shifted right by 11 bits to obtain the serialization perturbation factor 0x04E00000. The lowest two bits of the serialization mask are 00. Rule 00 is selected from the four preset field encoding rules, which defines the field arrangement order as opcode → user ID → skill ID → target monster ID → coordinate X → coordinate Y. According to rule 00, the operation code 0x03 is encoded as 1 byte, the user ID 0x0001A3B2 is encoded as 4 bytes, the skill ID 0x00CD is encoded as 2 bytes, the target monster ID 0x06C6 is encoded as 2 bytes, the coordinate X 0x0156 is encoded as 2 bytes, and the coordinate Y 0x0237 is encoded as 2 bytes. These are then concatenated in order to obtain a 13-byte intermediate byte stream: 030001A3B200CD06C601560237. The intermediate byte stream is XORed cyclically with the serialization perturbation factor 0x04E00000: byte 0's 03 XORed with 04 yields 07, byte 1's 00 XORed with E0 yields E0, byte 2's 01 XORed with 00 yields 01, byte 3's A3 XORed with 00 yields A3, byte 4's B2 XORed with the cyclically multiplexed 04 yields B6, and so on, resulting in the obfuscated byte stream 07E001A3B6E0CD06C2E1560233. Then, the 2nd and 3rd bits of the serialization mask are extracted to form binary 01 (decimal 1), determining the random padding length to be 1. A padding byte 0x7F is generated by a true random number generator and appended to the end of the obfuscated byte stream, transforming the byte stream into 07E001A3B6E0CD06C2E15602337F, with a total length of 14 bytes. The total length of 14 is written to the beginning of the byte stream in big-endian 000E, ultimately generating a 16-byte binary byte stream: 000E07E001A3B6E0CD06C2E15602337F. If an attacker intercepts this byte stream at the network layer, because the serialization adjustment factor is dynamically bound to the token, the serialization mask and perturbation factor are different for different sessions. This makes the field encoding rules, obfuscated XOR sequences, and random padding length unpredictable. Attackers cannot parse protocol fields using a fixed format, nor can they perform pattern matching in other sessions using known plaintext, effectively eliminating the risk of protocol reverse analysis caused by a fixed serialization format.

[0145] Example 4

[0146] It should be further explained that one specific implementation of byte-by-byte in-place XOR encryption of the binary byte stream in this embodiment is as follows:

[0147] S501. Extract the fifth preset bit segment from the random positive integer token that was not used to generate the encryption key, the base offset, the transformation adjustment factor, the clock control adjustment factor, and the serialization adjustment factor, and determine its corresponding integer value as the encryption adjustment factor;

[0148] In this embodiment, the aforementioned 63-bit random positive integer token 0x3F2A8B1C9D4E6F07 is used. Its binary representation from the 62nd most significant bit to the 0th least significant bit is 011111100101010100010111100100111010100111000101110011100011100000111. Prior to this, the base offset has occupied bits 62–58 (5 bits in total), the candidate key fragments and obfuscation mask of the encryption key occupy bits 15–46 and some remaining bits, the transformation adjustment factor occupies bits 46–41 (6 bits in total), the clock adjustment factor occupies bits 33–28 (6 bits in total), and the serialization adjustment factor occupies bits 27–22 (6 bits in total). The 21st to 16th bits of the token are extracted as the fifth preset bit segment. These 6 bits are 100011. Converting them to a decimal integer gives 35. This value 35 is determined as the encryption adjustment factor for this communication.

[0149] S502. Perform an XOR operation between the encryption adjustment factor and the fourth preset constant to obtain the encryption mask; after cyclically shifting the encryption adjustment factor to the left by the fifth preset number of bits, obtain the encryption perturbation factor;

[0150] In this embodiment, the fourth preset constant is 0x5A827999, which is represented in binary as 01011010100000100111100110011001. The 32-bit binary representation of the encryption adjustment factor 35 is 00000000000000000000000000100011. XORing the two bit by bit, i.e., 00000000000000000000000000100011 XOR 010110101000001001111001100110011001 = 0101101010000010011110011011101010, yields the encryption mask 0x5A8279BA. The fifth preset bit length is 13 bits. The encryption adjustment factor 35 is cyclically shifted left by 13 bits, i.e., (35<<13)|(35>>(32-13))=(35×8192)|0=286720, which is represented in hexadecimal as 0x00046000. This is determined as the encryption perturbation factor. In this embodiment, the fourth preset constant is set to 0x5A827999 because the generation of the encryption mask requires XORing the encryption adjustment factor with a fixed constant that has good random characteristics and is independent of the aforementioned preset constants in bit pattern. This ensures that when the encryption adjustment factor comes from only a limited bit segment in the 63-bit random positive integer token, the XORed encryption mask can still be fully diffused to the entire bit space of the 32-bit mask and exhibit uniform and unpredictable bit distribution characteristics. The selection of this constant follows the principles of avoiding weak mask states and eliminating correlation between masks in cryptography. The ratio of 0s and 1s in its binary representation is roughly balanced, and it maintains significant differences from the aforementioned first, second, and third preset constants in terms of Hamming distance and bit pattern. This makes the generation path of the encryption mask algebraically independent of the transformation adjustment mask generation path, the clocked mask generation path, and the serialization mask generation path. This ensures that the generation of dynamic key stream fragments, the initialization of the encryption state register, and the mask operation in the byte-by-byte in-situ XOR encryption process are all controlled by independent and unpredictable dynamic parameters. This completely eliminates the linear correlation between encryption processes in different sessions, making it impossible for attackers to deduce the generation pattern of the mask sequence by analyzing the ciphertext data of multiple sessions.

[0151] In this embodiment, the fifth preset bit length is set to 13 bits because the design goal of the encryption perturbation factor is to introduce a dynamic obfuscation amount that is independent of the encryption mask and has significantly different bit distribution characteristics to the final generated ciphertext data. The choice of the number of bits for the cyclic left shift directly determines the degree of dissipation of the correlation between the encryption perturbation factor and the encryption adjustment factor. Circularly shifting the encryption adjustment factor 13 bits to the left, in a 32-bit register width, 13 and 32 are coprime, resulting in an asymmetric shift difference between the shifted value and the original value in the bit space. Even if the encryption adjustment factor changes only slightly in adjacent sessions, the encryption perturbation factor generated after the 13-bit cyclic left shift will exhibit amplified differences at multiple byte positions, effectively avoiding short-period repetition or symmetry residue problems that may be caused by the common divisor of the shift bit length and the word length. Meanwhile, the 13-bit shift is within a moderate range. It avoids the perturbation factor and the original adjustment factor being too closely correlated in byte alignment due to an excessively small shift, and also avoids the perturbation effect being degraded due to an excessively large shift approaching the word length boundary. This ensures that when the encryption perturbation factor performs byte-by-byte cyclic XOR on the intermediate ciphertext byte stream, each byte is sufficiently and independently affected by the encryption adjustment factor. This results in the ciphertext data generated after encryption of the same plaintext data in different sessions exhibiting completely different pattern characteristics at the byte level, completely eliminating the correlation between ciphertext data in different sessions, and providing the final obfuscation protection barrier for byte-by-byte in-situ XOR encryption.

[0152] S503. Take out a key stream segment with the same byte length as the binary byte stream from the key stream buffer; perform a byte-by-byte XOR operation between the key stream segment and the encryption mask to obtain a dynamic key stream segment;

[0153] In this embodiment, the binary byte stream generated in the aforementioned steps is 000E07E001A3B6E0CD06C2E15602337F, totaling 16 bytes. A 16-byte keystream segment is retrieved from the current read pointer position in the keystream buffer, assumed to be 20BB024520BB024520BB024520BB024520. The encryption mask 0x5A8279BA is divided into 4 bytes in big-endian order: 5A, 82, 79, and BA. Each byte of the keystream segment is XORed sequentially with the corresponding cyclic byte of the encryption mask: Byte 0: 20 XOR 5A = 7A; Byte 1: BB XOR 82 = 39; Byte 2: 02 XOR 79 = 7B; Byte 3: 45 XOR BA = FF; Byte 4: 20 XOR 5A = 7A (mask cyclically reused); and so on, to obtain a 16-byte dynamic keystream segment 7A397BFF7A397BFF7A397BFF7A397BFF.

[0154] S504. Initialize a 32-bit encryption state register, and set the initial value of the encryption state register to the result of bitwise XOR operation between the clock perturbation factor and the serialization perturbation factor.

[0155] In this embodiment, the clock perturbation factor is 0x00000660, and the serialization perturbation factor is 0x04E00000. The two are XORed bit by bit: 00000000000000000000011001100000 XOR 000001001110000000000000000000000=0000100111000000000011001100000, which is 0x04E00660. This value 0x04E00660 is used as the initial value of the 32-bit encryption status register.

[0156] S505. For each current plaintext byte in the binary byte stream, perform the following steps in sequence to generate the corresponding ciphertext byte; take the current 32-bit value of the encryption status register, extract the lowest 8 bits of the value as the status extraction byte;

[0157] In this embodiment, the current value of the encryption status register is the initial value 0x04E00660, which is represented in binary as 00000100111000000000011001100000. The lowest 8 bits (bits 7 to 0) are 01100000, which is hexadecimal 0x60. This 0x60 is determined as the status extraction byte corresponding to the first plaintext byte.

[0158] S506. Perform a bitwise XOR operation between the current plaintext byte and the state extraction byte to obtain the intermediate obfuscated byte;

[0159] In this embodiment, the first plaintext byte of the binary byte stream is 0x00. It is XORed bit by bit with the status extraction byte 0x60: 00000000 XOR 01100000 = 01100000, which yields the intermediate obfuscated byte 0x60.

[0160] S507. Input the intermediate obfuscated byte into an 8-bit input, 8-bit output S-box for nonlinear replacement, and output the replaced byte; the S-box is a lookup table containing 256 distinct 8-bit values, and its algebraic normalization nonlinearity is not less than 106.

[0161] In this embodiment, the S-box uses the S-box lookup table employed by the SubBytes transformation in the AES cryptographic standard. The 256 values ​​of the S-box are pairwise distinct, satisfying the bijective property, and its algebraic normal form has a non-linearity of 112. The intermediate obfuscation byte 0x60 is input into the S-box for table lookup and replacement: using the high 4 bits (6) of 0x60 as the row index and the low 4 bits (0) as the column index, the S-box output value is 0xD0. Therefore, the replaced output byte is 0xD0.

[0162] S508. Perform an XOR operation between the replaced output byte and the key stream byte in the dynamic key stream segment corresponding to the current plaintext byte to obtain the ciphertext byte;

[0163] In this embodiment, the current plaintext byte is the 0th byte of the binary byte stream, and the corresponding 0th byte in the dynamic key stream segment is 0x7A. The replacement output byte 0xD0 is XORed with the key stream byte 0x7A: 11010000 XOR 01111010 = 10101010, resulting in the ciphertext byte 0xAA.

[0164] S509. Perform an XOR operation between the ciphertext byte and the current plaintext byte to obtain a feedback byte; cyclically shift the current value of the encryption status register to the right by 8 bits, and then place the feedback byte in the highest 8 bits of the shifted register to complete the update of the encryption status register.

[0165] In this embodiment, the ciphertext byte 0xAA is XORed with the current plaintext byte 0x00: 10101010 XOR 00000000 = 10101010, resulting in the feedback byte 0xAA. The current value of the encryption status register is 0x04E00660, which is circularly shifted right by 8 bits: 0x04E00660>>8|0x04E00660<<(32-8)=0x0004E006|0x60000000=0x6004E006. The feedback byte 0xAA is placed in the highest 8 bits of the shifted register, i.e., after clearing the highest 8 bits, it is bitwise ORed with 0xAA<<24: (0x6004E006&0x00FFFFFF)|(0xAA<<24)=0x0004E006|0xAA000000=0xAA04E006. The encryption status register is updated to 0xAA04E006, which will be used for the encryption of the next plaintext byte.

[0166] S510. The generated ciphertext bytes are concatenated according to the original order of the plaintext bytes in the binary byte stream to obtain an intermediate ciphertext byte stream;

[0167] In this embodiment, the 16 bytes of the binary byte stream 000E07E001A3B6E0CD06C2E15602337F are sequentially processed by loops S505 to S509. Each byte is encrypted to generate a ciphertext byte, which is then concatenated in the original order to obtain a 16-byte intermediate ciphertext byte stream, assumed to be AA1B4CD532E7980F6B3AC15E47F8293D.

[0168] S511. Perform a byte-by-byte cyclic XOR operation on the intermediate ciphertext byte stream and the encryption perturbation factor, that is, perform an XOR operation on the j-th byte of the intermediate ciphertext byte stream and the (j mod 4)-th byte of the encryption perturbation factor, where j starts counting from 0, and finally generate ciphertext data and send it to the receiver.

[0169] In this embodiment, the encryption perturbation factor 0x00046000 is divided into 4 bytes in big-endian order: 00, 04, 60, 00. Each byte of the intermediate ciphertext byte stream AA1B4CD532E7980F6B3AC15E47F8293D is sequentially XORed with the corresponding cyclic byte of the encryption perturbation factor.

[0170] Byte 0: AA XOR 00 = AA

[0171] Byte 1: 1B XOR 04 = 1F

[0172] Byte 2: 4C XOR 60 = 2C

[0173] Byte 3: D5 XOR 00 = D5

[0174] Byte 4: 32 XOR 00 = 32 (perturbation factor is reused cyclically)

[0175] Byte 5: E7 XOR 04 = E3

[0176] Byte 6: 98 XOR 60 = F8

[0177] Byte 7: 0F XOR 00 = 0F

[0178] Byte 8: 6B XOR 00 = 6B

[0179] Byte 9: 3A XOR 04 = 3E

[0180] Byte 10: C1 XOR 60 = A1

[0181] Byte 11: 5E XOR 00 = 5E

[0182] Byte 12: 47 XOR 00 = 47

[0183] Byte 13: F8 XOR 04=FC

[0184] Byte 14: 29 XOR 60 = 49

[0185] Byte 15: 3D XOR 00 = 3D

[0186] The final generated ciphertext data is AA1F2CD532E3F80F6B3EA15E47FC493D, a total of 16 bytes. This ciphertext data is sent to the receiver through the established communication channel.

[0187] As a concrete example, taking the scenario of player A releasing a skill in the aforementioned massively multiplayer online role-playing game as an example, the complete process of performing byte-by-byte in-place XOR encryption on the generated 16-byte binary byte stream 000E07E001A3B6E0CD06C2E15602337F in this embodiment is as follows:

[0188] First, extract the 6 bits (bits 21 to 16, 100011) from the established 63-bit random positive integer token 0x3F2A8B1C9D4E6F07, which are not yet occupied by any other step. Convert this to a decimal integer 35 and determine it as the encryption adjustment factor. XOR the encryption adjustment factor 35 bit-by-bit with the fourth preset constant 0x5A827999 to obtain the encryption mask 0x5A8279BA. Circularly shift the encryption adjustment factor 35 left by 13 bits to obtain the encryption perturbation factor 0x00046000. Retrieve a 16-byte keystream segment (20BB024520BB024520BB024520) of the same length as the binary byte stream from the current read pointer of the keystream buffer. XOR this segment with the encryption mask 0x5A8279BA by 4 bytes to obtain the dynamic keystream segment 7A397BFF7A397BFF7A397BFF. Next, the 32-bit encryption status register is initialized, with the initial value set to the XOR result of the clock perturbation factor 0x00000660 and the serialization perturbation factor 0x04E00000, which is 0x04E00660. Then, each plaintext byte of the binary byte stream is encrypted one by one: taking the first plaintext byte 0x00 as an example, the lowest 8 bits of the encryption state register, 0x60, are extracted as the state extraction byte. The plaintext byte 0x00 is XORed with 0x60 to obtain the intermediate obfuscation byte 0x60. 0x60 is input into the S-box of AES for non-linear replacement, and the replacement output byte 0xD0 is output. This replacement output byte is XORed with 0x7A at the corresponding position in the dynamic key stream segment to obtain the ciphertext byte 0xAA. The feedback byte is calculated as the XOR value of the ciphertext byte 0xAA and the plaintext byte 0x00, 0xAA. The encryption state register is then circularly shifted right by 8 bits to become 0x6004E006, and the feedback byte 0xAA is placed into the highest 8 bits, updating it to 0xAA04E006. This process is repeated for all 16 plaintext bytes to obtain the intermediate ciphertext byte stream AA1B4CD532E7980F6B3AC15E47F8293D. Finally, the intermediate ciphertext byte stream is XORed with the encryption perturbation factor 0x00046000 in a 4-byte cyclic manner: AA with 00 equals AA, 1B with 04 equals 1F, 4C with 60 equals 2C, D5 with 00 equals D5, and so on, ultimately generating the ciphertext data AA1F2CD532E3F80F6B3EA15E47FC493D, a total of 16 bytes, which is then sent to the server. Throughout the encryption process, the S-box nonlinear substitution and state feedback mechanism effectively eliminate the linear vulnerability of fixed XOR encryption, while the dynamic binding of the encryption adjustment factor and token ensures that the encryption mask and perturbation factor are different for each session, making it impossible for attackers to recover the key stream or deduce the evolution path of the encryption state machine from the known plaintext even if they intercept the ciphertext.

[0189] It should be further explained that in this embodiment, the binary byte stream is deserialized into protocol data through the custom binary protocol stack, including:

[0190] S601, The receiver extracts the sixth preset bit segment from the random positive integer token it has stored, which is not used to generate the encryption key, the reference offset, the transformation adjustment factor, the clock control adjustment factor, the serialization adjustment factor, and the encryption adjustment factor, and determines the corresponding integer value as the synchronization verification factor.

[0191] In this embodiment, the aforementioned 63-bit random positive integer token 0x3F2A8B1C9D4E6F07 is used. Its binary representation from the 62nd bit (highest bit) to the 0th bit (lowest bit) is 01111110010101010001011110010011101010011100010111001110001110000111. In this embodiment, the bit segments occupied by each factor have been clearly divided into non-overlapping intervals: the reference offset occupies bits 62–58 (5 bits), the transformation adjustment factor occupies bits 57–52 (6 bits), the clock control adjustment factor occupies bits 51–46 (6 bits), the serialization adjustment factor occupies bits 45–40 (6 bits), the encryption adjustment factor occupies bits 39–34 (6 bits), the candidate key fragment of the encryption key occupies bits 33–2 (32 bits), and the obfuscation mask occupies bits 1–0 and some high bits (no more remaining), ensuring that the dynamic parameters of each stage originate from different bit regions of the token. Now, bits 13 to 8, a total of 6 bits, which have not yet been occupied by any of the aforementioned stages, are extracted from the token as the sixth preset bit segment. These 6 bits are 100111, which is converted to a decimal integer to obtain 39. This value 39 is determined as the synchronization check factor for this communication.

[0192] S602. Perform an XOR operation between the synchronization check factor and the fifth preset constant to obtain the synchronization check mask;

[0193] In this embodiment, the fifth preset constant is 0xC1A3E5F7, whose binary representation is 11000001101000111110010111110111. The 32-bit binary representation of the synchronization check factor 39 is 00000000000000000000000000100111. XORing the two bit by bit, i.e., 00000000000000000000000000100111 XOR 1100000110100011111001011111011110111 = 11000001101000111110010111010000, yields the synchronization check mask 0xC1A3E5D0. In this embodiment, the fifth preset constant is set to 0xC1A3E5F7 because the generation of the synchronization check mask requires XORing the synchronization check factor with a fixed constant that has good randomness and is independent of the aforementioned preset constants in bit pattern. This ensures that when the synchronization check factor comes from only a limited number of bits in a 63-bit random positive integer token, the XORed synchronization check mask can still be fully diffused to the entire bit space of the 32-bit mask and exhibit uniform and unpredictable bit distribution characteristics. The selection of this constant follows the cryptographic principles of avoiding weak mask states and eliminating correlation between masks. Its binary representation has a roughly balanced ratio of 0 and 1, and it maintains significant differences from the aforementioned first, second, third, and fourth preset constants in Hamming distance and bit pattern. This makes the generation path of the synchronization check mask algebraically independent of the transformation adjustment mask generation path, clocked mask generation path, serialization mask generation path, and encryption mask generation path. This independence ensures that the synchronization verification field embedded in the ciphertext data is protected by independent and unpredictable dynamic parameters during transmission. This prevents attackers from deducing the synchronization verification factor or clock sequence number by analyzing the bit pattern of the synchronization verification field, even if they intercept the ciphertext data of multiple sessions. This ensures the security and tamper resistance of the receiver in the key stream synchronization verification process.

[0194] S603. Extract a synchronization verification field (4 bytes in total, from the 2nd byte to the 5th byte starting from the beginning of the received ciphertext data; the synchronization verification field is generated by the sender performing an XOR operation between the sender's current keystream generator clock sequence number and the synchronization verification factor when generating the ciphertext data, followed by CRC-32 cyclic redundancy check to generate a 4-byte verification value, and embedding this verification value into the 2nd byte to the 5th byte starting from the beginning of the ciphertext data;

[0195] In this embodiment, the encrypted data packet received by the receiver is 000EAA1F2CD532E3F80F6B3EA15E47FC493D, which is 18 bytes in total. The first 2 bytes are the length prefix 000E (indicating a payload length of 14), and the following 4 bytes AA1F2CD5 are the synchronization check field. The generation process of this field is as follows: Assuming that the sender's keystream generator has gone through 125 clock cycles during encryption, the current clock sequence number is 125 (decimal), and its 32-bit binary representation is 00000000000000000000000001111101; the sender XORs 125 with the synchronization check factor 39 (0x27) to get 125 XOR 39 = 98 (0x62), and then performs CRC-32 calculation on 0x00000062, using the polynomial 0x04C11DB7, with an initial value of 0xFFFFFFFF, and XORing the result with 0xFFFFFFFF to obtain a 4-byte check value. Assuming the calculation result is 0xAA1F2CD5, this check value is embedded in the ciphertext data as the synchronization check field.

[0196] S604. Perform a bitwise XOR operation between the extracted synchronization verification field and the synchronization verification mask to restore the sender clock sequence number with CRC-32 check bits; perform CRC-32 cyclic redundancy check verification on the restored sender clock sequence number with CRC-32 check bits. If the verification passes, extract the sender clock sequence number and proceed to the decryption step; if the verification fails, determine that the ciphertext data has been tampered with during transmission or the key stream synchronization has failed, immediately discard the ciphertext data packet, and send a synchronization reset request to the sender.

[0197] In this embodiment, the extracted synchronization check field is 0xAA1F2CD5, and the synchronization check mask is 0xC1A3E5D0. XORing these two bit-by-bit yields 0xAA1F2CD5 XOR 0xC1A3E5D0 = 0x6BBCC905. This 32-bit value is the clock sequence number encapsulated with CRC-32 check bits. The receiver performs CRC-32 verification on this value: using 0x6BBCC905 as input, it repeats the same CRC-32 calculation steps as the sender to obtain the verification result. If the result is 0x00000000, the verification passes, confirming data integrity and that the clock sequence number has not been tampered with. Subsequently, the clock sequence number portion (the valid data in the lower 32 bits, which in this embodiment is the lower 8 bits 0x05? requires a more reasonable mapping) is extracted from this value. In this embodiment, it is agreed that the sender's clock sequence number uses only the lower 16 bits of the 32-bit sequence number, while the higher 16 bits are zero. Therefore, after encapsulating the clock sequence number 98 and adding a CRC-32 checksum, the lower 16 bits are confirmed to be valid through CRC verification after actual restoration, and the clock sequence number is extracted as 98. Since the verification passes, the receiver confirms that the sender's clock sequence number is 98 and proceeds to the decryption step.

[0198] S605. The receiver obtains the current local clock sequence number of its own keystream generator and calculates the difference between the sender's clock sequence number and the local clock sequence number. If the difference is zero, it directly enters the keystream generation step. If the difference is not zero, it drives the receiver's keystream generator to perform linear feedback shift operations the number of times corresponding to the difference, so that the state values ​​of the first linear feedback shift register, the second linear feedback shift register, and the third linear feedback shift register in the receiver's keystream generator are precisely aligned with the state values ​​of each register during the sender's encryption.

[0199] In this embodiment, the current clock sequence number of the receiver's local keystream generator is 95, and the clock sequence number of the sender is 98, with a difference of 98-95=3. The receiver immediately drives its own clock control mechanism to continuously perform state updates for 3 clock cycles. Each cycle strictly follows the aforementioned triple clock control stop mechanism, selectively driving based on the carry bits of each register and the clock control drive code. After 3 steps, the internal state values ​​of the receiver's three linear feedback shift registers are completely consistent with the sender's state value at sequence number 98, achieving precise alignment.

[0200] S606. Generate a synchronization key stream segment with the same length as the ciphertext payload (excluding the synchronization verification field) in the ciphertext data, according to the same triple clock control stop mechanism as the sender.

[0201] In this embodiment, the total length of the ciphertext data is 18 bytes. After removing the 2-byte length prefix and the 4-byte synchronization check field, the ciphertext payload is 32E3F80F6B3EA15E47FC493D, a total of 12 bytes. After state alignment, the receiver continues to drive the triple clock stop mechanism to generate a 12-byte keystream and reads this 12-byte keystream segment from the keystream buffer, assuming it is 20BB024520BB024520BB0245.

[0202] S607. Perform a byte-by-byte XOR operation on the synchronization key stream segment and the same encryption mask used by the sender during encryption to obtain a dynamic synchronization key stream segment; initialize the encryption state register to the result of a bit-by-bit XOR operation on the clock perturbation factor and the serialization perturbation factor; for each ciphertext byte in the ciphertext payload, perform the following sequentially: take the lowest 8 bits of the current value of the encryption state register as the state extraction byte; perform an XOR operation on the ciphertext byte and the corresponding key stream byte in the dynamic synchronization key stream segment to obtain the restored byte; input the restored byte into the S-box for inverse nonlinear replacement to obtain the intermediate restored byte; perform an XOR operation on the intermediate restored byte and the state extraction byte to recover the plaintext byte; perform an XOR operation on the plaintext byte and the restored byte to obtain the decryption feedback byte; shift the encryption state register cyclically right by 8 bits and place the decryption feedback byte in the highest 8 bits to complete the state update; concatenate the recovered plaintext bytes in order to recover the binary byte stream;

[0203] In this embodiment, the encryption mask remains 0x5A8279BA. The synchronization keystream segment 20BB024520BB024520BB0245 is XORed with the encryption mask to obtain the dynamic synchronization keystream segment 7A397BFF7A397BFF7A397BFF (the same as the one used by the sender during encryption). The initial value of the encryption status register is set to the clock perturbation factor 0x00000660 XORed with the serialization perturbation factor 0x04E00000 = 0x04E00660. Decrypting the 0th byte (0x32) of the ciphertext payload: The lower 8 bits of the state extraction byte (0x04E00660) are 0x60; the 0th byte of the dynamic key byte is 0x7A, and the ciphertext byte (0x32) XOR 0x7A = 0x48 yields the restored byte; the restored byte (0x48) is input into the inverse S-box of AES (inverse transformation of the S-box) for table lookup, assuming the inverse S-box outputs the intermediate restored byte (0x00); the intermediate restored byte (0x00) XOR the state extraction byte (0x60) = 0x60, recovering the plaintext byte (0x60); calculating the feedback byte: plaintext byte (0x60) XOR the restored byte (0x48) = 0x28; the encryption state register is circularly shifted right by 8 bits to 0x6004E006, and the feedback byte (0x28) is placed in the highest 8 bits to obtain the new state (0x2804E006). Decrypt 12 bytes in sequence to recover the binary byte stream 000E07E001A3B6E0CD06C2E15602337F (the first 2 bytes are the length prefix).

[0204] S608. The recovered binary byte stream is deserialized through the custom binary protocol stack according to the field encoding rules determined by the lowest two bits of the serialization mask, and restored to protocol data.

[0205] In this embodiment, the serialization mask is 0xB7E15144, with its lowest two bits being 00, corresponding to field encoding rule 00. Following this rule, a 2-byte prefix of 000E (14-byte payload) is read from the binary byte stream. Then, padding bytes are skipped, the circular XOR obfuscation is de-interpreted, and the field arrangement is restored. This parses out the opcode 0x03, user ID 0x0001A3B2, skill ID 0x00CD, target monster ID 0x06C6, coordinates X 0x0156, and coordinates Y 0x0237. Finally, the complete protocol data is restored: release skill ID = 205, target monster ID = 1734, skill coordinates (x = 342, y = 567), achieving an end-to-end secure communication loop.

[0206] As a concrete example, taking the scenario of player A releasing a skill in the aforementioned massively multiplayer online role-playing game as an example, when the server receives the 18-byte encrypted data 000EAA1F2CD532E3F80F6B3EA15E47FC493D from the client, it immediately initiates the decryption and deserialization process. The server first extracts the 13th to 8th bits (100111, decimal 39) from the same 63-bit random positive integer token 0x3F2A8B1C9D4E6F07 stored within itself as a synchronization check factor, and then XORs it bit by bit with the fifth preset constant 0xC1A3E5F7 to obtain the synchronization check mask 0xC1A3E5D0. The 4-byte synchronization check field AA1F2CD5 is extracted from the beginning offset 2 bytes of the ciphertext data. XORing this with the synchronization check mask yields the clock sequence number encapsulated value 0x6BBCC905 with CRC-32 check bits. After successful CRC-32 verification, the clock sequence number 98 at the time of encryption by the sender is extracted. At this point, the clock sequence number of the server's local keystream generator is 95. The difference of 3 is calculated, and its triple clock-controlled stop mechanism immediately steps forward for 3 clock cycles, ensuring that the internal states of the three linear feedback shift registers are precisely aligned with the sender's state at clock sequence number 98. Subsequently, the server continues to generate a 12-byte synchronization keystream segment 20BB024520BB024520BB0245 of the same length as the ciphertext payload, and XORs it cyclically with the encryption mask 0x5A8279BA to obtain the dynamic synchronization keystream 7A397BFF7A397BFF7A397BFF. The encryption status register is initialized to 0x04E00660. The first ciphertext byte (32) of the payload is decrypted: the lower 8 bits of the status register (0x60) are taken, and the ciphertext byte (32) is XORed with the key byte (7A) to obtain the restored byte (48). This is then replaced by an AES inverse S-box to obtain the intermediate restored byte (00), which is XORed with the extracted status byte (60) to recover the plaintext byte (60). The status register is then updated with 60 XOR 48 = 28. All 12 bytes of the payload are decrypted sequentially, recovering the binary byte stream 000E07E001A3B6E0CD06C2E15602337F. Finally, based on the field encoding rule 00 selected by the lowest two bits 00 of the serialization mask 0xB7E15144, the length prefix 000E is read from the binary byte stream, the cyclic XOR obfuscation is removed, the padding bytes are removed, and each field is parsed in the order of opcode → user ID → skill ID → target monster ID → coordinate X → coordinate Y to completely restore the protocol data: opcode 0x03 (release skill), user ID 0x0001A3B2, skill ID 205, target monster ID 1734, skill coordinates (342, 567).The entire process is automatically completed on the server side, including synchronization verification, key stream alignment, decryption, and deserialization. Even if data packets are out of order due to network fluctuations, the decryption state can be quickly restored through precise synchronization of the clock sequence number. Any tampering will be immediately discarded and a reset will be triggered due to CRC verification failure, ensuring the integrity and real-time performance of the communication content.

[0207] Example 5

[0208] Please see Figure 3 Another embodiment of the present invention provides a communication encryption system based on triple clock-controlled stop-and-go stream cipher, comprising:

[0209] The token generation module is configured to: after the server and the client establish a connection, generate a random positive integer token, extract bits at preset positions from the token, and combine them into a 32-bit encryption key;

[0210] The initialization module is configured to: perform three asymmetric bit transformations on the encryption key to generate a first seed, a second seed, and a third seed respectively; and use the first seed, the second seed, and the third seed to generate the initial states of a first linear feedback shift register, a second linear feedback shift register, and a third linear feedback shift register with different tap configurations through multiple rounds of linear feedback shift initialization.

[0211] The key stream generation module is configured to: selectively drive some or all of the linear feedback shift registers to update their states based on the carry bit states of the first, second, and third linear feedback shift registers using a triple clock-controlled stop mechanism; and perform an XOR operation on the current state values ​​output by each linear feedback shift register to generate a key stream.

[0212] The serialization module is configured to serialize the protocol data to be transmitted into a big-endian binary byte stream using a custom binary protocol stack.

[0213] The encryption module is configured to: use the key stream to perform byte-by-byte in-situ XOR encryption on the binary byte stream, generate ciphertext data, and send it to the receiver;

[0214] The synchronous decryption module is configured such that: the receiver uses the same encryption key and clock control configuration as the sender to generate a key stream synchronized with the sender, performs byte-by-byte in-situ XOR decryption on the received ciphertext data to recover the binary byte stream, and then deserializes the binary byte stream into protocol data through the custom binary protocol stack.

[0215] Example 6

[0216] An electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement a communication encryption method based on triple clock-controlled stop-and-go stream cipher.

[0217] A computer-readable storage medium storing computer instructions that, when executed, perform a communication encryption method based on a triple clock-controlled stop-and-go stream cipher.

[0218] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the present invention. All of these variations are within the scope of protection of the present invention.

Claims

1. A communication encryption method based on triple clock-controlled stop-and-go stream cipher, characterized in that, include: Generate a random positive integer token, extract bits at preset positions from the token, and combine them into a 32-bit encryption key; The encryption key is subjected to three asymmetric bit transformations to generate a first seed, a second seed, and a third seed, respectively. Using the first seed, the second seed, and the third seed, multiple rounds of linear feedback shift initialization are performed to generate the initial states of a first linear feedback shift register, a second linear feedback shift register, and a third linear feedback shift register with different tap configurations. Through a triple clock-controlled stop mechanism, based on the carry bit states of the first, second, and third linear feedback shift registers, some or all of the linear feedback shift registers are selectively driven to update their states, and the current state values ​​output by each linear feedback shift register are XORed to generate a key stream. The protocol data to be transmitted is serialized into a big-endian binary byte stream using a custom binary protocol stack; Using the key stream, the binary byte stream is subjected to byte-by-byte in-situ XOR encryption to generate ciphertext data, which is then sent to the receiver. The receiver uses the same encryption key and clock control configuration as the sender to generate a key stream synchronized with the sender. It performs byte-by-byte in-situ XOR decryption on the received ciphertext data to recover the binary byte stream, and then deserializes the binary byte stream into protocol data through the custom binary protocol stack.

2. The communication encryption method based on triple clock-controlled stop-and-go stream cipher as described in claim 1, characterized in that, The combination into a 32-bit encryption key includes: Generate a random positive integer token, extract the first preset bit segment from the token, and determine its corresponding integer value as the reference offset; The extraction start position is obtained by performing a modulo operation between the reference offset and a preset base. Starting from the extraction start position in the token, continuously extract bits of a second preset length along a preset direction to form a candidate key fragment; Extract the remaining bits from the token that did not participate in generating the candidate key fragment and did not participate in generating the reference offset, select bits of a third preset length from them, and combine them into an obfuscation mask; The candidate key fragment is XORed with the obfuscation mask to obtain a 32-bit encryption key.

3. The communication encryption method based on triple clock-controlled stop-and-go stream cipher as described in claim 2, characterized in that, Perform three asymmetric bit transformations on the encryption key, including: Extract a preset bit segment from the random positive integer token that was not used to generate the encryption key, and determine its corresponding integer value as the transformation adjustment factor; The transformation adjustment factor is XORed with a first preset constant to obtain a first dynamic mask; the transformation adjustment factor is then cyclically shifted left by a first preset number of bits to obtain a second dynamic mask. After cyclically shifting the transformation adjustment factor to the right by a second preset number of bits, a third dynamic mask is obtained; The encryption key is XORed with the first dynamic mask. The XOR result is then processed by linear feedback and XORed with the third dynamic mask to obtain the first seed.

4. The communication encryption method based on triple clock-controlled stop-and-go stream cipher as described in claim 3, characterized in that, Performing three asymmetric bit transformations on the encryption key further includes: The first seed is subjected to parity bit swapping, the swapping result is inverted after linear feedback processing, and then the inverted result is XORed with the first dynamic mask to obtain the second seed. The second seed is subjected to half-byte swapping. The swapping result is then processed by linear feedback, and the processing result is XORed with the second dynamic mask to obtain the third seed.

5. The communication encryption method based on triple clock-controlled stop-and-go stream cipher as described in claim 4, characterized in that, The generation of the key stream includes: Extract the third preset bit segment from the random positive integer token that was not used to generate the encryption key, the reference offset, or the transformation adjustment factor, and determine its corresponding integer value as the clock control adjustment factor; The clock control adjustment factor is XORed with the second preset constant to obtain the clock control mask; the clock control adjustment factor is then cyclically shifted left by a third preset number of bits to obtain the clock control disturbance factor. In each clock cycle, the first clock sampling bit located at the highest bit in the current carry bit and corresponding current state value of the first linear feedback shift register, the second clock sampling bit located at the highest bit in the current carry bit and corresponding current state value of the second linear feedback shift register, and the third clock sampling bit located at the highest bit in the current carry bit and corresponding current state value of the third linear feedback shift register are respectively acquired.

6. The communication encryption method based on triple clock-controlled stop-and-go stream cipher as described in claim 5, characterized in that, The generation of the key stream also includes: The first clock control determination bit is obtained by performing an XOR operation between the current carry bit of the first linear feedback shift register and the first clock control sampling bit; the second clock control determination bit is obtained by performing an XOR operation between the current carry bit of the second linear feedback shift register and the second clock control sampling bit; and the third clock control determination bit is obtained by performing an XOR operation between the current carry bit of the third linear feedback shift register and the third clock control sampling bit. The first clock control decision bit, the second clock control decision bit, and the third clock control decision bit are concatenated from the high bit to the low bit to form a three-bit binary number, which is used as the clock control selection code; The clock selection code is XORed with the lowest three bits of the clock mask to obtain the clock drive code.

7. The communication encryption method based on triple clock-controlled stop-and-go stream cipher as described in claim 6, characterized in that, The generation of the key stream also includes: Based on the value of the clock control drive code, determine the combination of linear feedback shift registers that are driven to update the state in the current clock cycle; The intermediate key is obtained by XORing the current state values ​​of the clock-driven linear feedback shift registers and the current state values ​​of the non-clock-driven linear feedback shift registers. The intermediate key word is XORed with the clock perturbation factor to generate a 32-bit key word, which is then filled into the key stream buffer.

8. The communication encryption method based on triple clock-controlled stop-and-go stream cipher as described in claim 7, characterized in that, The determination of the combination of linear feedback shift registers driven for state updates within the current clock cycle includes: When the clock control drive code is 000 or 111, the first linear feedback shift register, the second linear feedback shift register, and the third linear feedback shift register are all driven to perform a linear feedback shift operation once. When the clock drive code is 001, 010, 100, 110, 101, or 011, only the two linear feedback shift registers corresponding to the 1 bits in the clock drive code perform a linear feedback shift operation once, while the other linear feedback shift register keeps its current state value unchanged.

9. A communication encryption system based on a triple clock-controlled stop-run stream cipher, used to implement the communication encryption method based on a triple clock-controlled stop-run stream cipher as described in any one of claims 1-8, characterized in that, include: The token generation module is configured to: generate a random positive integer token, extract bits at preset positions from the token, and combine them into a 32-bit encryption key; The initialization module is configured to: perform three asymmetric bit transformations on the encryption key to generate a first seed, a second seed, and a third seed respectively; and use the first seed, the second seed, and the third seed to generate the initial states of a first linear feedback shift register, a second linear feedback shift register, and a third linear feedback shift register with different tap configurations through multiple rounds of linear feedback shift initialization. The key stream generation module is configured to: selectively drive some or all of the linear feedback shift registers to update their states based on the carry bit states of the first, second, and third linear feedback shift registers using a triple clock-controlled stop mechanism, and perform an XOR operation on the current state values ​​output by each linear feedback shift register to generate a key stream.

10. The communication encryption system based on triple clock-controlled stop-and-go stream cipher as described in claim 9, characterized in that, The communication encryption system further includes: The serialization module is configured to serialize the protocol data to be transmitted into a big-endian binary byte stream using a custom binary protocol stack. The encryption module is configured to: use the key stream to perform byte-by-byte in-situ XOR encryption on the binary byte stream, generate ciphertext data, and send it to the receiver; The synchronous decryption module is configured such that: the receiver uses the same encryption key and clock control configuration as the sender to generate a key stream synchronized with the sender, performs byte-by-byte in-situ XOR decryption on the received ciphertext data to recover the binary byte stream, and then deserializes the binary byte stream into protocol data through the custom binary protocol stack.

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