Control circuit of camera equipment

Abstract

This application relates to a control circuit for a camera device. The circuit includes an adder circuit, a comparator circuit, and a delay circuit. The first input terminal of the adder circuit is connected to a first power input terminal. The output terminal of the adder circuit is connected to a second power input terminal of the camera device and a first input terminal of the comparator circuit. The second input terminal of the comparator circuit is connected to the first power input terminal. The output terminal of the comparator circuit is connected to an input terminal of the delay circuit. The output terminal of the delay circuit is connected to a third power input terminal of the camera device. The voltages of the first power input terminal and the second power input terminal are the same. This embodiment can improve the smoothness of mode switching in the camera device.

Description

Technical Field

[0001] This application relates to the field of camera equipment technology, and in particular to a control circuit for a camera equipment. Background Technology

[0002] With the development of science and technology, video recording technology has emerged, and the application of video recording via cameras has become increasingly widespread. Current video cameras typically have multiple different recording modes, allowing for the optimization of relevant camera parameters based on different shooting scenarios to meet the shooting needs of various situations.

[0003] When a camera has multiple recording modes, there is a need to switch between them during use. However, in some related technologies, horizontal lines appear on the camera's screen when switching modes, and it may even cause the camera to freeze, resulting in a lack of smoothness during mode switching. Summary of the Invention

[0004] Therefore, it is necessary to provide a control circuit for a camera device to address the aforementioned technical problems and reduce the issue of low smoothness when switching camera modes.

[0005] In a first aspect, this application provides a control circuit for a camera device, the circuit comprising: an adder circuit, a comparator circuit, and a delay circuit;

[0006] The first input terminal of the adder circuit is connected to the first power input terminal, the output terminal of the adder circuit is connected to the second power input terminal and the first input terminal of the comparator circuit, the second input terminal of the comparator circuit is connected to the first power input terminal, the output terminal of the comparator circuit is connected to the input terminal of the delay circuit, the output terminal of the delay circuit is connected to the third power input terminal of the camera device, and the voltages of the first power input terminal and the second power input terminal are the same.

[0007] The control circuit based on this embodiment connects to the first power input terminal via an adder circuit, thereby collecting the output current from the first power input terminal. Based on the collected current, signals are output to the second power input terminal and the first input terminal of the comparator circuit, thus realizing voltage output from the first power input terminal to the second power input terminal. The comparator circuit receives the output signal from the adder circuit and the signal from the first power input terminal simultaneously. After comparison, the comparison result is delayed by a delay circuit and then output to the third power terminal of the camera device. Thus, by combining the adder circuit, the comparator circuit, and the delay circuit, a relatively stable current is provided to the third power terminal of the camera device. This allows for dynamic adjustment of the power input to the third power terminal of the camera device, thereby controlling the input power of the camera device. This reduces the possibility of excessive current changes when the camera switches camera modes, lowers the likelihood of poor smoothness during mode switching, and improves the smoothness of mode switching.

[0008] In some embodiments, the adder circuit includes an adder U1, the first input terminal of the adder U1 is connected to the first power input terminal, the second input terminal of the adder U1 is left floating, and the output terminal of the adder U1 is connected to the second power input terminal and the first input terminal of the comparator circuit.

[0009] Based on this embodiment, the adder circuit includes an adder whose second input terminal is left floating. That is, the adder actually performs addition processing on the current of the first power input terminal connected to the first input terminal, thereby enabling the collection of the current output from the first power input terminal, which helps to further improve the current constant performance.

[0010] In some embodiments, the adder circuit further includes a first resistor R1, a sixth resistor R6, and a transistor Q1;

[0011] The first input terminal of the adder is connected to the first power input terminal through the first resistor R1. The output terminal of the adder is connected to the base of the transistor. The collector of the transistor Q1 and the first input terminal of the adder are connected to one end of the sixth resistor R6 and the first input terminal of the comparator circuit. The other end of the sixth resistor R6 is connected to the second power input terminal. The emitter of the transistor Q1 is grounded.

[0012] Based on this embodiment, the adder circuit also includes a first resistor R1, a sixth resistor R6, and a transistor Q1. Thus, by setting the transistor Q1, the on / off control of the signal output to the second power input terminal and the first input terminal of the comparator circuit based on the output result of the adder U1 can be achieved. Combined with the setting of the first resistor R1 and the sixth resistor R6, the current limiting effect of the first resistor R1 and the sixth resistor R6 can ensure that the adder U1 and the transistor Q1 operate in an appropriate state, thereby improving the performance of the control circuit.

[0013] In some embodiments, the adder circuit further includes a second resistor R2 and a first grounding capacitor C1. The control terminal of the adder is connected to the first grounding capacitor C1 and one end of the second resistor R2, and the other end of the second resistor R2 is connected to a fourth power supply.

[0014] Based on this embodiment, the adder circuit also includes a circuit consisting of a second resistor R2 and a first grounding capacitor C1 connected to the control terminal of the adder. This allows the adder U1 to be controlled based on the fourth power supply combined with the second resistor R2 and the first grounding capacitor C1, which helps to achieve precise control of the adder and thus improves the constant current performance of the control circuit.

[0015] In some embodiments, the adder circuit further includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a seventh resistor R7;

[0016] The output of the adder is connected to the base of the transistor Q1 through the third resistor R3. The fourth resistor R4 and the fifth resistor R5 are connected in parallel, with one end connected to the emitter of the transistor and the other end grounded. The seventh resistor R7 is connected between the first input of the adder, the collector of the transistor and one end of the sixth resistor R6, the common terminal, and the first input of the comparator circuit.

[0017] Based on this embodiment, the states of adder U1 and transistor Q1 can be further adjusted by combining the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the seventh resistor R7. This helps to achieve precise control over the states of adder U1 and transistor Q1, thereby further improving the constant current performance of the control circuit. Furthermore, by setting the seventh resistor R7, current limiting can be achieved, preventing excessive current output from adder circuit 10 from affecting the comparator circuit, thus helping to improve the stability of the comparator circuit and the control circuit.

[0018] In some embodiments, the control circuit further includes an eighth resistor R8, which is disposed between the first power input terminal and the second input terminal of the comparator circuit.

[0019] Based on this embodiment, an eighth resistor R8 is provided between the second input terminal and the first power input terminal of the comparator circuit, thereby achieving current limiting and avoiding the influence of excessive current output from the first power input terminal on the comparator circuit, which helps to improve the stability of the comparator circuit and the control circuit.

[0020] In some embodiments, the control circuit further includes: a first circuit connected in parallel with the eighth resistor R8, the first circuit including a diode D1, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12.

[0021] The negative terminal of diode D1 and one end of the ninth resistor R9 are connected to the first power input terminal. The other end of the ninth resistor R9 is connected to the tenth resistor R10. The positive terminal of diode D1 and the other end of the tenth resistor R10 are grounded through the eleventh resistor R11. The common terminal of the ninth resistor R9 and the tenth resistor R10 is connected to the second input terminal of the comparator circuit through the twelfth resistor R12.

[0022] Based on this embodiment, a first circuit connected in parallel with the eighth resistor is also provided between the second input terminal and the first power input terminal of the comparator circuit. Combined with the voltage division effect of the ninth resistor R9 and the tenth resistor R10, it can adapt to the voltage range of the first power input terminal. Combined with the reverse setting of the diode, it can simultaneously realize input protection of the comparator circuit, which helps to improve the stability of the comparator circuit and the control circuit.

[0023] In some embodiments, the comparison circuit includes a comparator and a thirteenth resistor R13 connected between a first input terminal and an output terminal of the comparator.

[0024] Based on this embodiment, by connecting the thirteenth resistor R13 between the first input terminal and the output terminal of the comparator, feedback can be introduced to enable the comparator to operate in the linear region, thereby achieving voltage following and helping to improve the stability and accuracy of constant current control.

[0025] In some embodiments, the delay circuit includes a fourteenth resistor R14 and a capacitor assembly, one end of the fourteenth resistor R14 being connected to the output terminal of the comparator circuit and the other end being connected to the capacitor assembly, and the other end of the capacitor assembly being connected to the third power supply terminal of the camera device.

[0026] Based on this embodiment, by setting the delay circuit, adaptive adjustments can be made according to the changes in load current, which helps to improve the stability and accuracy of constant current control.

[0027] In some embodiments, the capacitor assembly includes a plurality of grounded capacitors connected in parallel.

[0028] In some embodiments, the control circuit may further include a fifteenth resistor R15 connected between the first power input terminal and the second power input terminal.

[0029] Based on this embodiment, by setting a fifteenth resistor R15 between the first power input terminal and the second power input terminal, the current at the first power input terminal can be output to the second power input terminal via the fifteenth resistor R15 when constant current processing is not required, so as to realize the output after power conversion.

[0030] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 This is a schematic diagram of the control circuit of a camera device in one embodiment;

[0033] Figure 2 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0034] Figure 3 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0035] Figure 4 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0036] Figure 5 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0037] Figure 6 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0038] Figure 7 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0039] Figure 8 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0040] Figure 9 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0041] Figure 10 This is a schematic diagram of the control circuit of a camera device in another embodiment;

[0042] Figure 11 This is a schematic diagram of the control circuit of a camera device in a specific example.

[0043] Figure 12 This is a schematic diagram of the current collected during the camera device mode switching process before and after the control circuit of the camera device using the embodiments of this application, as shown in a specific example. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0048] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0049] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0051] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0052] Currently, when camera devices (such as camcorders) have multiple different recording modes, there is a need to switch between these modes during use. However, in related technologies, when switching recording modes, horizontal lines appear on the camera's display screen, and it may even cause the camera to freeze, resulting in a lack of smoothness during mode switching.

[0053] Research revealed that the horizontal stripes appearing on the camera during mode switching are caused by excessive current fluctuations during this process. Taking a mobile digital video recorder (DVR) as an example, the power supply to the DVR causes black horizontal stripes on the 18M line, but these stripes disappear when powered solely by a 12V power supply. Therefore, it can be determined that the issue is caused by centralized power supply, primarily due to significant current fluctuations at the camera end during centralized power supply. This is because the aviation connector cable has four wires: power, ground, signal, and ground. The power current flows back from both grounds simultaneously. When the mobile extension cable is long, the impedance at the wire end is high, resulting in significant voltage fluctuations on the signal ground due to current changes. This affects the CVI differential signal reaching the DVR, and when these voltage fluctuations reach a certain value, visible horizontal stripes appear on the image.

[0054] To address the issue of horizontal lines appearing when a camera switches modes, relevant solutions include using power isolation chips and circuits to isolate the power supply for different modes, or using driver chips to stabilize current fluctuations in the camera's backend circuitry. However, these methods are relatively expensive.

[0055] Accordingly, embodiments of this application provide a control circuit for a camera device. This solves the problem of low smoothness when switching camera modes at a low cost, and reduces horizontal lines during mode switching.

[0056] refer to Figure 1 As shown, the control circuit of the camera device in some embodiments of this application includes: an adder circuit 10, a comparator circuit 20, and a delay circuit 30;

[0057] The first input terminal of the adder circuit 10 is connected to the first power input terminal S1. The output terminal of the adder circuit 10 is connected to the second power input terminal S2 and the first input terminal of the comparator circuit 20. The second input terminal of the comparator circuit 20 is connected to the first power input terminal S1. The output terminal of the comparator circuit 20 is connected to the input terminal of the delay circuit 30. The output terminal of the delay circuit 30 is connected to the third power input terminal S3 of the camera device. The voltages of the first power input terminal S1 and the second power input terminal S2 are the same.

[0058] The adder circuit is a circuit structure that can generate and output a sum of signals. The input terminal of the adder circuit is connected to the first power input terminal S1, so that the current output from the first power input terminal can be accumulated and summed to output the result of the accumulated sum.

[0059] A comparator circuit is a circuit that can compare two input signals and output a signal corresponding to the comparison result. The first input terminal and the second input terminal of the comparator circuit are respectively connected to the output terminal of the adder circuit and the first power input terminal S1. Thus, the signal output by the adder circuit can be compared with the signal obtained from the first power input terminal S1, and the output can be combined with the comparison result to output a constant signal based on the comparison result.

[0060] The delay circuit is a circuit that outputs the input signal after a certain delay, thereby enabling precise control of the signal output to the third power supply terminal S3.

[0061] Here, the first power input terminal S1 and the second power input terminal S2 are external power input ports of the camera device, such as the power ports of the camera device's external adapter. The first power input terminal S1 and the second power input terminal S2 have the same voltage, so they can be connected to the same external power input port to achieve the input of the same voltage power supply.

[0062] The third power supply terminal S3 is the power supply terminal of the camera device. The output terminal of the delay circuit is connected to the power supply section of the camera device, so the power supply section of the camera device can be regarded as a load. The signal output by the delay circuit can control the current change of the third power supply terminal S3, thereby controlling the current change of the power supply section of the camera device to achieve constant current and constant current of the camera device.

[0063] The control circuit based on this embodiment connects to the first power input terminal via an adder circuit, thereby collecting the output current from the first power input terminal. Based on the collected current, signals are output to the second power input terminal of the camera device and the first input terminal of the comparator circuit, thus achieving voltage output from the first power input terminal to the second power input terminal. The comparator circuit receives the output signal from the adder circuit and the signal from the first power input terminal simultaneously, compares them, and outputs the comparison result to the third power input terminal of the camera device after a delay by a delay circuit. Thus, by combining the adder circuit, the comparator circuit, and the delay circuit, a relatively stable current is provided to the third power input terminal of the camera device. This allows for dynamic adjustment of the power input to the third power input terminal of the camera device, thereby controlling the input power of the camera device. This reduces the possibility of excessive current fluctuations when the camera switches camera modes, lowers the likelihood of poor smoothness during mode switching, and improves the smoothness of mode switching.

[0064] In some embodiments, reference Figure 2 As shown, the adder circuit 10 includes an adder U1. The first input terminal 1 of the adder U1 is connected to the first power input terminal S1, the second input terminal 2 of the adder U1 is left floating, and the output terminal 3 of the adder U1 is used to connect to the second power input terminal S2 and the first input terminal of the comparator circuit 20.

[0065] The specific implementation of adder U1 is not limited; in some embodiments, it can be implemented using an operational amplifier.

[0066] Based on this embodiment, the adder circuit includes adder U1, whose second input terminal 2 is left floating. That is, adder U1 actually performs addition processing on the current of the first power input terminal connected to the first input terminal 1, thereby enabling the collection of the current output from the first power input terminal S1, which helps to further improve the current constant performance.

[0067] In some embodiments, reference Figure 3 As shown, the adder circuit 10 also includes a first resistor R1, a sixth resistor R6, and a transistor Q1.

[0068] The first input terminal of adder U1 is connected to the first power input terminal S1 through the first resistor R1. The output terminal of adder U1 is connected to the base B of transistor Q1. The collector C of transistor Q1 and the first input terminal of adder U1 are connected to one end of the sixth resistor R6 and the first input terminal of comparator circuit 20. The other end of the sixth resistor R6 is connected to the second power input terminal S2. The emitter E of transistor Q1 is grounded.

[0069] Based on this embodiment, the adder circuit also includes a first resistor R1, a sixth resistor R6, and a transistor Q1. Thus, by setting the transistor Q1, the on / off control of the signal output to the second power input terminal S2 and the first input terminal of the comparator circuit 20 based on the output result of the adder U1 can be achieved. Combined with the setting of the first resistor R1 and the sixth resistor R6, the current limiting effect of the first resistor R1 and the sixth resistor R6 can ensure that the adder U1 and the transistor Q1 operate in an appropriate state, thereby improving the performance of the control circuit.

[0070] In some embodiments, reference Figure 4 As shown, the adder circuit 10 also includes a second resistor R2 and a first grounding capacitor C1. The control terminal of the adder U1 is connected to the first grounding capacitor C1 and one end of the second resistor R2, and the other end of the second resistor R2 is connected to the fourth power supply S0.

[0071] Based on this embodiment, the adder circuit 10 also includes a circuit consisting of a second resistor R2 and a first grounding capacitor C1 connected to the control terminal of the adder U1. This allows the adder U1 to be controlled based on the fourth power supply S0 in combination with the second resistor R2 and the first grounding capacitor C1, which helps to achieve precise control of the adder U1 and thus improves the constant current performance of the control circuit.

[0072] In some embodiments, reference Figure 5 As shown, the adder circuit 10 also includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a seventh resistor R7.

[0073] The output of adder U1 is connected to the base B of transistor Q1 through the third resistor R3. The fourth resistor R4 and the fifth resistor R5 are connected in parallel, with one end connected to the emitter E of transistor and the other end grounded. The seventh resistor R7 is connected between the first input of adder U1, the collector C of transistor Q1 and one end of the sixth resistor R6, and the first input of comparator circuit 20.

[0074] Based on this embodiment, the states of adder U1 and transistor Q1 can be further adjusted by combining the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the seventh resistor R7. This helps to achieve precise control over the states of adder U1 and transistor Q1, thereby further improving the constant current performance of the control circuit. Furthermore, by setting the seventh resistor R7, current limiting can be achieved, preventing excessive current output from adder circuit 10 from affecting comparator circuit 20, thus helping to improve the stability of comparator circuit 20 and the control circuit.

[0075] In some embodiments, reference Figure 6 As shown, the control circuit also includes an eighth resistor R8, which is disposed between the first power input terminal S1 and the second input terminal of the comparison circuit 20.

[0076] Based on this embodiment, an eighth resistor R8 is provided between the second input terminal of the comparator circuit 20 and the first power input terminal S1, thereby achieving current limiting and avoiding the influence of excessive current output from the first power input terminal S1 on the comparator circuit 20, which helps to improve the stability of the comparator circuit 20 and the control circuit.

[0077] In some embodiments, reference Figure 7 As shown, the control circuit further includes a first circuit connected in parallel with the eighth resistor R8, the first circuit including a diode D1, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12.

[0078] The negative terminal of diode D1 and one end of the ninth resistor R9 are connected to the first power input terminal S1. The other end of the ninth resistor R9 is connected to the tenth resistor R10. The positive terminal of diode D1 and the other end of the tenth resistor R10 are grounded through the eleventh resistor R11. The common terminal of the ninth resistor R9 and the tenth resistor R10 is connected to the second input terminal of the comparator circuit 20 through the twelfth resistor R12.

[0079] Based on this embodiment, a first circuit connected in parallel with the eighth resistor R8 is also provided between the second input terminal of the comparator circuit 20 and the first power input terminal S1. Combined with the voltage division effect of the ninth resistor R9 and the tenth resistor R10, it can adapt to the voltage range of the first power input terminal S1. Combined with the reverse setting of the diode D1, it can simultaneously realize input protection of the comparator circuit 20, which helps to improve the stability of the comparator circuit 20 and the control circuit.

[0080] The implementation of the comparator circuit 20 is not limited; in some embodiments, refer to... Figure 8As shown, in some embodiments, the comparison circuit 20 includes a comparator U2 and a thirteenth resistor R13 connected between the first input terminal and the output terminal of the comparator U2.

[0081] The specific implementation of comparator U2 is not limited; in some embodiments, it can be implemented using an operational amplifier.

[0082] Based on this embodiment, by connecting the thirteenth resistor R13 between the first input terminal and the output terminal of comparator U2, feedback can be introduced to make comparator U2 operate in the linear region, thereby achieving voltage following and helping to improve the stability and accuracy of constant current control.

[0083] The specific implementation of the delay circuit 30 is not limited; in some embodiments, refer to... Figure 9 As shown, the delay circuit 30 includes a fourteenth resistor R14 and a capacitor assembly 301. One end of the fourteenth resistor R14 is connected to the output terminal of the comparator circuit 20, and the other end is connected to the capacitor assembly 301. The other end of the capacitor assembly 301 is connected to the third power supply terminal S3 of the camera device.

[0084] The capacitor assembly 301 may include only one capacitor or multiple capacitors connected in parallel. Taking a capacitor assembly 301 containing four capacitors connected in parallel as an example... Figure 9 The illustration uses capacitor assembly 301, which includes capacitors C2, C3, C4, and C5, as an example.

[0085] Based on this embodiment, by setting the delay circuit 30, adaptive adjustments can be made according to the changes in load current, which helps to improve the stability and accuracy of constant current control.

[0086] In some embodiments, reference Figure 10 As shown, the control circuit may also include a fifteenth resistor R15 connected between the first power input terminal S1 and the second power input terminal S2.

[0087] Therefore, by setting a fifteenth resistor R15 between the first power input terminal S1 and the second power input terminal S2, the current of the first power input terminal S1 can be output to the second power input terminal S2 through the fifteenth resistor R15 when constant current processing is not required, so as to realize the output after power conversion.

[0088] In some embodiments, reference Figure 10As shown, the control circuit may further include a connecting line 40 disposed between the first power input terminal S1 and the second power input terminal S2. Thus, as needed, the first power input terminal S1 and the second power input terminal S2 can be directly connected via the connecting line 40, and the voltage of the first power input terminal S1 can be directly output through the second power input terminal S2.

[0089] In this embodiment, the voltages of the first power input terminal S1 and the second power input terminal S2 can be set to the same value, for example, both 12V. The voltage of the fourth power supply S0 is lower than the voltage of the first power input terminal S1, for example, it can be 3.3V.

[0090] Taking a scenario where both the first power input terminal S1 and the second power input terminal S2 have a voltage of 12V, and combining this with the embodiment described above, a schematic diagram of the control circuit in a specific example is shown below. Figure 11 As shown.

[0091] Figure 11 In the diagram, the voltage at node V5 of adder U1 can be expressed as:

[0092] V5=(k1+1)*(V2+V4) / 2-k1*V3 (1)

[0093] Where k1 = R6 / R1, V2 is Figure 11 The voltage at node V2 is shown in the diagram, and V4 is... Figure 11 The voltage at node V4 is shown in the diagram, and V3 is... Figure 11 The voltage at node V3 is shown in the diagram.

[0094] Comparator U2 is an open-loop operational amplifier. Assuming it operates in the linear region, the voltage at node V6 of its output can be expressed as:

[0095] V6=k2*(V5-V3) (2)

[0096] Where k2 is the open-loop gain of the comparator U2.

[0097] Combining equations (1) and (2) above, we have: V6=(k1+1)*k2*(V2+V4-V3) / 2 (3)

[0098] Due to packaging limitations and small resistance values, assuming the resistance values ​​of the seventh resistor R7 and the twelfth resistor R12 are fixed at 0.9R, when the power supply current is constant and stable, then:

[0099] V3-V4=R12*L=0.9L (4)

[0100] Substituting it into equation (3) above, we have

[0101] V6=(k1+1)*k2*(V2-0.9*L) / 2 (5)

[0102] Adjust the values ​​of coefficient k1, node voltage V2, third resistor R3, and load resistor R4 to make transistor Q1 in a semi-conducting state. At this time, the quiescent operating point is set at the midpoint of the load current. It can change in both directions, increasing and decreasing the load current, or it can be moved up or down according to the actual direction of load change.

[0103] Among them, combined Figure 11 As shown, the voltage at node V2, V2 = V1 - V, can be determined by diode D1, the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11. Diode D1 stabilizes the voltage across the ninth resistor R9 and the eleventh resistor R11 at approximately 3.3V. Therefore, it can be calculated that:

[0104] V = 3.3 * R11 / (R11 + R9).

[0105] Therefore, after determining the third resistor R8 and the fourth resistor R4, the static operating point of transistor Q1 can be set by adjusting the voltage at node V2.

[0106] From equation (5), when the load current at node V4 decreases, the voltage at node V3 immediately rises, while the voltage at node V6 remains unchanged due to the delay of the RC charging circuit at the output of comparator U2. At this time, the collector current of transistor Q1 increases, i.e., the load current increases. When the voltage at node V3 rises, the voltage at the twelfth resistor R12 decreases, and the load current decreases again. The load current compensates for the decrease in the power supply current, thus keeping the total current at node V1 constant. When the power supply current increases, the direction of change is opposite to the above. Therefore, dynamic adjustment of the current can be achieved.

[0107] based on Figure 11 The example shown demonstrates a test of the mode switching process of a camera device. The currents obtained without and with the circuitry of this application are as follows: Figure 12 A and Figure 12 As shown in B, in comparison Figure 12 A and Figure 12 As can be seen from B, the circuit provided in this application embodiment can effectively solve the problem of large current fluctuations in the back-end of the camera device due to mode switching or centralized power supply. After using the control circuit of this application embodiment, the current fluctuation is small, effectively improving the problem of camera device crashing due to large current fluctuations during mode switching. Moreover, based on the circuit of this application embodiment, micro constant current control can be achieved without additional isolation power supply circuits and control chips, and the cost is also lower.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A control circuit for a camera device, characterized in that, The circuit includes: an adder circuit, a comparator circuit, and a delay circuit; The first input terminal of the adder circuit is connected to the first power input terminal, the output terminal of the adder circuit is connected to the second power input terminal and the first input terminal of the comparator circuit, the second input terminal of the comparator circuit is connected to the first power input terminal, the output terminal of the comparator circuit is connected to the input terminal of the delay circuit, the output terminal of the delay circuit is connected to the third power input terminal of the camera device, and the voltages of the first power input terminal and the second power input terminal are the same.

2. The control circuit according to claim 1, characterized in that, The adder circuit includes an adder (U1), the first input terminal of the adder (U1) is connected to the first power input terminal, the second input terminal of the adder (U1) is left floating, and the output terminal of the adder (U1) is connected to the second power input terminal and the first input terminal of the comparator circuit.

3. The control circuit according to claim 2, characterized in that, The adder circuit also includes a first resistor (R1), a sixth resistor (R6), and a transistor (Q1). The first input terminal of the adder is connected to the first power input terminal through the first resistor (R1), and the output terminal of the adder is connected to the base of the transistor. The collector of the transistor (Q1) and the first input terminal of the adder are connected to one end of the sixth resistor (R6) and the first input terminal of the comparator circuit. The other end of the sixth resistor (R6) is connected to the second power input terminal. The emitter of the transistor (Q1) is grounded.

4. The control circuit according to claim 3, characterized in that, The adder circuit also includes a second resistor (R2) and a first grounding capacitor (C1). The control terminal of the adder (U1) is connected to the first grounding capacitor (C1) and one end of the second resistor (R2), and the other end of the second resistor (R2) is connected to a fourth power supply.

5. The control circuit according to claim 4, characterized in that, The adder circuit also includes a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), and a seventh resistor (R7). The output terminal of the adder is connected to the base of the transistor (Q1) through the third resistor (R3); the fourth resistor (R4) and the fifth resistor (R5) are connected in parallel, with one end connected to the emitter of the transistor (Q1) and the other end grounded. The seventh resistor (R7) is connected between the first input terminal of the adder (U1), the collector of the transistor (Q1) and one end of the sixth resistor (R6), and the first input terminal of the comparator circuit.

6. The control circuit according to any one of claims 1 to 5, characterized in that, The control circuit further includes an eighth resistor (R8), which is disposed between the first power input terminal and the second input terminal of the comparator circuit.

7. The control circuit according to claim 6, characterized in that, The control circuit further includes a first circuit connected in parallel with the eighth resistor (R8), the first circuit including a diode (D1), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), and a twelfth resistor (R12). The negative terminal of the diode (D1) and one end of the ninth resistor (R9) are connected to the first power input terminal. The other end of the ninth resistor (R9) is connected to the tenth resistor (R10). The positive terminal of the diode (D1) and the other end of the tenth resistor (R10) are grounded through the eleventh resistor (R11). The common terminal of the ninth resistor (R9) and the tenth resistor (R10) is connected to the second input terminal of the comparator circuit through the twelfth resistor (R12).

8. The control circuit according to any one of claims 1 to 5, characterized in that, The comparison circuit includes a comparator and a thirteenth resistor (R13) connected between the first input terminal and the output terminal of the comparator.

9. The control circuit according to any one of claims 1 to 5, characterized in that, The delay circuit includes a fourteenth resistor (R14) and a capacitor assembly. One end of the fourteenth resistor (R14) is connected to the output terminal of the comparator circuit, and the other end is connected to the capacitor assembly. The other end of the capacitor assembly is connected to the third power supply terminal of the camera device.

10. The control circuit according to any one of claims 1 to 5, characterized in that, The control circuit further includes a fifteenth resistor (R15) connected between the first power input terminal and the second power input terminal.

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