Exposure time control circuit and CIS line array chip

Abstract

This invention proposes an exposure time control circuit and a CIS linear array chip, relating to the field of contact image sensor technology. The circuit includes an exposure start-up module, an exposure reference signal generation module, and an exposure timing signal generation module. The exposure start-up module generates an exposure start-up signal and its corresponding inverted signal based on the chip's main clock signal, chip reset signal, and charge transfer signal. The exposure reference signal generation module generates an exposure reference signal based on the chip reset signal, exposure start-up signal, chip oscillator clock signal, and the inverted signal. The exposure timing signal generation module generates an exposure timing signal based on the chip reset signal, chip oscillator clock signal, and exposure reference signal. This circuit enables the generation of the exposure timing signal within the chip, eliminating reliance on external light source switching control and simplifying the control logic. Furthermore, the exposure time can be changed by altering the period of the chip oscillator clock signal, achieving flexible control of the exposure time.

Description

Technical Field

[0001] This invention relates to the field of contact image sensor technology, and more specifically, to an exposure time control circuit and a CIS linear array chip. Background Technology

[0002] With the widespread application of CIS (Contact Image Sensor) in scanners, copiers and other equipment, the performance of linear array chips, as the core imaging component, directly affects the scanning speed and image quality of the equipment.

[0003] Current CIS linear array chips generally employ a "light source driven" exposure control method, meaning the exposure time is controlled by the illumination time of the LED light source. Charge accumulation only occurs when the light source illuminates the CIS linear array chip; therefore, the illumination time is crucial. For example... Figure 1 The diagram shows the timing of an existing CIS line array chip. TR represents the line array start pulse, EXPO represents the exposure time or light source turn-on time, and OUT represents the chip readout time. Each TR represents a cycle, within which exposure and readout operations must be completed. To improve the scanning speed of the CIS line array chip, exposure and readout are performed in parallel. That is, the signal read out in the current cycle is the exposure value of the previous cycle, and the exposure value of the current cycle is sent to the next cycle for readout.

[0004] The existing exposure control methods for CIS linear array chips have the following drawbacks: 1. The system control is relatively complex, from... Figure 1 As can be seen from the timing diagram, an exposure is required for each TR cycle, which means that the LED light source is turned on and off once. This requires additional circuitry to control the state of the LED light source. Secondly, the exposure time cannot be too short, usually around 100us to 300us, which limits the output efficiency of the sensor's current or charge. In addition, as the demand for high-speed scanning gradually increases, a longer exposure time will also limit the working efficiency of the entire scanning system. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide an exposure time control circuit and a CIS line array chip to solve the problems of high control complexity and inflexible control of exposure time in the prior art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, the present invention provides an exposure time control circuit integrated into a CIS linear array chip. The exposure time control circuit includes an exposure start module, an exposure reference signal generation module, and an exposure timing signal generation module, which are electrically connected in sequence. The exposure start module is used to generate an exposure start signal and its corresponding inverted signal based on the received chip master clock signal, chip reset signal and charge transfer signal in the CIS line array chip; The exposure reference signal generation module is used to generate an exposure reference signal based on the received chip reset signal, exposure start signal, chip oscillator clock signal, and inverted signal; the high-level duration of the exposure reference signal is determined by the exposure reference signal generation module based on the chip oscillator clock signal; The exposure timing signal generation module is used to generate an exposure timing signal based on the received chip reset signal, chip oscillator clock signal and exposure reference signal; the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal.

[0007] In an optional implementation, the exposure start-up module includes a signal delay unit and a signal inversion unit, the signal delay unit and the signal inversion unit are electrically connected, and both the signal delay unit and the signal inversion unit are electrically connected to the exposure reference signal generation module; The signal delay unit is used to receive the chip master clock signal, the chip reset signal, and the charge transfer signal in the CIS line array chip, and delays the charge transfer signal based on the chip master clock signal and the chip reset signal to obtain the exposure start signal; The signal inversion unit is used to invert the received exposure start signal to obtain the inverted signal corresponding to the exposure start signal.

[0008] In an optional implementation, the signal delay unit includes a first NOR gate and a plurality of cascaded first D flip-flops. The data input terminal of the first-stage first D flip-flop is used to receive the charge transfer signal. The non-inverting output terminal of the previous stage first D flip-flop is electrically connected to the data input terminal of the next stage first D flip-flop. The non-inverting output terminal of the last stage first D flip-flop is left floating. The inverting output terminal of the last stage first D flip-flop is electrically connected to the first input terminal of the first NOR gate. The inverting output terminals of the remaining first D flip-flops, except for the last stage first D flip-flop, are left floating. The non-inverting output of the first D flip-flop preceding the last stage is electrically connected to the second input of the first NOR gate; the clock inputs of all the first D flip-flops are used to receive the chip's main clock signal, and the reset inputs of all the first D flip-flops are used to receive the chip's reset signal; the output of the first NOR gate is electrically connected to the signal inverting unit.

[0009] In an optional implementation, the exposure reference signal generation module includes a gating unit, a counting unit, and a signal generation unit, wherein the gating unit, the counting unit, and the signal generation unit are electrically connected in sequence, the gating unit is also electrically connected to the exposure start module, and the signal generation unit is also electrically connected to the exposure timing signal generation module. The gating unit is used to receive the chip reset signal, the exposure start signal, and the chip oscillator clock signal, and determines whether to allow the chip oscillator clock signal to pass based on the chip reset signal and the exposure start signal, thereby obtaining a gating clock signal; The counting unit is used to receive the exposure start signal, the inverted signal, and the gated clock signal, and counts the gated clock signal based on the exposure start signal and the inverted signal. When the count value reaches a preset value, it outputs a high level to obtain a counting pulse signal. The signal generation unit is used to receive the counting pulse signal and the exposure start signal, and generate an exposure reference signal based on the counting pulse signal and the exposure start signal; wherein, the exposure reference signal changes from low level to high level when the rising edge of the exposure start signal arrives, and changes from high level to low level when the rising edge of the counting pulse signal arrives.

[0010] In an optional implementation, the gating unit includes a first RS flip-flop and an AND gate. The reset input of the first RS flip-flop is used to receive the chip reset signal, the set input of the first RS flip-flop is used to receive the exposure start signal, the non-inverting output of the first RS flip-flop is electrically connected to the first input of the AND gate, and the inverting output of the first RS flip-flop is left floating. The second input of the AND gate is used to receive the chip oscillator clock signal. The AND gate is used to output the gated clock signal based on the signal output from the non-inverting output terminal of the first RS flip-flop and the clock signal of the chip oscillator.

[0011] In an optional implementation, the counting unit includes a second NOR gate, a second D flip-flop, and multiple cascaded third D flip-flops. The inverted outputs of all the third D flip-flops are electrically connected to the data inputs. The clock input of the first-stage third D flip-flop is used to receive the gated clock signal. The set input of the second D flip-flop and the set inputs of the remaining third D flip-flops except the last stage are all used to receive the inverted signal. In the remaining third D flip-flops except for the last stage, the clock input of the next stage third D flip-flop is electrically connected to the non-inverting output of the previous stage third D flip-flop; the clock input of the last stage third D flip-flop is electrically connected to the inverting output of the corresponding previous stage third D flip-flop; the reset input of the last stage third D flip-flop is used to receive the exposure start signal; the non-inverting output of the last stage third D flip-flop is electrically connected to the first input of the second NOR gate; the inverting output of the stage preceding the last stage third D flip-flop is also electrically connected to the second input of the second NOR gate; and the non-inverting output of the stage preceding the last stage third D flip-flop is electrically connected to the data input of the second D flip-flop. The clock input of the second D flip-flop is used to receive the gated clock signal; the non-inverting output of the second D flip-flop is electrically connected to the third input of the second NOR gate; the inverting output of the second D flip-flop is left floating; and the output of the second NOR gate is electrically connected to the signal generation unit. The second NOR gate is used to output the counting pulse signal based on the signal output from the non-inverting output terminal of the last stage third D flip-flop, the signal output from the inverting output terminal of the stage preceding the last stage third D flip-flop, and the signal output from the non-inverting output terminal of the second D flip-flop.

[0012] In an optional implementation, the signal generation unit includes a second RS flip-flop, the set input of the second RS flip-flop is electrically connected to the counting unit, the reset input of the second RS flip-flop is used to receive the exposure start signal, the non-inverting output of the second RS flip-flop is left floating, and the inverting output of the second RS flip-flop is electrically connected to the exposure timing signal generation module.

[0013] In an optional implementation, the exposure timing signal generation module includes a clock division unit, a resampling unit, and a signal truncation unit. The clock division unit is electrically connected to both the resampling unit and the signal truncation unit, and the resampling unit is electrically connected to both the exposure reference signal generation module and the signal truncation unit. The clock division unit is used to divide the received chip oscillator clock signal according to the received chip reset signal to obtain a divided clock signal; The resampling unit is used to resample the received exposure reference signal according to the received chip reset signal and the frequency division clock signal to obtain a sampled signal; The signal interception unit is used to generate an exposure timing signal based on the received frequency division clock signal and the sampling signal.

[0014] In an optional implementation, the clock division unit includes a fourth D flip-flop, the resampling unit includes a fifth D flip-flop, and the signal truncation unit includes a sixth, a seventh, an eighth, and a ninth D flip-flop. The clock input terminal of the fourth D flip-flop is used to receive the clock signal of the chip oscillator. The data input terminal of the fourth D flip-flop is electrically connected to the inverting output terminal. The reset input terminal of the fourth D flip-flop is used to receive the chip reset signal. The non-inverting output terminal of the fourth D flip-flop is electrically connected to the clock input terminals of the fifth D flip-flop, the sixth D flip-flop, and the seventh D flip-flop. The data input terminal of the fifth D flip-flop is electrically connected to the exposure reference signal generation module. The reset input terminal of the fifth D flip-flop is used to receive the chip reset signal. The non-inverting output terminal of the fifth D flip-flop is floating. The inverting output terminal of the fifth D flip-flop is electrically connected to the reset input terminals of the sixth D flip-flop, the seventh D flip-flop, the eighth D flip-flop, and the ninth D flip-flop. The data input terminal of the sixth D flip-flop is electrically connected to its inverted output terminal, and the non-inverted output terminal of the sixth D flip-flop is electrically connected to the data input terminal of the seventh D flip-flop; the inverted output terminal of the seventh D flip-flop is left floating, and the non-inverted output terminal of the seventh D flip-flop is electrically connected to the clock input terminal of the eighth D flip-flop; the data input terminal of the eighth D flip-flop is electrically connected to its inverted output terminal, and the non-inverted output terminal of the eighth D flip-flop is electrically connected to the clock input terminal of the ninth D flip-flop; the data input terminal of the ninth D flip-flop is electrically connected to its inverted output terminal, and the non-inverted output terminal of the ninth D flip-flop is used to output the exposure timing signal.

[0015] In a second aspect, the present invention provides a CIS line array chip, including the exposure time control circuit described in any of the foregoing embodiments.

[0016] The exposure time control circuit and CIS linear array chip provided in this embodiment of the invention are integrated within the CIS linear array chip. The exposure time control circuit includes an exposure start-up module, an exposure reference signal generation module, and an exposure timing signal generation module, which are electrically connected in sequence. The exposure start-up module generates an exposure start-up signal and its corresponding inverted signal based on the received chip master clock signal, chip reset signal, and charge transfer signal in the CIS linear array chip. The exposure reference signal generation module generates an exposure reference signal based on the received chip reset signal, exposure start-up signal, chip oscillator clock signal, and the inverted signal. The high-level duration of the exposure reference signal is determined by the exposure reference signal generation module based on the chip oscillator clock signal. The exposure timing signal generation module generates an exposure timing signal based on the received chip reset signal, chip oscillator clock signal, and exposure reference signal. The high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal. Because the exposure time control circuit is integrated into the CIS linear array chip, the exposure timing signal can be generated within the chip, eliminating the need for external light source switching. During scanner operation, the light source can remain continuously on, unlike traditional structures that repeatedly switch the light source on and off. This simplifies the control logic at the system level and reduces the requirements for the light source. Furthermore, the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal. The duration of the high-level range of the exposure reference signal is determined by the chip oscillator clock signal. Therefore, the actual exposure time is controlled by the period of the chip oscillator clock signal. By changing the period of the chip oscillator clock signal, the exposure time can be altered, achieving flexible control of the exposure time.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The timing diagram of an existing CIS line array chip is shown. Figure 2 This diagram shows a structural block diagram of an exposure time control circuit provided in an embodiment of the present invention; Figure 3This invention illustrates a structural block diagram of an exposure start-up module in an exposure time control circuit provided in an embodiment of the invention. Figure 4 This invention illustrates a circuit structure diagram of an exposure start-up module in an exposure time control circuit provided in an embodiment of the present invention. Figure 5 This invention illustrates a structural block diagram of an exposure reference signal generation module in an exposure time control circuit provided in an embodiment of the present invention. Figure 6 This invention illustrates a circuit structure diagram of an exposure reference signal generation module in an exposure time control circuit provided in an embodiment of the present invention. Figure 7 This invention illustrates a structural block diagram of an exposure timing signal generation module in an exposure time control circuit provided in an embodiment of the present invention. Figure 8 This invention illustrates a circuit structure diagram of an exposure timing signal generation module in an exposure time control circuit provided in an embodiment of the present invention. Figure 9 A timing diagram of the exposure time control circuit provided in an embodiment of the present invention is shown.

[0020] Icons: 100 - Exposure time control circuit; 110 - Exposure start module; 120 - Exposure reference signal generation module; 130 - Exposure timing signal generation module; 111 - Signal delay unit; 112 - Signal inversion unit; 1111 - First NOR gate; 1112 - First D flip-flop; 1121 - NOT gate; 121 - Gating unit; 122 - Counting unit; 123 - Signal generation unit; 1211 - First RS flip-flop; 1212 - AND gate; 1221 - Second NOR gate; 1222 - Second D flip-flop; 1223 - Third D flip-flop; 1231 - Second RS flip-flop; 131 - Clock divider unit; 132 - Resampling unit; 133 - Signal interception unit; 1311 - Fourth D flip-flop; 1321 - Fifth D flip-flop; 1331 - Sixth D flip-flop; 1332 - Seventh D flip-flop; 1333 - Eighth D flip-flop; 1334 - Ninth D flip-flop. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0024] To address the issues of high control complexity and inflexible exposure time control in existing CIS linear array chips, this invention provides an exposure time control circuit and a CIS linear array chip. By integrating the exposure time control circuit within the CIS linear array chip, the exposure timing signal can be generated within the chip, eliminating reliance on external light source switching. During scanner operation, the light source can remain continuously on, unlike the repeated switching operations in traditional structures. This simplifies the control logic at the system level and reduces the requirements for the light source. Furthermore, the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal, and the duration of the high-level range of the exposure reference signal is determined by the chip oscillator clock signal. Therefore, the actual exposure time is controlled by the period of the chip oscillator clock signal. By changing the period of the chip oscillator clock signal, the exposure time can be altered, thereby achieving flexible exposure time control.

[0025] The embodiments of the present invention will now be described in detail.

[0026] Please refer to Figure 2 This is a structural block diagram of an exposure time control circuit 100 provided in an embodiment of the present invention. The exposure time control circuit 100 is integrated into a CIS line array chip and includes an exposure start module 110, an exposure reference signal generation module 120, and an exposure timing signal generation module 130, which are electrically connected in sequence.

[0027] The exposure start module 110 is used to generate an exposure start signal and its corresponding inverted signal based on the received chip master clock signal, chip reset signal and charge transfer signal in the CIS line array chip.

[0028] In this embodiment, the chip reset signal RST is the reset signal of the CIS linear array chip. The chip reset signal RST is a reset signal generated internally by the CIS linear array chip, obtained by delaying the linear array start pulse TR signal. Each cycle of the chip reset signal RST represents one scan cycle. At the beginning of each scan cycle, the chip reset signal RST generates a high pulse, and at the same time performs a reset operation on the exposure start module 110.

[0029] The charge transfer signal TG is the charge transfer timing signal in a CIS linear array chip. Most current mainstream CIS readout circuits employ a scheme where readout and exposure are performed simultaneously to improve scanner efficiency. Therefore, before performing the readout operation, the charge generated by the CIS linear array chip needs to be transferred and stored.

[0030] The chip master clock signal MCK usually comes from an external clock excitation source of the CIS linear array chip. It is mainly used to drive the exposure start module 110 to work. By delaying the charge transfer signal TG, the exposure start signal PRE_EXPO is obtained. The exposure start signal PRE_EXPO is inverted and output to obtain the inverted signal PRE_EXPON.

[0031] In this embodiment, the exposure start signal PRE_EXPO can be understood as a start command before exposure, which represents the start of the exposure process.

[0032] The exposure reference signal generation module 120 is used to generate an exposure reference signal based on the received chip reset signal, exposure start signal, chip oscillator clock signal and inverted signal; the high level duration of the exposure reference signal is determined by the exposure reference signal generation module 120 based on the chip oscillator clock signal.

[0033] In this embodiment, the exposure reference signal generation module 120 receives the chip reset signal RST, the chip oscillator clock signal OSCIN, the exposure start signal PRE_EXPO output by the exposure start module 110, and the corresponding inverted signal PRE_EXPON, and performs a series of logical operations to obtain the exposure reference signal RS2QN.

[0034] The chip oscillator clock signal OSCIN is generated by the oscillator inside the CIS linear array chip, and the exposure start signal PRE_EXPO is driven by the chip master clock signal MCK. Therefore, the generation of the exposure reference signal RS2QN involves two clock signals from different sources. The high-level duration of the exposure reference signal RS2QN is not a fixed value, but will have a small deviation. Therefore, the exposure reference signal RS2QN cannot be directly used as the exposure timing signal and needs further processing.

[0035] The exposure timing signal generation module 130 is used to generate an exposure timing signal based on the received chip reset signal, chip oscillator clock signal and exposure reference signal; the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal.

[0036] In this embodiment, the exposure timing signal generation module 130 mainly receives the chip reset signal RST, the chip oscillator clock signal OSCIN, and the exposure reference signal RS2QN. It then processes the exposure reference signal RS2QN by resampling, delaying, and truncation to eliminate the deviation of the exposure reference signal RS2QN. This allows the middle section of the high-level range of the exposure reference signal RS2QN to be truncated as the high-level range of the exposure timing signal EXPO, ultimately obtaining a stable and fixed-duration on-chip exposure timing signal EXPO.

[0037] In this embodiment, the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal. This can be understood as the rising edge of the high-level range of the exposure timing signal being later than the rising edge of the high-level range of the exposure reference signal, and the falling edge of the high-level range of the exposure timing signal being earlier than the falling edge of the high-level range of the exposure reference signal.

[0038] As can be seen, the exposure time control circuit provided in this embodiment of the invention, being integrated within the CIS linear array chip, enables the generation of the exposure timing signal within the chip, eliminating reliance on the switching control of an external light source. During scanner operation, the light source can remain continuously on, unlike the repeated switching operations in traditional structures. This simplifies the control logic at the system level and reduces the requirements for the light source. Furthermore, the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal, and the duration of the high-level range of the exposure reference signal is determined by the chip oscillator clock signal. Therefore, the actual exposure time is controlled by the period of the chip oscillator clock signal. By changing the period of the chip oscillator clock signal, the exposure time can be altered within a wide range, even covering a span from microseconds to milliseconds, achieving flexible control of the exposure time.

[0039] In one implementation, please refer to Figure 3The exposure start module 110 includes a signal delay unit 111 and a signal inversion unit 112. The signal delay unit 111 and the signal inversion unit 112 are electrically connected. Both the signal delay unit 111 and the signal inversion unit 112 are electrically connected to the exposure reference signal generation module 120.

[0040] The signal delay unit 111 is used to receive the chip master clock signal, the chip reset signal and the charge transfer signal in the CIS line array chip, and delay the charge transfer signal based on the chip master clock signal and the chip reset signal to obtain the exposure start signal; the signal inversion unit 112 is used to invert the received exposure start signal to obtain the inverted signal corresponding to the exposure start signal.

[0041] In one implementation, please refer to Figure 4 The signal delay unit 111 includes a first NOR gate 1111 and multiple cascaded first D flip-flops 1112. The data input terminal D of the first-stage first D flip-flop 1112 is used to receive the charge transfer signal TG. The non-inverting output terminal Q of the previous stage first D flip-flop 1112 is electrically connected to the data input terminal D of the next stage first D flip-flop 1112. The non-inverting output terminal Q of the last stage first D flip-flop 1112 is left floating, and the inverting output terminal QN of the last stage first D flip-flop 1112 is electrically connected to the first input terminal of the first NOR gate 1111. Except for the last stage... The inverted output QN of all first D flip-flops 1112 except the first stage first D flip-flop 1112 is left floating; the non-inverted output Q of the first D flip-flop 1112 preceding the last stage first D flip-flop 1112 is electrically connected to the second input of the first NOR gate 1111; the clock input CK of all first D flip-flops 1112 is used to receive the chip master clock signal MCK, and the reset input R of all first D flip-flops 1112 is used to receive the chip reset signal RST; the output of the first NOR gate 1111 is electrically connected to the signal inversion unit 112.

[0042] In this embodiment, at the beginning of each scan cycle, the chip reset signal RST generates a high pulse, which simultaneously resets the cascaded first D flip-flops 1112. The charge transfer signal TG is processed by the cascaded first D flip-flops 1112 (all driven by the chip main clock signal MCK) and the first NOR gate 1111, which can achieve a certain clock cycle delay, and finally obtain the exposure start signal PRE_EXPO.

[0043] It should be noted that, Figure 4 This example uses three first D flip-flops 1112 as an example. In actual applications, the number of first D flip-flops 1112 can be set as needed, and this embodiment does not limit this.

[0044] In one implementation, continue to refer to Figure 4The signal inversion unit 112 includes an NOT gate 1121. The input terminal of the NOT gate 1121 is electrically connected to the signal delay unit 111, and the output terminal of the NOT gate 1121 is electrically connected to the exposure reference signal generation module 120.

[0045] In this embodiment, NOT gate 1121 is also an inverter. Specifically, the input terminal of NOT gate 1121 is electrically connected to the output terminal of the first NOR gate 1111. The exposure start signal PRE_EXPO output by the first NOR gate 1111 can generate the corresponding inverted signal PRE_EXPON after passing through NOT gate 1121.

[0046] In one implementation, please refer to Figure 5 The exposure reference signal generation module 120 includes a gating unit 121, a counting unit 122, and a signal generation unit 123. The gating unit 121, the counting unit 122, and the signal generation unit 123 are electrically connected in sequence. The gating unit 121, the counting unit 122, and the signal generation unit 123 are all electrically connected to the exposure start module 110. The signal generation unit 123 is also electrically connected to the exposure timing signal generation module 130.

[0047] The gating unit 121 is used to receive the chip reset signal, the exposure start signal and the chip oscillator clock signal, and determine whether to allow the chip oscillator clock signal to pass based on the chip reset signal and the exposure start signal, so as to obtain the gating clock signal.

[0048] In this embodiment, the gating unit 121 is specifically electrically connected to the signal delay unit 111 in the exposure start module 110 to receive the exposure start signal PRE_EXPO output by the signal delay unit 111. The gating unit 121 determines whether to allow the chip oscillator clock signal OSCIN to pass based on the chip reset signal RST and the exposure start signal PRE_EXPO, and then outputs the gating clock signal TRIG_OSC to the counting unit 122.

[0049] In one implementation, please refer to Figure 6The gating unit 121 includes a first RS flip-flop 1211 and an AND gate 1212. The reset input R of the first RS flip-flop 1211 is used to receive the chip reset signal RST. The set input S of the first RS flip-flop 1211 is electrically connected to the output of the first NOR gate 1111 and is used to receive the exposure start signal PRE_EXPO output by the output of the first NOR gate 1111. The non-inverting output Q of the first RS flip-flop 1211 is electrically connected to the first input of the AND gate 1212. The inverting output QN of the first RS flip-flop 1211 is left floating. The second input of the AND gate 1212 is used to receive the chip oscillator clock signal OSCIN. The AND gate 1212 is used to output the gating clock signal TRIG_OSC based on the signal RS1Q output by the non-inverting output Q of the first RS flip-flop 1211 and the chip oscillator clock signal OSCIN.

[0050] In other words, the reset input R of the first RS flip-flop 1211 receives the chip reset signal RST, and the set input S receives the exposure start signal PRE_EXPO. When the pulse of the chip reset signal RST arrives, the signal RS1Q output from the non-inverting output Q of the first RS flip-flop 1211 changes from high to low. When the pulse of the exposure start signal PRE_EXPO arrives, RS1Q changes from low to high. RS1Q is sent to AND gate 1212, acting as a gate for the chip oscillator clock signal OSCIN. When RS1Q is high, OSCIN is allowed to pass, providing clock drive for subsequent circuit units; when RS1Q is low, OSCIN cannot be propagated, and the signal output by AND gate 1212 is low, preventing the subsequent circuit units from functioning properly. Thus, AND gate 1212 can output the gated clock signal TRIG_OSC.

[0051] The counting unit 122 is used to receive the exposure start signal, the inverted signal, and the gated clock signal. It counts the gated clock signal based on the exposure start signal and the inverted signal. When the count value reaches the preset value, it outputs a high level to obtain a counting pulse signal.

[0052] In this embodiment, the counting unit 122 is electrically connected to the signal delay unit 111 and the signal inversion unit 112 in the exposure start module 110, so as to receive the exposure start signal PRE_EXPO output by the signal delay unit 111 and the inverted signal PRE_EXPON output by the signal inversion unit 112. The counting unit 122 mainly counts the gated clock signal TRIG_OSC. When the count value reaches the preset value, it will output a high level, thereby obtaining the counting pulse signal COUNT.

[0053] In one implementation, please continue to refer to Figure 6The counting unit 122 may include a second NOR gate 1221, a second D flip-flop 1222, and multiple cascaded third D flip-flops 1223. The inverted output terminal QN of all the third D flip-flops 1223 is electrically connected to the data input terminal D. The clock input terminal CK of the first-stage third D flip-flop 1223 is electrically connected to the output terminal of the AND gate 1212 to receive the gated clock signal TRIG_OSC output by the output terminal of the AND gate 1212. The set input terminal SN of the second D flip-flop 1222 and the set input terminals SN of the remaining third D flip-flops 1223 except for the last stage third D flip-flop 1223 are all electrically connected to the NOT gate 1121 to receive the inverted signal PRE_EXPON output by the NOT gate 1121.

[0054] Except for the last stage third D flip-flop 1223, the clock input CK of the next stage third D flip-flop 1223 is electrically connected to the non-inverting output Q of the previous stage third D flip-flop 1223; the clock input CK of the last stage third D flip-flop 1223 is electrically connected to the inverting output QN of the corresponding previous stage third D flip-flop 1223; and the reset input R of the last stage third D flip-flop 1223 is electrically connected to the output of the first NOR gate 1111, for receiving the output of the first NOR gate 1111. The exposure start signal PRE_EXPO is output from the output terminal of 11. The non-inverting output terminal Q of the last stage third D flip-flop 1223 is electrically connected to the first input terminal of the second NOR gate 1221. The inverting output terminal QN of the previous stage third D flip-flop 1223 is also electrically connected to the second input terminal of the second NOR gate 1221. The non-inverting output terminal Q of the previous stage third D flip-flop 1223 is electrically connected to the data input terminal D of the second D flip-flop 1222.

[0055] The clock input terminal CK of the second D flip-flop 1222 is electrically connected to the output terminal of the AND gate 1212 to receive the gated clock signal TRIG_OSC output by the output terminal of the AND gate 1212. The non-inverting output terminal Q of the second D flip-flop 1222 is electrically connected to the third input terminal of the second NOR gate 1221. The inverting output terminal QN of the second D flip-flop 1222 is left floating. The output terminal of the second NOR gate 1221 is electrically connected to the signal generation unit 123.

[0056] The second NOR gate 1221 is used to output a counting pulse signal based on the signal output by the non-inverting output Q of the last stage third D flip-flop 1223, the signal output by the inverting output QN of the previous stage third D flip-flop 1223, and the signal output by the non-inverting output Q of the second D flip-flop 1222.

[0057] Understandable, Figure 6In the circuit structure of the counting unit 122 shown, the clock input terminal CK of the first-stage third D flip-flop 1223 receives the gated clock signal TRIG_OSC, that is, the gated clock signal TRIG_OSC acts as the clock input to the first-stage third D flip-flop 1223. The non-inverting output terminal Q is connected to the clock input terminal CK of the second-stage third D flip-flop 1223. The set input terminal SN receives PRE_EXPON. The data input terminal D is connected to its own inverting output terminal QN, so as to divide TRIG_OSC by two, that is, the output frequency of the non-inverting output terminal Q of the first-stage third D flip-flop 1223 is half of TRIG_OSC.

[0058] The non-inverting output Q of the second-stage third-stage D flip-flop 1223 is connected to the clock input CK of the third-stage third-stage D flip-flop 1223, and the set input SN receives PRE_EXPON. The second-stage third-stage D flip-flop 1223 is driven by the output signal of the non-inverting output Q of the first-stage third-stage D flip-flop 1223, and the data input D is connected to its own inverting output QN. Therefore, it can divide the divided-by-two signal output by the non-inverting output Q of the first-stage third-stage D flip-flop 1223 by two, which is equivalent to dividing TRIG_OSC by four. Therefore, the output frequency of the non-inverting output Q of the second-stage third-stage D flip-flop 1223 is one-quarter of TRIG_OSC.

[0059] The inverted output QN of the third-stage third D flip-flop 1223 is connected to the clock input CK of the fourth-stage third D flip-flop 1223 and the second NOR gate 1221. The non-inverted output Q is connected to the data input D of the second D flip-flop 1222. The set input SN receives PRE_EXPON. The third-stage third D flip-flop 1223 is driven by the output signal of the non-inverted output Q of the second-stage third D flip-flop 1223, and the data input D is connected to its own inverted output QN. Therefore, it can divide the frequency by four of the frequency output Q of the second-stage third D flip-flop 1223 by two, which is equivalent to dividing TRIG_OSC by eight. Therefore, the output frequency of the non-inverted output Q of the third-stage third D flip-flop 1223 is one-eighth of TRIG_OSC.

[0060] The non-inverting output Q of the fourth-stage third D flip-flop 1223 is connected to the second NOR gate 1221, and the reset input R receives PRE_EXPO. The fourth-stage third D flip-flop 1223 is driven by the output signal of the inverting output QN of the third-stage third D flip-flop 1223, and the data input D is connected to its own inverting output QN. Therefore, it can divide the signal output by QN of the third-stage third D flip-flop 1223 by two. The signal output by QN of the third-stage third D flip-flop 1223 is inverted by the divided-by-eight signal output by Q of the third-stage third D flip-flop 1223. Therefore, the output frequency of Q of the fourth-stage third D flip-flop 1223 is one-sixteenth of TRIG_OSC.

[0061] The clock input CK of the second D flip-flop 1222 receives the gated clock signal TRIG_OSC, the inverted output QN is left floating, the non-inverted output Q is connected to the second NOR gate 1221, and the data input D receives the output signal of the non-inverted output Q of the third stage third D flip-flop 1223. Its main function is to delay the signal output by the non-inverted output Q of the third stage third D flip-flop 1223 by one TRIG_OSC clock cycle.

[0062] In this embodiment, the counting unit 122 is mainly composed of a second NOR gate 1221, a second D flip-flop 1222, and multiple cascaded third D flip-flops 1223. During the counting process, the gate clock signal TRIG_OSC drives the counting unit 122 to flip. Only when the signal output by the inverted output terminal QN of the third-stage third D flip-flop 1223 (which is inverted from the divided-eight signal output by the third-stage third D flip-flop 1223), the signal output by the non-inverted output terminal Q of the second D flip-flop 1222 (which is obtained by delaying the divided-eight signal output by the third-stage third D flip-flop 1223 by one TRIG_OSC clock cycle), and the signal output by the non-inverted output terminal Q of the fourth-stage third D flip-flop 1223 (which is obtained by dividing the signal output by the inverted output terminal QN of the third-stage third D flip-flop 1223 by two) are all low, the second NOR gate 1221 will output a high level, indicating that the count value has reached the preset value. As long as RS1Q remains high, the counting unit 122 will continue to count and periodically output a high level, thereby obtaining the counting pulse signal COUNT.

[0063] It should be noted that, Figure 6 This example uses only one second D flip-flop 1222 and four third D flip-flops 1223. In actual applications, the number of third D flip-flops 1223 can be set as needed, and this embodiment does not limit this.

[0064] The signal generation unit 123 is used to receive the counting pulse signal and the exposure start signal, and generate an exposure reference signal based on the counting pulse signal and the exposure start signal; wherein, the exposure reference signal changes from low level to high level when the rising edge of the exposure start signal arrives, and changes from high level to low level when the rising edge of the counting pulse signal arrives.

[0065] In this embodiment, the signal generation unit 123 is electrically connected to the signal delay unit 111 in the exposure start module 110 so as to receive the exposure start signal PRE_EXPO output by the signal delay unit 111. The signal generation unit 123 generates an exposure reference signal RS2QN with controllable high-level pulse width based on the received counting pulse signal COUNT and the exposure start signal PRE_EXPO.

[0066] In one implementation, please continue to refer to Figure 6 The signal generation unit 123 includes a second RS flip-flop 1231. The set input S of the second RS flip-flop 1231 is electrically connected to the counting unit 122. The reset input R of the second RS flip-flop 1231 is electrically connected to the output of the first NOR gate 1111, and is used to receive the exposure start signal PRE_EXPO output by the output of the first NOR gate 1111. The non-inverting output Q of the second RS flip-flop 1231 is left floating. The inverting output QN of the second RS flip-flop 1231 is electrically connected to the exposure timing signal generation module 130.

[0067] In this embodiment, the set input S of the second RS flip-flop 1231 receives the counting pulse signal COUNT, and the reset input R receives the exposure start signal PRE_EXPO. When the rising edge of PRE_EXPO arrives, the output signal of the inverted output QN of the second RS flip-flop 1231 changes from low to high. After a period of time, when the rising edge of COUNT arrives, the output signal of the inverted output QN of the second RS flip-flop 1231 changes from high to low. Although the COUNT signal will continue to pulse, the PRE_EXPO pulse only appears once at the beginning of each exposure cycle. Therefore, the final generated exposure reference signal RS2QN also only appears once in each exposure cycle. Thus, the exposure reference signal RS2QN with a controllable high-level pulse width can be obtained at the inverted output QN of the second RS flip-flop 1231. The duration of the high level of the exposure reference signal RS2QN is controlled by the counting unit 122, which is driven by the chip oscillator clock signal OSCIN. Therefore, the duration of the high level of the exposure reference signal RS2QN is determined by the clock period of the chip oscillator clock signal OSCIN.

[0068] It should be noted that although the high-level duration of the exposure reference signal RS2QN can be controlled by the chip oscillator clock signal OSCIN, RS2QN cannot be directly used as the exposure timing signal. This is because the high-level duration of RS2QN is not a fixed value but will have a slight deviation. The exposure reference signal RS2QN has two sources: the exposure start signal PRE_EXPO and the counting pulse signal COUNT. As analyzed above, the exposure start signal PRE_EXPO is driven by the chip's main clock signal MCK, while the counting pulse signal COUNT is driven by the chip oscillator clock signal OSCIN. The chip's main clock signal MCK usually comes from an external clock source, while the chip oscillator clock signal OSCIN is generated by an internal oscillator. Since these two clock signals are from different sources, the final generated exposure reference signal RS2QN will have a deviation. To obtain an exposure timing signal of a fixed duration, further processing of the exposure reference signal RS2QN is required.

[0069] In one implementation, please refer to Figure 7 The exposure timing signal generation module 130 includes a clock division unit 131, a resampling unit 132, and a signal interception unit 133. The clock division unit 131 is electrically connected to the resampling unit 132 and the signal interception unit 133. The resampling unit 132 is electrically connected to the exposure reference signal generation module 120 and the signal interception unit 133.

[0070] The clock division unit 131 is used to divide the received chip oscillator clock signal OSCIN according to the received chip reset signal RST to obtain a divided clock signal; the resampling unit 132 is used to resample the received exposure reference signal RS2QN according to the received chip reset signal RST and the divided clock signal to obtain a sampled signal; the signal interception unit 133 is used to generate an exposure timing signal EXPO according to the received divided clock signal and the sampled signal.

[0071] In this embodiment, the clock division unit 131 mainly divides the received chip oscillator clock signal OSCIN to generate a divided clock signal, which is then supplied to the subsequent resampling unit 132 and signal extraction unit 133, thereby providing a stable clock signal for the subsequent circuits. The resampling unit 132 resamples the exposure reference signal RS2QN using the divided clock signal, which can eliminate the interference introduced by the chip master clock signal MCK. Based on the received divided clock signal and the sampled signal, the signal extraction unit 133 performs signal delay, pulse width truncation, and other processing to finally extract a segment from the high-level range of the exposure reference signal RS2QN as the exposure timing signal EXPO and output it.

[0072] In one implementation, please refer to Figure 8 The clock divider unit 131 includes a fourth D flip-flop 1311, the resampling unit 132 includes a fifth D flip-flop 1321, and the signal interception unit 133 includes a sixth D flip-flop 1331, a seventh D flip-flop 1332, an eighth D flip-flop 1333, and a ninth D flip-flop 1334.

[0073] The clock input terminal CK of the fourth D flip-flop 1311 is used to receive the chip oscillator clock signal OSCIN. The data input terminal D of the fourth D flip-flop 1311 is electrically connected to the inverted output terminal QN. The reset input terminal R of the fourth D flip-flop 1311 is used to receive the chip reset signal RST. The non-inverted output terminal Q of the fourth D flip-flop 1311 is electrically connected to the clock input terminals CK of the fifth D flip-flop 1321, the sixth D flip-flop 1331, and the seventh D flip-flop 1332.

[0074] It can be understood that the fourth D flip-flop 1311 divides the input chip oscillator clock signal OSCIN by two to generate a divided clock signal that supplies the clock input CK of the fifth D flip-flop 1321, the clock input CK of the sixth D flip-flop 1331, and the clock input CK of the seventh D flip-flop 1332.

[0075] The data input terminal D of the fifth D flip-flop 1321 is electrically connected to the exposure reference signal generation module 120. The reset input terminal R of the fifth D flip-flop 1321 is used to receive the chip reset signal RST. The non-inverting output terminal Q of the fifth D flip-flop 1321 is left floating. The inverting output terminal QN of the fifth D flip-flop 1321 is electrically connected to the reset input terminals R of the sixth D flip-flop 1331, the seventh D flip-flop 1332, the eighth D flip-flop 1333, and the ninth D flip-flop 1334.

[0076] It can be understood that the data input terminal D of the fifth D flip-flop 1321 receives the exposure reference signal RS2QN output by the second RS flip-flop 1231, the clock input terminal CK receives the frequency-divided clock signal output by the fourth D flip-flop 1311, and the reset input terminal R receives the chip reset signal RST. By resampling the exposure reference signal RS2QN with the frequency-divided clock signal, the deviation introduced by different source clocks (MCK and OSCIN) is eliminated. That is to say, the fifth D flip-flop 1321 obtains the sampled signal by delaying the exposure reference signal RS2QN by one clock cycle based on the frequency-divided clock signal and then inverting it. The sampled signal output by the inverted output terminal QN of the fifth D flip-flop 1321 is used to reset the sixth D flip-flop 1331, the seventh D flip-flop 1332, the eighth D flip-flop 1333, and the ninth D flip-flop 1334 in the subsequent stage. In other words, the sixth D flip-flop 1331, the seventh D flip-flop 1332, the eighth D flip-flop 1333, and the ninth D flip-flop 1334 will only work normally (i.e., be able to respond to the clock and input, and perform frequency division, delay, and other operations) when the sampling signal is low; while when the sampling signal is high, the outputs of the sixth D flip-flop 1331, the seventh D flip-flop 1332, the eighth D flip-flop 1333, and the ninth D flip-flop 1334 will be reset to low level.

[0077] The data input terminal D of the sixth D flip-flop 1331 is electrically connected to the inverted output terminal QN, and the non-inverted output terminal Q of the sixth D flip-flop 1331 is electrically connected to the data input terminal D of the seventh D flip-flop 1332. The inverted output terminal QN of the seventh D flip-flop 1332 is left floating, and the non-inverted output terminal Q of the seventh D flip-flop 1332 is electrically connected to the clock input terminal CK of the eighth D flip-flop 1333. The data input terminal D of the eighth D flip-flop 1333 is electrically connected to the inverted output terminal QN, and the non-inverted output terminal Q of the eighth D flip-flop 1333 is electrically connected to the clock input terminal CK of the ninth D flip-flop 1334. The data input terminal D of the ninth D flip-flop 1334 is electrically connected to the inverted output terminal QN, and the non-inverted output terminal Q of the ninth D flip-flop 1334 is used to output the exposure timing signal EXPO.

[0078] It can be understood that the sixth D flip-flop 1331 divides the frequency-divided clock signal received at the clock input CK by two, while the seventh D flip-flop 1332 delays the signal output from the non-inverting output Q of the sixth D flip-flop 1331 by one clock cycle based on the received frequency-divided clock signal. The eighth D flip-flop 1333 divides the signal output from the non-inverting output Q of the seventh D flip-flop 1332 by two, and the ninth D flip-flop 1334 divides the signal output from the non-inverting output Q of the eighth D flip-flop 1333 by two. Finally, the exposure timing signal EXPO is output at the non-inverting output Q of the ninth D flip-flop 1334. Specifically, when the sampling signal output by the inverting output terminal QN of the fifth D flip-flop 1321 is low, the sixth D flip-flop 1331, the seventh D flip-flop 1332, the eighth D flip-flop 1333, and the ninth D flip-flop 1334 sequentially perform frequency division, delay, frequency division, and frequency division operations. When the rising edge of the signal output by the non-inverting output terminal Q of the eighth D flip-flop 1333 arrives, the non-inverting output terminal Q of the ninth D flip-flop 1334 flips from low to high at that rising edge, forming the rising edge of the exposure timing signal EXPO. The ninth D flip-flop 1334 continues to wait for the next rising edge of the signal input by its clock input terminal CK (the signal output by the non-inverting output terminal Q of the eighth D flip-flop 1333). When the next rising edge arrives, the non-inverting output terminal Q of the ninth D flip-flop 1334 flips again, changing from high to low, forming the falling edge of the exposure timing signal EXPO.

[0079] As can be seen, the exposure timing signal generation module 130 mainly implements the functions of frequency division and delay. By extracting the middle part of the exposure reference signal RS2QN when it is at a high level, the exposure timing signal EXPO is finally obtained.

[0080] To facilitate understanding of the working principle of the exposure time control circuit 100 described above, embodiments of the present invention also provide... Figure 9 The timing diagram of the exposure time control circuit 100 shown here mainly illustrates the timing relationship of some key signals in the exposure time control circuit 100, including the chip reset signal RST, the charge transfer signal TG, the exposure start signal PRE_EXPO, the signal RS1Q output from the non-inverting output terminal Q of the first RS flip-flop 1211, the counting pulse signal COUNT, the exposure reference signal RS2QN, and the exposure timing signal EXPO.

[0081] like Figure 9 As shown, at the beginning of each scan cycle, the chip reset signal RST generates a high pulse, and at the same time performs a reset operation on the exposure start module 110; the charge transfer signal TG is delayed by the exposure start module 110 for a certain clock cycle to obtain the exposure start signal PRE_EXPO.

[0082] After the chip reset signal RST and the exposure start signal PRE_EXPO are processed by the logic of the first RS flip-flop 1211, the non-inverting output terminal Q of the first RS flip-flop 1211 outputs the signal RS1Q. When the rising edge of the chip reset signal RST arrives, RS1Q changes from high level to low level, and when the rising edge of the exposure start signal PRE_EXPO arrives, RS1Q changes from low level to high level.

[0083] The counting pulse signal COUNT is generated by the second NOR gate 1221 in counting unit 122 based on the signal output from the inverted output QN of the third-stage third D flip-flop 1223, the signal output from the non-inverted output Q of the second D flip-flop 1222, and the signal output from the non-inverted output Q of the fourth-stage third D flip-flop 1223. The second NOR gate 1221 outputs a high level only when all three are simultaneously low. The counting unit 122 is driven by the gate clock signal TRIG_OSC. As long as RS1Q remains high, the gate clock signal TRIG_OSC will remain, thus allowing the counting unit 122 to periodically output a high level, thereby obtaining the counting pulse signal COUNT. Figure 9 As can be seen, the pulse of the counting pulse signal COUNT appears during the high-level duration of RS1Q.

[0084] After the counting pulse signal COUNT and the exposure start signal PRE_EXPO are processed by the second RS flip-flop 1231, the exposure reference signal RS2QN is output at the inverted output terminal QN of the second RS flip-flop 1231. Specifically, when the rising edge of PRE_EXPO arrives, RS2QN changes from low to high; after a period of time, when the rising edge of COUNT arrives, RS2QN changes from high to low. Figure 9 As can be seen, the exposure reference signal RS2QN also appears only once in each exposure cycle (i.e., each cycle of PRE_EXPO).

[0085] The exposure timing signal EXPO is generated when the exposure reference signal RS2QN is at a high level. Through frequency division and delay processing by the exposure timing signal generation module 130, the middle portion of the high-level range of the exposure reference signal RS2QN is extracted, ultimately yielding the exposure timing signal EXPO. Figure 9As can be seen, the rising edge of the high-level interval of the exposure timing signal EXPO is later than the rising edge of the high-level interval of the exposure reference signal RS2QN, and the falling edge of the high-level interval of the exposure timing signal EXPO is earlier than the falling edge of the high-level interval of the exposure reference signal RS2QN. For example, assuming that the high-level duration of the exposure reference signal RS2QN is 16 clock cycles, through the frequency division and delay processing of the exposure timing signal generation module 130, the rising edge of the exposure reference signal RS2QN can be delayed by 4 clock cycles to obtain the rising edge of the exposure timing signal EXPO, and the falling edge of the exposure reference signal RS2QN can be advanced by 4 clock cycles to obtain the falling edge of the exposure timing signal EXPO. Then, the high-level interval of the exposure timing signal EXPO is the middle 8 relatively stable clock cycles extracted from the high-level interval of the exposure reference signal RS2QN.

[0086] As can be seen, the exposure time control circuit 100 integrated within the CIS linear array chip provided in this embodiment of the invention utilizes the chip oscillator clock signal OSCIN generated by the oscillator within the CIS linear array chip, in conjunction with key timing signals (such as charge transfer signal TG) within the CIS linear array chip. After processing by a series of logic circuits such as counters and flip-flops, a definable exposure timing signal EXPO is finally obtained. Because it is integrated within the CIS linear array chip, the exposure timing signal can be generated within the chip, eliminating the need for external light source switching control. During scanner operation, the light source can remain continuously on, instead of the repeated switching operations of the light source as in traditional structures. This simplifies the control logic at the system level and reduces the requirements for the light source. In addition, the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal, and the duration of the high-level range of the exposure reference signal is determined by the chip oscillator clock signal. Therefore, the exposure time is actually controlled by the period of the chip oscillator clock signal. By changing the period of the chip oscillator clock signal, the exposure time can be changed, and it can be adjusted within a wide range, even covering a range from microseconds to milliseconds, thus achieving flexible control of the exposure time.

[0087] Optionally, embodiments of the present invention also provide a CIS line array chip, which includes the exposure time control circuit 100 provided in the above embodiments.

[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An exposure time control circuit, characterized in that, Integrated within a CIS line array chip, the exposure time control circuit includes an exposure start-up module, an exposure reference signal generation module, and an exposure timing signal generation module, which are electrically connected in sequence. The exposure start module is used to generate an exposure start signal and its corresponding inverted signal based on the received chip master clock signal, chip reset signal and charge transfer signal in the CIS line array chip; The exposure reference signal generation module is used to generate an exposure reference signal based on the received chip reset signal, exposure start signal, chip oscillator clock signal, and inverted signal; the high-level duration of the exposure reference signal is determined by the exposure reference signal generation module based on the chip oscillator clock signal; The exposure timing signal generation module is used to generate an exposure timing signal based on the received chip reset signal, chip oscillator clock signal and exposure reference signal; the high-level range of the exposure timing signal is extracted from the high-level range of the exposure reference signal.

2. The exposure time control circuit according to claim 1, characterized in that, The exposure start-up module includes a signal delay unit and a signal inversion unit, which are electrically connected. Both the signal delay unit and the signal inversion unit are electrically connected to the exposure reference signal generation module. The signal delay unit is used to receive the chip master clock signal, the chip reset signal, and the charge transfer signal in the CIS line array chip, and delays the charge transfer signal based on the chip master clock signal and the chip reset signal to obtain the exposure start signal; The signal inversion unit is used to invert the received exposure start signal to obtain the inverted signal corresponding to the exposure start signal.

3. The exposure time control circuit according to claim 2, characterized in that, The signal delay unit includes a first NOR gate and multiple cascaded first D flip-flops. The data input terminal of the first-stage first D flip-flop is used to receive the charge transfer signal. The non-inverting output terminal of the previous stage first D flip-flop is electrically connected to the data input terminal of the next stage first D flip-flop. The non-inverting output terminal of the last stage first D flip-flop is left floating. The inverting output terminal of the last stage first D flip-flop is electrically connected to the first input terminal of the first NOR gate. The inverting output terminals of the remaining first D flip-flops, except for the last stage first D flip-flop, are left floating. The non-inverting output of the first D flip-flop preceding the last stage is electrically connected to the second input of the first NOR gate. The clock input terminals of all first D flip-flops are used to receive the chip's main clock signal, and the reset input terminals of all first D flip-flops are used to receive the chip's reset signal; the output terminal of the first NOR gate is electrically connected to the signal inverting unit.

4. The exposure time control circuit according to claim 1, characterized in that, The exposure reference signal generation module includes a gating unit, a counting unit, and a signal generation unit. The gating unit, the counting unit, and the signal generation unit are electrically connected in sequence. The gating unit, the counting unit, and the signal generation unit are all electrically connected to the exposure start module. The signal generation unit is also electrically connected to the exposure timing signal generation module. The gating unit is used to receive the chip reset signal, the exposure start signal, and the chip oscillator clock signal, and determines whether to allow the chip oscillator clock signal to pass based on the chip reset signal and the exposure start signal, thereby obtaining a gating clock signal; The counting unit is used to receive the exposure start signal, the inverted signal, and the gated clock signal, and counts the gated clock signal based on the exposure start signal and the inverted signal. When the count value reaches a preset value, it outputs a high level to obtain a counting pulse signal. The signal generation unit is used to receive the counting pulse signal and the exposure start signal, and generate an exposure reference signal based on the counting pulse signal and the exposure start signal; wherein, the exposure reference signal changes from low level to high level when the rising edge of the exposure start signal arrives, and changes from high level to low level when the rising edge of the counting pulse signal arrives.

5. The exposure time control circuit according to claim 4, characterized in that, The gating unit includes a first RS flip-flop and an AND gate. The reset input of the first RS flip-flop is used to receive the chip reset signal, the set input of the first RS flip-flop is used to receive the exposure start signal, the non-inverting output of the first RS flip-flop is electrically connected to the first input of the AND gate, and the inverting output of the first RS flip-flop is left floating. The second input of the AND gate is used to receive the chip oscillator clock signal. The AND gate is used to output the gated clock signal based on the signal output from the non-inverting output terminal of the first RS flip-flop and the clock signal of the chip oscillator.

6. The exposure time control circuit according to claim 4, characterized in that, The counting unit includes a second NOR gate, a second D flip-flop, and multiple cascaded third D flip-flops. The inverted output terminals of all the third D flip-flops are electrically connected to the data input terminals. The clock input terminal of the first-stage third D flip-flop is used to receive the gated clock signal. The set input terminal of the second D flip-flop and the set input terminals of the remaining third D flip-flops except for the last stage are all used to receive the inverted signal. In the remaining third D flip-flops except for the last stage, the clock input of the next stage third D flip-flop is electrically connected to the non-inverting output of the previous stage third D flip-flop; the clock input of the last stage third D flip-flop is electrically connected to the inverting output of the corresponding previous stage third D flip-flop; the reset input of the last stage third D flip-flop is used to receive the exposure start signal; the non-inverting output of the last stage third D flip-flop is electrically connected to the first input of the second NOR gate; the inverting output of the stage preceding the last stage third D flip-flop is also electrically connected to the second input of the second NOR gate; and the non-inverting output of the stage preceding the last stage third D flip-flop is electrically connected to the data input of the second D flip-flop. The clock input of the second D flip-flop is used to receive the gated clock signal; the non-inverting output of the second D flip-flop is electrically connected to the third input of the second NOR gate; the inverting output of the second D flip-flop is left floating; and the output of the second NOR gate is electrically connected to the signal generation unit. The second NOR gate is used to output the counting pulse signal based on the signal output from the non-inverting output terminal of the last stage third D flip-flop, the signal output from the inverting output terminal of the stage preceding the last stage third D flip-flop, and the signal output from the non-inverting output terminal of the second D flip-flop.

7. The exposure time control circuit according to claim 4, characterized in that, The signal generation unit includes a second RS flip-flop. The set input of the second RS flip-flop is electrically connected to the counting unit. The reset input of the second RS flip-flop is used to receive the exposure start signal. The non-inverting output of the second RS flip-flop is left floating. The inverting output of the second RS flip-flop is electrically connected to the exposure timing signal generation module.

8. The exposure time control circuit according to claim 1, characterized in that, The exposure timing signal generation module includes a clock division unit, a resampling unit, and a signal truncation unit. The clock division unit is electrically connected to the resampling unit and the signal truncation unit. The resampling unit is electrically connected to the exposure reference signal generation module and the signal truncation unit. The clock division unit is used to divide the received chip oscillator clock signal according to the received chip reset signal to obtain a divided clock signal; The resampling unit is used to resample the received exposure reference signal according to the received chip reset signal and the frequency division clock signal to obtain a sampled signal; The signal interception unit is used to generate an exposure timing signal based on the received frequency division clock signal and the sampling signal.

9. The exposure time control circuit according to claim 8, characterized in that, The clock division unit includes a fourth D flip-flop, the resampling unit includes a fifth D flip-flop, and the signal truncation unit includes a sixth, a seventh, an eighth, and a ninth D flip-flop. The clock input terminal of the fourth D flip-flop is used to receive the clock signal of the chip oscillator. The data input terminal of the fourth D flip-flop is electrically connected to the inverting output terminal. The reset input terminal of the fourth D flip-flop is used to receive the chip reset signal. The non-inverting output terminal of the fourth D flip-flop is electrically connected to the clock input terminals of the fifth D flip-flop, the sixth D flip-flop, and the seventh D flip-flop. The data input terminal of the fifth D flip-flop is electrically connected to the exposure reference signal generation module. The reset input terminal of the fifth D flip-flop is used to receive the chip reset signal. The non-inverting output terminal of the fifth D flip-flop is floating. The inverting output terminal of the fifth D flip-flop is electrically connected to the reset input terminals of the sixth D flip-flop, the seventh D flip-flop, the eighth D flip-flop, and the ninth D flip-flop. The data input terminal of the sixth D flip-flop is electrically connected to the inverting output terminal, and the non-inverting output terminal of the sixth D flip-flop is electrically connected to the data input terminal of the seventh D flip-flop. The inverting output terminal of the seventh D flip-flop is left floating, and the non-inverting output terminal of the seventh D flip-flop is electrically connected to the clock input terminal of the eighth D flip-flop. The data input terminal of the eighth D flip-flop is electrically connected to the inverting output terminal, and the non-inverting output terminal of the eighth D flip-flop is electrically connected to the clock input terminal of the ninth D flip-flop. The data input terminal of the ninth D flip-flop is electrically connected to the inverting output terminal, and the non-inverting output terminal of the ninth D flip-flop is used to output the exposure timing signal.

10. A CIS linear array chip, characterized in that, The circuit includes the exposure time control circuit according to any one of claims 1-9.

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