Hardware supplements for interplanetary communication systems

Abstract

This invention discloses a hardware supplementation method and system for an interplanetary communication system, relating to the field of aerospace communication technology. The invention switches transmission channels between laser and radio frequency links according to preset priority rules, attempts multiple alternative protocol versions in parallel when receiving ground signals, employs a gradual, phase-transition-free clock source switching method, and actively extends the generation cycle of low-priority data when the buffer occupancy rate continuously exceeds a threshold and the link quality falls below the threshold. All processes in this invention are automatically executed by pure hardware circuitry, requiring no software or central processing unit intervention, thus improving the reliability and adaptability of the interplanetary communication system and solving the technical problems of susceptibility to interference and low reliability inherent in existing software-implemented communication control mechanisms.

Description

Technical Field

[0001] This invention relates to the field of aerospace communication technology, and in particular to a hardware supplementation method and system for an interplanetary communication system. Background Technology

[0002] In interplanetary communication scenarios, communication systems need to cope with extreme conditions such as ultra-long transmission distances, dynamic changes in link status, strong space radiation interference, and high difficulty in ground maintenance. Most existing interplanetary communication systems employ software-based control mechanisms, using a central processing unit to run programs for link switching, protocol adaptation, clock synchronization, and flow control to ensure the normal operation of the communication system.

[0003] However, the software-implemented communication control mechanism has the following drawbacks: First, the software operation relies on a central processing unit and an operating system, making it susceptible to factors such as cosmic rays and space electromagnetic interference, which can cause the communication control mechanism to fail and lead to communication interruptions. Second, the software's serial execution has a large response delay, making it difficult to quickly adapt to the dynamic changes of interplanetary links, and it is prone to problems such as data congestion and transmission interruptions. Finally, the software control mechanism requires the central processing unit to run continuously, resulting in high power consumption, which is not suitable for deep space exploration spacecraft with limited energy.

[0004] Therefore, those skilled in the art are dedicated to developing a purely hardware-based supplementary mechanism for interplanetary communication systems to address the aforementioned problems in the prior art. Summary of the Invention

[0005] 1. Technical problems to be solved The purpose of this invention is to overcome the shortcomings of the prior art and provide a hardware supplementation method and system for interplanetary communication systems. The entire process is executed through pure hardware circuitry, without a central processing unit, instruction execution, or software code operation. This solves the problems of existing interplanetary communication systems, such as susceptibility to interference, low reliability, large response delay, and high power consumption, thereby improving the operational stability and environmental adaptability of interplanetary communication systems in extreme environments.

[0006] 1. Technical Solution To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a hardware supplementation method for an interplanetary communication system, comprising the following steps: The transmission channel is switched between the laser link and the radio frequency link according to a preset priority rule; When receiving ground signals, multiple alternative protocol versions are tried in parallel. The clock source switching uses a gradual transition without phase jumps; When the cache utilization rate continuously exceeds the threshold and the link quality is lower than the threshold, the generation cycle of low-priority data is proactively extended.

[0007] Furthermore, all processes are executed automatically and continuously by pure hardware circuits without manual intervention. They run continuously after power-on without software intervention or central processing unit participation. The switching of transmission channels between the laser link and the radio frequency link according to preset priority rules follows the following preset priority rules: laser priority, radio frequency backup, dual-link collaboration, and recovery hysteresis.

[0008] Furthermore, the method also includes: replacing the Transmission Control Protocol / Internet Protocol with a delay-tolerant network protocol, and the packet header includes a source node identifier, a destination node identifier, a generation timestamp, a time to live, a hop count counter, and a priority field.

[0009] Furthermore, the method also includes: performing end-to-end digital signature verification on each data packet, maintaining hop-by-hop reputation values ​​of adjacent nodes, and prioritizing forwarding data packets sent by nodes with higher reputation values.

[0010] Furthermore, when receiving ground signals, multiple alternative protocol versions are tried in parallel, using a parallel frame header comparison method. All alternative protocol versions are matched simultaneously, and demodulation parameters are automatically switched after a successful match.

[0011] Secondly, the present invention provides a hardware supplementary system for an interplanetary communication system that implements the above-mentioned method, characterized in that it includes a heterogeneous redundancy switching circuit, a protocol adaptive circuit, a time synchronization circuit, and a data transmission management circuit; the output of the heterogeneous redundancy switching circuit is connected to a transmission channel switching execution terminal, the output of the protocol adaptive circuit is connected to a demodulation parameter switching execution terminal, the output of the time synchronization circuit is connected to a clock source switching execution terminal, and the output of the data transmission management circuit is connected to a data generation control terminal; all processes of the system are automatically executed by pure hardware circuits, without the participation of a central processing unit, without instruction execution, and without software code execution.

[0012] Furthermore, the heterogeneous redundancy switching circuit includes a laser link quality monitoring terminal and an RF link quality monitoring terminal; it also includes a heterogeneous link arbitration circuit, used to implement the priority logic of laser priority and RF backup in pure hardware, and outputs a link selection signal according to the link quality; the protocol adaptive circuit includes multiple parallel independent frame header comparators, each corresponding to a version frame header in the historical protocol version table, and if any match is successful, the corresponding version demodulation parameter switching signal is output in pure hardware; the time synchronization circuit uses a digitally controlled oscillator to achieve continuous phase adjustment, and outputs a continuously changing phase control signal in pure hardware when the clock source is switched; the data transmission management circuit includes a buffer occupancy monitoring circuit and a data generation current limiting circuit, the buffer occupancy monitoring circuit outputs a buffer occupancy rate exceeding a threshold indication signal, and the data generation current limiting circuit outputs a data generation period extension control signal in pure hardware when the buffer occupancy exceeds the threshold and the link quality is lower than the threshold.

[0013] Furthermore, the system also includes: a delay-tolerant network protocol hardware adapter circuit, including packet header assembly logic and hop-by-hop forwarding control logic; an end-to-end packet signature verification circuit, including source node signature verification logic; and a hop-by-hop reputation management circuit, including neighbor node forwarding behavior statistics logic and reputation score comparison logic.

[0014] Furthermore, the entire process of channel switching, protocol matching, clock switching, and data cycle adjustment in the system is automatically executed by hardware circuits, without any software logic involved in the judgment and control.

[0015] 1. Beneficial effects Compared with the prior art, the present invention has the following advantages: 1. Effectively improves the operational reliability of interstellar communication systems: All processes in this invention are automatically executed by pure hardware circuits without the need for software or central processing unit participation. It is not easily affected by factors such as cosmic rays and space electromagnetic interference, and can operate stably in the extreme environment of interstellar space, significantly reducing the risk of communication interruption.

[0016] 2. Significantly reduced communication control response time: This invention uses pure hardware circuits to implement functions such as link switching, protocol adaptation, clock synchronization, and flow control. All operations are executed in parallel hardware, which greatly reduces response latency and enables rapid adaptation to the dynamic changes of interplanetary links, reducing data congestion and transmission interruption problems.

[0017] 3. Excellent link and protocol adaptability: This invention achieves automatic switching between laser and radio frequency links through heterogeneous redundant switching circuits and enables rapid adaptation of multiple protocol versions through parallel frame header comparison. It can effectively cope with scenarios of changing interplanetary communication link states and iterative protocol versions, ensuring communication continuity.

[0018] 4. Achieve shock-free clock source switching: This invention uses a digitally controlled oscillator to achieve continuous phase adjustment clock switching, which can avoid phase jumps during clock source switching, ensure the time synchronization stability of the communication system, and reduce communication errors caused by clock jitter.

[0019] 5. Adaptive traffic management capability: This invention achieves linkage management of cache usage and link quality through pure hardware circuitry. It can proactively adjust the generation cycle of low-priority data when the link quality is poor, avoid cache overflow, ensure reliable transmission of high-priority data, and effectively reduce system power consumption, making it suitable for the energy-limited usage scenarios of deep space exploration spacecraft. Detailed Implementation

[0020] The present invention will now be described in further detail and in complete detail with reference to specific embodiments. Those skilled in the art can implement the technical solutions of the present invention, solve corresponding technical problems, and achieve the intended technical effects based on the content disclosed in these embodiments.

[0021] All circuits in this embodiment are designed using radiation-resistant complementary metal-oxide-semiconductor (CMOS) technology to meet the total dose radiation and single-event protection requirements of the space on-orbit environment. All circuits are implemented using pure digital logic circuits, without embedded processors, instruction sets, or software code storage and execution units. Example

[0022] This embodiment provides a hardware supplement system for an interplanetary communication system, including a heterogeneous redundancy switching circuit, a protocol adaptive circuit, a time synchronization circuit, and a data transmission management circuit. The output of the heterogeneous redundancy switching circuit is connected to the transmission channel switching execution terminal, the output of the protocol adaptive circuit is connected to the demodulation parameter switching execution terminal, the output of the time synchronization circuit is connected to the clock source switching execution terminal, and the output of the data transmission management circuit is connected to the data generation control terminal. All processes of the system are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

[0023] The heterogeneous redundancy switching circuit includes a laser link quality monitoring terminal and an RF link quality monitoring terminal, as well as a heterogeneous link arbitration circuit. This circuit implements a pure hardware-based priority logic of laser-first, RF-backup, and outputs a link selection signal based on link quality. When the laser link quality meets a preset threshold, it is prioritized as the primary transmission channel. When the laser link quality falls below the threshold, it automatically switches to the RF link as the backup channel. When the laser link quality recovers and exceeds the hysteresis threshold, it smoothly switches back to the laser link, avoiding frequent switching.

[0024] The protocol adaptation circuit includes four parallel and independent frame header comparators, each corresponding to a different frame header format from the historical protocol version table. When receiving ground signals, the four frame header comparators simultaneously perform parallel matching on the received data. If any comparator successfully matches, a hardware-based demodulation parameter switching signal for the corresponding version is output, automatically adjusting the demodulation module's operating parameters to adapt to the corresponding protocol version.

[0025] The time synchronization circuit uses a digitally controlled oscillator to achieve continuous phase adjustment. When switching between the primary and backup clock sources, the pure hardware outputs a continuously changing phase control signal, so that the phase of the output clock smoothly transitions from the original clock source to the new clock source without any phase jump, thus avoiding system timing disorder caused by clock switching.

[0026] The data transmission management circuit includes a buffer occupancy monitoring circuit and a data generation rate limiting circuit. The buffer occupancy monitoring circuit monitors the occupancy rate of the transmission buffer in real time. If the occupancy rate exceeds a preset threshold for three consecutive monitoring cycles, and the link quality monitoring result is lower than the preset threshold, the data generation rate limiting circuit outputs a data generation cycle extension control signal in pure hardware. This actively extends the generation cycle of low-priority telemetry data, reduces the data transmission rate, and avoids buffer overflow.

[0027] This embodiment also includes a latency-tolerant network protocol hardware adapter circuit, comprising packet header assembly logic and hop-by-hop forwarding control logic. It uses a latency-tolerant network protocol instead of the Transmission Control Protocol / Internet Protocol (TCP / IP) to adapt to interplanetary communication scenarios with long latency and high interruptibility. Simultaneously, it includes an end-to-end packet signature verification circuit and a hop-by-hop reputation management circuit. The end-to-end packet signature verification circuit verifies the signature of each received packet to prevent illegal data injection. The hop-by-hop reputation management circuit analyzes the forwarding behavior of neighboring nodes, maintains node reputation values, and prioritizes forwarding packets sent by nodes with higher reputation values, thereby improving the reliability of network transmission.

[0028] The working process of this embodiment is as follows: 1. The heterogeneous redundancy switching circuit monitors the quality of the laser link and the radio frequency link in real time, and automatically switches the transmission channel according to the preset rule of laser priority and radio frequency backup; 2. When receiving ground signals, the multiple parallel frame header comparators of the protocol adaptive circuit simultaneously attempt to match multiple alternative protocol versions. After a successful match, the corresponding demodulation parameters are automatically switched. 3. When switching between primary and backup clock sources, the time synchronization circuit outputs a continuously changing phase control signal through a digitally controlled oscillator to achieve smooth clock switching without phase jumps; 4. The buffer occupancy monitoring circuit monitors the occupancy rate of the sending buffer in real time. When the buffer occupancy rate exceeds the threshold continuously and the link quality is lower than the threshold, the data generation rate limiting circuit actively extends the generation cycle of low-priority data. 5. The delay-tolerant network protocol hardware adapter circuit completes the header assembly and hop-by-hop forwarding of data packets, adapting to interplanetary long-delay communication scenarios; 6. The end-to-end data packet signature verification circuit performs signature verification on the received data packets, and the hop-by-hop reputation management circuit maintains the reputation value of adjacent nodes and prioritizes forwarding data packets from high-reputation nodes. Example

[0029] The difference between this embodiment and Embodiment 1 is that the number of parallel frame header comparators in the protocol adaptive circuit can be configured to 8 according to actual needs, supporting parallel matching of more historical protocol versions, further improving the compatibility of protocol adaptation, and is suitable for long-cycle deep space exploration missions with many protocol version iterations.

Claims

1. A hardware supplementation method for an interplanetary communication system, characterized in that, Includes the following steps: The transmission channel is switched between the laser link and the radio frequency link according to a preset priority rule; When receiving ground signals, multiple alternative protocol versions are tried in parallel. The clock source switching uses a gradual transition without phase jumps; When the cache utilization rate continuously exceeds the threshold and the link quality is lower than the threshold, the generation cycle of low-priority data is proactively extended.

2. A hardware supplementary system for an interplanetary communication system implementing the method of claim 1, characterized in that, The system includes a heterogeneous redundancy switching circuit, a protocol adaptive circuit, a time synchronization circuit, and a data transmission management circuit. The output of the heterogeneous redundancy switching circuit is connected to the transmission channel switching execution terminal, the output of the protocol adaptive circuit is connected to the demodulation parameter switching execution terminal, the output of the time synchronization circuit is connected to the clock source switching execution terminal, and the output of the data transmission management circuit is connected to the data generation control terminal. All processes of the system are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

3. The system according to claim 2, characterized in that, The heterogeneous redundancy switching circuit includes a laser link quality monitoring terminal and an RF link quality monitoring terminal; it also includes a heterogeneous link arbitration circuit, which is used to implement the priority logic of laser priority and RF backup in pure hardware, and outputs a link selection signal according to the link quality. The protocol adaptive circuit includes multiple parallel and independent frame header comparators, each corresponding to a frame header of a version in the historical protocol version table. If any match is successful, the corresponding version demodulation parameter switching signal is output purely in hardware. The time synchronization circuit uses a digitally controlled oscillator to achieve continuous phase adjustment, and the pure hardware outputs a continuously changing phase control signal when the clock source is switched. The data transmission management circuit includes a buffer occupancy monitoring circuit and a data generation rate limiting circuit. The buffer occupancy monitoring circuit outputs a buffer occupancy rate exceeding the threshold indication signal. The data generation rate limiting circuit is purely hardware-based and outputs a data generation cycle extension control signal when the buffer occupancy exceeds the threshold and the link quality is lower than the threshold.

4. The method according to claim 1, characterized in that, All processes are executed automatically and continuously by pure hardware circuits without manual intervention. They run continuously after power-on without software intervention or central processing unit participation. The switching of transmission channels between the laser link and the radio frequency link according to preset priority rules follows the following preset priority rules: laser priority, radio frequency backup, dual-link coordination, and recovery hysteresis.

5. The method according to claim 1, characterized in that, Also includes: A delay-tolerant network protocol is used instead of the Transmission Control Protocol / Internet Protocol. The packet header includes source node identifier, destination node identifier, generation timestamp, time to live, hop count counter and priority field.

6. The method according to claim 1, characterized in that, Also includes: Each data packet undergoes end-to-end digital signature verification, and hop-by-hop reputation values ​​of adjacent nodes are maintained, prioritizing the forwarding of data packets sent by nodes with higher reputation values.

7. The system according to claim 2, characterized in that, Also includes: Delay-tolerant network protocol hardware adapter circuit, including packet header assembly logic and hop-by-hop forwarding control logic; End-to-end data packet signature verification circuit, including source node signature verification logic; The hop-by-hop reputation management circuit includes logic for statistical analysis of forwarding behavior of adjacent nodes and logic for comparing reputation scores.

8. The method according to claim 1, characterized in that, When receiving ground signals, multiple alternative protocol versions are tried in parallel. A parallel frame header comparison method is used, and all alternative protocol versions are matched at the same time. After a successful match, the demodulation parameters are automatically switched.

9. The system according to claim 2, characterized in that, The entire process of channel switching, protocol matching, clock switching, and data cycle adjustment in the system is automatically executed by hardware circuits, without any software logic involved in the judgment and control.