Methods and communication systems for providing dynamic low-latency transmission for high-priority traffic

Abstract

This invention provides a method and communication system for providing dynamic low-latency transmission for high-priority traffic. If the data packet currently planned for transmission is a high-priority data packet, data transmission is performed in low-latency mode to reduce environmental interference and improve the success rate of transmission. If the data packet currently planned for transmission is not a high-priority data packet, data transmission is performed in normal mode to achieve optimal performance advantages.

Description

[0001] Cross-references

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 758,387, filed February 14, 2025, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to communication systems, and more particularly, to methods and related communication systems for providing dynamic low-latency transmission for high-priority traffic. Background Technology

[0004] Wireless communication systems are being widely deployed to provide various types of communication services, such as voice and data. Generally, a wireless communication system is a multiple access system capable of supporting communication with multiple users by sharing available system resources, such as bandwidth and transmission power. Examples of multiple access systems include Code Division Multiple Access (CDMA), Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Orthogonal Frequency Division Multiple Access (OFDMA), Single-Carrier Frequency Division Multiple Access (SC-FDMA), and Multi-Carrier Frequency Division Multiple Access (MC-FDMA).

[0005] Multilink operation (MLO) enables devices to transmit and receive data on links across different frequency bands. Connections across multiple frequency bands can increase throughput, reduce latency, and improve reliability. Enhanced Multilink Single Radio (eMLSR) is a type of MLO that allows single-radio multilink devices to switch between links across different frequency bands to improve throughput and latency.

[0006] Enhanced Distributed Channel Access (EDCA) is a Quality of Service (QoS) mechanism defined for Wireless Local Area Network (WLAN) technology in the IEEE 802.11 standard family, in which higher-priority traffic has a greater chance of transmission than lower-priority traffic. To facilitate this result, EDCA assigns frames / packets to access classes corresponding to their priority levels. These access classes may include, in ascending order of priority: Background Information Access Class (AC_BK), Best Effort Access Class (AC_BE), Video Access Class (AC_VI), and Voice Access Class (AC_VO).

[0007] Each access class defines different time intervals for contention window-related parameters, such as Arbitrated Inter-Frame Spaces (AIFs) and Contention Window (CW). To ensure that relatively higher priority traffic has a greater chance of transmission than relatively lower priority traffic, the contention window-related parameters for higher priority access classes typically define shorter time intervals than those for relatively lower priority access classes. With these shorter time intervals, relatively higher priority traffic is more likely to win the contention.

[0008] However, giving higher priority traffic a greater chance of transmission does not necessarily guarantee a higher success rate. Environmental interference can cause transmission collisions and multiple retries, leading to increased latency. Therefore, a method for dynamic, low-latency transmission of high-priority traffic is needed. Summary of the Invention

[0009] This disclosure provides a method for providing dynamic low-latency transmission for high-priority traffic. The method includes: receiving data packets from multiple application streams by a communication system; and when it is determined that the first data packet currently scheduled for transmission is a high-priority data packet, transmitting the data packet by the communication system in a low-latency mode, wherein the low-latency mode prioritizes network connection response time.

[0010] This disclosure also provides a communication system including at least one machine-readable storage medium and processor circuitry. The at least one machine-readable storage medium stores program instructions. The processor circuitry is coupled to the at least one machine-readable storage medium and configured to execute the program instructions to: receive data packets from a plurality of application streams and transmit the data packets in a low-latency mode within a protection time, wherein the low-latency mode prioritizes network connection response time when it is determined that the first data packet currently scheduled for transmission is a high-priority data packet.

[0011] These and other objectives of the invention will undoubtedly become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments, which are illustrated in various figures and drawings. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a communication system that provides dynamic, low-latency transmission for high-priority traffic according to one embodiment of this disclosure.

[0013] Figure 2 This is a flowchart illustrating a method that, according to an embodiment of this disclosure, provides dynamic low-latency transmission for high-priority traffic.

[0014] Figure 3This is a diagram illustrating a computer system that can be used to implement a method for dynamic low-latency transmission of high-priority traffic according to an embodiment of the present disclosure. Detailed Implementation

[0015] Various exemplary embodiments are described using terminology commonly used by those skilled in the art in order to convey the essence of the disclosure to others skilled in the art. However, it will be apparent to those skilled in the art that many alternative embodiments can be practiced using portions of the described aspects. Specific figures, materials, and configurations are set for illustrative purposes to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that alternative embodiments can be practiced without specific details. In other instances, well-known features may have been omitted or simplified to avoid obscuring the exemplary embodiments.

[0016] Furthermore, multiple discrete operations will be described in a manner most conducive to understanding the exemplary embodiments; however, the order of description should not be construed as implying that these operations are necessarily sequentially dependent. In particular, these operations do not need to be performed in the order presented.

[0017] The phrases “in one embodiment,” “in one embodiment,” and “in some embodiments” are used repeatedly herein. These phrases do not typically refer to the same embodiment; however, they may. The terms “comprising,” “having,” and “including” are synonyms unless the context otherwise requires. The phrases “A or B” and “A / B” mean “(A), (B), or (A and B).”

[0018] The term "circuit" herein refers to, is a part of, or includes hardware components such as electronic circuits, logic circuits, processors (shared, dedicated, or grouped) or memories (shared, dedicated, or grouped), application-specific integrated circuits (ASICs), field-programmable devices (FPDs) (e.g., field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex PLDs (CPLDs), high-capacity PLDs (HCPLDs), structured ASICs, or programmable system-on-chips (SoCs)), digital signal processors (DSPs), etc., which are configured to provide the described functionality. In some embodiments, the circuit may execute one or more software or firmware programs to provide at least a portion of the described functionality. The term "circuit" may also refer to a combination of one or more hardware elements (or a combination of circuits used in an electrical or electronic system) and program code for performing the functionality of the program code. In these embodiments, the combination of hardware elements and program code may be referred to as a particular type of circuit.

[0019] The term "processor circuit" as used herein refers to, is part of, or includes circuitry capable of sequentially and automatically performing sequences of arithmetic or logical operations, or recording, storing, or transmitting digital data. The term "processor circuit" can refer to an application processor, baseband processor, central processing unit (CPU), graphics processing unit, single-core processor, dual-core processor, triple-core processor, quad-core processor, or any other device capable of executing or operating computer-executable instructions, such as program code, software modules, or functional processes.

[0020] The term "interface circuit" as used herein refers to, is part of, or includes circuitry that enables the exchange of information between two or more components or devices. The term "interface circuit" can refer to one or more hardware interfaces, such as buses, I / O interfaces, peripheral component interfaces, network interface cards, or similar devices.

[0021] The term "User Equipment" or "UE" in this document refers to a device with wireless communication capabilities and may describe a remote user of network resources in a communication network. The term "User Equipment" or "UE" can be considered synonymous and may refer to a client, mobile device, mobile terminal, user terminal, mobile unit, mobile workstation, mobile user, subscriber, user, remote workstation, access agent, user agent, receiver, wireless device, reconfigurable wireless device, reconfigurable mobile device, etc. Furthermore, the term "User Equipment" or "UE" can include any type of wireless / wired device or any computing device containing a wireless communication interface.

[0022] The term "channel" in this document refers to any medium used for the transmission of communication data or data streams, whether tangible or intangible. The term "channel" may be synonymous or equivalent to "communication channel," "data communication channel," "transmission channel," "data transmission channel," "read channel," "data read channel," "link," "data link," "carrier," "radio frequency carrier," or any other term indicating a path or medium through which data is transmitted. Furthermore, the term "link" in this document refers to a connection between two devices used for transmitting and receiving information.

[0023] The term "connection" may mean that two or more elements establish a signaling relationship on a common communication protocol layer through a communication channel, link, interface, or reference point.

[0024] The term "radio frequency (RF) signal" as used herein includes an electromagnetic wave of a given frequency that transmits information in the space between a transmitter and a receiver. In this document, a transmitter may transmit a single "RF signal" or multiple "RF signals" to a receiver. However, due to the propagation characteristics of RF signals through multipath channels, a receiver may receive multiple "RF signals" corresponding to each transmitted RF signal. The same transmitted RF signal on different paths between the transmitter and receiver can be referred to as a "multipath" RF signal. In this document, an RF signal may also be referred to as a "wireless signal" or simply a "signal," where, in the context, "signal" explicitly refers to either a wireless signal or an RF signal.

[0025] Figure 1 This is a block diagram illustrating a communication system 100 that provides dynamic low-latency transmission for high-priority traffic according to one embodiment of the present disclosure. As shown, the communication system 100 includes an antenna module 110, an RF front-end circuit 120, a baseband processor 130, a processor circuit 140, a program storage module 150, a network interface circuit 160, a communication interface circuit 170, and at least one machine-readable storage medium 180.

[0026] In various embodiments, the communication system 100 may be a smartphone, tablet, laptop, personal digital assistant (PDA), mobile computing device, navigation system, automated vehicle control system (ADAS), mobile data collection platform, Internet of Things device, computer system, or any user equipment (UE) capable of providing data traffic prioritization and scheduling functions. However, the type of communication system 100 does not limit the scope of this disclosure.

[0027] Antenna module 110 is configured to facilitate the transmission and reception of electromagnetic waves in the radio frequency (RF) spectrum across a wide range of devices and applications. By way of example and not limitation, antenna module 110 may include one or more RF antennas configured to detect and transmit / receive Radio Access Technology (RAT) signals in a service area or location associated with communication system 100. For example, Long Term Evolution (LTE), including LTE-A, LTE-U, and LTE-LAA signals, may serve as the basis for communication between communication system 100 and various mobile devices. One or more RF antennas may include multiple spatially diverse individual elements in a MIMO or MISO configuration to increase coverage area by utilizing the spatial diversity of transmitted and received signals. Communication system 100 may also utilize spatial multiplexing (SM) to enhance data throughput, for example, by multiplexing data streams across different antennas of antenna module 110. However, implementation of antenna module 110 does not limit the scope of this disclosure.

[0028] RF front-end circuitry 120 is configured to process the transmission and reception of RF signals via antenna module 110. By way of example and not limitation, RF front-end circuitry 120 may include one or more filters, duplexers, low-noise amplifiers (LNAs), power amplifiers (PAs), frequency converters, phase shifters, attenuators, and switches. Filters are used to isolate and separate signals within a specific frequency range, ensuring that the desired frequency band is transmitted or received. Duplexers allow transmission and reception on the same frequency band using a single antenna. LNAs amplify weak input RF signals from antenna module 110 with minimal noise. Power amplifiers amplify RF signals before transmission. Frequency converters use RF mixers to convert intermediate frequency signals to RF signals and vice versa. Phase shifters adjust the phase of the signal in real time and control the direction of transmitted or received signals when used in beamforming and phased array antenna systems. Attenuators control signal strength by introducing controlled signal loss. Switches route signals between different components. However, implementation of RF front-end circuitry 120 does not limit the scope of this disclosure.

[0029] The baseband processor 130 is configured to handle digital signal processing (DSP), signal modulation / demodulation, error correction, and the conversion of RF signals into a format understandable to the end user or device. By way of example and not limitation, the baseband processor 130 may be a microprocessor implementing baseband signal processing and radio control functions, including, in one variant, physical layer (PHY) and layer 2 functions such as media access control (MAC). The PHY layer performs encoding and decoding, modulation and demodulation, antenna mapping and demapping, and resource mapping and demapping. The MAC layer performs data priority control, retransmission processing via Hybrid Automatic Repeat Request (HARQ), random access procedures, etc. However, the implementation of the baseband processor 130 does not limit the scope of this disclosure.

[0030] Processor circuitry 140 is configured to execute at least one computer program / firmware and / or control hardware components to perform various functions, such as communication with associated functional modules. By way of example and not limitation, processor circuitry 140 may include one or more central processing units (CPUs), digital signal processors, semiconductor-based microprocessors, field-programmable gate arrays (FPGAs), graphics processing units (GPUs), or multiple processing components mounted on one or more substrates, adapted to retrieve and execute instructions stored in machine-readable storage medium 180 to control processes or operations involving flow scheduling prioritization / optimization. As an alternative or supplement to retrieving and executing instructions, processor circuitry 140 may include one or more electronic circuits containing electronic components for performing one or more instruction functions, such as FPGAs, application-specific integrated circuits (ASICs), or other electronic circuits. However, implementation of processor circuitry 140 does not limit the scope of this disclosure.

[0031] The program storage module 150 may implement one or more direct memory access (DMA) type hardware to facilitate data access in relation to the communication system 100. By way of example and not limitation, the program storage module 150 may contain one or more computer-executable instructions that are executed by the processor circuitry 140. Figure 1 In the illustrated embodiment, the program storage module 150 includes traffic profile analysis logic 152 and a packet scheduler 154. The traffic profile analysis logic 152 includes various functions, including receiving and assembling configuration and traffic profile (TP) data associated with the communication system 100, including Customer Premises Equipment (CPE) ID, default bearer ID, number of network users served, traffic type data for each user / client, and priority for each user / client. The traffic profile analysis logic 152 can process the assembly of configuration and TP data to uniquely associate the data (and the resulting schedule) with each participating CPE. In some embodiments, the traffic profile analysis logic 152 can be configured to tag certain packets with additional tags or identifiers to associate them with specific function or service flows established in the packet scheduler 154 logic. The packet scheduler 154 logic is configured to perform scheduling operations based on the TP data obtained from the traffic profile analysis logic 152. However, the implementation of the program storage module 150 does not limit the scope of this disclosure.

[0032] Network interface circuitry 160 is configured to connect communication system 100 to a network element. By way of example and not limitation, network interface circuitry 160 can be any signal or data interface, including but not limited to FireWire, USB, Ethernet, MoCA, Coaxsys, RF tuner, LTE, Wi-Fi, WiMAX, Z-wave, PAN, or power line carrier (PLC) series. However, implementation of network interface circuitry 160 does not limit the scope of this disclosure.

[0033] The communication interface circuit 170 includes hardware, software, or simultaneously provides one or more interfaces for communication (e.g., packet-based communication) between the communication system 10 and one or more other electronic devices or one or more networks. Figure 1 In the illustrated embodiment, the communication interface circuit 170 includes a network interface controller (NIC) 172 and a host interface (HIF) 174.

[0034] By way of example and not limitation, the communication interface circuitry 170 may be configured to communicate with Ethernet or other wired networks or with wireless networks (such as Wi-Fi networks) via the NIC 172. In one embodiment, via the NIC 172 of the communication interface circuitry 170, the communication system 100 may communicate with one or more portions of a temporary network, a personal area network (PAN), a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), or the Internet, or a combination of two or more of these, wherein one or more of the one or more portions of the network may be wired or wireless. In one embodiment, via the NIC 172 of the communication interface circuitry 170, the communication system 100 may communicate with a wireless PAN (WPAN), a Wi-Fi network, a Wi-MAX network, a cellular telephone network, or other suitable wireless networks, or a combination of two or more of these. The communication system 100 may include any communication interface circuitry 170 suitable for these networks, where appropriate. The communication interface circuitry 170 may include one or more communication interfaces, where appropriate. While this disclosure describes and illustrates a particular communication interface, this disclosure contemplates any suitable communication interface.

[0035] HIF 174 defines a standard set of kernel services that interface user applications to the host operating system. As an example, and not a limitation, HIF 174 can be implemented in its own way in each emulator, hardware device, and high-level language. Kernel services provide the minimum functionality required to interface high-level language library functions to user operating system code.

[0036] Machine-readable storage medium 180 is configured to store one or more program instructions. By way of example and not limitation, machine-readable storage medium 180 may include any type of integrated circuit or other storage device suitable for storing digital data, including computer hard drives, DVR devices, random access memory (RAM), non-volatile RAM (NVRAM), electrically erasable programmable read-only memory (EEPROM), RAID devices or arrays, optical media, or any other device or medium capable of storing executable instructions, content, or other information. However, implementations of machine-readable storage medium 180 do not limit the scope of this disclosure.

[0037] Figure 2 This is a flowchart illustrating a method for providing dynamic low-latency transmission for high-priority traffic according to an embodiment of this disclosure. Figure 2 The method 200 shown can be executed by the communication system 100 and includes the following steps: Step 210: Receive data packets from multiple application streams.

[0038] Step 220: Determine the QoE score for each of the multiple traffic flows.

[0039] Step 230: Prioritize packet processing based on the QoE score of each traffic flow.

[0040] Step 240: Arrange the transmission or reception of data packets from the queue according to priority.

[0041] Step 250: Determine whether the data packet currently scheduled for transmission is a high-priority data packet; if yes, proceed to step 260; if not, proceed to step 270.

[0042] Step 260: Transmit data packets in low-latency mode within the protection time; proceed to step 250.

[0043] Step 270: Transmit data packets in normal mode; proceed to step 250.

[0044] In one embodiment, the program instructions related to steps 210-270 may be stored in a machine-readable storage medium 180 of the communication system 100. The processor circuitry 140 may retrieve and execute the program instructions related to steps 210-270 to provide dynamic low-latency transmission for high-priority traffic.

[0045] In step 210, the processor circuit 140 may execute program instructions related to step 210 to control the communication system 100 to receive data packets of multiple traffic streams through the communication interface circuit 170.

[0046] In step 220, processor circuitry 140 may execute program instructions related to step 220 to determine the QoE score of each of the multiple traffic flows. This gives traffic flows with higher QoE scores a greater chance to access the channel, thereby reducing latency for low-latency services.

[0047] In one embodiment, the Quality of Service (QoE) score for each of the multiple traffic flows can be determined by traffic profile analysis logic 152 according to the QoS extensions defined for Wireless Local Area Network (WLAN) technologies in the IEEE 802.11 standard family. For example, some QoS extensions of the 802.11 protocol may prioritize the transmission of voice packets and video packets. In particular, Wi-Fi Multimedia (WMM), formerly known as Wireless Multimedia Extension (WME), is a subset of the 802.11e WLAN specification that enhances QoS on the network by prioritizing packets according to four access categories: Voice Access Category (AC_VO), Video Access Category (AC_VI), Best Effort Access Category (AC_BE), and Background Information Access Category (AC_BK). The QoS parameters (or read channel configuration parameters) for each access category include the following types: Maximum Contention Window (CWmax), Minimum Contention Window (CWmin), Arbitration Inter-Frame Interval (AIFSN), and Transmission Opportunity (TXOP) limit. By giving higher priority to AC_VI and AC_VO packets, WMM enables concurrent VoIP calls with minimal latency and highest quality, prioritizing all other data traffic and supporting three to four Standard Defined Television (SDTV) streams or one High Definition Television (HDTV) stream over the WLAN. AC_BE packets include those from legacy devices or applications / devices lacking QoS standards. AC_BK packets include file downloads, print jobs, and other traffic unaffected by increased latency.

[0048] In one embodiment, the QoE score of each of the plurality of traffic flows can be calculated by traffic profile analysis logic 152 by at least one of the following: jitter parameter of the traffic flow, latency parameter of the traffic flow, packet loss parameter of the traffic flow, throughput parameter of the traffic flow, and time-in-flight parameter of the traffic flow.

[0049] In step 230, processor circuitry 140 can execute program instructions related to step 230 to prioritize data packets based on the QoE score of each traffic stream, thereby providing a performance-oriented transmission scheme that maximizes the advantages of efficient traffic movement in a wireless network. Thus, traffic streams with higher QoE scores, such as those requiring more processing in allocating wireless resources from access points, may have a greater chance of successfully preempting a channel in a shorter time.

[0050] In step 240, processor circuitry 140 may execute program instructions related to step 240 to schedule data packets for transmission or reception from the queue according to priority. For example, processor circuitry 140 may instruct packet scheduler 154 to schedule data packets for transmission or reception from the queue according to the priority obtained in step 230.

[0051] In step 250, processor circuitry 140 may execute program instructions related to step 250 to determine whether the currently planned data packet to be transmitted is a high-priority data packet. If it is determined in step 250 that the currently planned data packet to be transmitted is a high-priority data packet, then step 260 is executed to transmit the data packet in low-latency mode within the protection time. If it is determined in step 250 that the currently planned data packet to be transmitted is not a high-priority data packet, then step 270 is executed to transmit the data packet in normal mode. In this disclosure, low-latency mode prioritizes fast real-time response time for network connectivity, while normal mode prioritizes optimal network performance.

[0052] As mentioned earlier, performance-oriented transmission schemes prioritize data through WMM queues, giving higher-priority data more opportunities to access the channel and reducing latency for low-latency services. However, giving relatively higher-priority traffic more transmission opportunities does not necessarily guarantee a higher success rate. Environmental interference can cause transmission collisions and multiple retries, leading to increased latency, which may hinder the realization of the advantages of high priority. Furthermore, applications developed for new technologies, such as virtual reality (VR), may require high bandwidth and low-latency guarantees to provide an acceptable user experience.

[0053] To provide low-latency transmission for high-priority traffic, if it is determined in step 250 that the data packet currently scheduled for transmission is a high-priority data packet (e.g., an AC_VO or AC_VI packet), then processor circuitry 140 is configured to instruct antenna module 110 to transmit the high-priority data packet in low-latency mode in step 260 to minimize interference and retransmissions. As an example, and not a limitation, antenna module 110 may employ a space-time block coding (STBC) transmission method, lower transmission bandwidth, lower quadrature amplitude modulation (QAM), and / or dual-carrier modulation (DCM) / extended range (ER) rate in low-latency mode. This allows high-priority data packets to be transmitted in a timely manner, achieving the low-latency advantage. After the protection time has elapsed since the data packet was transmitted in low-latency mode in step 260, the current method returns to step 250 to determine if there are still high-priority data packets scheduled for transmission.

[0054] If it is determined in step 250 that the data packet currently scheduled for transmission is not a high-priority data packet, then the processor circuitry 140 is configured to instruct the antenna module 110 to transmit the data packet in normal mode in step 270 to achieve optimal performance advantages.

[0055] Figure 3 This is a schematic diagram illustrating a computer system 300, which can be used to implement... Figure 2 The method shown provides dynamic low-latency transmission for high-priority traffic, according to one embodiment of this application. By way of example and not limitation, computer system 300 can be any type of interconnected electronic device, computer device, or various components of a computer that are communicatively coupled to each other and configured to share computing or network resources. Figure 3 In an example implementation, computer system 300 includes a hardware processor 310 and at least one machine-readable storage medium 320.

[0056] By way of example and not limitation, hardware processor 310 may be one or more CPUs, semiconductor-based microprocessors, and / or other hardware devices suitable for retrieving and executing program instructions stored in machine-readable storage medium 320. Hardware processor 310 may acquire, decode, and execute program instructions, such as steps 210-270 shown in the program instructions, to control a process or operation for traffic scheduling optimization, thereby providing dynamic low-latency transmission for high-priority traffic. As an alternative to or supplement to retrieving and executing instructions, hardware processor 310 may include one or more electronic circuits containing electronic components for performing the functions of one or more program instructions, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or other electronic circuits. However, implementation of hardware processor 310 does not limit the scope of this disclosure.

[0057] By way of example and not limitation, machine-readable storage medium 320 may include any type of integrated circuit or other storage device suitable for storing digital data, including computer hard disk drives, DVR devices, RAM, NVRAM, EEPROM, RAID devices or arrays, optical media, or any other device or medium capable of storing executable instructions, content, or other information. However, implementations of machine-readable storage medium 320 do not limit the scope of this disclosure.

[0058] In summary, this disclosure provides a method for providing dynamic low-latency transmission for high-priority traffic. If the data packet currently scheduled for transmission is a high-priority data packet, data transmission is performed in a low-latency mode to reduce environmental interference and improve the success rate of transmission. If the data packet currently scheduled for transmission is not a high-priority data packet, data transmission is performed in a normal mode to achieve optimal performance advantages.

[0059] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while retaining the teachings of the invention. Therefore, the above disclosure should be limited only to the scope of the claims.

Claims

1. A method for providing dynamic low-latency transmission for high-priority traffic, comprising: The communication system receives data packets from multiple application streams. as well as When it is determined that the first data packet to be transmitted is a high-priority data packet, the communication system transmits the data packet in a low-latency mode, where the low-latency mode takes into account the response time of the network connection.

2. The method of claim 1, further comprising: When it is determined that the first data packet is not the high-priority data packet, the communication system transmits the data packet in normal mode, where the normal mode prioritizes optimal network performance.

3. The method of claim 1, further comprising: The communication system determines the Quality of Service (QoE) score for each of the multiple traffic flows based on the access category of each traffic flow as defined in the IEEE 802.11 standard series. The communication system prioritizes processing the data packet based on the QoE score of each traffic stream; as well as The communication system schedules the transmission of the data packet into the queue according to its priority.

4. The method of claim 3, wherein: The high-priority data packet is either a voice access class AC_VO packet or a video access class AC_VI packet, which are defined in this IEEE 802.11 standard family.

5. The method of claim 1, further comprising: The communication system determines the QoE score for each of the multiple traffic streams by calculating the jitter parameter, latency parameter, packet loss parameter, throughput parameter and / or time-of-flight parameter for each traffic stream. The communication system prioritizes processing the data packet based on the QoE score of each traffic stream; as well as The communication system schedules the transmission of the data packet into the queue according to its priority.

6. The method of claim 1, further comprising: After a protection period during which the data packet is transmitted in this low-latency mode, the communication system determines whether the second data packet currently scheduled for transmission is the high-priority data packet. as well as When it is determined that the second data packet is not the high-priority data packet, the communication system transmits the data packet in normal mode.

7. The method of claim 1, further comprising: The communication system transmits the data packet in this low-latency mode using the Space-Time Block Coding (STBC) transmission method, lower transmission bandwidth, low Quadrature Amplitude Modulation (QAM), and / or Dual Carrier Modulation (DCM) / Extended Range (ER) rate.

8. A communication system, comprising: At least one machine-readable storage medium for storing program instructions; as well as A processor circuit coupled to the at least one machine-readable storage medium and configured to execute the program instructions to: Receive data packets from multiple application streams; and When it is determined that the first data packet to be transmitted is a high-priority data packet, the data packet is transmitted in a low-latency mode within the protection period, where the low-latency mode takes into account the response time of the network connection.

9. The communication system as described in claim 8, wherein: The processor circuitry is further configured to execute the program instructions to transmit the packet in normal mode when it is determined that the first packet is not the high-priority packet; and the normal mode prioritizes optimal network performance.

10. The communication system of claim 8, wherein the processor circuitry is further configured to execute the program instructions to: Based on the access category of each traffic flow as defined in the IEEE 802.11 standard series, determine the Quality of Service (QoE) score for each of the multiple traffic flows. The packet is processed preferentially based on the QoE score of each traffic flow; and The data packet is scheduled to be transmitted to the queue according to its priority.

11. The communication system of claim 10, wherein: The high-priority data packet is either a voice access class AC_VO packet or a video access class AC_VI packet, which are defined in this IEEE 802.11 standard family.

12. The communication system of claim 8, wherein the processor circuitry is further configured to execute program instructions to: determine a QoE score for each of a plurality of traffic streams by calculating jitter parameters, delay parameters, packet loss parameters, throughput parameters and / or airtime parameters for each traffic stream; prioritize data packets based on the QoE score of each traffic stream; and schedule data packets to be transmitted to a queue according to their priority.

13. The communication system of claim 8, wherein the processor circuitry is further configured to execute program instructions to: after transmitting data packets in a low-latency mode for a protection period, determine whether the second data packet currently scheduled for transmission is a high-priority packet; and if it is determined that the second data packet is not a high-priority packet, transmit the data packet in a normal mode.

14. The communication system of claim 8, wherein the processor circuitry is further configured to execute program instructions to: transmit data packets in a low-latency mode using a space-time block coding space-time block coding (STBC) transmission method, lower transmission bandwidth, low quadrature amplitude modulation (QAM), and / or dual-carrier modulation (DCM) / extended range ER rate.

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