5g message resource pushing system and method for education field

Abstract

The present application relates to the technical field of wireless communication baseband chip data flow scheduling, and discloses a 5G message resource pushing system and method for the education field, which comprises the following steps: a hardware demultiplexing module demultiplexes wireless signals into downlink data packets; a routing arbitration module processes the downlink data packets to generate routing control words; a direct memory access control module controls the shunting of signaling data packets and multimedia slice messages according to the routing control words; and a topology control module monitors the cache space occupation and locks the double-channel queue topology state when the change rate gradient of the cache queue occupation rate is greater than the congestion threshold, thereby blocking queue merging. The present application cuts off the head-of-line blocking of burst signaling caused by high-bandwidth media flow, suppresses the bus deadlock caused by frequent switching, improves the processing time delay certainty, and reduces the on-chip bus power consumption.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication baseband chip data stream scheduling technology, and particularly relates to a 5G message resource push system and method for the education field. Background Technology

[0002] Currently, in cellular communication services, the temporary storage of downlink heterogeneous data streams typically relies on a linear linked list between the network service layer and the data link layer. The common practice is to divide the receive buffer into a static queue, and complete the packet movement and sequential distribution through periodic bus polling. This storage pool framework maintains the throughput balance between the protocol stack bottom and the application layer, and is the mainstream technology for current wireless communication protocol processing. The underlying mechanism of baseband chip protocol distribution relies on the cooperation of bus cycles and hardware demultiplexing modules. The digital code stream received by the channel is written into the storage space formed by static random access memory. The protocol microcode parser reads the hardware packet header field to extract the routing mark, and finally relies on the hardware state machine to maintain the internal state transition of the protocol stack.

[0003] However, when the processor faces the specific high-concurrency conditions of the system, with sudden media slices and high-frequency signaling intertwined, the existing framework reveals physical defects. Large volumes of media packets transiently occupy storage space, and the linear single queue, lacking spatial orthogonal isolation, causes critical short signaling packets to encounter physical head-of-line blocking, hindering microcode state machine transitions and inducing link-layer retransmissions. This results in the internal bus being filled with repeated interrupt requests, ultimately causing power consumption and overheating. To eliminate blocking, increasing memory capacity leads to increased manufacturing costs and static leakage current, and cannot eliminate resource preemption within the queue. Introducing rigid priority gating, under deep fading noise disturbances in the channel, can cause the media stream to fall into scheduling starvation deadlock due to prolonged inability to acquire bus cycles. It is clear that the above improvement approaches cannot provide an effective solution due to triggering new constraint conflicts. Besides the limitations of adjusting the physical cache architecture, the underlying... The layer control methods and signal shifting strategies also have shortcomings. For example, Chinese invention patent CN106230443B discloses a baseband downlink signal processing device that uses a multi-core system in conjunction with hardware units to complete downlink data reception and continuous address shifting. However, this scheduling mechanism implicitly relies on the traditional carrier throughput environment with stable service load. In the face of complex working conditions with high-bandwidth media slicing and sudden signaling, it lacks on-chip bus dynamic weight adjustment and queue topology space isolation methods for heterogeneous data streams. It cannot perceive the gradient of the transient rate of change of the buffer space. When faced with the continuous injection of ultra-wideband massive media packets, it cannot smooth out the frequent switching of scheduling states caused by frequent fluctuations in the wireless channel. Not only can it not eliminate the physical head-of-line blockage of control signaling caused by multimedia backlog, it is also easy for the protocol processor to fall into the bottleneck of bus deadlock and abnormal power consumption.

[0004] Therefore, the technical problem to be solved by this invention is how to provide a 5G message resource push system for the education field that can achieve spatial isolation and timing adaptive arbitration of data flow topology within a single buffer, and eliminate the delay loss caused by media backlog to bus speed. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A 5G message resource push system for the education field, the system comprising: The hardware demultiplexing module is used to demultiplex downlink cellular radio signals into downlink data packets; The routing arbitration module is used to process downlink data packets according to the feedforward gated routing algorithm to generate the first routing control word and the second routing control word; The direct memory access control module is used to attach control signaling data packets to the head of the signaling-level high-priority logical topology sub-queue according to the first routing control word, and to input multimedia slice data packets to the tail of the media-level broadband logical topology sub-queue according to the second routing control word. The topology control module includes a cache occupancy monitoring module and a hysteresis flow control state determination module. The cache occupancy monitoring module is used to collect the storage space occupancy at a sampling period of 2ms and generate a gradient of the cache queue occupancy rate change rate. The hysteresis flow control state determination module is used to lock the dual-channel queue topology state composed of signaling-level high-priority logical topology sub-queues and media-level broadband logical topology sub-queues when the gradient of the cache queue occupancy rate change rate is greater than the critical congestion gradient threshold, and to block the merging of the dual-channel queue topology state within a 15ms lockout period. The timing adaptive adjustment module is used to adjust the bus service weight based on the real-time delay time of the dual-channel queue topology.

[0006] Preferably, the routing arbitration module includes a hardware-level header extraction module and a Bloom filter hash mapping module; the hardware-level header extraction module is used to extract the physical packet length feature parameter and service type field of the downlink data packet; the Bloom filter hash mapping module is used to hash the service type field to the data flow type identification result, and the feedforward gated routing algorithm generates the first routing control word when the physical packet length feature parameter is less than or equal to 128B.

[0007] Preferably, the feedforward gated routing algorithm generates a second routing control word when the physical packet length characteristic parameter of the downlink data packet is greater than 128B, which drives the direct memory access control module to input the multimedia slice data packet to the tail of the media-level broadband logical topology subqueue.

[0008] Preferably, within a 15ms deadlock period, even if the gradient of the rate of change of the cache queue generated by the cache occupancy monitoring module falls back to below the critical congestion gradient threshold, the hysteresis flow control state determination module blocks the merging of the dual-channel queue topology state.

[0009] Preferably, the signaling-level high-priority logical topology subqueue and the media-level broadband logical topology subqueue are cascaded at the acceleration interface of the chip's internal bus module to enable control signaling data packets to bypass the general network layer parsing queue.

[0010] Preferably, the cache utilization monitoring module includes a clock counting module and a status sampling module; the status sampling module is used to sample the storage space utilization within a fixed clock cycle, and the clock counting module is used to calculate the gradient of the cache queue utilization rate based on the ratio of the difference between the current storage space utilization and the previous sampling cycle to the 2ms sampling cycle.

[0011] Preferably, the topology control module further includes a threshold comparison module; the threshold comparison module is used to compare the gradient of the rate of change of the cache queue occupancy rate with the critical congestion gradient threshold, and to maintain the locked state of the dual-channel queue topology when the gradient of the rate of change of the cache queue occupancy rate is greater than the critical congestion gradient threshold.

[0012] Preferably, the output end of the media-level broadband logical topology sub-queue is connected to an educational resource unpacking module; the educational resource unpacking module is used to read multimedia slice data packets from the head of the media-level broadband logical topology sub-queue and extract multimedia educational resource streams from them.

[0013] Preferably, the system also includes a chip microcode control module; the chip microcode control module is connected to the topology control module and the timing adaptive adjustment module, and is used to dynamically adjust the allocation timing of system resources according to the bus service weight.

[0014] A method for pushing 5G messaging resources in the education sector, implemented through a 5G messaging resource push system for the education sector, includes the following steps: Step S1: The hardware demultiplexing module demultiplexes the downlink cellular radio signal into downlink data packets; In step S2, the routing arbitration module processes the downlink data packets according to the feedforward gated routing algorithm to generate the first routing control word and the second routing control word. Step S3: The direct memory access control module attaches the control signaling data packet to the head of the signaling-level high-priority logical topology sub-queue according to the first routing control word, and inputs the multimedia slice data packet to the tail of the media-level broadband logical topology sub-queue according to the second routing control word. Step S4: The cache occupancy rate monitoring module in the topology control module collects the storage space occupancy at a sampling period of 2ms and generates a gradient of the cache queue occupancy rate change rate. When the gradient of the cache queue occupancy rate change rate is greater than the critical congestion gradient threshold, the hysteresis flow control state determination module locks the dual-channel queue topology state composed of the signaling-level high-priority logical topology sub-queue and the media-level broadband logical topology sub-queue, and blocks the merging of the dual-channel queue topology state within a 15ms lockout period. Step S5: The timing adaptive adjustment module adjusts the bus service weight based on the real-time delay time of the dual-channel queue topology status.

[0015] Compared with existing technologies, the 5G message resource push system of this invention for the education field has the following advantages: 1. In 5G message resource push for the education sector, the cache occupancy monitoring unit collects the transient space occupancy of the downlink receiving buffer at fixed intervals and uses a digital differential to calculate the gradient of the cache queue occupancy rate change. When the gradient exceeds the preset critical congestion gradient threshold, the topology controller is triggered to start the feedforward topology fission rule, which converts the single linked list space into mutually orthogonal and logically isolated signaling-level high-priority logical topology sub-queues and media-level broadband logical topology sub-queues. This multi-queue collaborative transformation cuts off the congestion propagation path between heterogeneous data streams at the spatial level, allowing high-frequency burst signaling to get rid of the physical preemption of on-chip storage space by large-volume media data packets, and ensuring the latency determinism of the protocol layer when carrying high-bandwidth media streams.

[0016] 2. The routing arbitration unit is cascaded at the output of the hardware demultiplexing module. It extracts the physical packet length feature parameters and service type field of the downlink data packets, uses the embedded feedforward gated routing operator to complete the logical convergence calculation and generate the first routing control word and the second routing control word. It drives the direct memory access controller to bypass the general network layer parsing queue and attach the low-latency control signaling data packets to the head of the signaling-level high-priority logical topology sub-queue in place. This linkage flow path based on hardware-level header extraction and Bloom filter hash mapping eliminates the microprocessor computing load and microcode execution delay caused by cross-layer protocol stack parsing flow. It works closely with the aforementioned queue topology transformation and provides traffic splitting and isolation.

[0017] 3. The hysteresis flow control state determination module embedded in the topology controller forcibly locks the current heterogeneous dual-channel queue topology state when the feedforward topology fission rule is activated. Within the rigid 15ms state lock-up period, even if the gradient of the rate of change of the buffer queue occupancy rate falls back to below the critical congestion gradient threshold, the queue merging logic is prohibited. This constraint effectively controls the frequent switching of flow control state caused by deep channel fading under the impact of high-concurrency network resources, eliminates the logic bounce loss caused by the microcode level frequently reconstructing the topology within the bus cycle, avoids the risk of bus deadlock caused by the interrupt response limit of the protocol processor, and maintains the stability of the control bus in the wireless channel environment. Attached Figure Description

[0018] Figure 1 This is a flowchart of the 5G message resource push method with feedforward gated routing and topology state control according to the present invention; Figure 2 This is a scheduling diagram of the 5G message resource push system based on the multi-dimensional flow control mechanism and dual-channel queue of this invention. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] A 5G messaging resource push system for the education sector, the system includes: The hardware demultiplexing module is used to demultiplex downlink cellular radio signals into downlink data packets; The routing arbitration module is used to process downlink data packets according to the feedforward gated routing algorithm to generate the first routing control word and the second routing control word; The direct memory access control module is used to attach control signaling data packets to the head of the signaling-level high-priority logical topology sub-queue according to the first routing control word, and to input multimedia slice data packets to the tail of the media-level broadband logical topology sub-queue according to the second routing control word. The topology control module includes a cache occupancy monitoring module and a hysteresis flow control state determination module. The cache occupancy monitoring module is used to collect the storage space occupancy at a sampling period of 2ms and generate a gradient of the cache queue occupancy rate change rate. The hysteresis flow control state determination module is used to lock the dual-channel queue topology state composed of signaling-level high-priority logical topology sub-queues and media-level broadband logical topology sub-queues when the gradient of the cache queue occupancy rate change rate is greater than the critical congestion gradient threshold, and to block the merging of the dual-channel queue topology state within a 15ms lockout period. The timing adaptive adjustment module is used to adjust the bus service weight based on the real-time delay time of the dual-channel queue topology.

[0021] Preferably, the routing arbitration module includes a hardware-level header extraction module and a Bloom filter hash mapping module; the hardware-level header extraction module is used to extract the physical packet length feature parameter and service type field of the downlink data packet; the Bloom filter hash mapping module is used to hash the service type field to the data flow type identification result, and the feedforward gated routing algorithm generates the first routing control word when the physical packet length feature parameter is less than or equal to 128B.

[0022] Preferably, the feedforward gated routing algorithm generates a second routing control word when the physical packet length characteristic parameter of the downlink data packet is greater than 128B, which drives the direct memory access control module to input the multimedia slice data packet to the tail of the media-level broadband logical topology subqueue.

[0023] Preferably, within a 15ms deadlock period, even if the gradient of the rate of change of the cache queue generated by the cache occupancy monitoring module falls back to below the critical congestion gradient threshold, the hysteresis flow control state determination module blocks the merging of the dual-channel queue topology state.

[0024] Preferably, the signaling-level high-priority logical topology subqueue and the media-level broadband logical topology subqueue are cascaded at the acceleration interface of the chip's internal bus module to enable control signaling data packets to bypass the general network layer parsing queue.

[0025] Preferably, the cache utilization monitoring module includes a clock counting module and a status sampling module; the status sampling module is used to sample the storage space utilization within a fixed clock cycle, and the clock counting module is used to calculate the gradient of the cache queue utilization rate based on the ratio of the difference between the current storage space utilization and the previous sampling cycle to the 2ms sampling cycle.

[0026] Preferably, the topology control module further includes a threshold comparison module; the threshold comparison module is used to compare the gradient of the rate of change of the cache queue occupancy rate with the critical congestion gradient threshold, and to maintain the locked state of the dual-channel queue topology when the gradient of the rate of change of the cache queue occupancy rate is greater than the critical congestion gradient threshold.

[0027] Preferably, the output end of the media-level broadband logical topology sub-queue is connected to an educational resource unpacking module; the educational resource unpacking module is used to read multimedia slice data packets from the head of the media-level broadband logical topology sub-queue and extract multimedia educational resource streams from them.

[0028] Preferably, the system also includes a chip microcode control module; the chip microcode control module is connected to the topology control module and the timing adaptive adjustment module, and is used to dynamically adjust the allocation timing of system resources according to the bus service weight.

[0029] A method for pushing 5G messaging resources in the education sector, implemented through a 5G messaging resource push system for the education sector, includes the following steps: Step S1: The hardware demultiplexing module demultiplexes the downlink cellular radio signal into downlink data packets; In step S2, the routing arbitration module processes the downlink data packets according to the feedforward gated routing algorithm to generate the first routing control word and the second routing control word. Step S3: The direct memory access control module attaches the control signaling data packet to the head of the signaling-level high-priority logical topology sub-queue according to the first routing control word, and inputs the multimedia slice data packet to the tail of the media-level broadband logical topology sub-queue according to the second routing control word. Step S4: The cache occupancy rate monitoring module in the topology control module collects the storage space occupancy at a sampling period of 2ms and generates a gradient of the cache queue occupancy rate change rate. When the gradient of the cache queue occupancy rate change rate is greater than the critical congestion gradient threshold, the hysteresis flow control state determination module locks the dual-channel queue topology state composed of the signaling-level high-priority logical topology sub-queue and the media-level broadband logical topology sub-queue, and blocks the merging of the dual-channel queue topology state within a 15ms lockout period. Step S5: The timing adaptive adjustment module adjusts the bus service weight based on the real-time delay time of the dual-channel queue topology status.

[0030] Example 1: In the data stream scheduling loop of the wireless communication baseband chip for the burst push of multimedia message resources in the preset theme teaching simulation environment, the downlink cellular wireless signal is mixed with the transmission of a large amount of media data stream and a high-frequency burst control signaling stream. Since the large-size multimedia slice data packets and the low-latency control signaling short packets compete for the on-chip storage space of the chip network protocol processing layer, the unified physical buffer area will instantly become congested due to the lack of spatial isolation. This will cause the subsequent control signaling packets to encounter long-term physical head-of-line blocking, causing the underlying protocol stack to retransmit at the wireless link layer. This will cause the processor's internal bus to generate a physical layer retransmission interrupt request, resulting in an increase in the chip's on-chip bus power consumption and heat loss. It will also cause functional degradation problems such as data stream reception timing loss and control interaction deadlock on the multi-mode interactive remote terminal side.

[0031] When the system faces a sudden surge in traffic caused by the aforementioned multimedia message resource push, the cache utilization monitoring unit running at the chip network protocol processing layer collects the transient space occupancy of the on-chip static random access memory physical cache area at a sampling period of 2ms. The continuous time window is calculated using a built-in digital differencer. Gradient of change in cache queue occupancy rate Calculate the expression that satisfies the linear operator. ,in, The gradient of the rate of change of cache queue occupancy. This represents the storage space usage for the current sampling period. This represents the storage space usage of the previous sampling period. The sampling period is 2ms; the cache occupancy monitoring unit will calculate the gradient of the real-time cache queue occupancy rate change. The data is sent to the topology controller, which then... Compared with the preset critical congestion gradient threshold Complete the numerical comparison and determination, when Greater than At this time, the topology controller triggers the feedforward topology splitting rule, suspending the flattened singly linked list allocation method of the on-chip static random access memory (SRAM) cache space. It then divides the physical address space held by the SRAM physical cache into mutually orthogonal and logically isolated signaling-level high-priority logical topology subqueues and media-level broadband logical topology subqueues. The physical address boundaries of the signaling-level high-priority logical topology subqueues are rigidly defined to reserve 15% of the resident bus space. This 15% resident memory space reservation is calculated based on the maximum peak throughput engineering requirements of the signaling-level high-priority logical topology subqueues when carrying high-frequency burst control signaling. If the reserved space is lower than this physical lower bound, under extremely high-concurrency multimedia resource loading conditions, the instantaneous influx of short control signaling packets will overflow due to insufficient physical address buffering, leading to an increased packet loss rate in the control signaling stream. This leads to frequent retransmission interruptions at the protocol layer, causing an abnormal increase in on-chip bus power consumption. Furthermore, if the reserved space exceeds the physical upper limit of 15%, it excessively encroaches on the physical storage addresses allocated to the media-level broadband logical topology sub-queues. This causes large-size multimedia slice data packets to frequently trigger network-wide flow control due to limited available storage space, significantly reducing the overall downlink throughput efficiency of multimedia resources. Through engineering boundary constraints addressing these two side effects, a 15% adaptation parameter was ultimately established, balancing signaling latency determinism with multimedia throughput efficiency. Simultaneously with the logical topology fission, the routing arbitration unit initiates environment-adaptive routing, cascaded to the output of the chip hardware demultiplexing module to directly acquire downlink data packets. The feedforward gated routing operator embedded in the routing arbitration unit skips cross-layer service packet parsing and directly extracts the physical packet length feature parameters of each incoming data packet using the hardware-level header extraction module. The service type field is hashed and mapped to a data stream type identification result using a Bloom filter hash mapping module. When the service type field points to high-frequency burst signaling, and the physical packet length feature parameter... When the physical packet length is less than or equal to 128 bytes, the routing arbitration unit generates the first routing control word, which drives the direct memory access control module to bypass the general network layer parsing queue and directly attach the corresponding low-latency control signaling data packet to the head of the signaling-level high-priority logical topology sub-queue. When the physical packet length characteristic parameters... When the length exceeds 128 bytes, a second routing control word is generated, driving the direct memory access control module to input the corresponding multimedia slice data packet to the tail of the media-level broadband logical topology sub-queue. This completes the spatial and temporal splitting of the heterogeneous data stream flow path within the chip. Specifically, the logical convergence calculation process of the feedforward gated routing operator is executed by the gate-level combinational logic hardware state machine within the chip. This operator receives in parallel the 16-bit physical packet length feature data and the 8-bit service type code input from the hardware-level header extraction module. The operator internally establishes a dual-input, single-output logical convergence mapping table, which maps the received physical packet length feature data to a preset packet length threshold of 1. The 28-byte subtraction circuit compares the data in the hardware comparator and outputs a one-bit high / low level marker. The service type code is processed by multi-path parallel hash calculation through a hardware Bloom filter, and outputs a one-bit data stream category identification marker in a single clock cycle. The logic convergence calculation is performed by combining the level marker of the packet length comparison result with the stream category identification marker using an AND gate. Finally, it directly drives the generation of a 2-bit binary routing control word, where binary code 01 represents the first routing control word and binary code 10 represents the second routing control word. Thus, at the hardware flow level, the logic convergence calculation result is directly output as a control instruction to the direct memory access control module.

[0032] The cache utilization monitoring module collects the storage space occupancy of the static random access memory physical cache area within a fixed clock cycle through an internal hardware counter. The difference between the storage space occupancy of the current sampling period and the previous sampling period is subtracted by the hardware subtraction circuit of the on-chip digital differential. The resulting byte difference is shifted to the right in the hardware shift register according to the 2-millisecond sampling period to calculate the gradient of the cache queue utilization rate change rate, and then sent to the topology control module hysteresis flow control status determination module.

[0033] When the gradient of the rate of change of cache queue occupancy exceeds the critical congestion gradient threshold and the hysteresis flow control state determination module initiates the feedforward topology fission rule, the direct memory access control module issues a hardware-level pause signal and interrupts the current write request. The microcode controller reads the active tail pointer of the current flat singly linked list and remaps the corresponding base address to the head of the media-level broadband logical topology sub-queue to carry the existing data. The dynamic address mapping unit rewrites the hard boundary register of the static random access memory controller to isolate a resident memory bus space accounting for 15% of the total capacity in the physically continuous high-end space domain, and binds the starting physical address to the signaling-level high-priority logical topology sub-queue head pointer. The space isolation switch is completed within 4 system clock cycles, and after the write enable of the direct memory access control module is restored, the subsequent heterogeneous data streams are assigned to the corresponding topology sub-queue.

[0034] To suppress bus scheduling uncertainty jitter caused by frequent microcode interrupts under high concurrency, the hysteretic flow control state determination module embedded in the topology controller locks the current dual-channel queue topology state when the feedforward topology fission rule is activated. During this rigidly limited 15ms lockout period, even if the cache occupancy monitoring unit collects and generates the gradient of the cache queue occupancy rate change, the system will remain locked. Falling back to the critical congestion gradient threshold The hysteresis flow control state determination module also blocks the merging of the dual-channel queue topology state, thereby eliminating the overhead of memory space linked list rearrangement caused by frequent microcode topology reconstruction. At the same time, as a backup defense mechanism, the timing adaptive adjustment module continuously monitors and reads the real-time processing latency of the media-level broadband logical topology sub-queues through the microcode register. Real-time processing latency of high-priority logical topology subqueues at the signaling level The time delay differential deviation is calculated by the internal subtractor. ,in, This is the time delay differential deviation. The real-time processing latency of the media-level broadband logical topology subqueue. The real-time processing latency of the high-priority logical topology subqueue at the signaling level is measured in the latency differential deviation. When the first derivative exceeds the safe convergence boundary window, the timing adaptive adjustment module dynamically rewrites the weight matrix of the internal loop bus arbiter, tilting the bus service weights towards the latency degradation side. The adjustment magnitude of the bus service weights is related to... The first derivative is positively correlated. This dual-channel queue topology, in conjunction with dynamic weight arbitration, cuts off the physical preemption of high-bandwidth media push streams on burst control signaling, stabilizing the queuing delay of the signaling-level high-priority logic topology sub-queue within the range of 11.5ms to 15.3ms. The packet loss rate of the control signaling stream remains at 0, reducing the on-chip bus power consumption by 12.6% compared to the unlocked state. It also maintains the stable operation of the data flow scheduling control bus inside the wireless communication baseband chip. In actual operation, the specific control algorithm for dynamically rewriting the weight matrix of the internal loop bus arbiter is implemented through the register configuration logic in the hardware timing adaptive adjustment module. The loop bus arbiter holds a 4x4 initial weight matrix allocated to the dual-channel queue by default, corresponding to a default service cycle ratio of 50% to 50% for the signaling-level queue and the media-level queue. When the first derivative of the time delay differential deviation exceeds the preset safe convergence boundary window of ±2 milliseconds per microsecond, the excess increment calculated by the hardware subtraction circuit is sent to the timing allocation state machine. The state machine updates the weights in the registers based on this increment through the shift-add circuit. The coefficient value is adjusted by increasing the bus service priority weight of the latency degradation side queue by 5% each time, while simultaneously reducing the bus service weight of the non-degradation side by an equal amount of 5%. The rewritten weight data directly overwrites the current control register of the bus arbiter. Thus, by changing the ratio of the bus clock enable cycle, the system resource allocation timing is dynamically reconstructed at the chip hardware level. When the first derivative of the latency differential deviation exceeds the convergence boundary of ±2 milliseconds per microsecond, the timing adaptive adjustment module temporarily stores the calculated adjustment allocation weight parameters in the on-chip shadow register. The hardware monitoring circuit determines the bus idle state by continuously capturing the bus transmission end signal of the internal bus data transmission link. Once the bus is idle, the weight update state machine uses the new weight parameters in the shadow register to overwrite the current control register of the bus arbiter at the rising edge of the single system clock pulse. The bus service weight of the latency degradation side logical topology sub-queue is gradually increased by 5% each time to the upper limit of the threshold of 85% of the bus transmission bandwidth. The system resource allocation timing is reconstructed while maintaining the basic service cycle of the non-degradation side logical topology sub-queue.

[0035] Example 2: In a wireless communication baseband chip test and verification platform environment jointly constructed by a hardware simulation accelerator and a chip network protocol processor core, the test platform actively superimposes Gaussian white noise with a signal-to-noise ratio of 20dB and injects power frequency interference harmonics at a frequency of 50Hz onto the wireless signal input end to simulate the deep fading and electromagnetic noise environment of mobile cellular network channels. This is used to monitor the transient space occupancy of the on-chip static random access memory physical cache area. Sampling period The setting is based on a causal balance between the characteristics of bursty data streams and processor logic overhead. One technical factor is the transient bandwidth fluctuations of bursty message resource streams, and the other is the core throughput overhead of the baseband processor. When the bandwidth of the bursty data packet stream caused by multimedia message resource pushes increases, to avoid signal aliasing during data feature reconstruction and to ensure the capture of complete physical head-of-line congestion characteristics, the sampling period... The sampling period tends towards the lower limit of its value window. However, excessively reducing the sampling period will cause the processor to read registers at high frequencies, leading to an abnormal increase in on-chip bus power consumption. Under this technical constraint, for typical multimedia teaching resource push scenarios with sub-throughput reaching megabits per second, a suitable numerical range is obtained by establishing a discrete state judgment equation for sampling change gradient perception, and the sampling period is determined. The set value is 2ms. During the benchmark determination phase, the test platform inputs the original received signal stream containing the aforementioned Gaussian white noise and power frequency interference to the receiving end. The control group adopts a single-link buffer allocation mechanism, while the test group introduces a feedback closed loop consisting of a buffer occupancy monitoring module and a topology control module. In five consecutive sampling points, the buffer occupancy monitoring module reads the physical buffer space occupancy. The gradients of the rate of change of cache queue occupancy, calculated by a digital differential, are 1024B, 3125B, 7198B, 14412B, and 26715B, respectively. It exhibits an increasing trend, and the specific numerical sequences calculated are 1050.5 B / ms, 2036.5 B / ms, 3607.0 B / ms, and 6151.5 B / ms, respectively. The calculations satisfy the linear operator equation. ,in, The gradient of the rate of change of cache queue occupancy. This represents the storage space usage for the current sampling period. This represents the storage space usage of the previous sampling period. The sampling period is defined as the period when the fifth sampling point is generated. The congestion rate reached 6151.5 B / ms and exceeded the preset critical congestion gradient threshold. At that time, the hysteresis flow control state determination module in the topology control module starts the feedforward topology splitting rule, divides the physical buffer space into logically isolated signaling-level high-priority logical topology sub-queues and media-level broadband logical topology sub-queues, and locks the current dual-channel queue topology state.

[0036] To establish the stability of the logical isolation boundary and the rationality of the parameter window, the test platform was configured with a multi-dimensional test array including a first missing control group, a second missing control group, a first out-of-range control group, and a second out-of-range control group. The first missing control group lacked a hysteresis flow control state determination module, the second missing control group lacked a timing adaptive adjustment module, the first out-of-range control group had a state lock-up period set to 5ms, and the second out-of-range control group had a state lock-up period set to 50ms. Under high-order interference conditions with high-throughput congestion, in the control group using a single-link buffer allocation mechanism, due to the suppression of short signaling packets by large-size multimedia slice data packets, the measured control signaling flow queuing delay time increased to 148.62ms, and the packet loss rate of the control signaling flow reached 8.43% due to buffer overflow, triggering high-frequency retransmission interruptions at the protocol layer, and the measured on-chip bus power consumption increased to 412.53mW. Meanwhile, under the same congestion intensity... Under interference conditions, the experimental group, under the joint control of the feedforward topology splitting rule and the 15ms state lock-up period, reserved 15% of the resident bus space at the physical address boundary of the signaling-level high-priority logical topology sub-queue. Its measured control signaling stream processing latency remained within the characteristic range of 11.53ms to 15.28ms, the packet loss rate decreased to 0, and the bus power consumption decreased to 231.42mW, exhibiting a non-linear control adjustment state. The first missing control group and the first out-of-range control group, lacking sufficient hysteresis lock-up protection period, experienced high-frequency reconstruction of the storage topology by their internal processors under downlink sudden network fluctuations, leading to scheduling oscillation losses on the microcode bus. Their bus power consumption increased to 386.74mW, demonstrating the technical necessity of using a 15ms lock-up period to eliminate topology switching losses. The second missing control group, lacking a timing adaptive adjustment module for dynamic adjustment of bus service weights, experienced a decrease in the latency of its media-level broadband logical topology sub-queue. The saturation backlog occurred and increased to 325.84ms, causing the broadband multimedia stream to be interrupted by the protocol layer response. The second out-of-range control group remained at 50ms due to the excessively long state lock-in period. It could not dynamically reclaim the storage address space as the downlink burst congestion was eliminated, which limited the reuse efficiency of the physical buffer space. Its measured average protocol throughput delay jitter increased by 42.56%.

[0037] Based on the time-domain response data collected under different congestion intensity gradients, the experimental group maintained the stability of the data link under the action of the physical feature diversion mechanism. Through the discrete differential calculation of storage space occupancy by the cache occupancy monitoring module, the topology control module's partitioning action was triggered. Combined with the multi-dimensional physical feature criteria of the routing arbitration module, under the condition of simultaneous input of large-size multimedia slice data packets and high-frequency burst control signaling, different types of data packets were spatiotemporally isolated on the protocol processor bus link, suppressing the hardware interruption overhead caused by frequent topology changes and reducing the latency differential deviation. Forced convergence is achieved within the safe convergence boundary window, and the time delay deviation equation is satisfied. ,in, This is the time delay differential deviation. The real-time processing latency of the media-level broadband logical topology subqueue. To reduce the real-time processing delay of the signaling-level high-priority logic topology sub-queue, this method controls the packet loss rate of the control signaling flow to 0 while maintaining the original capacity of the on-chip memory hardware entity, and reduces the on-chip bus power consumption by 12.6%, thus maintaining the stable operation of the physical channel of the data flow scheduling bus inside the wireless communication baseband chip.

[0038] Example 3: When the system faces the condition that the throughput of ultra-wideband message resources reaches the upper limit of the on-chip bus transmission bandwidth of the wireless communication baseband chip, the downlink receiving physical buffer is continuously flooded with media data packet streams. The consumption rate of the physical buffer space of the static random access memory approaches the physical limit of the storage medium, and the free blocks in the physical buffer area show a decreasing trend. Under this state, the arrival rate of burst control signaling packets synchronously reaches the peak wake-up frequency of the retransmission state machine of the wireless link layer protocol stack. This causes the head-of-queue blockage at the on-chip system bus interface due to the space sharing of the single-queue storage management architecture, resulting in control interaction delay.

[0039] Driven by the clock signal of the static random access memory controller, the cache utilization monitoring unit collects the transient space occupancy of the physical cache area at a sampling period of 2ms. The data in this storage space is then sent to the on-chip differential processor to calculate the continuous time window. Gradient of change in cache queue occupancy rate Calculate to satisfy the equation ,in, The gradient of the rate of change of cache queue occupancy. This represents the storage space usage for the current sampling period. This represents the storage space usage of the previous sampling period. The sampling period is 2ms; the gradient of the rate of change of the cache queue occupancy rate. Greater than the preset critical congestion gradient threshold At this time, the topology control module terminates the singly linked list allocation method of the on-chip static random access memory (SRAM) cache space, divides the physical address space held by the SRAM physical cache area into mutually orthogonal and spatially isolated signaling-level high-priority logical topology sub-queues and media-level broadband logical topology sub-queues, and marks the physical address boundaries of the signaling-level high-priority logical topology sub-queues to reserve 15% of the storage bus space; while the on-chip SRAM storage address space is being divided, the routing arbitration unit connects to the output of the hardware demultiplexing module to obtain downlink data packets, and the on-chip header extraction hardware circuit intercepts the data packet header and extracts its physical packet length characteristic parameters. The data stream category is determined using a Bloom filter circuit based on the hash value of the service type field. This applies when the service type field points to control signaling and the physical packet length characteristic parameter... When the length is less than or equal to 128 bytes, the first routing control word is output to drive the direct memory access control module, which directly mounts the control signaling data packet to the head of the high-priority logical topology sub-queue across the general network layer parsing queue. When the physical packet length characteristic parameters... When the length is greater than 128 bytes, a second routing control word is output to drive the direct memory access control module, inputting the corresponding multimedia slice data packet to the tail of the media-level broadband logical topology sub-queue. To eliminate potential contradictions between the physical packet length feature parameter determination and the Bloom filter hash mapping result under extreme abnormal conditions, this invention configures a dimensionality reduction arbitration hardware logic within the routing arbitration unit. When the Bloom filter hash mapping result identifies the data packet as multimedia slice data, but the physical packet length feature parameter measured by the hardware-level header extraction module is less than or equal to 128 bytes, the dimensionality reduction arbitration logic executes to control the packet length. The security-first decision rule reduces the dimensionality of the Bloom filter output, determines the current data packet as an ultra-short control frame carrying control signaling, and generates the first routing control word. Conversely, if the Bloom filter maps the service type field to high-frequency burst signaling, but the physical packet length feature parameter is greater than 128 bytes, the dimensionality reduction arbitration logic determines it as an abnormally grouped multimedia pseudo-signaling stream. To prevent storage space from being preempted by large packets, it is forcibly classified as a multimedia data packet based on the absolute priority of the physical packet length feature and a second routing control word is generated, thus establishing a completely deterministic two-dimensional conflict resolution mapping path.

[0040] When the storage bus data throughput rate reaches its limit and the scheduling overhead reaches its maximum load, the hysteresis flow control state determination module embedded in the topology control module forcibly locks the current heterogeneous dual-channel queue topology state when the feedforward topology fission condition is met. Within this 15ms lockout maintenance period, even if the gradient of the cache queue occupancy rate obtained from discrete sampling calculations is not considered... Falling back to the critical congestion gradient threshold The hysteresis flow control state determination module also blocks the merging operation of heterogeneous dual-channel queue topology states to eliminate the overhead of memory space linked list rearrangement caused by microcode scheduling topology switching; at the same time, the backup timing adaptive adjustment module continuously monitors and reads the real-time processing latency of the media-level broadband logical topology sub-queue through the baseband microcode register. Real-time processing latency of high-priority logical topology subqueues at the signaling level The time delay differential deviation is calculated by the internal subtractor. ,in, This is the time delay differential deviation. The real-time processing latency of the media-level broadband logical topology subqueue. The real-time processing latency of the high-priority logical topology subqueue at the signaling level is measured in the latency differential deviation. When the first derivative exceeds the preset convergence boundary window, the timing adaptive adjustment module dynamically rewrites the weight matrix of the internal loop bus arbiter, tilting the bus service weight towards the delay side. The adjustment range of the bus service weight is related to... The first derivative is positively correlated; to prevent severe oscillations in system scheduling due to overcompensation when the bus service weight is tilted between the two channels, the timing adaptive adjustment module integrates an anti-saturation smoothing mechanism with dead-zone suppression and dynamic upper limit interception. When the increase in bus service weight increases positively with the first derivative of the delay differential deviation, the arbitrator sets a hard safety threshold upper limit of up to 85% of the bus bandwidth to ensure that the bus allocation weight obtained by any single queue cannot block the basic life cycle of the other queue. At the same time, when the first derivative of the calculated delay differential deviation falls back to the preset dead-zone threshold, i.e., within 0.5 milliseconds per microsecond, the weight update state machine will automatically freeze the current matrix configuration and prohibit the bus service weight. Frequent high-frequency flips occur. Through this closed-loop state decoupling path based on boundary truncation and hysteresis dead-zone control, the system can effectively eliminate bus oscillation losses caused by alternating saturation of the two-level queues while eliminating multimedia backlog with tilted weights. The coordinated operation of this heterogeneous dual-channel queue topology and dynamic weight arbitration cuts off the physical preemption of burst control signaling data packets by the high-bandwidth multimedia message push stream, stabilizes the queuing delay of the signaling-level high-priority logic topology sub-queue within the range of 11.5ms to 15.3ms, keeps the packet loss rate of the control signaling stream at 0, reduces the on-chip bus power consumption by 12.6% compared to the unlocked state, and maintains the stable operation of the internal data flow scheduling and control bus of the wireless communication baseband chip under preset boundary input conditions.

[0041] Example 4: When the system faces the conditions of chip power-on initialization and physical reference benchmark establishment, the chip network protocol processor, in a static state without network traffic load, uses an on-chip hardware counter to continuously read the storage space occupancy for 100 sampling cycles and calculate the arithmetic mean, thereby establishing the initial cache reference value of the static random access memory physical cache area. Next, the test platform incrementally feeds simulated data packet streams to the receiving end through the simulation signal interface until the head-of-line congestion state machine of the on-chip system bus triggers the first congestion alarm. The system latches the dynamic rate of change at this point in situ and uses it as the critical congestion gradient threshold. The data is written into the register and serves as the sole physical criterion for initiating subsequent feedforward topology splitting rules. Specifically, the head-of-line congestion state machine includes four internal states constructed from register logic: idle, warning, alarm, and locked. During the simulation signal increment injection phase, the state machine is in the idle state by default. When the queuing depth of the physical buffer of the on-chip system bus exceeds 70% of the full capacity for three consecutive clock cycles, the state machine transitions to the warning state. When the queuing depth continues to climb and reaches 85% of the full capacity for the first time, and at the same time, the count of retransmission requests for pending signaling messages on the chip's internal interrupt request bus accumulates to more than 10 times within 5 microseconds, the state machine triggers and outputs a high-level pulse, which is the triggering of the first congestion alarm. This quantitative judgment criterion establishes the absolute logical criteria for the state machine's state transition by combining the hard index of physical buffer depth with the retransmission interrupt frequency.

[0042] In the physical environment of an educational communication network where multimedia push services are continuously running, the increase in static leakage current of the storage lattice due to chip temperature rise affects the aforementioned initial cache reference value. Nonlinear physical drift that varies with temperature occurs. To correct measurement deviations caused by thermal effects, the timing adaptive adjustment module triggers on-chip calibration microcode when it detects that the bus idle period lasts for more than 50ms. The latest memory space occupancy measurement data is smoothed and denoised using a low-pass filtering algorithm, and the initial cache reference value in the register is dynamically rewritten using a sliding time window overlap method. This causes the gradient of the rate of change of the current cache queue occupancy. The differential calculation is always based on the dynamic calibration benchmark. Under this dynamic hedging mechanism of physical parameters, even if the electromagnetic interference waveform of the externally injected channel causes transient fluctuations, each isolated logic topology sub-queue can maintain stable data flow transmission within the state lock-up maintenance period. Finally, the processing delay of the control signaling flow is always maintained within the preset convergence window as the internal temperature gradient of the chip evolves.

[0043] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A 5G messaging resource push system for the education sector, characterized in that, The system includes: The hardware demultiplexing module is used to demultiplex downlink cellular radio signals into downlink data packets; The routing arbitration module is used to process downlink data packets according to the feedforward gated routing algorithm to generate the first routing control word and the second routing control word; The direct memory access control module is used to attach control signaling data packets to the head of the signaling-level high-priority logical topology sub-queue according to the first routing control word, and to input multimedia slice data packets to the tail of the media-level broadband logical topology sub-queue according to the second routing control word. The topology control module includes a cache occupancy monitoring module and a hysteresis flow control state determination module. The cache occupancy monitoring module is used to collect the storage space occupancy at a sampling period of 2ms and generate a gradient of the cache queue occupancy rate change rate. The hysteresis flow control state determination module is used to lock the dual-channel queue topology state composed of signaling-level high-priority logical topology sub-queues and media-level broadband logical topology sub-queues when the gradient of the cache queue occupancy rate change rate is greater than the critical congestion gradient threshold, and to block the merging of the dual-channel queue topology state within a 15ms lockout period. The timing adaptive adjustment module is used to adjust the bus service weight based on the real-time delay time of the dual-channel queue topology.

2. The 5G message resource push system for the education field according to claim 1, characterized in that, The routing arbitration module includes a hardware-level header extraction module and a Bloom filter hash mapping module. The hardware-level header extraction module is used to extract the physical packet length feature parameter and service type field of downlink data packets. The Bloom filter hash mapping module is used to hash the service type field to the data flow type identification result. The feedforward gated routing algorithm generates the first routing control word when the physical packet length feature parameter is less than or equal to 128B.

3. A 5G message resource push system for the education field according to claim 1, characterized in that, When the physical packet length characteristic parameter of the downlink data packet is greater than 128B, the feedforward gated routing algorithm generates a second routing control word to drive the direct memory access control module to input the multimedia slice data packet to the tail of the media-level broadband logical topology subqueue.

4. A 5G message resource push system for the education field according to claim 1, characterized in that, Within the 15ms deadlock period, even if the gradient of the rate of change of the cache queue generated by the cache occupancy monitoring module falls back to below the critical congestion gradient threshold, the hysteresis flow control state determination module blocks the merging of the dual-channel queue topology state.

5. A 5G message resource push system for the education field according to claim 1, characterized in that, The signaling-level high-priority logical topology subqueue and the media-level broadband logical topology subqueue are cascaded at the acceleration interface of the chip's internal bus module to enable control signaling data packets to bypass the general network layer parsing queue.

6. A 5G message resource push system for the education field according to claim 1, characterized in that, The cache utilization monitoring module includes a clock counting module and a status sampling module. The status sampling module is used to sample the storage space utilization within a fixed clock cycle, and the clock counting module is used to calculate the gradient of the cache queue utilization rate based on the ratio of the difference between the current storage space utilization and the previous sampling cycle to the 2ms sampling cycle.

7. A 5G message resource push system for the education field according to claim 1, characterized in that, The topology control module also includes a threshold comparison module; the threshold comparison module is used to compare the gradient of the rate of change of the cache queue occupancy rate with the critical congestion gradient threshold, and to keep the dual-channel queue topology state locked when the gradient of the rate of change of the cache queue occupancy rate is greater than the critical congestion gradient threshold.

8. A 5G message resource push system for the education field according to claim 1, characterized in that, The output end of the media-level broadband logical topology sub-queue is connected to an educational resource unpacking module; the educational resource unpacking module is used to read multimedia slice data packets from the head of the media-level broadband logical topology sub-queue and extract multimedia educational resource streams from them.

9. A 5G message resource push system for the education field according to claim 1, characterized in that, The system also includes a chip microcode control module; the chip microcode control module is connected to the topology control module and the timing adaptive adjustment module, and is used to dynamically adjust the allocation timing of system resources according to the bus service weight.

10. A 5G message resource push method for the education field, which is implemented using the 5G message resource push system for the education field as described in claim 1, characterized in that, Includes the following steps: Step S1: The hardware demultiplexing module demultiplexes the downlink cellular radio signal into downlink data packets; In step S2, the routing arbitration module processes the downlink data packets according to the feedforward gated routing algorithm to generate the first routing control word and the second routing control word. Step S3: The direct memory access control module attaches the control signaling data packet to the head of the signaling-level high-priority logical topology sub-queue according to the first routing control word, and inputs the multimedia slice data packet to the tail of the media-level broadband logical topology sub-queue according to the second routing control word. Step S4: The cache occupancy rate monitoring module in the topology control module collects the storage space occupancy at a sampling period of 2ms and generates a gradient of the cache queue occupancy rate change rate. When the gradient of the cache queue occupancy rate change rate is greater than the critical congestion gradient threshold, the hysteresis flow control state determination module locks the dual-channel queue topology state composed of the signaling-level high-priority logical topology sub-queue and the media-level broadband logical topology sub-queue, and blocks the merging of the dual-channel queue topology state within a 15ms lockout period. Step S5: The timing adaptive adjustment module adjusts the bus service weight based on the real-time delay time of the dual-channel queue topology status.

Images