Method and apparatus for real-time dynamic positioning using mobile base stations

Abstract

This application discloses a method and apparatus for real-time kinematic (RTK) positioning using a mobile base station. An example apparatus for generating virtual reference station (VRS) observation results includes an interface circuit system communicatively coupled to a receiver of a mobile base station, machine-readable instructions, and at least one processor circuit programmed by the machine-readable instructions to determine changes in the reception of Global Navigation Satellite System (GNSS) signals between the mobile base station and the VRS, generate VRS observation results based on the determined changes, and cause the VRS observation results to be transmitted to a rover platform for its RTK navigation.

Description

[0001] Government interests This invention was completed with the support of the U.S. government. The U.S. government may hold certain rights to this invention. Technical Field

[0002] This disclosure relates generally to navigation, and more specifically to methods and apparatus for real-time dynamic positioning using mobile base stations. Background Technology

[0003] Real-time dynamic (RTK) positioning is used in known systems as a relatively low-cost alternative to providing centimeter (cm) level navigation data. In known systems, RTK implementations require fixed base stations with known locations to broadcast their raw observations (i.e., their “corrected results”) to rover units in the nearby neighborhood. However, fixed base stations may not be readily available, and setting up temporary base stations may be impractical. Summary of the Invention

[0004] An example apparatus for generating virtual reference station (VRS) observation results includes an interface circuit system communicatively coupled to a receiver of a mobile base station, machine-readable instructions, and at least one processor circuit, which is programmed by the machine-readable instructions to determine changes in the reception of Global Navigation Satellite System (GNSS) signals between the mobile base station and the VRS, generate VRS observation results based on the determined changes, and cause the VRS observation results to be transmitted to a rover platform for its navigation.

[0005] An exemplary non-transitory machine-readable medium includes machine-readable instructions to cause at least one processor circuitry to at least determine changes in the reception of Global Navigation Satellite System (GNSS) signals between a mobile base station and a virtual reference station (VRS), generate VRS observations based on the determined changes, and cause a transmitter to provide the VRS observations to a rover platform for its navigation.

[0006] One example method includes determining changes in the reception of Global Navigation Satellite System (GNSS) signals between a mobile base station and a virtual reference station (VRS), generating VRS observations based on the determined changes, and transmitting the VRS observations to a rover platform for its navigation. Attached Figure Description

[0007] Figure 1 This is an example navigation system based on the teachings of this disclosure.

[0008] Figure 2 This is a schematic overview of an example communication system that can be implemented in the examples disclosed herein.

[0009] Figure 3This is an example process flow that can be implemented in the examples disclosed in this article.

[0010] Figure 4 This is a block diagram of an example implementation of an example navigation analysis system that can be implemented in the examples disclosed herein.

[0011] Figure 5 and Figure 6 This is a flowchart representing example machine-readable instructions and / or example operations that can be executed, instantiated, and / or implemented by an example programmable circuit system to achieve... Figure 4 The navigation analysis system.

[0012] Figure 7 This is a block diagram of an example processing platform, which includes a programmable circuit system configured to execute, instantiate, and / or perform example machine-readable instructions and / or perform... Figure 5 and Figure 6 Example operations to implement Figure 4 The navigation analysis system.

[0013] Figure 8 yes Figure 7 A block diagram of an example implementation of a programmable circuit system.

[0014] Figure 9 yes Figure 7 A block diagram of another example implementation of a programmable circuit system.

[0015] Generally, the same reference numerals will be used throughout the accompanying drawings and written description to refer to the same or similar parts. These drawings are not necessarily drawn to scale. Instead, the thickness of some layers or areas may be exaggerated in the drawings. Although these drawings show some layers and areas with clean lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, mixed, and / or irregular. Detailed Implementation

[0016] Figure 1 This is an example navigation system 100 based on the teachings of this disclosure. Figure 1The example shown defines a virtual reference station (VRS) 104 as a mobile base station 102 implemented as an aircraft and / or airborne platform. Specifically, the mobile base station 102 is communicatively coupled to a rover platform (e.g., a rover, a guided vehicle, a mobile platform, a vehicle, etc.) 106 (hereinafter referred to as rover platforms 106a, 106b, 106c, etc.) such that the mobile base station 102 transmits signals to the rover platforms 106a, 106b, 106c. In this example, rover platform 106a is an unmanned aerial vehicle (UAV), rover platform 106b is a manned aircraft, and rover platform 106c is a land-based vehicle (e.g., a land-based unmanned vehicle, a car, truck, van, bus, train or other rail-based vehicle, tank or other military vehicle, hovercraft, etc.). However, any other vehicle, rover, or mobile platform can be implemented instead, including but not limited to submersibles, spacecraft, projectiles, etc. Although mobile base station 102 is implemented in an airborne platform in this example, mobile base station 102 can be implemented in any suitable mobile platform, such as, but not limited to, ocean liners, spacecraft, submersibles, etc. Although three of the rover platforms 106 are shown, any other suitable number of rover platforms 106 can be implemented instead (e.g., one, two, four, five, ... ten, ... fifty, etc.).

[0017] In this example, rover platforms 106a, 106b, and 106c each include at least one receiver (e.g., an RTK-enabled GNSS receiver, etc.) for receiving GNSS and VRS signals for their navigation. In known systems, the RTK-enabled GNSS receiver of a vehicle typically receives observations from a stationary (for precise positioning) corresponding RTK base station. These known systems typically cannot combine RTK signals from a mobile base station. Compared to known systems, this example advantageously enables these vehicles to receive RTK signals from a non-stationary base station. According to the example disclosed herein, the mobile base station can generate RTK signals as if the base station were stationary; this is referred to as the aforementioned virtual reference station or VRS. Also according to the example disclosed herein, the mobile base station does not need to be at the same altitude or location as the VRS, which makes airborne mobile base stations possible compared to known implementations. Therefore, the example disclosed herein enables the generation of RTK signals from a stationary VRS, which allows RTK positioning on all types of RTK-enabled GNSS receivers (even those not specifically designed for mobile RTK base stations).

[0018] Figure 2This is a schematic overview of an example communication system 200 that can be implemented in the examples disclosed herein. The illustrated example communication system 200 utilizes GNSS data transmitted from at least one satellite 201. The example communication system 200 includes a mobile base station 102, which in turn includes a precision GNSS receiver 202, a processor (e.g., a processor executing software, a processor circuit system, a processor device, a processing system, etc.) 204, and a data link circuit system 206. Figure 2 The example antenna configuration shown is merely an example and can be modified to implement any other suitable number of antennas. Additionally or alternatively, the example mobile base station 102 includes a calibration service receiver 208. According to some examples disclosed herein, antenna 210 corresponds to a precision GNSS receiver 202, antenna 212 corresponds to a calibration service receiver 208, and antenna 214 corresponds to the aforementioned data link circuitry system 206. As can be seen in the illustrated example, the communication system 200 includes an example roaming platform 106. Furthermore, the example roaming platform 106 includes a data link 216 and an RTK-enabled GNSS receiver 218. In this example, antenna 220 corresponds to the RTK-enabled GNSS receiver 218, while antenna 224 corresponds to the data link 216.

[0019] In operation, GNSS signals are provided from satellite 201 to precision GNSS receiver 202 at base station 102 via antenna 210. Processor 204 then generates the necessary GNSS signal adjustments for creating a VRS, taking into account the motion of mobile base station 102 (e.g., flight motion, flight path, etc.), atmospheric delay differences between the mobile base station and the VRS (e.g., tropospheric delay differences, etc.), and positional differences between the mobile base station and the GNSS satellite motion. According to the examples disclosed herein, adjustments and / or corrections for GNSS observations can be provided as VRS observations to data link 216 of rover platform 106 via the GNSS link 216. As a result, rover platform 106 can obtain GNSS observation data from base station 102 as if the rover platform were receiving GNSS observation data from a stationary RTK base station. Compared to known RTK-based systems, the examples disclosed herein allow the RTK base station to be non-stationary (e.g., in flight, in the air, at sea, etc.) and at different altitudes.

[0020] In some examples, base station 102 utilizes the aforementioned correction service receiver 208 to enable base station 102 to accurately determine its own location (a key requirement for generating VRS). Alternatively, mobile base station 102 may utilize other means to accurately determine its location, such as an external reference system, a pseudosatellite system, another RTK base station, a navigation-grade IMU, etc. In some examples, base station 102 utilizes the aforementioned correction service receiver 208 to provide information about GNSS error sources, which can be used to further improve the aforementioned VRS observations used by rover platform 106. This information includes, but is not limited to, tropospheric delay, satellite clock errors, and satellite ephemeris errors.

[0021] Figure 3 This is example process flow 300, which can be implemented in the examples disclosed herein. Figure 3 In the example shown, input / parameter 302 corresponding to the mobile base station (e.g., mobile base station 102, airborne platform, etc.) is used to generate VRS observations for use by a rover platform (e.g., rover platform 106, etc., with an RTK-enabled GNSS receiver). In this example, inputs include, but are not limited to, the absolute position and velocity of the mobile base station and / or its receiver, satellite position, raw GNSS observations / data, and tropospheric delay at the mobile base station and / or its receiver. However, any other suitable inputs may be used in addition to and / or in lieu of those listed.

[0022] According to the example disclosed herein, calculation 304 is performed. Specifically, the relative position and / or relative velocity between the mobile base station (e.g., the receiver of the mobile base station, etc.) and the GNSS satellite are calculated. Furthermore, in this example, the relative position and / or relative velocity between the mobile base station (e.g., the receiver of the mobile base station, etc.) and the virtual base station (which...) are calculated and / or estimated. Figure 3 The increment / difference of atmospheric delay (e.g., tropospheric delay, etc.) between (represented as VRS).

[0023] To generate VRS observation results, the example algorithm performs calculation 306 for each satellite and frequency of the aforementioned GNSS system. Figure 3In the example shown, the difference / increment of the distance between the mobile base station's receiver and the VRS is calculated, and the apparent pseudorange of the VRS is further calculated. Furthermore, the apparent absolute signal frequency of the mobile base station's receiver, assumed to be at zero velocity, is calculated, and as a result, the apparent Doppler shift of the VRS is calculated, assuming, for example, that the VRS is stationary. According to the example disclosed herein, the difference / increment between the carrier periods of the mobile base station's receiver and the VRS is calculated, and the apparent carrier phase at the VRS is determined. As a result, observation 310 of the VRS is determined, which may correspond to, for example, the Maritime Service Radio Technical Committee (RTCM) standard.

[0024] In this example, VRS observations (e.g., virtual RTK signals) that take into account numerous parameters related to the virtualization of the VRS are calculated / determined. VRS observations may consider parameters including, but not limited to, the apparent pseudorange of the VRS, the apparent Doppler shift corresponding to the VRS, and the apparent carrier phase at the VRS. However, VRS observations may consider any other suitable parameters / factors. In this example, observation 310 is provided as an RTK signal to the rover platform for its navigation.

[0025] The calculations and topography shown in the disclosed examples are merely examples and can be modified to perform any other appropriate calculations or topography. Furthermore, any other appropriate calculations and / or sequence determinations can be performed.

[0026] Figure 4 This is a block diagram of an example navigation system 400 for determining VRS observations transmitted from a mobile base station (e.g., mobile base station 102) to a roaming platform (e.g., a roaming platform such as roaming platform 106). Based on the examples disclosed herein, the example navigation system 400 can... Figure 1 The mobile base station 102 and / or shown Figure 2 Implemented in the processor 204 shown. Figure 4 The navigation system 400 can be instantiated (e.g., instantiated, implemented, materialized, or carried out) by a programmable circuit system (such as a central processing unit (CPU)) that executes the first instructions. Additionally or alternatively, Figure 4 The navigation system 400 can be instantiated (e.g., instantiated, materialized, implemented, etc., for any length of time) by: (i) an application-specific integrated circuit (ASIC) and / or (ii) a field-programmable gate array (FPGA), which is structured and / or configured in response to the execution of a second instruction to perform an operation corresponding to the first instruction. It should be understood that, therefore Figure 4Some or all of the circuit systems can be instantiated at the same or different times. For example, Figure 4 Some or all of the circuitry can be instantiated in one or more threads that execute concurrently on hardware and / or serially on hardware. Furthermore, in some examples, Figure 4 Some or all of the circuitry can be implemented by a microprocessor circuitry that executes instructions and / or an FPGA circuitry that performs operations to implement one or more virtual machines and / or containers.

[0027] The example navigation system 400 includes an example GNSS signal analyzer circuit system 402, an example position calculator circuit system 404, an example VRS observation result generator circuit system 406, an example platform command circuit system 408, and an example communication control circuit system 410.

[0028] exist Figure 4 In the example shown, the GNSS signal analyzer circuit system 402 is implemented to process, analyze, and / or extract data from raw GNSS signals received at the GNSS receiver of a mobile base station. Therefore, the example GNSS signal analyzer circuit system 402 can utilize raw GNSS data / observations and / or GNSS correction data from a Precise Point Position (PPP) system received at the mobile base station. In some examples, the location calculator circuit system is instantiated by a programmable circuit system that executes location calculator circuit system instructions and / or configured to perform actions such as... Figure 5 and Figure 6 The flowchart represents the operations of those operations.

[0029] Example location calculator circuit system 404 determines the absolute position and / or absolute velocity of a mobile base station. For example, location calculator circuit system 404 utilizes high-precision GNSS data received from a precision GNSS receiver to determine at least one of the absolute position and / or absolute velocity of the GNSS receiver and / or the mobile base station carrying the GNSS receiver. Furthermore, example location calculator circuit system 404 can also determine the relative position and / or velocity between the mobile base station and a VRS established and / or generated by the mobile base station. According to the examples disclosed herein, location calculator circuit system 404 can determine satellite positions of GNSS systems, etc. In some examples, location calculator circuit system 404 is instantiated by a programmable circuit system that executes location calculator circuit system instructions and / or configured to perform actions such as... Figure 5 and Figure 6 The flowchart represents the operations of those operations.

[0030] According to the example disclosed herein, VRS observation result generator circuitry 406 determines the changes in the reception of GNSS signals between the mobile base station and the VRS in order to generate VRS observation results that will be provided to the rover platform for its navigation. Specifically, VRS observation result generator circuitry 406 generates VRS observation results based on the aforementioned changes in reception. Furthermore, the VRS observation results are transmitted to the rover platform to simulate and / or mimic GNSS observation results transmitted from a stationary RTK base station spaced a distance from the mobile base station. In this example, VRS observation result generator circuitry 406 takes into account the motion of the mobile base station (e.g., a mobile base station in flight, etc.) and the tropospheric delay difference between the mobile base station (e.g., the mobile base station's receiver, etc.) and the VRS, or any other suitable parameter. Example VRS observation result generator circuitry 406 performs calculations for each satellite and frequency, such that the difference / increment of the distance between the mobile base station's receiver and the VRS is calculated, and further, the apparent pseudorange of the VRS is calculated. Furthermore, the example VRS observation generator circuit system 406 calculates the apparent absolute signal frequency of the mobile base station (under the assumption of zero velocity) and the apparent Doppler shift of the assumed static VRS. According to the examples disclosed herein, the example VRS observation generator circuit system 406 calculates the difference / increment between the mobile base station (e.g., a receiver of the mobile base station, etc.) and the VRS to determine the apparent carrier phase at the VRS. According to the examples disclosed herein, the VRS observation generator circuit system 406 calculates the VRS observation based on the apparent pseudorange, apparent Doppler shift, and apparent carrier phase corresponding to the VRS. In some examples, the VRS observation generator circuit system 406 is instantiated by a programmable circuit system executing VRS observation generator instructions and / or configured to perform actions such as... Figure 5 and Figure 6 The flowchart represents the operations of those operations.

[0031] According to some examples disclosed herein, the platform command circuit system 408 processes and / or utilizes observations to generate VRS observations for the rover platform to use for its navigation. In some such examples, the platform command circuit system 408 adapts the aforementioned correction / observation signal to a VRS observation signal to simulate and / or mimic GNSS observations transmitted from the VRS. In some examples, the VRS observation signal (e.g., the GNSS observation signal) is generated using the RTCM standard. However, it can be alternatively utilized using any other suitable standard and / or protocol. In some examples, the platform command circuit system 408 is instantiated by a programmable circuit system that executes platform command circuit system instructions and / or configured to perform actions such as... Figure 5 and Figure 6 The flowchart represents the operations of those operations.

[0032] Example communication control circuitry 410 controls and / or instructs the transmitter / transceiver of the mobile base station to transmit the aforementioned VRS observations to the roaming platform. As a result, the VRS observations are used by the roaming platform for its navigation. In some examples, communication control circuitry 410 is instantiated by and / or configured by a programmable circuitry that executes communication control circuitry instructions to perform actions such as... Figure 5 and Figure 6 The flowchart represents the operations of those operations.

[0033] Although Figure 4 The implementation is shown in the figure. Figure 4 The example method of the navigation analysis system 400, but Figure 4 One or more of the elements, processes, and / or devices shown may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, the example GNSS signal analyzer circuit system 402, the example location calculator circuit system 404, the example VRS observation result generator circuit system 406, the example platform command circuit system 408, the example communication control circuit system 410, and / or more generally... Figure 4 The example navigation analysis system 400 can be implemented solely by hardware or by a combination of hardware and software and / or firmware. Therefore, for example, any of the example GNSS signal analyzer circuit system 402, the example position calculator circuit system 404, the example VRS observation result generator circuit system 406, the example platform instruction circuit system 408, the example communication control circuit system 410, and / or more generally, the example navigation analysis system 400, can be implemented by a programmable circuit system in combination with: machine-readable instructions (e.g., firmware or software), processor circuit systems, analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs) such as FPGAs. Furthermore, Figure 4 Example navigation analysis system 400 may include additional or replacement Figure 4 One or more of the elements, processes and / or devices shown, and / or may include more than one of any or all of the illustrated elements, processes and devices.

[0034] Figure 5 and Figure 6 The diagram illustrates example machine-readable instructions and / or flowcharts representing example operations that can be executed by a programmable circuit system to implement and / or instantiate. Figure 4 The navigation analysis system 400, these operations can be executed by a programmable circuit system to implement and / or instantiate them. Figure 4The navigation analysis system 400. Machine-readable instructions can be used by a programmable circuit system (e.g., in conjunction with the following). Figure 7 The programmable circuit system 712 shown in the example processor platform 700 under discussion executes one or more executable programs or a portion thereof, and / or may be a combination thereof. Figure 8 and / or Figure 9 The example programmable circuit system discussed (such as an FPGA) performs one or more functions or a portion of functions. In some examples, machine-readable instructions cause operations, tasks, etc., to be performed and / or executed in an automated manner in the real world. As used herein, “automation” means without human intervention.

[0035] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical discs (e.g., Blu-ray discs, high-density optical discs (CDs), digital versatile optical discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., random access memory (RAM) of any type), and / or any other storage device or storage disk. The instructions on the non-transitory computer-readable and / or machine-readable media may program and / or be executed by a programmable circuit system located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than the programmable circuit system. Machine-readable instructions can be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices can be implemented by endpoint client hardware devices (e.g., hardware devices associated with human and / or machine users) or intermediate client hardware device gateways (e.g., radio access networks (RANs)) that facilitate communication between server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media can include one or more media. Furthermore, although references... Figure 5 and Figure 6The flowchart shown describes an example program, but many other methods of implementing the example navigation analysis system 400 can be used alternatively. For example, the execution order of blocks in the flowchart can be changed, and / or some of the described blocks can be modified, eliminated, or combined. Additionally or alternatively, any or all blocks of the flowchart can be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, comparator, operational amplifier, logic circuitry, etc.) configured to perform the corresponding operations without executing software or firmware. The programmable circuitry can be distributed across different network locations and / or located locally on one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, a programmable circuit system may be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, and / or any combination thereof.

[0036] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and encapsulated format. As described herein, machine-readable instructions can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., machine-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., as part of instructions, code, code representations, etc.), which can be used to create, manufacture, and / or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations within a network or network set (e.g., in the cloud, at an edge device, etc.). Machine-readable instructions may require installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, reallocation, compilation, etc., to make them directly readable, interpretable, and / or executable by computing devices and / or other machines. For example, machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, wherein these parts, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations, which together may form a program (such as the program described herein).

[0037] In another example, machine-readable instructions may be stored in a state that can be read by a programmable circuit system, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the machine-readable instructions on a specific computing device or other device. In another example, machine-readable instructions may need to be configured (e.g., storage settings, data input, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, machine-readable, computer-readable, and / or machine-readable media as used herein may include instructions and / or programs, regardless of their specific format or state.

[0038] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented by any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0039] As mentioned above, Figure 5 and Figure 6Example operations can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are explicitly defined to include any type of computer-readable storage device and / or storage disk, excluding propagation signals and transmission media. Examples of such non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk in which information is stored for any duration (e.g., extended time periods, permanent, brief moments, temporary buffering, and / or caching for information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as including any physical (mechanical, magnetic, and / or electrical) hardware designed to retain information for a period of time, excluding propagation signals and transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disc, hard disk, disk drive, and / or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as mechanical and / or electrical equipment, hardware, and / or circuitry, which may or may not be configured with computer-readable instructions, machine-readable instructions, etc., and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0040] Figure 5 This is a flowchart representing example machine-readable instructions and / or example operations 500, which can be executed, instantiated, and / or implemented by a programmable circuit system to guide the rover platform via a VRS observation result base station generated / constructed by a mobile base station (in this example, an aircraft). Figure 5 Example machine-readable instructions and / or example operations 500 begin at block 502, where example GNSS signal analyzer circuitry 402 acquires GNSS data.

[0041] According to the examples disclosed herein, the example GNSS signal analyzer circuit system 402 receives and / or accesses precision GNSS signals. Additionally or alternatively, the example GNSS signal analyzer circuit system 402 receives and / or accesses correction data (e.g., from a correction source).

[0042] At block 504, example location calculator circuitry 404 and / or example VRS observation generator circuitry 406 generate and / or define VRS. Figure 5 In the example shown, the VRS observation result generator circuit system 406 generates, defines, and / or assumes that the VRS is stationary relative to the rover platform. In this example, even if the VRS does not physically exist, the VRS observation result generator circuit system 406 generates a mathematical construction / representation / evaluation of the VRS.

[0043] At block 506, the example location calculator circuitry 404 performs receiver calculations. According to the examples disclosed herein, the location calculator circuitry 404 determines at least one location and / or velocity of a mobile base station. In this example, the location calculator circuitry 404 (e.g., via a PPP receiver) determines the precise location and / or velocity of the mobile base station. According to some examples disclosed herein, the example location calculator circuitry 404 estimates a delay. In this example, the delay corresponds to the atmospheric delay (e.g., tropospheric delay) between the receiver of the base station platform and the VRS.

[0044] At block 507, combine as follows: Figure 6 As will be discussed in more detail, the example VRS observation result generator circuitry 406 generates and / or determines observation results. Based on some examples disclosed herein, the VRS observation result generator circuitry 406 determines variations, offsets, and / or errors in the GNSS signal between the mobile base station's receiver and the VRS for use in determining the observation results.

[0045] At block 508, in some examples, example VRS observation generator circuitry 406 and / or example platform instruction circuitry 408 determine / generate VRS observations (e.g., virtual signals / observations, etc.) based on variations, offsets, and / or errors between the mobile base station's receiver and the VRS. According to the examples disclosed herein, the VRS observations correspond to signals that the roaming platform's RTK system may have received from a stationary base station.

[0046] At block 510, in some examples, example platform instruction circuitry 408 causes the transmitter and / or transceiver to provide VRS observations as signals (e.g., transmit, cause transmission, etc.) to the rover platform for its navigation.

[0047] At block 512, the example platform instruction circuitry 408 and / or the example communication control circuitry 410 determine whether to repeat the process. If the process is to be repeated (block 512), control of the process returns to block 502. Otherwise, the process ends. The determination of whether to repeat the process can be based on whether the roaming platform needs further navigation and / or whether the mobile base station needs to continue operating as a mobile base station.

[0048] Figure 6 This is a flowchart representing example machine-readable instructions and / or example operations 507, which can be executed, instantiated, and / or implemented by a programmable circuit system to determine observations corresponding to errors, offsets, and / or variations in the reception of GNSS signals between a mobile base station and a VRS (e.g., a defined / constructed / assumed VRS).

[0049] At block 602, the illustrated example of the VRS observation result generator circuit system 406 calculates the incremental distance between the mobile base station's receiver and the aforementioned VRS.

[0050] At block 604, following the example disclosed herein, the VRS observation generator circuitry 406 calculates the apparent pseudorange at the VRS.

[0051] At block 606, example VRS observation generator circuitry 406 calculates the absolute signal frequency at the receiver of a mobile base station with an assumed zero speed.

[0052] At block 608, the illustrated VRS observation generator circuit system 406 calculates the Doppler frequency shift at the stationary VRS.

[0053] At block 610, the example VRS observation generator circuit system 406 calculates the incremental carrier period between the receiver and the VRS.

[0054] At block 612, following the example disclosed herein, the VRS observation generator circuit system 406 calculates the apparent carrier phase of the VRS.

[0055] At block 614, the example VRS observation result generator circuitry 406 determines whether to repeat the process. If the process is to be repeated (block 614), control of the process returns to block 602. Otherwise, the process ends / returns to... Figure 5 The example process is shown.

[0056] Combination Figure 2 Any aspect shown and described may be Figure 5 and / or Figure 6 The example process shown is implemented as follows.

[0057] Figure 7 This is a block diagram of an example programmable circuit system platform 700, which is configured to perform and / or instantiate... Figure 5 and Figure 6 Example machine-readable instructions and / or example operations for implementation Figure 4The navigation analysis system 400. The programmable circuit system platform 700 can be, for example, a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., cellular phone, smartphone, such as iPad). TM Tablet computers, personal digital assistants (PDAs), internet devices, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (such as augmented reality (AR) head-mounted devices, virtual reality (VR) head-mounted devices, etc.) or other wearable devices, or any other type of computing device and / or electronic device.

[0058] The illustrated programmable circuit system platform 700 includes a programmable circuit system 712. The illustrated programmable circuit system 712 is hardware. For example, the programmable circuit system 712 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 712 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 712 implements an example GNSS signal analyzer circuit system 402, an example location calculator circuit system 404, an example VRS observation result generator circuit system 406, an example platform instruction circuit system 408, and an example communication control circuit system 410.

[0059] The illustrated programmable circuit system 712 includes local memory 713 (e.g., cache, registers, etc.). The illustrated programmable circuit system 712 communicates via bus 718 with main memories 714, 716, including volatile memory 714 and non-volatile memory 716. Volatile memory 714 may be implemented using synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. Non-volatile memory 716 may be implemented using flash memory and / or any other desired type of memory device. Access to the illustrated main memories 714, 716 is controlled by a memory controller 717. In some examples, the memory controller 717 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuit system from any desired series or manufacturer to manage the flow of data into and out of main memories 714, 716.

[0060] The illustrated programmable circuit system platform 700 also includes an interface circuit system 720. The interface circuit system 720 can be implemented using hardware that conforms to any type of interface standard (e.g., Ethernet interface, Universal Serial Bus (USB) interface, Bluetooth® interface, Near Field Communication (NFC) interface, Peripheral Component Interconnect (PCI) interface, and / or Peripheral Component Interconnect Fast (PCIe) interface).

[0061] In the illustrated example, one or more input devices 722 are connected to the interface circuit system 720. The input devices 722 allow users (e.g., human users, machine users, etc.) to input data and / or commands into the programmable circuit system 712. The input devices 722 can be implemented using, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, isopoint devices, and / or voice recognition systems.

[0062] One or more output devices 724 are also connected to the interface circuitry system 720 of the illustrated example. The output devices 724 can be implemented, for example, by means of: display devices (e.g., light-emitting diode (LED), organic light-emitting diode (OLED), liquid crystal display (LCD), cathode ray tube (CRT) display, in-place switching (IPS) display, touchscreen, etc.), haptic output devices, printers, and / or speakers. Therefore, the interface circuitry system 720 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry system (such as a GPU).

[0063] The illustrated interface circuit system 720 also includes communication devices (e.g., transmitter, receiver, transceiver, modem, residential gateway, wireless access point, and / or network interface) to facilitate data exchange with external machines (e.g., any kind of computing device) via network 726. This communication can be performed via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, beyond-line-of-sight wireless systems, line-of-sight wireless systems, cellular telephone systems, optical connections, etc.

[0064] The illustrated programmable circuit system platform 700 also includes one or more mass storage disks or devices 728 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 728 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0065] It can be by Figure 5 and Figure 6The machine-readable instructions 732 implemented by the machine-readable instructions can be stored in a mass storage device 728, a volatile memory 714, a non-volatile memory 716 and / or at least one non-transitory computer-readable storage medium (such as a CD or DVD) (which may be removable).

[0066] Figure 8 yes Figure 7 A block diagram of an example embodiment of the programmable circuit system 712. In this example, Figure 7 The programmable circuit system 712 is implemented by the microprocessor 800. For example, the microprocessor 800 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit system). The microprocessor 800 executes... Figure 5 and Figure 6 The flowchart contains some or all of the machine-readable instructions to effectively translate... Figure 4 The circuit system is instantiated as a logic circuit that performs operations corresponding to these machine-readable instructions. In some such examples, the microprocessor 800 is instantiated by combining hardware circuitry with machine-readable instructions. Figure 4 The circuit system. For example, microprocessor 800 can be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. While it can include any number of example cores 802 (e.g., 1 core), this example microprocessor 800 is a multi-core semiconductor device including N cores. The cores 802 of microprocessor 800 can operate independently or can cooperate to execute machine-readable instructions. For example, machine code corresponding to firmware, embedded software programs, or software programs can be executed by one core of core 802, or can be executed by multiple cores of core 802 at the same or different times. In some examples, the machine code corresponding to firmware, embedded software programs, or software programs is divided into threads and executed in parallel by two or more cores of core 802. Software programs can correspond to those executed by... Figure 5 and Figure 6 The flowchart represents part or all of the machine-readable instructions and / or operations.

[0067] Core 802 can communicate via a first example bus 804. In some examples, the first bus 804 can be implemented by a communication bus to enable communication associated with one or more cores in core 802. For example, the first bus 804 can be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 804 can be implemented by any other type of computing or electrical bus. Core 802 can obtain data, instructions, and / or signals from one or more external devices via example interface circuitry 806. Core 802 can output data, instructions, and / or signals to one or more external devices via interface circuitry 806. While the core 802 of this example includes example local memory 820 (e.g., a Level 1 (L1) cache that may be partitioned into an L1 data cache and an L1 instruction cache), the microprocessor 800 also includes example shared memory 810 that can be shared by cores (e.g., a Level 2 (L2) cache) for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from shared memory 810. The local memory 820 and shared memory 810 of each of the cores 802 can be multi-level cache memory and main memory (e.g., ...). Figure 7 The cache is part of the storage device hierarchy (714, 716) of the main memory. Generally, higher-level memories in the hierarchy exhibit lower access times and have smaller storage capacities compared to lower-level memories. Changes to the various levels of the cache hierarchy are managed through cache coherence strategies (e.g., coordination).

[0068] Each core 802 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuit system. Each core 802 includes a control unit circuit system 814, an arithmetic and logic (AL) circuit system (sometimes referred to as an ALU) 816, multiple registers 818, local memory 820, and a second example bus 822. Other structures may exist. For example, each core 802 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating-point unit (FPU) circuit system, etc. The control unit circuit system 814 includes semiconductor-based circuitry configured to control (e.g., coordinate) the movement of data within the corresponding core 802. The AL circuit system 816 includes semiconductor-based circuitry configured to perform one or more mathematical and / or logical operations on the data within the corresponding core 802. Some examples of the AL circuit system 816 perform integer-based operations. In other examples, the AL circuit system 816 also performs floating-point operations. In other examples, the AL circuit system 816 may include a first AL circuit system that performs integer-based operations and a second AL circuit system that performs floating-point operations. In some examples, the AL circuit system 816 may be referred to as an arithmetic logic unit (ALU).

[0069] Register 818 is a semiconductor-based structure used to store data and / or instructions (such as the results of one or more operations performed by the AL circuit system 816 of the corresponding core 802). For example, register 818 may include vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Register 818 can be as follows: Figure 8 The arrangement shown is in the memory bank. Alternatively, register 818 can be organized in any other arrangement, format, or structure, for example, by distributing it throughout core 802 to reduce access time. The second bus 822 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0070] Each core 802 and / or more generally, the microprocessor 800 may include additional and / or alternative structures to those structures shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergent / common grid stop devices (CMS), one or more shifters (e.g., barrel shifters), and / or other circuitry may be present. The microprocessor 800 is a semiconductor device manufactured to include a plurality of transistors interconnected to implement the above-described structures in one or more integrated circuits (ICs) contained in one or more packages.

[0071] Microprocessor 800 may include one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.) and / or cooperate with them. In some examples, accelerators are implemented by logic circuitry to perform certain tasks faster and / or more efficiently (compared to those that a general-purpose processor might accomplish). Examples of accelerators include ASICs and FPGAs (such as those discussed herein). GPUs, DSPs, and / or other programmable devices may also be accelerators. Accelerators may be mounted on microprocessor 800, reside in the same chip package as microprocessor 800, and / or reside in one or more separate packages from microprocessor 800.

[0072] Figure 9 yes Figure 7 A block diagram of another example embodiment of the programmable circuit system 712. In this example, the programmable circuit system 712 is implemented by an FPGA circuit system 900. For example, the FPGA circuit system 900 can be implemented by an FPGA. The FPGA circuit system 900 can be used, for example, to perform operations that would otherwise be performed by... Figure 8 The example microprocessor 800 executes the corresponding machine-readable instructions. However, once configured, the FPGA circuit system 900 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware, and therefore can generally execute these operations / functions much faster (compared to the speed at which they can be executed by a general-purpose microprocessor executing the corresponding software).

[0073] More specifically, with the above Figure 8 The microprocessor 800 (which can be programmed to execute) Figure 5 and Figure 6 Compared to a flowchart representing a general-purpose device with some or all of its machine-readable instructions, but whose interconnects and logic circuitry are fixed once manufactured, Figure 9 The example FPGA circuit system 900 includes interconnects and logic circuit systems that can be configured, structured, programmed, and / or interconnected in different ways after manufacturing to instantiate, for example, with... Figure 5 and Figure 6 The flowchart represents some or all of the machine-readable instructions corresponding to operations / functions. Specifically, the FPGA circuit system 900 can be considered as an array of logic gates, interconnects, and switches. Switches can be programmed to change the way logic gates are interconnected via interconnects, thereby effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit system 900 is reprogrammed). The configured logic circuits enable logic gates to cooperate in different ways, thereby performing different operations on data received from the input circuit system. These operations can correspond to... Figure 5 and Figure 6 The flowchart represents some or all of the instructions (e.g., software and / or firmware). Therefore, the FPGA circuit system 900 can be configured and / or constructed to effectively integrate with... Figure 5 and Figure 6 The machine-readable instructions in the flowchart instantiate some or all of the operations / functions corresponding to these software instructions into dedicated logic circuits, thereby executing the operations / functions corresponding to these software instructions in a dedicated manner similar to that of an ASIC. Therefore, the FPGA circuit system 900 can execute operations / functions corresponding to these software instructions more quickly. Figure 5 and Figure 6 Operations / functions corresponding to some or all of the machine-readable instructions (compared to operations / functions that a general-purpose microprocessor might perform).

[0074] exist Figure 9 In some examples, the FPGA circuit system 900 is configured and / or constructed in response to being programmed (and / or reprogrammed once or multiple times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or programs corresponding to one or more operations / functions using HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., low-level language code / program) can be converted into a binary file (e.g., through a compiler, software application, etc.). In some examples, Figure 9 The FPGA circuit system 900 can access and / or load binary files to cause Figure 9 The FPGA circuit system 900 is configured and / or constructed to perform one or more operations / functions. For example, a binary file can be transmitted via... Figure 9 The FPGA circuit system 900 can access bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to implement, in order to cause Figure 9 The configuration and / or structuring of the FPGA circuit system 900 or a portion thereof.

[0075] In some examples, the binary file is compiled, generated, transformed, and / or otherwise output from a unified software platform used for programming the FPGA. For instance, the unified software platform can translate first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 9 The FPGA circuit system 900 can access and / or load binary files to cause Figure 9 The FPGA circuit system 900 is configured and / or constructed to perform one or more operations / functions. For example, a binary file can be transmitted via... Figure 9 The FPGA circuit system 900 can access bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to implement, in order to cause Figure 9 The configuration and / or structuring of the FPGA circuit system 900 or a portion thereof.

[0076] Figure 9 The FPGA circuit system 900 includes an example input / output (I / O) circuit system 902 for obtaining and / or outputting data to / from an example configuration circuit system 904 and / or external hardware 906. For example, the configuration circuit system 904 may be implemented via an interface circuit system to configure the FPGA circuit system 900 or a portion thereof, wherein the interface circuit system can obtain a binary file, which can be implemented as a bitstream, data, and / or machine-readable instructions. In some such examples, the configuration circuit system 904 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file), and / or any combination thereof. In some examples, the external hardware 906 may be implemented by an external hardware circuit system. For example, the external hardware 906 may be... Figure 8 The microprocessor 800 is used for implementation.

[0077] The FPGA circuit system 900 also includes an array of example logic gate circuit systems 908, multiple example configurable interconnects 910, and example memory circuit systems 912. The logic gate circuit system 908 and the configurable interconnects 910 are configurable to instantiate one or more operations / functions, which can correspond to... Figure 5 and Figure 6 At least some of the machine-readable instructions and / or other desired operations. Figure 9 The logic gate system 908 shown is manufactured in blocks or groups. Each block includes a semiconductor-based electrical structure configurable into a logic circuit. In some examples, the electrical structure includes logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for the logic circuit. Electrically controlled switches (e.g., transistors) are present within each logic gate system 908 to implement the configuration of the electrical structure and / or logic gates, thereby forming a circuit for performing the desired operation / function. The logic gate system 908 may include other electrical structures, such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0078] The configurable interconnect 910 illustrated is a conductive path, trace, via, etc., which may include an electrically controlled switch (e.g., a transistor) whose state can be changed (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuit systems 908, thereby programming the desired logic circuit.

[0079] The illustrated storage circuit system 912 is configured to store the results of one or more operations performed by corresponding logic gates. The storage circuit system 912 can be implemented using registers, etc. In the illustrated example, the storage circuit system 912 is distributed among the logic gate circuit system 908 to facilitate access and improve execution speed.

[0080] Figure 9The example FPGA circuit system 900 also includes an example dedicated operating circuit system 914. In this example, the dedicated operating circuit system 914 includes a dedicated circuit system 916 that can be invoked to implement common functions to avoid the need for field programming of these functions. Examples of such dedicated circuit systems 916 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier-accumulator circuit systems. Other types of dedicated circuit systems may be present. In some examples, the FPGA circuit system 900 may also include an example general-purpose programmable circuit system 918, such as an example CPU 920 and / or an example DSP 922. Other general-purpose programmable circuit systems 918 (e.g., GPUs, XPUs, etc.) may additionally or alternatively exist and can be programmed to perform other operations.

[0081] although Figure 8 and Figure 9 It shows Figure 7 These are two example implementations of the programmable circuit system 712, but many other solutions are considered. For example, the FPGA circuit system may include an onboard CPU, such as... Figure 8 One or more of the example CPUs 920. Therefore, Figure 7 The programmable circuit system 712 can additionally be combined with at least Figure 8 Example microprocessor 800 and Figure 9 The example FPGA circuit system 900 is used for implementation. In some such hybrid examples, Figure 8 One or more 802 cores can execute commands by Figure 5 and Figure 6 The flowchart represents the first part of the machine-readable instructions to perform a first operation / function, while Figure 9 The FPGA circuit system 900 can be configured and / or constructed to perform operations with... Figure 5 and Figure 6 The flowchart illustrates the second part of the machine-readable instructions corresponding to the second operation / function, and / or the ASIC can be configured and / or constructed to perform the operation / function described above. Figure 5 and Figure 6 The flowchart represents the third operation / function corresponding to the third part of the machine-readable instruction.

[0082] It should be understood that Figure 4 Some or all of the circuit systems can therefore be instantiated at the same or different times. For example, Figure 8 The same and / or different parts of the microprocessor 800 can be programmed to execute a portion of machine-readable instructions at the same and / or different times. In some examples, Figure 9The same and / or different parts of the FPGA circuit system 900 can be configured and / or constructed to perform operations / functions corresponding to a portion of machine-readable instructions at the same and / or different times.

[0083] In some examples, Figure 4 Some or all of the circuitry can be instantiated, for example, in one or more threads that execute concurrently and / or serially. For example, Figure 8 The microprocessor 800 can execute machine-readable instructions in one or more threads that execute concurrently and / or serially. In some examples, Figure 9 The FPGA circuit system 900 can be configured and / or constructed to perform operations / functions concurrently and / or serially. Furthermore, in some examples, it can... Figure 8 One or more virtual machines and / or containers running on a microprocessor 800 Figure 4 Some or all of the circuit systems.

[0084] In some examples, Figure 7 The programmable circuit system 712 can be housed in one or more packages. For example, Figure 8 microprocessors 800 and / or Figure 9 The FPGA circuitry system 900 can be housed in one or more packages. In some examples, the XPU can be... Figure 7 The programmable circuit system 712 is used for implementation, and the programmable circuit system 712 can be in one or more packages. For example, the XPU can be a CPU in one package (e.g., Figure 8 microprocessor 800, Figure 9 CPU 920, etc.), and DSP in another package (e.g., Figure 9 The DSP 922), the GPU in another package, and the FPGA in yet another package (e.g., Figure 9 FPGA circuit system 900).

[0085] "Including" and "comprising" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "include" or "comprise" (e.g., includes, includes, comprising, including, having, etc.) as a preamble or in any kind of claim statement, it should be understood that additional elements, terms, etc., may be present without exceeding the scope of the corresponding claim or statement. As used herein, when the phrase "at least" is used as a transitional term, for example in the preamble of a claim, it is as open-ended as the terms "comprising" and "including" are. For example, when used in the form of A, B, and / or C, the term “and / or” refers to any combination or subset of A, B, and C, such as: (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A and B” is intended to refer to an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, or things, the phrase “at least one of A or B” is intended to refer to an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" is intended to refer to an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" is intended to refer to an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0086] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude plurals. As used herein, the term "a" or "an" refers to one or more of those objects. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements, or actions may be implemented by, for example, the same entity or object. Moreover, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not mean that the combination of features is not feasible and / or not advantageous.

[0087] As used herein, unless otherwise stated, the term "above" describes the relationship of two components relative to the Earth. The first component is above the second component if the second component has at least a portion located between the Earth and the first component. Similarly, as used herein, the first component is "below" the second component when the first component is closer to the Earth than the second component. As stated above, the first component may be above or below the second component in one or more of the following situations: when there are one or more other components between them, when there are no other components between them, when the first and second components are in contact, or when the first and second components are not in direct contact with each other.

[0088] As used in this patent, a statement that any component (e.g., layer, film, region, area, or plate) is situated on another component in any manner (e.g., positioned thereon, placed thereon, disposed thereon, or formed thereon, etc.) indicates that either the referenced component is in contact with the other component, or the referenced component is above the other component with one or more intermediate components in between.

[0089] As used herein, unless otherwise stated, connective terms (e.g., attachment, coupling, connection, and joining) may include intermediate components between elements referenced by the connective term and / or relative movement between these elements. Therefore, a connective term does not necessarily imply that two elements are directly connected and / or in a fixed relationship with each other. As used herein, declaring any component "in contact" with another component is defined as meaning that there are no intermediate components between the two components.

[0090] Unless otherwise specified, descriptors such as “first,” “second,” and “third” used herein do not in any way indicate priority, physical order, arrangement in a list, and / or sorting, but are merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in a particular embodiment, while the same element may be referred to by different descriptors (such as “second” or “third”) in the claims. In such cases, it should be understood that these descriptors are only used to clearly identify these elements in the context of the discussion (e.g., within the claims), where these elements may otherwise share the same name, for example.

[0091] As used herein, “approximately” and “about” modify their subject matter / numerical values ​​to identify the potential presence of variations that occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may be inaccurate due to manufacturing tolerances and / or other real-world defects as would be understood by one of ordinary skill in the art. For example, unless otherwise specified herein, “approximately” and “about” may indicate that these dimensions may be within tolerances of + / - 10%.

[0092] As used in this article, "near-real-time" means occurring in a near-instantaneous manner, recognizing that there may be real-world delays in computation time, transmission time, etc. Therefore, unless otherwise specified, "near-real-time" means real-time plus 1 second.

[0093] As used herein, the phrase “to communicate” (including variations thereof) encompasses direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, pre-arranged intervals, non-periodic intervals and / or one-off events.

[0094] As used herein, a “programmable circuit system” is defined as including: (i) one or more application-specific circuits (e.g., application-specific integrated circuits (ASICs)) configured to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits programmable with instructions to perform specific functions and / or operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as a central processing unit (CPU) capable of executing first instructions to perform one or more operations and / or functions; a field-programmable gate array (FPGA) capable of being programmed with second instructions to result in the configuration and / or structuring of an FPGA to instantiate one or more operations and / or functions corresponding to the first instructions; a graphics processing unit (GPU) capable of executing first instructions to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) capable of executing first instructions to perform one or more operations and / or functions; one or more microcontrollers and / or integrated circuits such as application-specific integrated circuits (ASICs) capable of executing first instructions to perform one or more operations and / or functions. For example, an XPU can be implemented by a heterogeneous computing system and an orchestration technique (e.g., an application programming interface (API)) that includes a variety of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) that can distribute computing tasks to any one or more of the various types of programmable circuit systems that are suitable and available to perform the computing tasks.

[0095] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages that house one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of the following: ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0096] This document discloses example methods, apparatuses, systems, and articles of art that enable accurate control of a rover platform without requiring expensive, bulky, and space-consuming equipment. Further examples and combinations thereof include the following: Example 1 includes an apparatus for generating Virtual Reference Station (VRS) observations for navigation of a rover platform. The apparatus includes an interface circuitry communicatively coupled to a receiver of the mobile base station, machine-readable instructions, and at least one processor circuitry programmed by the machine-readable instructions to determine changes in the reception of Global Navigation Satellite System (GNSS) signals between the mobile base station and the VRS, generate the VRS observations based on the determined changes, and cause the VRS observations to be transmitted to the rover platform for its navigation.

[0097] Example 2 includes the apparatus according to Example 1, wherein the VRS is defined as stationary and spaced at a distance from the mobile base station.

[0098] Example 3 includes an apparatus according to any one of Examples 1 or 2, wherein one or more of the at least one processor circuitry determines the tropospheric delay difference between the mobile base station and the VRS to determine the variation.

[0099] Example 4 includes an apparatus according to any one of Examples 1 to 3, wherein the variation includes a Doppler frequency shift at the VRS, and wherein one or more of the at least one processor circuitry generates the VRS observation based on the Doppler frequency shift at the VRS.

[0100] Example 5 includes an apparatus according to any one of Examples 1 to 4, wherein one or more of the at least one processor circuitry generates the VRS observation results based on the distance difference between the receiver of the mobile base station and the defined location of the VRS.

[0101] Example 6 includes an apparatus according to any one of Examples 1 to 5, wherein the variation includes at least one of the apparent pseudorange at the VRS, the apparent Doppler shift at the VRS, or the apparent carrier phase at the VRR.

[0102] Example 7 includes the apparatus according to any one of Examples 1 to 6, further including a precision point location PPP receiver for the mobile base station, and wherein the output of the PPP receiver is used to determine the location of the mobile base station.

[0103] Example 8 includes at least one non-transitory machine-readable medium comprising machine-readable instructions to cause at least one processor circuitry to perform at least the following operations: determine a change in the reception of a Global Navigation Satellite System (GNSS) signal between a mobile base station and a virtual reference station (VRS), generate VRS observations based on the determined changes, and cause a transmitter to provide the VRS observations to a roaming platform for its navigation.

[0104] Example 9 includes at least one non-transitory machine-readable medium according to Example 8, wherein the VRS is defined as being stationary and spaced at a distance from the mobile base station.

[0105] Example 10 includes at least one non-transitory machine-readable medium according to any one of Examples 8 or 9, wherein the machine-readable instructions cause one or more of the at least one processor circuitry to determine the tropospheric delay difference between the mobile base station and the VRS to determine the variation.

[0106] Example 11 includes at least one non-transitory machine-readable medium according to any one of Examples 8 to 10, wherein the variation includes a Doppler shift, and wherein the machine-readable instructions cause one or more of the at least one processor circuitry to generate the VRS observation based on the Doppler shift at the VRS.

[0107] Example 12 includes at least one non-transitory machine-readable medium according to any one of Examples 8 to 11, wherein the machine-readable instructions cause one or more of the at least one processor circuitry to generate the VRS observation results based at least on the relative distance between the receiver of the mobile base station and the defined location of the VRS.

[0108] Example 13 includes at least one non-transitory machine-readable medium according to any one of Examples 8 to 12, wherein the machine-readable instructions cause one or more of the at least one processor circuitry to cause the transmitter to transmit the VRS observations during the movement of the mobile base station.

[0109] Example 14 includes at least one non-transitory machine-readable medium according to any one of Examples 8 to 13, wherein the change is determined based on the movement of the mobile base station.

[0110] Example 15 includes at least one non-transitory machine-readable medium according to any one of Examples 8 to 14, wherein the VRS observation corresponds to a location specified for the VRS.

[0111] Example 16 includes at least one non-transitory machine-readable medium according to any one of Examples 8 to 15, wherein the machine-readable instructions cause one or more of the at least one processor circuitry to determine a first atmospheric delay at the mobile base station and to determine a difference between a second atmospheric delay of the VRS and the first atmospheric delay, wherein the determination of the change is based on the difference.

[0112] Example 17 includes a method comprising determining a change in the reception of a Global Navigation Satellite System (GNSS) signal between a mobile base station and a virtual reference station (VRS), generating VRS observations based on the determined changes, and transmitting the VRS observations to a rover platform for its navigation.

[0113] Example 18 includes the method according to Example 17, further comprising determining the tropospheric delay difference between the mobile base station and the VRS to determine the variation.

[0114] Example 19 includes the method according to any one of Examples 17 or 18, further comprising defining the VRS as stationary and spaced at a distance from the mobile base station.

[0115] Example 20 includes the method according to any one of Examples 17 to 19, and further includes determining the Doppler frequency shift of the VRS to determine the change.

[0116] As should be understood from the foregoing, example systems, apparatuses, articles, and methods have been disclosed that enable precision navigation of vehicles (such as aircraft) without requiring specialized equipment, thereby saving the weight and space typically required for precision navigation. The disclosed systems, apparatuses, articles, and methods improve the efficiency of using computing devices by reducing the computational resources typically required for high-precision navigation systems in vehicles (such as aircraft). Therefore, the disclosed systems, apparatuses, articles, and methods relate to one or more improvements in the operation of machines such as computers or other electronic and / or mechanical equipment.

[0117] According to the examples disclosed herein, an airborne base station can interact with a rover in the vicinity of the local area. The examples disclosed herein can take into account the motion of the aircraft and the difference in tropospheric delay. The examples disclosed herein create, generate, and / or define a virtual RTK base station that does not physically exist. Therefore, VRS observations are generated as if a stationary base station existed, rather than an airborne / mobile base station. To generate the virtual RTK base station, the examples disclosed herein determine the raw GNSS satellite signals and timing that the virtual station would experience and / or encounter in the event of a physical presence. To this end, the examples disclosed herein utilize a series of equations to transform the raw airborne GNSS observations, which take into account the motion of the aircraft in the air, the motion of the GNSS satellites, and the variation in tropospheric delay between the airborne base station and the virtual base station relative to the estimated base station observations. As a result, at least one rover in the area receiving the observations can utilize corrections as if they were transmitted from the virtual base station, and they can achieve relatively high positional accuracy (e.g., cm-level accuracy, etc.) through the RTK implementation. Because RTK generates relative positional information, the absolute position of the airborne RTK base station, which can be obtained via a PPP solution, is determined.

[0118] The appended claims are hereby incorporated herein by reference. Although certain example systems, apparatuses, articles of manufacture, and methods have been disclosed herein, the scope of this patent is not limited thereto. Rather, this patent covers all systems, apparatuses, articles of manufacture, and methods that fall entirely within the scope of the claims of this patent.

Claims

1. An apparatus (100) for generating virtual reference station (VRS) observation results for navigation of a rover platform (106), the apparatus comprising: An interface circuit system (720) is communicatively coupled to the receiver (218) of the mobile base station. Machine-readable instructions (732); as well as At least one processor circuit (712) will be programmed by the machine-readable instructions to: Determine the changes in the reception of Global Navigation Satellite System (GNSS) signals between the mobile base station and the VRS (104); The VRS observation results are generated based on the determined changes; as well as This prompts the VRS observation results to be transmitted to the roaming platform for its navigation.

2. The apparatus of claim 1, wherein the VRS is defined as stationary and spaced at a certain distance from the mobile base station.

3. The apparatus of claim 1, wherein one or more of the at least one processor circuitry determines the tropospheric delay difference between the mobile base station and the VRS to determine the variation.

4. The apparatus of claim 1, wherein the change includes a Doppler frequency shift at the VRS, and wherein one or more of the at least one processor circuitry generates the VRS observation based on the Doppler frequency shift at the VRS.

5. The apparatus of claim 1, wherein one or more of the at least one processor circuitry generates the VRS observation results based on the distance difference between the receiver of the mobile base station and the defined location of the VRS.

6. The apparatus of claim 1, wherein the variation comprises at least one of the apparent pseudorange at the VRS, the apparent Doppler shift at the VRS, or the apparent carrier phase at the VRR.

7. The apparatus of claim 1 further includes a precision point location PPP receiver (202) for the mobile base station, wherein the output of the PPP receiver is used to determine the location of the mobile base station.

8. At least one non-transitory machine-readable medium comprising machine-readable instructions to cause at least one processor circuitry to perform at least the following operations: Determine the changes in the reception of GNSS signals between the mobile base station and the virtual reference station (VRS); VRS observations are generated based on the identified changes; and This prompts the transmitter to provide the VRS observation results to the roaming platform for its navigation.

9. The at least one non-transitory machine-readable medium according to claim 8, wherein the VRS is defined as being stationary and spaced at a distance from the mobile base station.

10. The at least one non-transitory machine-readable medium of claim 8, wherein the machine-readable instructions cause one or more of the at least one processor circuitry to determine the convection layer delay difference between the mobile base station and the VRS to determine the variation.

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