LED chips and LED strings

Abstract

A light-emitting diode (LED) chip and an LED string are disclosed, wherein the LED chip includes a working circuit and a voltage clamping device. The working circuit is electrically connected between a working voltage source and a ground terminal to provide power control and / or light emission control for the LED chip. The voltage clamping device is connected in parallel to the working circuit and includes a switch. The switch is electrically connected between the working voltage source and the ground terminal. After the LED chip is powered on, when the working voltage increases beyond a reference voltage, the switch is controlled to conduct, forming a conductive path between the working voltage source and the ground terminal, and a large current flows through the conductive path, causing the voltage clamping device to clamp the working voltage supplied to the working circuit. Accordingly, the voltage regulation of the conduction voltage can be actively adjusted according to different working voltages.

Description

Technical Field

[0001] This invention relates to the technical field of light-emitting diode (LED) beads, and more particularly to an LED bead and LED string with active voltage clamping. Background Technology

[0002] Because light-emitting diodes (LEDs) have advantages such as high luminous efficiency, low power consumption, long lifespan, fast response speed, and high reliability, they are widely used in lighting fixtures or decorative lighting applications, such as Christmas tree lights and light-up effects on sneakers, in series, parallel, or series-parallel connection methods, in light bars or light strings.

[0003] Taking festive lighting as an example, a complete LED lighting fixture basically consists of an LED string (with several LEDs) and a driver unit that drives the LEDs. The driver unit is electrically connected to the LED string and controls the LEDs by providing the necessary power and control signals with light emission data, either in a point-control or synchronous manner, to achieve diverse lighting output effects and variations.

[0004] In DC parallel-series LED strings, the voltage decreases as the number of LEDs and the length of the wiring increases. Although current LEDs incorporate constant current and bypass current to maintain a fixed current flow at any given time, thus achieving a fixed impedance and evenly distributing voltage, Ohm's Law (V=IR, where V is voltage, I is current, and R is impedance) means that a fixed current does not necessarily mean a fixed impedance. If the impedance of one LED drops, causing a sudden voltage drop, the voltage of other LEDs may increase. Therefore, a Zener diode can be added to each LED to clamp its voltage and maintain a stable operating voltage.

[0005] Furthermore, in automatically sorted parallel-to-series LED strings, during sorting, a particular LED might require the controller to detect a voltage change due to a current fluctuation. However, because of the series connection, other LEDs will increase or decrease their voltages to cancel out this voltage change, resulting in no voltage change at the controller or the voltage change becoming so small that it cannot be detected. Therefore, adding a Zener diode can solve this problem; that is, a Zener diode clamps the LED to a fixed voltage, preventing it from rising significantly and thus canceling out the voltage change to be detected.

[0006] However, the problem is that Zener diodes typically have a fixed forward voltage. As mentioned earlier, the voltage decreases towards the end of the lamp string. When the voltage is low, the Zener diode's forward voltage remains fixed, causing it to become ineffective. Therefore, Zener diodes are not suitable for operating environments with large load variations and high currents.

[0007] Therefore, how to design a light-emitting diode (LED) chip and LED string, especially an LED chip and LED string with active voltage clamping that can actively adjust the conduction voltage regulation according to different operating voltages, and solve the problems and technical bottlenecks of the existing technology, is an important research topic for the inventors of this case. Summary of the Invention

[0008] One object of the present invention is to provide a light-emitting diode (LED) chip. The LED chip includes a working circuit and a voltage clamping device. The working circuit is electrically connected between a working voltage and a ground terminal to provide at least power control and / or light emission control for the LED chip. The voltage clamping device is connected in parallel to the working circuit. The voltage clamping device includes a switch. The switch is electrically connected between the working voltage and the ground terminal. When the LED chip is powered on, if the working voltage increases beyond a reference voltage, the switch is controlled to turn on, forming a conductive path between the working voltage and the ground terminal, and a large current flows through this conductive path, causing the voltage clamping device to clamp the working voltage supplied to the working circuit.

[0009] In one embodiment, the voltage clamping device includes a capacitor, a first amplifier, and a switch. The capacitor receives the operating voltage and is charged by the operating voltage to establish a capacitor voltage, which is recorded as the reference voltage after the operating voltage stabilizes. The first amplifier receives the reference voltage and a voltage divider corresponding to the operating voltage, and compares the voltage divider with the reference voltage to generate a switch signal. The switch receives and is controlled by the switch signal. When the operating voltage increases beyond the reference voltage, the switch signal controls the switch to turn on, causing a large current to flow through the conduction path.

[0010] In one embodiment, the voltage clamping device further includes a first switch. The first switch is connected in series with the capacitor and is controlled by a control signal provided by the operating circuit. When the control signal turns on the first switch, the operating voltage charges the capacitor to establish the capacitor voltage.

[0011] In one embodiment, the voltage clamping device further includes a voltage divider resistor network. The voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the divided voltage.

[0012] In one embodiment, the voltage clamping device further includes a second amplifier. The second amplifier receives the capacitor voltage and provides the capacitor voltage as the reference voltage after the operating voltage has stabilized.

[0013] In one embodiment, the voltage clamping device includes an analog-to-digital converter (ADC), a third amplifier, and the switch. The ADC receives the operating voltage and records it as a reference voltage after the operating voltage stabilizes. The third amplifier receives the reference voltage and a voltage divider corresponding to the operating voltage, and compares the voltage divider with the reference voltage to generate a switch signal. The switch receives and is controlled by the switch signal. When the operating voltage increases beyond the reference voltage, the switch signal controls the switch to turn on, causing a large current to flow through the conduction path.

[0014] In one embodiment, the voltage clamping device further includes a voltage divider resistor network. The voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the divided voltage.

[0015] In one embodiment, the voltage clamping device includes a constant voltage circuit, a first comparator, a second comparator, a buffer, and a switch. The constant voltage circuit receives the operating voltage and records it as a reference voltage after the operating voltage stabilizes. The first comparator receives the reference voltage and a first voltage divider corresponding to the operating voltage, and compares the first voltage divider with the reference voltage to generate a first temporary signal. The second comparator receives the reference voltage and a second voltage divider corresponding to the operating voltage, and compares the second voltage divider with the reference voltage to generate a second temporary signal. The buffer receives the first and second temporary signals and generates a temporary output signal based on the levels of the first and second temporary signals. The switch receives and is controlled by the temporary output signal. When the operating voltage increases beyond the reference voltage, the temporary output signal controls the switch to turn on, causing a large current to flow through the conduction path.

[0016] In one embodiment, the voltage clamping device further includes a first voltage divider resistor network and a second voltage divider resistor network. The first voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the first voltage divider. The second voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the second voltage divider.

[0017] In one embodiment, the voltage clamping device further includes a fourth amplifier. The fourth amplifier receives the temporary output signal and a second reference voltage, and compares the temporary output signal and the second reference voltage to generate a switching signal for controlling the switch.

[0018] In one embodiment, the voltage clamping device further includes a third voltage divider resistor network. The third voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the second reference voltage.

[0019] In one embodiment, the voltage clamping device further includes an analog switch. The analog switch receives the temporary output signal and the switching signal output by the fourth amplifier. When the temporary output signal enables the analog switch, the analog switch outputs the switching signal to control the switch.

[0020] In one embodiment, the voltage clamping device further includes an inverter and a second switch. The inverter is coupled to the buffer and is used to invert the level of the temporary output signal to a second switch signal. The second switch is coupled to the inverter and the switch and is controlled by the second switch signal.

[0021] In one embodiment, when the operating voltage decreases below the reference voltage, the second switching signal controls the second switch to turn on, causing the current in the conduction path to decrease significantly until zero current.

[0022] Another object of the present invention is to provide a light-emitting diode (LED) string. The LED string includes a plurality of LED chips. Each LED chip is connected in series, and each LED chip includes a working circuit and a voltage clamping device. The working circuit is electrically connected between a working voltage and a ground terminal to provide power control and / or light emission control for the LED chip. The voltage clamping device is connected in parallel to the working circuit. The voltage clamping device includes a switch. The switch is electrically connected between the working voltage and the ground terminal. When the LED string is powered on, if the working voltage of each LED chip in the LED string increases beyond a reference voltage, the switch of the LED chip is controlled to turn on, forming a conductive path between the working voltage and the ground terminal, and a large current flows through the conductive path, causing the voltage clamping device to clamp the working voltage supplied to the working circuit of the LED chip.

[0023] To gain a deeper understanding of the techniques, means, and effects employed by this invention to achieve its intended purpose, please refer to the following detailed description and accompanying drawings. It is believed that the purpose, features, and characteristics of this invention can be understood in a thorough and specific manner from these drawings. However, the accompanying drawings are provided for reference and illustration only and are not intended to limit the scope of this invention. Attached Figure Description

[0024] Figure 1 This is a circuit block diagram of the LED string of the present invention.

[0025] Figure 2 This is a block diagram of a light-emitting diode (LED) bead with a voltage clamping device according to the present invention.

[0026] Figure 3A This is a circuit diagram of a first embodiment of the voltage clamping device in this invention.

[0027] Figure 3B for Figure 3A The diagram shows the working voltage and the current in the conduction path in the first embodiment.

[0028] Figure 4A This is a circuit diagram of a second embodiment of the voltage clamping device in this invention.

[0029] Figure 4B for Figure 4A The diagram shows the working voltage and the current in the conduction path in the second embodiment.

[0030] Figure 5A This is a circuit diagram of a third embodiment of the voltage clamping device in this invention.

[0031] Figure 5B for Figure 5A The diagram shows the operating voltage, current in the conduction path, and buffer signals in the third embodiment.

[0032] Explanation of symbols in the attached diagram: 1: LED string lights; 500: Working circuit; 100, 200, 300: Voltage clamping device; CONT: Control signal; VDD: Operating voltage, DC voltage; GND: Grounding terminal; C 11 :capacitance; D 11 :diode; Q 11 First switch; Q 12 Second switch; A 12 First amplifier; A 11 Second amplifier; R 11 First resistor; R 12 Second resistor; R 13 ,R 14 :resistance; 201: Analog-to-digital converter circuit; Q 21 Third switch; A 21 Third amplifier; R 21 Third resistor; R 22Fourth resistor; R 23 ,R 24 :resistance; 301: Constant voltage circuit; 302: Buffer; 303: Analog switch; R 31 : Fifth resistor; R 33 The sixth resistor; R 32 The seventh resistor; R 34 :Eighth resistor; R 38 The ninth resistor; R 39 : The tenth resistor; R 35 ,R 36 ,R 37 ,R 30 :resistance; Q 31 Fourth switch; Q 32 Fifth switch; A 31 First comparator; A 32 Second comparator; A 33 Fourth amplifier; N 31 Inverter; I: Current; 11,12,13,…,1N: LED chips; 10: Control device; VDC: DC power supply; VDC+: Positive voltage terminal; VDC-: Negative voltage terminal. Detailed Implementation

[0033] The technical content and detailed description of the present invention are explained below with reference to the accompanying drawings.

[0034] Please see Figure 1 As shown, it is a circuit block diagram of the LED string of the present invention. Figure 1 The LED string 1 shown has several LED chips 11, 12, 13, ..., 1N connected in series. For example... Figure 1As shown, the LED string 1 receives a DC power supply VDC and includes a control device 10 and several LED chips 11, 12, 13, ..., 1N. The control device 10 is connected between the positive voltage terminal VDC+ and the negative voltage terminal VDC- of the DC power supply VDC.

[0035] For each LED chip 11, 12, 13, ..., 1N, due to the non-ideal characteristics of its components, such as the impedance differences of the RGB LEDs, the LED string will experience a large voltage drop under heavy load. Therefore, if the impedance of one LED decreases, it will cause a sudden voltage drop, resulting in an increase in the voltage of other LEDs and affecting their operation.

[0036] like Figure 2 As shown, each LED chip 11, 12, 13, ..., 1N includes a working circuit 500 and voltage clamping devices 100, 200, 300. The working circuit 500 may include, for example, but not limited to, a buffer, a sequencing circuit, a sorting circuit, an LED control circuit, etc., to provide power control and / or light emission control for the corresponding LED chips 11, 12, 13, ..., 1N. The voltage clamping devices 100, 200, 300 are coupled to the working circuit 500, and the working circuit 500 and the voltage clamping devices 100, 200, 300 are electrically connected between the DC voltage VDD and the ground terminal GND (in this embodiment, the ground terminal GND is used as an example; in other embodiments, it may be a negative voltage terminal). Compared to the Zener diodes used in existing voltage clamping technologies, which are passive components, the Zener diodes do not change according to the voltage drop across each LED chip 11, 12, 13, ..., 1N of the DC voltage VDD. Therefore, the LED chips 11, 12, 13, ..., 1N at the end of the series LED string may fail to start the voltage regulation effect (i.e., voltage regulation failure).

[0037] Therefore, the present invention achieves the voltage clamping effect by using the voltage clamping device 100, 200, 300 of the active component. In this way, regardless of the change in the voltage drop of the DC voltage VDD (that is, the working voltage VDD, hereinafter referred to as such) on each light-emitting diode 11, 12, 13, ..., 1N, the voltage clamping effect on the working circuit 500 can be achieved by controlling the active component.

[0038] Please see Figure 3A The diagram shown is a circuit diagram of a first embodiment of the voltage clamping device of the present invention. The voltage clamping device 100 mainly includes a capacitor C. 11 First switch Q 11 Second switch Q 12 First amplifier A 12 Second amplifier A 11and the voltage divider resistor network (first resistor R) 11 The second resistor R 12 ).

[0039] The voltage clamping device 100 is controlled by the control signal CONT provided by the operating circuit 500. Therefore, the control signal CONT is used to start or stop the voltage regulation function of the voltage clamping device 100. Specifically, the control signal CONT is used to control the first switch Q. 11 In this embodiment, the first switch Q 11 It is an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), with the first switch Q. 11 The gate receives and is controlled by the control signal CONT. The first switch Q... 11 The source of the device is powered by the operating voltage VDD.

[0040] When the control signal CONT turns on the first switch Q 11 The operating voltage VDD powers the voltage clamping device 100. The operating voltage VDD is supplied through diode D. 11 The forward power supply path for capacitor C 11 Charging, therefore capacitor C 11 The voltage across the diode (i.e., the capacitor voltage) gradually increases. Therefore, diode D... 11 With capacitor C 11 Forming a voltage source as the second amplifier A 11 The input power supply.

[0041] Second amplifier A 11 The positive input terminal (or non-inverting input terminal) is connected to diode D. 11 With capacitor C 11 It is used to receive the capacitor voltage, and its negative input terminal (or inverting input terminal) is connected to the second amplifier A. 11 The output terminal of the second amplifier A, therefore 11 This forms a voltage follower (or unity-gain buffer), which has high input impedance and low output impedance, and is used as an impedance matching and buffer circuit. Therefore, the capacitor voltage passes through the second amplifier A. 11 A non-inverting amplifier with a voltage gain of 1 outputs to the second amplifier A. 11 The output terminal of the second amplifier A. 11 The output voltage is passed through resistor R 13 Provided to the first amplifier A 12 The negative input terminal receives the signal, which then serves as the first amplifier A. 12 The reference voltage.

[0042] First amplifier A 12 The positive input terminal is connected to a voltage divider resistor network (the first resistor R).11 The second resistor R 12 ), which includes a first resistor R 11 With the second resistor R 12 It is used to receive the operating voltage VDD and divide the operating voltage VDD, so the divided voltage (i.e., the voltage of the first amplifier A) is... 12 The voltage received at the positive input terminal is equal to .

[0043] When the operating voltage VDD increases, the voltage across the first resistor R... 11 With the second resistor R 12 The voltage divided (i.e., the voltage of the first amplifier A) 12 The voltage received at the positive input terminal also increases accordingly; similarly, when the operating voltage VDD decreases, the voltage received through the first resistor R... 11 With the second resistor R 12 The voltage divided by the amplifier also decreases accordingly. This is because the first amplifier A... 12 It receives a divided voltage (through the positive input terminal) and a reference voltage (through the negative input terminal) respectively, and uses them to amplify the reference voltage. The amplification gain is related to the resistor R. 14 Resistance R 13 And it is related to the voltage divider voltage. Therefore, the larger the operating voltage VDD, the larger the voltage divider voltage, which makes the first amplifier A... 12 The output terminal outputs a high-level signal; conversely, the smaller the operating voltage VDD, the smaller the voltage divider voltage, making the first amplifier A... 12 The output terminal then outputs a low-level signal. In this embodiment, the second switch Q... 12 It is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), with the second switch Q. 12 The gate receiver of the first amplifier A 12 The output signal, and the second switch Q 12 The drain and source terminals receive the operating voltage VDD and are connected to the ground terminal GND, respectively.

[0044] Therefore, when the operating voltage VDD is too high, the first amplifier A... 12 The output terminal outputs a high-level signal to control the second switch Q. 12 Conduction occurs. Therefore, a path with minimal impedance is formed between the operating voltage VDD and the ground terminal GND, thereby generating a large current I in this conductive path to clamp the operating voltage VDD. For example... Figure 3B As shown, it is Figure 3A The diagram shows the working voltage and the current in the conduction path in the first embodiment.

[0045] In summary, this case... Figure 3A The first embodiment disclosed uses capacitor C 11This is achieved in the manner described by the first switch Q. 11 After the control signal CONT turns on the power for a period of time until the operating voltage VDD stabilizes, i.e., after capacitor C... 11 When the capacitor voltage reaches a certain value, the capacitor C is used. 11 Record this fixed capacitor voltage as the operating voltage VDD. And after recording the operating voltage VDD, the first switch Q... 11 The capacitor C is turned off by the control signal CONT. 11 The charging path is established, and this voltage value is used as a reference voltage to provide power to the first amplifier A. 12 .

[0046] When the operating voltage VDD is too high, it will cause the first amplifier A to... 12 The generated signal is at a high level, which in turn controls the second switch Q. 12 When the circuit is turned on, a large current I flows through the path between the operating voltage VDD and the ground terminal GND, thereby clamping the operating voltage VDD to the originally recorded value. Therefore, even if the operating voltage VDD is too high, the voltage clamping device 100 can clamp and stabilize the operating voltage VDD at the desired operating voltage VDD.

[0047] Please see Figure 4A The diagram shown is a circuit diagram of a second embodiment of the voltage clamping device of the present invention. The voltage clamping device 200 mainly includes an analog-to-digital conversion circuit 201 and a third switch Q. 21 Third amplifier A 21 and the voltage divider resistor network (third resistor R) 21 Fourth resistor R 22 Compared to Figure 3A In the first embodiment, the first switch Q is omitted. 11 Diode D 11 Capacitor C 11 and the second amplifier A 11 The use of [other circuits] is replaced directly by the analog-to-digital converter circuit 201. That is, the analog-to-digital converter circuit 201 can be used to achieve the aforementioned first switch Q. 11 Diode D 11 Capacitor C 11 and the second amplifier A 11 Its operation and function.

[0048] The analog-to-digital converter circuit 201 directly receives the operating voltage VDD and converts the analog operating voltage VDD into a digital voltage signal, which can replace the first switch Q in the first embodiment. 11 Control of conduction and shutdown, capacitor C 11 The repeated charging and discharging operation also replaces the second amplifier A.11 The provided voltage follows the operation. Therefore, the analog-to-digital converter 201 directly sets and records the desired operating voltage VDD value through digital control. Furthermore, the analog-to-digital converter 201 provides a third amplifier A. 21 The reference voltage.

[0049] Third amplifier A 21 The positive input terminal is connected to a voltage divider resistor network (the third resistor R). 21 Fourth resistor R 22 ), which includes a third resistor R 21 With the fourth resistor R 22 It is used to receive the operating voltage VDD and divide the operating voltage VDD, so the divided voltage (i.e., the voltage of the third amplifier A) is... 21 The voltage received at the positive input terminal is equal to .

[0050] When the operating voltage VDD increases, it passes through the third resistor R 21 With the fourth resistor R 22 The voltage divided (i.e., the voltage of the third amplifier A) 21 The voltage received at the positive input terminal also increases accordingly; similarly, when the operating voltage VDD decreases, the voltage received through the third resistor R... 21 With the fourth resistor R 22 The voltage divided by the amplifier also decreases accordingly. This is because the third amplifier A... 21 It receives a divided voltage (through the positive input terminal) and a reference voltage (through the negative input terminal) respectively, and uses them to amplify the reference voltage. The amplification gain is related to the resistor R. 24 Resistance R 23 And it is related to the voltage divider voltage. Therefore, the larger the operating voltage VDD, the larger the voltage divider voltage, which makes the third amplifier A... 21 The output terminal of the amplifier outputs a high-level signal; conversely, the smaller the operating voltage VDD, the smaller the voltage divider voltage, making the third amplifier A... 21 The output terminal then outputs a low-level signal. In this embodiment, the third switch Q... 21 It is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), with the third switch Q. 21 Gate receiver third amplifier A 21 The output signal, and the third switch Q 21 The drain and source terminals receive the operating voltage VDD and are connected to the ground terminal GND, respectively.

[0051] Therefore, when the operating voltage VDD is too high, the third amplifier A... 21 The output terminal outputs a high-level signal to control the third switch Q. 21Conduction occurs. Therefore, a path with minimal impedance is formed between the operating voltage VDD and the ground terminal GND, thereby generating a large current I in this conductive path to clamp the operating voltage VDD. For example... Figure 4B As shown, it is Figure 4A The diagram shows the working voltage and the current in the conduction path in the second embodiment.

[0052] In summary, this case... Figure 4A The second embodiment disclosed is implemented using an analog-to-digital converter circuit 201. After the operating voltage VDD is powered on for a period of time until it stabilizes, the analog-to-digital converter circuit 201 sets and records the voltage value (digital voltage value) of the operating voltage VDD to be clamped and regulated. After recording the voltage value of the operating voltage VDD, this voltage value is used as a reference voltage to provide to the third amplifier A. 21 .

[0053] When the operating voltage VDD is too high, it will cause the third amplifier A to... 21 The generated signal is at a high level, which in turn controls the third switch Q. 21 When the circuit is turned on, a large current I flows through the path between the operating voltage VDD and the ground terminal GND, thereby clamping the operating voltage VDD to the originally recorded value. Therefore, even if the operating voltage VDD is too high, the voltage clamping device 200 can clamp and stabilize the operating voltage VDD at the desired operating voltage VDD.

[0054] In the second embodiment, it is implemented by analog-to-digital conversion circuit 201, which records and sets the voltage value of the working voltage VDD. The voltage value is not affected by voltage changes during operation, thus having better stability and accuracy.

[0055] Please see Figure 5A The diagram shown is a circuit diagram of a third embodiment of the voltage clamping device of the present invention. The voltage clamping device 300 mainly includes a constant voltage circuit 301, a first voltage divider resistor network (the fifth resistor R...). 31 The sixth resistor R 33 ), the second voltage divider resistor network (the seventh resistor R) 32 The eighth resistor R 34 First comparator A 31 Second comparator A 32 Buffer 302, Fourth Amplifier A 33 Analog switch 303, fourth switch Q 31 Fifth switch Q 32 And the third voltage divider resistor network (the ninth resistor R) 38 The tenth resistor R 39 ).

[0056] The constant voltage circuit 301 is controlled by the control signal CONT provided by the operating circuit 500. Therefore, the control signal CONT is used to start or stop the voltage regulation function of the voltage clamping device 300. In one embodiment, the constant voltage circuit 301 can be a simple capacitor assembly, a supercapacitor assembly, a linear regulator, a switching regulator, etc.

[0057] After the operating voltage VDD is powered on for a period of time until it stabilizes, the voltage value of the operating voltage VDD to be clamped and regulated is set and recorded by the voltage setting circuit 301. After recording the voltage value of the operating voltage VDD, this voltage value is used as a reference voltage to provide to the first comparator A. 31 With the second comparator A 32 .

[0058] First comparator A 31 The positive input terminal is connected to the second voltage divider resistor network (the seventh resistor R). 32 The eighth resistor R 34 ), which includes the seventh resistor R 32 With the eighth resistor R 34 It is used to receive the operating voltage VDD and divide the operating voltage VDD, so the second divided voltage (i.e., the voltage from the first comparator A) is... 31 The voltage received at the positive input terminal is equal to Second comparator A 32 The negative input terminal is connected to the first voltage divider resistor network (the fifth resistor R). 31 The sixth resistor R 33 ), which includes the fifth resistor R 31 With the sixth resistor R 33 It is used to receive the operating voltage VDD and divide the operating voltage VDD, so the first divided voltage (that is, the second comparator A) is used to receive the operating voltage VDD and divide the operating voltage VDD. 32 The voltage received at the negative input terminal is equal to .

[0059] When the operating voltage VDD increases (especially a rapid increase, or an instantaneous increase, the same applies below and will not be emphasized further), it passes through the seventh resistor R 32 With the eighth resistor R 34 The voltage divided (i.e., the voltage of the first comparator A) 31 The voltage received at the positive input terminal also increases accordingly; similarly, when the operating voltage VDD decreases, the voltage received at the seventh resistor R... 32 With the eighth resistor R 34 The voltage divided by the voltage also decreases accordingly. Furthermore, when the operating voltage VDD increases, the voltage decreases through the fifth resistor R. 31 With the sixth resistor R 33 The voltage divided (i.e., the voltage of the second comparator A)32 The voltage received at the negative input terminal also increases accordingly; similarly, when the operating voltage VDD decreases, the voltage received at the fifth resistor R... 31 With the sixth resistor R 33 The voltage of the divided voltage also decreases accordingly.

[0060] Because the first comparator A 31 The first comparator A receives a second divided voltage (through its positive input terminal) and a reference voltage (through its negative input terminal) respectively, and compares the second divided voltage with the reference voltage. Therefore, when the second divided voltage is greater than the reference voltage, the first comparator A... 31 The output of the first comparator A is a high-level signal; conversely, when the second voltage divider is less than the reference voltage, the first comparator A... 31 The output of the second comparator A then outputs a low-level signal. Furthermore, because the second comparator A... 32 The second comparator A receives a first divided voltage (through the negative input terminal) and a reference voltage (through the positive input terminal) respectively, and compares the first divided voltage with the reference voltage. Therefore, when the first divided voltage is greater than the reference voltage, the second comparator A... 32 The output of the first comparator A is a low-level signal; conversely, when the first voltage divider is less than the reference voltage, the second comparator A... 32 The output terminal outputs a high-level signal.

[0061] See also Figure 5B As shown, it is Figure 5A The diagram shows the operating voltage, current in the conduction path, and register signals in the third embodiment. When the operating voltage VDD increases (especially rapidly) at time t1, causing the second voltage divider voltage to be greater than the reference voltage and the first voltage divider voltage to be greater than the reference voltage, the first comparator A... 31 The output terminal of the second comparator A outputs a high-level signal, and the second comparator A... 32 The output terminal outputs a low-level signal. In this embodiment, the buffer 302 is implemented as an RS flip-flop. In this case, the first comparator A 31 The high-level output signal is provided to the S (setting) input of the buffer 302, while the second comparator A 32 The low-level output signal is provided to the R (reset) input of the buffer 302.

[0062] Since the S (set) input of buffer 302 receives a high-level signal and the R (reset) input receives a low-level signal, the Q output of buffer 302 generates a high-level signal (e.g., Figure 5B (As shown), and this high-level signal is provided to analog switch 303 and inverter N respectively. 31 The high-level signal is transmitted via inverter N. 31 A low-level signal is generated to control the fifth switch Q.32 Off. In this embodiment, the fifth switch Q 32 It is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), with the fifth switch Q. 32 Gate receiver inverter N 31 The output signal, and the fifth switch Q 32 The drain and source are respectively connected to the fourth switch Q. 31 The gate and ground terminal GND. Simultaneously, this high-level signal enables analog switch 303, causing analog switch 303 to output the fourth amplifier A. 33 The signal, thereby accurately controlling the fourth switch Q. 31 The on and off states.

[0063] In this invention, the analog switch 303 can be a transmission gate (TMG), which is implemented using CMOS technology and is used to control the conduction and cutoff of signals. Its core components are a PMOS and an NMOS field-effect transistor, and the conduction is determined by complementary control signals.

[0064] In addition to the operation of the aforementioned circuit, when the operating voltage VDD increases, it passes through the ninth resistor R 38 With the tenth resistor R 39 The provided third voltage divider (i.e., the fourth amplifier A) 33 The voltage received at the positive input terminal of the fourth amplifier (A) also increases accordingly. 33 It receives the third voltage divider (through the positive input terminal) and the reference voltage (through the negative input terminal) respectively, and uses them to amplify the reference voltage. The amplification gain is related to the resistor R. 35 Resistance R 36 Resistance R 37 Resistance R 30 And it is related to the third voltage divider. The larger the operating voltage VDD, the larger the third voltage divider, which will affect the fourth amplifier A. 33 The output terminal outputs a high-level signal, which, after being enabled by analog switch 303, controls the fourth switch Q. 31 On. Incidentally, if analog switch 303 is not enabled, this high-level signal will not control the fourth switch Q. 31 On, in other words, even if the fourth amplifier A is turned on. 33 The output signal is at a high level. If analog switch 303 is not enabled, the fourth switch Q... 31 It will not be connected.

[0065] In this embodiment, the fourth switch Q 31 It is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), with the fourth switch Q. 31Gate receiver of the fourth amplifier A 33 The output signal, and the fourth switch Q 31 The drain and source of the circuit receive the operating voltage VDD and the ground terminal GND, respectively. Therefore, a path with minimal impedance is formed between the operating voltage VDD and the ground terminal GND, thereby generating a large current I in this conductive path to clamp the operating voltage VDD.

[0066] Furthermore, please refer to the following: Figure 5B When the operating voltage VDD decreases at time t3 (especially rapidly, or instantaneously, the same applies below, and will not be emphasized further), causing the second voltage divider to be less than the reference voltage and the first voltage divider to be less than the reference voltage, the first comparator A... 31 The output terminal of the second comparator A outputs a low-level signal. 32 The output terminal of the first comparator A outputs a high-level signal. In this case, the first comparator A... 31 The low-level output signal is provided to the S (setting) input of the buffer 302, while the second comparator A 32 The high-level output signal is provided to the R (reset) input of the buffer 302.

[0067] Since the S (set) input of buffer 302 receives a low-level signal and the R (reset) input receives a high-level signal, the Q output of buffer 302 generates a low-level signal (e.g., Figure 5B (As shown), and the low-level signal is provided to analog switch 303 and inverter N respectively. 31 The low-level signal is transmitted via inverter N. 31 A high-level signal is generated to directly control the fifth switch Q. 32 The circuit is turned on. Simultaneously, the low-level signal disable analog switch 303 will prevent the analog switch 303 from outputting the fourth amplifier A. 33 The output signal. Furthermore, although the third voltage divider increases, due to the fifth switch Q... 32 The circuit is grounded, thus forming a path with extremely high impedance between the operating voltage VDD and the ground terminal GND, thereby significantly reducing the current in the circuit along this path until it reaches zero.

[0068] In summary, this case... Figure 5A The disclosed third embodiment is implemented using a buffer 302 and an analog switch 303 to design a circuit that responds to rapid changes in the operating voltage VDD. That is, when the operating voltage VDD increases rapidly, the first comparator A... 31 A high-level signal is provided to the S (setting) input of the register 302 to determine the control of the fourth switch Q. 31When the second comparator A is turned on, a path with minimal impedance is formed between the operating voltage VDD and the ground terminal GND, thereby generating a large current in this conduction path to clamp the operating voltage VDD. Conversely, when the operating voltage VDD decreases rapidly, the second comparator A... 32 A high-level signal is provided to the R (reset) input of buffer 302 to determine the control of the fifth switch Q. 32 The conduction of the circuit creates a path with extremely high impedance between the operating voltage VDD and the ground terminal GND, thereby significantly reducing the current in the circuit along this path until it reaches zero.

[0069] The above description is merely a detailed explanation and illustration of preferred embodiments of the present invention, but the features of the present invention are not limited thereto and are not intended to limit the present invention. The scope of the present invention should be determined by the following claims. All embodiments that conform to the spirit of the claims and similar variations thereof should be included in the scope of the present invention. Any variations or modifications that can be easily conceived by those skilled in the art within the field of the present invention can be covered by the following claims.

Claims

1. A light-emitting diode (LED) chip, characterized in that, include: A working circuit is electrically connected between a working voltage and a ground terminal to provide power control and / or light emission control for the LED chip; as well as A voltage clamping device is connected in parallel to the operating circuit. The voltage clamping device includes: A switch electrically connects the operating voltage to the ground terminal; When the LED bead is powered on, and the operating voltage increases to exceed a reference voltage, the switch is turned on, forming a conductive path between the operating voltage and the ground terminal, and a large current flows through the conductive path, so that the voltage clamping device clamps the operating voltage supplied to the working circuit.

2. The light-emitting diode (LED) chip according to claim 1, characterized in that, The voltage clamping device includes: A capacitor receives the operating voltage and is charged by the operating voltage to establish a capacitor voltage, and after the operating voltage stabilizes, the capacitor voltage is recorded as the reference voltage; A first amplifier receives the reference voltage and a voltage divider corresponding to the operating voltage, and compares the voltage divider with the reference voltage to generate a switching signal; and The switch receives the switch signal and is controlled by the switch signal; When the operating voltage increases beyond the reference voltage, the switch signal controls the switch to turn on, causing a large current to flow through the conduction path.

3. The light-emitting diode (LED) chip according to claim 2, characterized in that, The voltage clamping device further includes: A first switch is connected in series with the capacitor and is controlled by a control signal provided by the working circuit; When the control signal turns on the first switch, the operating voltage charges the capacitor to establish the capacitor voltage.

4. The light-emitting diode (LED) chip according to claim 2, characterized in that, The voltage clamping device further includes: A voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the divided voltage.

5. The light-emitting diode (LED) chip according to claim 2, characterized in that, The voltage clamping device further includes: A second amplifier receives the capacitor voltage and provides the capacitor voltage as the reference voltage after the operating voltage stabilizes.

6. The light-emitting diode (LED) chip according to claim 1, characterized in that, The voltage clamping device includes: An analog-to-digital converter circuit receives the operating voltage and records it as the reference voltage after the operating voltage stabilizes. A third amplifier receives the reference voltage and a voltage divider corresponding to the operating voltage, and compares the voltage divider with the reference voltage to generate a switching signal; and The switch receives the switch signal and is controlled by the switch signal; When the operating voltage increases beyond the reference voltage, the switch signal controls the switch to turn on, causing a large current to flow through the conduction path.

7. The light-emitting diode (LED) chip according to claim 6, characterized in that, The voltage clamping device further includes: A voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the divided voltage.

8. The light-emitting diode (LED) chip according to claim 1, characterized in that, The voltage clamping device includes: A circuit with a fixed voltage receives the operating voltage and records it as the reference voltage after the operating voltage stabilizes. A first comparator receives the reference voltage and a first voltage divider corresponding to the operating voltage, and compares the first voltage divider with the reference voltage to generate a first temporary signal; A second comparator receives the reference voltage and a second voltage divider corresponding to the operating voltage, and compares the second voltage divider with the reference voltage to generate a second temporary signal; A buffer receives the first temporary signal and the second temporary signal, and generates a temporary output signal based on the levels of the first temporary signal and the second temporary signal; and The switch receives the temporary output signal and is controlled by the temporary output signal; When the operating voltage increases beyond the reference voltage, the temporary output signal controls the switch to turn on, causing a large current to flow through the conduction path.

9. The light-emitting diode (LED) chip according to claim 8, characterized in that, The voltage clamping device further includes: A first voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the first voltage divider; and A second voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the second voltage divider.

10. The light-emitting diode (LED) chip according to claim 8, characterized in that, The voltage clamping device further includes: A fourth amplifier receives the temporary output signal and a second reference voltage, and compares the temporary output signal and the second reference voltage to generate a switching signal to control the switch.

11. The light-emitting diode (LED) chip according to claim 10, characterized in that, The voltage clamping device further includes: A third voltage divider resistor network receives the operating voltage and divides the operating voltage to provide the second reference voltage.

12. The light-emitting diode (LED) chip according to claim 10, characterized in that, The voltage clamping device further includes: An analog switch receives the temporary output signal and the switch signal output by the fourth amplifier; Specifically, when the temporary output signal enables the analog switch, the analog switch outputs the switch signal to control the switch.

13. The light-emitting diode (LED) chip according to claim 8, characterized in that, The voltage clamping device further includes: An inverter, coupled to the buffer, is used to invert the level of the temporary output signal into a second switching signal; and A second switch is coupled to the inverter and the switch, and is controlled by the signal of the second switch.

14. The light-emitting diode (LED) chip according to claim 13, characterized in that, When the operating voltage decreases below the reference voltage, the second switch signal controls the second switch to turn on, causing the current in the conduction path to decrease significantly until zero current.

15. A string of light-emitting diodes, characterized in that, include: A plurality of light-emitting diode (LED) beads are connected in series, and each LED bead includes: A working circuit, electrically connected between a working voltage and a ground terminal, is used to provide power control and / or light emission control for the LED chip; and A voltage clamping device is connected in parallel to the operating circuit. The voltage clamping device includes: A switch electrically connects the operating voltage to the ground terminal; When the LED string is powered on, if the operating voltage of each LED in the LED string increases to exceed a reference voltage, the switch of the LED is turned on, forming a conductive path between the operating voltage and the ground terminal, and a large current flows through the conductive path, so that the voltage clamping device clamps the operating voltage supplied to the working circuit of the LED.

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