LED driver circuit

Abstract

An LED driver circuit is provided, including a power switch transistor, and configured to: switch from a non-deep dimming mode to a deep dimming mode when the high-level duration or duty cycle of a pulse width modulation dimming signal is detected to be less than a preset value; in the non-deep dimming mode, generate a switching control signal for controlling the on and off of the power switch transistor based on the minimum LED margin voltage among the LED margin voltages associated with each LED string connected to the LED driver circuit, a first reference voltage, and the pulse width modulation dimming signal; and in the deep dimming mode, generate the switching control signal based on an output voltage feedback voltage divider characterizing the system output voltage of the LED driver circuit and a second reference voltage, wherein the second reference voltage is greater than the first reference voltage.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more specifically to an LED driving circuit. Background Technology

[0002] In LED driver applications, especially automotive backlighting, the requirements for dimming depth and light sensitivity are becoming increasingly stringent. To improve dimming sensitivity, pulse width modulation (PWM) dimming is typically used in low-current dimming scenarios, adjusting the brightness by regulating the duty cycle of the PWM dimming signal. Adaptive voltage regulation LED driver circuits are favored by applications due to their high efficiency. However, for this type of LED driver circuit, when the pulse width of the PWM dimming signal is less than the bandwidth of the boost loop, the boost loop cannot output sufficient energy to supply the LED channel in time. This leads to a decrease in the output voltage supplied to the LED channel and a reduction in the LED current flowing through the LED string, resulting in lower-than-expected LED brightness. Consequently, the dimming sensitivity deteriorates, and in some cases, dimming becomes impossible when the PWM dimming signal pulse width is very narrow, resulting in poor dimming depth. Summary of the Invention

[0003] An LED driving circuit according to an embodiment of the present invention includes a power switch and is configured to: switch from a non-deep dimming mode to a deep dimming mode when the high-level duration or duty cycle of a PWM dimming signal is detected to be less than a preset value; in the non-deep dimming mode, generate a switching control signal for controlling the on and off of the power switch based on the minimum LED margin voltage among the LED margin voltages associated with each LED string connected to the LED driving circuit, a first reference voltage, and the PWM dimming signal; and in the deep dimming mode, generate the switching control signal based on an output voltage feedback voltage divider characterizing the system output voltage of the LED driving circuit and a second reference voltage, wherein the second reference voltage is greater than the first reference voltage. Attached Figure Description

[0004] The invention can be better understood from the following description of specific embodiments of the invention in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram illustrating the working principle of a traditional LED driver circuit is shown.

[0005] Figure 2 It shows Figure 1 The diagram shows example operating waveforms of multiple signals in the LED driver circuit when the PWM dimming signal changes from a large duty cycle to a small duty cycle.

[0006] Figure 3 It shows Figure 1The diagram shows example operating waveforms of multiple signals in the LED driver circuit when the duty cycle of the PWM dimming signal is small.

[0007] Figure 4 A schematic diagram illustrating the working principle of an LED driving circuit according to an embodiment of the present invention is shown.

[0008] Figure 5 It shows Figure 4 The diagram shows example operating waveforms of multiple signals in the LED driver circuit when the PWM dimming signal changes from a large duty cycle to a small duty cycle.

[0009] Figure 6 It shows Figure 4 The diagram shows a schematic of the example circuit implementation of the depth dimming mode detection unit.

[0010] Figure 7 It shows Figure 4 The depth dimming mode detection unit shown uses Figure 6 The circuit shown is illustrated with example operating waveforms of several related signals during implementation.

[0011] Figure 8 A schematic diagram illustrating the working principle of an LED driving circuit according to another embodiment of the present invention is shown.

[0012] Figure 9 It shows Figure 8 The diagram shows example operating waveforms of multiple signals in an LED driver circuit.

[0013] Figure 10 It shows Figure 8 The diagram shows a schematic of the example circuit implementation of the successive approximation circuit module.

[0014] Figure 11 It shows Figure 10 The example operating waveforms of the relevant signals of the successive approximation circuit module are shown. Detailed Implementation

[0015] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configuration and algorithm presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description in order to avoid unnecessarily obscuring the invention. Furthermore, it should be noted that the term "A connected to B" as used herein can mean "A and B are directly connected" or "A and B are indirectly connected via one or more other elements."

[0016] Figure 1 A schematic diagram illustrating the working principle of a traditional LED driver circuit is shown. Figure 1The illustrated LED driver circuit 100 includes a boost loop 102 and one or more LED channel loops 104. The boost loop 102 adaptively adjusts the system output voltage VOUT based on the minimum LED margin voltage VLED_min among the LED margin voltages VLED associated with each LED string connected to the respective LED channel loop (each LED string connected to each LED channel loop 104 is connected between the LED channel loop and the system output voltage VOUT). The LED channel loop 104 adjusts the LED current ILED flowing through the corresponding LED string according to application requirements. The boost loop 102 and the LED channel loop 104 work together to ensure stable and efficient operation of the entire system. When the PWM dimming signal DIM is low, the LED current ILED flowing through the LED string is zero, the error amplifier EA stops working, and the boost loop 102 does not need to control the switching transistor Q1 to switch between on and off states to provide energy to the LED string. When the PWM dimming signal DIM is high, the error amplifier EA operates, and the boost loop 102 controls the switch Q1 to rapidly switch between on and off states to adjust the system output voltage VOUT. Here, the system output voltage VOUT = VLED + Vdrop, where Vdrop is the forward voltage drop of the LED string. With a constant number of LED strings, the magnitude of the forward voltage drop Vdrop varies with the LED current ILED flowing through the LED string. However, regardless of the change in the LED current ILED, the boost loop 102 maintains the LED margin voltage VLED associated with the LED string at the reference voltage VREF, and the system output voltage VOUT always changes with the magnitude of the LED current ILED flowing through the LED string.

[0017] Figure 2 It shows Figure 1 The diagram shows example waveforms of multiple signals in the LED driver circuit when the PWM dimming signal changes from a large duty cycle to a small duty cycle. Figure 2 As shown, after the duty cycle of the PWM dimming signal DIM decreases, the dimming depth increases, the dimming time decreases, and the system output voltage VOUT decreases, resulting in insufficient operating voltage for the LED string. This leads to a decrease in the LED current ILED flowing through the LED string and a decrease in the LED margin voltage VLED associated with the LED string.

[0018] Figure 3 It shows Figure 1 The diagram shows example waveforms of multiple signals in the LED driver circuit when the duty cycle of the PWM dimming signal is small. Figure 3As shown, during the high-level period of the PWM dimming signal DIM, the output drive voltage SW can only switch between high and low levels a few times to charge the output capacitor COUT. When the charging speed of the output capacitor COUT cannot keep up with the energy consumption rate of the LED string, the system output voltage VOUT continues to decrease. When the system output voltage VOUT decreases, the forward voltage drop Vdrop of the LED string remains unchanged, which leads to a decrease in the LED margin voltage VLED associated with the LED string. When the decrease in the LED margin voltage VLED associated with the LED string causes the LED channel loop 104 to malfunction, the LED current ILED flowing through the LED string will decrease, resulting in a deterioration in the dimming light performance. When the duration of the high-level PWM dimming signal DIM further decreases, it will cause the LED string to turn off, making deep dimming of the LED string impossible.

[0019] In view of the above problems, an LED driving circuit according to an embodiment of the present invention is proposed, which can enter a deep dimming mode when the high-level duration or duty cycle of the PWM dimming signal becomes smaller to a certain extent, thereby realizing deep dimming of the LED string.

[0020] Figure 4 A schematic diagram illustrating the working principle of an LED driving circuit according to an embodiment of the present invention is shown. Figure 4 As shown, the LED driver circuit 400-1 includes a power switch Q1 and is configured to: switch from a non-deep dimming mode to a deep dimming mode when the high-level duration or duty cycle of the PWM dimming signal DIM is detected to be less than a preset value; in the non-deep dimming mode, a switching control signal Gate_Q1 for controlling the on and off of the power switch Q1 is generated based on the minimum LED margin voltage VLED_min among the LED margin voltages VLED associated with each LED string connected to the LED driver circuit 400-1, a first reference voltage VREF1, and the PWM dimming signal DIM; and in the deep dimming mode, the switching control signal Gate_Q1 is generated based on the output voltage feedback divider VOUT_FB (e.g., the voltage generated by the feedback resistors RFBH and RFBL dividing the system output voltage VOUT) and a second reference voltage VREF2, which characterize the system output voltage VOUT of the LED driver circuit 400-1, wherein the second reference voltage VREF2 is greater than the first reference voltage VREF1.

[0021] like Figure 4As shown, in some embodiments, the LED driver circuit 400-1 includes a boost loop 402 and at least one LED channel loop 404. The boost loop 402 includes a deep dimming mode detection unit 4022, configured to detect the high-level duration or duty cycle of the PWM dimming signal DIM, and generate a deep dimming control signal Deep_mode based on a comparison between the high-level duration or duty cycle of the PWM dimming signal DIM and a preset value. When the deep dimming control signal Deep_mode is high, the LED driver circuit 400-1 is in deep dimming mode. When the deep dimming control signal Deep_mode is low, the LED driver circuit 400-1 is in non-deep dimming mode. Here, the function and connection relationship of the LED channel loop 404 are related to the combination... Figure 1 The LED channel loop 104 described is similar and will not be repeated here.

[0022] Specifically, such as Figure 4 As shown, when the depth dimming mode detection unit 4022 detects that the high-level duration or duty cycle of the PWM dimming signal DIM is less than the set value, the depth dimming control signal Deep_mode changes from low to high, and the system enters the depth dimming mode. The feedback voltage VFB switches from the minimum LED margin voltage VLED_min to the output voltage feedback divider VOUT_FB, and the reference voltage VREF switches from the first reference voltage VREF1 to the second reference voltage VREF2. In this case, the system output voltage VOUT = VREF2 * (1 + RFBH / RFBL), that is, the system output voltage VOUT is determined by the second reference voltage VREF2 and the feedback resistors RFBH and RFBL. The system output voltage VOUT can be set to a higher voltage through the feedback resistors RFBH and RFBL so that the LED channel loop 404 can operate normally under the maximum LED current of the system. At this time, the boost loop 402 and the LED channel loop 404 are independent of each other. The PWM dimming signal DIM has no effect on the turn-on and turn-off of the power switch Q1. The boost loop 402 adjusts the system output voltage VOUT based on the output voltage feedback voltage divider VOUT_FB to ensure that the LED channel loop 404 can maintain a positive LED current even when the dimming time is shortened.

[0023] like Figure 4As shown, in some embodiments, the boost loop 402 further includes an error amplifier 4024, a first comparator 4026, and a switch control logic unit 4028, wherein: the error amplifier 4024 is configured to generate an error amplification signal (not shown) based on the output voltage feedback divider VOUT_FB and the second reference voltage VREF2 when the depth dimming control signal Deep_mode is high; the first comparator 4026 is configured to generate a first comparison result signal (not shown) based on the error amplification signal and a current sensing voltage Vsense characterizing the current Isense flowing through the power switch Q1 (e.g., the voltage generated across resistor R by the total current resulting from the sum of the current Isense and the ramp current Islope); and the switch control logic unit 4028 is configured to generate a switch control signal Gate_Q1 based on a first clock signal CLK1 and the first comparison result signal when the depth dimming control signal Deep_mode is high.

[0024] like Figure 4 As shown, in some embodiments, the error amplifier 4024 is further configured to generate an error amplification signal based on the minimum LED margin voltage VLED_min and the first reference voltage VREF1 when the depth dimming control signal Deep_mode is at a low level and the PWM dimming signal DIM is at a high level, and the switch control logic unit 4028 is further configured to generate a switch control signal Gate_Q1 based on the first clock signal CLK1, the first comparison result signal, and the PWM dimming signal DIM when the depth dimming control signal Deep_mode is at a low level.

[0025] like Figure 4 As shown, in some embodiments, the boost loop 402 further includes a first switch S1, which is in an on state when the depth dimming control signal Deep_mode is high and in an off state when the depth dimming control signal Deep_mode is low. When the first switch S1 is on, the output voltage feedback divider VOUT_FB is input to the inverting input of the error amplifier 4024. When the first switch S1 is off, the minimum LED margin voltage VLED_min is input to the inverting input of the error amplifier 4024.

[0026] In some embodiments, such as Figure 4As shown, the boost loop 402 also includes a second switch S2, which is in an on state when the depth dimming control signal Deep_mode is high and in an off state when the depth dimming control signal Deep_mode is low. When the second switch S2 is on, the second reference voltage VREF2 is input to the non-inverting input of the error amplifier 4024. When the second switch S1 is off, the first reference voltage VREF1 is input to the non-inverting input of the error amplifier 4024.

[0027] Figure 5 It shows Figure 4 The diagram shows example waveforms of multiple signals in the LED driver circuit when the PWM dimming signal changes from a large duty cycle to a small duty cycle. Figure 5 As shown, when the high-level duration or duty cycle of the PWM dimming signal DIM is less than a preset value, the system enters deep dimming mode, and the deep dimming control signal Deep_mode changes from low to high. In deep dimming mode, the reference voltage VREF switches from the first reference voltage VREF1 to the higher second reference voltage VREF2, and the feedback voltage VFB switches from the minimum LED margin voltage VLED_min to the output voltage feedback divider VOUT_FB. The system output voltage VOUT increases, meeting the voltage required for the normal operation of the LED string. The LED current ILED flowing through the LED string can be output normally, and the peak value of the LED current remains unchanged, ensuring the dimming depth and linearity of the LED current in deep dimming mode.

[0028] Figure 6 It shows Figure 4 The diagram shows a schematic of an example circuit implementation for the depth dimming mode detection unit. Figure 6 As shown, in some embodiments, the depth dimming mode detection unit 4022 is configured to use a cascaded D flip-flop to time the high-level duration of the PWM dimming signal DIM based on a second clock signal CLK2. Here, the second clock signal CLK2 is a high-frequency clock with a fixed frequency (e.g., 10MHz). It should be noted that the periodic timing detection principle of the PWM dimming signal DIM is similar to... Figure 6 The principle of high-level duration timing detection is similar. After completing the timing of the period and high-level duration of the PWM dimming signal DIM, the depth dimming mode detection unit 4022 can calculate the duty cycle of the PWM dimming signal DIM based on the high-level duration and period of the PWM dimming signal DIM.

[0029] Figure 7 It shows Figure 4 The depth dimming mode detection unit shown uses Figure 6The circuit shown is illustrated with example operating waveforms of several related signals during implementation. Figure 7 As shown, when using a 10MHz clock signal CLK_10M as the second clock signal CLK2 to time the duration of the high level of the PWM dimming signal DIM: if the PWM dimming signal DIM is at a high level when the timer ends, it indicates that the duration of the high level of the PWM dimming signal DIM is greater than the set value, which is a non-deep dimming mode, and the deep dimming control signal Deep_mode is at a low level; if the PWM dimming signal DIM is at a low level when the timer ends, it indicates that the duration of the high level of the PWM dimming signal DIM is less than the set value, which is a deep dimming mode, and the deep dimming control signal Deep_mode is at a high level.

[0030] Figure 8 A schematic diagram illustrating the working principle of an LED driving circuit according to another embodiment of the present invention is shown. Figure 8 The LED driver circuit 400-2 shown is relative to Figure 4 The difference between the LED driver circuit 400-1 shown is that... Figure 8 The LED driver circuit 400-2 shown is also configured to, in deep dimming mode: when the minimum LED margin voltage VLED_min is greater than the product of the first reference voltage VREF1 and the first multiple k1 VREF1*k1, the second reference voltage VREF2 is successively reduced to the product of the first reference voltage VREF1 and the first multiple k1 VREF1*k1, where the first multiple k1 is greater than 1; and when the minimum LED margin voltage VLED_min is less than the product of the first reference voltage VREF1 and the second multiple k2 VREF1*k2, the second reference voltage VREF2 is successively increased to the product of the first reference voltage VREF1 and the second multiple k2 VREF1*k2, where the second multiple k2 is less than 1 and greater than 0.

[0031] like Figure 8 As shown, in some embodiments, Figure 8The LED driving circuit 400-2 shown further includes a margin voltage detection module 406 and a successive approximation circuit module 408. The margin voltage detection module 406 includes a second comparator 4062 and a third comparator 4064. The second comparator 4062 is configured to generate a second comparison result signal VLED_H based on the product of the minimum LED margin voltage VLED_min and the first reference voltage VREF1 with a first multiple k1 (e.g., k1 = 110%), VREF1*k1. The third comparator 4064 is configured to generate a second comparison result signal VLED_H based on the product of the minimum LED margin voltage VLED_min and the first reference voltage VREF1 with a second multiple k1 (e.g., k1 = 110%). The product of k2 (e.g., k2 = 90%), VREF1*k2, is used to generate the third comparison result signal VLED_L. The successive approximation circuit module 408 is configured to, when the depth dimming control signal Deep_mode is high, successively reduce the second reference voltage VREF2 to the product of the first reference voltage VREF1 and the first multiple k1, VREF1*k1, based on the second comparison result signal VLED_H, or successively increase the second reference voltage VREF2 to the product of the first reference voltage VREF1 and the second multiple k2, VREF1*k2, based on the third comparison result signal VLED_L.

[0032] compared to Figure 4 The LED driver circuit shown is 400-1. Figure 8 The LED driver circuit 400-2 shown further optimizes system efficiency in deep dimming mode. Figure 4 When the LED driver circuit 400-1 shown is in deep dimming mode, the switching between the on and off states of the power switch Q1 is independent of the duty cycle of the PWM dimming signal DIM, ensuring that the system output voltage VOUT is always sufficient for the LED channel loop 404 to operate. However, the forward voltage drop Vdrop of the LED string varies with the LED current ILED flowing through it. When the system output voltage VOUT remains constant, the power loss under different LED currents will be very large, resulting in very low system efficiency. Figure 8 In the LED driver circuit 400-2 shown, when the reference voltage VREF is the second reference voltage VREF2 in deep dimming mode, the output voltage system VOUT=VREF2*(1+RFBH / RFBL) is sufficient for the LED channel loop 404 to operate under the maximum LED current of the system; when the reference voltage VREF is the first reference voltage VREF1 in non-deep dimming mode, this determines that the LED margin voltage VLED can ensure that the LED channel loop 404 operates normally with high efficiency.

[0033] like Figure 8As shown, in deep dimming mode, when the minimum LED margin voltage VLED_min is greater than the first reference voltage VREF1 by a certain degree (e.g., VLED_min is greater than VREF1*110%), the successive approximation circuit module 408 starts working, gradually decreasing the reference voltage VREF input to the non-inverting input terminal of the error amplifier 4024 from the second reference voltage VREF2 to reduce the system output voltage VOUT. When the minimum LED margin voltage VLED_min decreases to near the first reference voltage VREF1 (e.g., VLED_min is less than VREF1*110%), the successive approximation circuit module 408 stops working, and VREF input to the non-inverting input terminal of the error amplifier 4024 remains unchanged. At this time, the minimum LED margin voltage VLED_min is lower than VREF1*110% but greater than VREF1, ensuring that the LED channel loop 404 operates efficiently. When the minimum LED margin voltage VLED_min is less than the first reference voltage VREF1 by a certain degree (e.g., VLED_min is less than VREF1*90%), the successive approximation circuit module 408 starts working again, gradually increasing the reference voltage VREF input to the non-inverting input terminal of the error amplifier 4024 in a step-by-step manner until the minimum LED margin voltage VLED_min rises to a level close to the first reference voltage VREF1 (e.g., VLED_min is greater than VREF1*90%). At this point, the reference voltage VREF input to the non-inverting input terminal of the error amplifier 4024 remains unchanged again. At this time, the minimum LED margin voltage VLED_min is greater than VREF1*90%, but less than VREF1, ensuring that the LED channel loop 404 operates normally with high efficiency. Figure 8 The control architecture shown ensures that the minimum LED margin voltage VLED_min is maintained near the first reference voltage VREF1 (e.g., in the 90%~110% range of VREF1) in deep dimming mode, making the LED channel loop 404 efficient and normal.

[0034] Figure 9 It shows Figure 8 The diagram shows example operating waveforms of multiple signals in an LED driver circuit. Figure 9As shown, after the LED driver circuit 400-2 enters the deep dimming mode, the reference voltage VREF switches from the first reference voltage VREF1 to the second reference voltage VREF2. Subsequently, the system output voltage VOUT increases, causing the output voltage feedback divider VOUT_FB and the minimum LED margin voltage VLED_min to increase accordingly. After the minimum LED margin voltage VLED_min rises to a value greater than VREF1*110%, the second comparison result signal VLED_H changes from low to high. While the second comparison result signal VLED_H is high, the reference voltage VREF decreases stepwise from the second reference voltage VREF2 to reduce the system output voltage VOUT, thus reducing the output voltage feedback divider VOUT_FB and the minimum LED margin voltage VLED_min. When the minimum LED margin voltage VLED_min decreases to a value less than VREF1*110%, the reference voltage VREF remains unchanged. When the minimum LED margin voltage VLED is lower than VREF1*90%, the reference voltage VREF starts to increase step by step again until the minimum LED margin voltage VLED_min is greater than VREF1*90%, after which the reference voltage VREF remains unchanged again.

[0035] Figure 10 It shows Figure 8 The diagram shows a schematic representation of the example circuit implementation of the successive approximation circuit module. Figure 10 As shown, the successive approximation circuit module 408 includes a successive approximation digital circuit 4082 and a digital-to-analog converter (DAC) 4084. The successive approximation digital circuit 4082 operates in deep dimming mode. Specifically: when the second comparison result signal VLED_H is high, the DAC 4084 is controlled to decrease the second reference voltage VREF2 in a step-by-step manner based on the third clock signal CLK3. After the second comparison result signal VLED_H changes from high to low, the DAC 4084 stops operating, keeping the reference voltage VREF constant. When the third comparison result signal VLED_L is high, the DAC 4084 is controlled to increase the second reference voltage VREF2 in a step-by-step manner based on the third clock signal CLK3. After the third comparison result signal VLED_L changes from high to low, the DAC 4084 stops operating, keeping the reference voltage VREF constant. The period of the third clock signal CLK3 should be greater than the response time of the boost loop 402 to ensure that after each step change of the reference voltage VREF, the boost loop 402 can stabilize the system output voltage VOUT before detecting and judging whether to further gradually approach it. Figure 11 It shows Figure 10 The example operating waveforms of the relevant signals of the successive approximation circuit module are shown.

[0036] This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment can be modified without departing from the basic spirit of the invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning and scope of the claims and their equivalents are thus included within the scope of the invention.

Claims

1. An LED driver circuit, comprising a power switching transistor, and configured as follows: When the high-level duration or duty cycle of the pulse width modulation dimming signal is detected to be less than the preset value, switch from non-deep dimming mode to deep dimming mode; In the non-deep dimming mode, a switching control signal for controlling the on and off of the power switching transistor is generated based on the minimum LED margin voltage among the LED margin voltages associated with each LED string connected to the LED driving circuit, a first reference voltage, and the pulse width modulation dimming signal; and In the deep dimming mode, the switching control signal is generated based on the output voltage feedback voltage divider, which characterizes the system output voltage of the LED driving circuit, and a second reference voltage, wherein the second reference voltage is greater than the first reference voltage.

2. The LED driving circuit according to claim 1 further includes: The depth dimming mode detection unit is configured to detect the high-level duration or duty cycle of the pulse width modulation dimming signal, and generate a depth dimming control signal based on the comparison between the high-level duration or duty cycle of the pulse width modulation dimming signal and the preset value. When the depth dimming control signal is at a high level, the LED driving circuit is in the depth dimming mode, and when the depth dimming control signal is at a low level, the LED driving circuit is in the non-depth dimming mode.

3. The LED driving circuit according to claim 2 further includes: An error amplifier is configured to generate an error amplification signal based on the output voltage feedback divider and the second reference voltage when the depth dimming control signal is at a high level; The first comparator is configured to generate a first comparison result signal based on the error amplification signal and a current sensing voltage characterizing the current flowing through the power switch. as well as The switch control logic unit is configured to generate the switch control signal based on a first clock signal and a first comparison result signal when the depth dimming control signal is high.

4. The LED driving circuit according to claim 3, wherein, The error amplifier is further configured to generate the error amplification signal based on the minimum LED margin voltage and the first reference voltage when the depth dimming control signal is low and the pulse width modulation dimming signal is high, and the switch control logic unit is further configured to generate the switch control signal based on the first clock signal, the first comparison result signal, and the pulse width modulation dimming signal when the depth dimming control signal is low.

5. The LED driving circuit according to claim 4 further includes: The first switch is in an on state when the depth dimming control signal is high and in an off state when the depth dimming control signal is low. When the first switch is on, the output voltage feedback divider is input to the inverting input of the error amplifier. When the first switch is off, the minimum LED margin voltage is input to the inverting input of the error amplifier.

6. The LED driving circuit according to claim 4 further includes: The second switch is in an on state when the depth dimming control signal is at a high level and in an off state when the depth dimming control signal is at a low level. When the second switch is in an on state, the second reference voltage is input to the non-inverting input terminal of the error amplifier. When the second switch is in an off state, the first reference voltage is input to the non-inverting input terminal of the error amplifier.

7. The LED driving circuit according to claim 2, wherein, The depth dimming mode detection unit is also configured to use a cascaded D flip-flop to time one or both of the high-level duration and period of the pulse width modulation dimming signal based on a second clock signal.

8. The LED driving circuit according to claim 2 is further configured in the depth dimming mode: When the minimum LED margin voltage is greater than the product of the first reference voltage and the first multiple, the second reference voltage is gradually reduced in steps to the product of the first reference voltage and the first multiple, wherein... The first multiple is greater than 1; as well as When the minimum LED margin voltage is less than the product of the first reference voltage and the second multiple, the second reference voltage is gradually increased to the product of the first reference voltage and the second multiple, wherein the second multiple is less than 1 and greater than 0.

9. The LED driving circuit according to claim 8, further comprising: The second comparator is configured to generate a second comparison result signal based on the minimum LED margin voltage and the product of the first reference voltage and the first multiple. The third comparator is configured to generate a third comparison result signal based on the minimum LED margin voltage and the product of the first reference voltage and the second multiple; as well as The successive approximation circuit module is configured to, when the depth dimming control signal is high, successively reduce the second reference voltage to the product of the first reference voltage and the first multiple based on the second comparison result signal, or successively increase the second reference voltage to the product of the first reference voltage and the second multiple based on the third comparison result signal.

10. The LED driving circuit according to claim 9, wherein, The successive approximation circuit module includes a successive approximation digital circuit and a digital-to-analog converter. The successive approximation digital circuit is configured to, when the depth dimming control signal is at a high level, control the analog-to-digital converter to successively reduce the second reference voltage in a stepwise manner to the product of the first reference voltage and the first multiple, based on a third clock signal and a second comparison result signal, or to successively increase the second reference voltage in a stepwise manner to the product of the first reference voltage and the second multiple, based on the third clock and the third comparison result signal.

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