Control circuit for controlling light-emitting elements

Abstract

This invention provides a control circuit for controlling a light-emitting element. The control circuit includes a storage circuit, an arithmetic circuit, and a timer. The arithmetic circuit calculates a unit period based on a set frequency and the order of the operating cycle, and generates a unit count value based on the operating frequency and the unit period. The arithmetic circuit stores the unit count value in the storage circuit. The timer controls the arithmetic circuit to generate a control signal based on the unit count value stored in the storage circuit. The arithmetic circuit uses the control signal to control the light-emitting element. The operating frequency is higher than the set frequency.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly to a control circuit for controlling a light-emitting element. Background Technology

[0002] The emission of light from current light-emitting elements can be controlled by a control circuit. However, the control circuit generates a control signal based on a fixed frequency. The frequency and period of the control signal cannot be changed. Therefore, the emission of light from current light-emitting elements is based on a fixed frequency, thus limiting the emission patterns of the element. Summary of the Invention

[0003] This invention provides a control circuit for controlling light-emitting elements, which can generate a variety of control signals.

[0004] In one embodiment of the present invention, the control circuit includes a storage circuit, an arithmetic circuit, and a timer. The arithmetic circuit is coupled to the storage circuit. The arithmetic circuit receives a set frequency and the order of the operating cycle, calculates a unit cycle based on the set frequency and the order, and generates a unit count value based on the operating frequency and the unit cycle. The arithmetic circuit stores the unit count value in the storage circuit. The timer is coupled to the arithmetic circuit. The timer controls the arithmetic circuit to generate a control signal based on the unit count value stored in the storage circuit. The arithmetic circuit uses the control signal to control the light-emitting element. The operating frequency is higher than the set frequency.

[0005] Based on the above, the control circuit calculates the unit period according to the set frequency and order, and generates a unit count value according to the operation frequency and unit period. The timer receives the unit count value and controls the operation circuit to generate control signals based on the unit count value. In this way, the control circuit can generate a variety of control signals. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a control circuit according to an embodiment of the present invention.

[0007] Figure 2 This is an operation flowchart of a control circuit illustrated according to an embodiment of the present invention.

[0008] Figure 3 This is a waveform diagram of the control signal drawn according to an embodiment of the present invention.

[0009] Figure 4 This is a schematic diagram of a control circuit according to an embodiment of the present invention.

[0010] Explanation of reference numerals in the attached figures

[0011] 100, 200: Control circuit

[0012] 110: Storage circuit

[0013] 120, 220: Operational circuits

[0014] 130: Timer

[0015] 221: Decoder

[0016] 222: Calculation Circuit

[0017] BS: Startup bit

[0018] CI: Control Interface

[0019] CMD: Commands

[0020] CNT: Unit count value

[0021] FC: Operational Frequency

[0022] FS: Set frequency

[0023] K1: First multiple

[0024] K2: Second multiple

[0025] LD: Light-emitting element

[0026] PUNIT: Unit period

[0027] S100: Operating Procedures

[0028] S110~S140: Steps

[0029] SC, SC1, SC2, SC3, SC4: Control signals

[0030] SCL: Order

[0031] T1, T2, T3: Period Detailed Implementation

[0032] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples in the claims of the present invention.

[0033] Please refer to Figure 1 , Figure 1This is a schematic diagram of a control circuit according to an embodiment of the present invention. In this embodiment, the control circuit 100 includes a storage circuit 110, an arithmetic circuit 120, and a timer 130. The arithmetic circuit 120 is coupled to the storage circuit 110. The arithmetic circuit 120 receives a set frequency FS and a duty cycle order SCL, calculates a unit period PUNIT based on the set frequency FS and the order SCL, and generates a unit count value CNT based on the arithmetic frequency FC and the unit period PUNIT. The arithmetic circuit 120 stores the unit count value CNT in the storage circuit 110. In this embodiment, the arithmetic frequency FC is higher than the set frequency FS.

[0034] In this embodiment, timer 130 is coupled to arithmetic circuit 120. Timer 130 controls arithmetic circuit 120 to generate control signal SC based on unit count value CNT stored in storage circuit 110. Arithmetic circuit 120 uses control signal SC to control light-emitting element LD.

[0035] In this embodiment, the control circuit 100 calculates the unit period PUNIT based on the set frequency FS and the order of the operating cycle SCL, and generates a unit count value CNT based on the operation frequency FC and the unit period PUNIT. The timer 130 receives the unit count value CNT and controls the operation circuit 120 to generate a control signal SC based on the unit count value CNT. Therefore, the control circuit 100 can change the frequency and / or waveform of the control signal SC based on the set frequency FS and the order of the operating cycle SCL. In this way, the control circuit 100 can generate various control signals SC.

[0036] In this embodiment, the set frequency FS is the frequency applicable to the light-emitting element LD. The order SCL is equal to the grayscale level applicable to the light-emitting element LD. That is, the order SCL is the number of different grayscale levels that the light-emitting element LD can achieve. For example, if the light-emitting element LD is designed to achieve 255 levels of brightness, the order SCL is equal to "255".

[0037] In this embodiment, the set frequency FS and the order SCL can be stored in the storage circuit 110. The set frequency FS and the order SCL can be input to the storage circuit 110, for example, through the control interface CI. However, the present invention is not limited to the source of the set frequency FS and the order SCL.

[0038] In this embodiment, the arithmetic circuit 120 calculates the unit count value CNT in response to the start bit BS. For example, the storage circuit 110 provides the start bit BS in response to the arithmetic command CMD. The arithmetic command CMD may be provided, for example, by the control interface CI. However, the invention is not limited to the source of the arithmetic command CMD.

[0039] When the arithmetic circuit 120 receives the start bit BS, it receives the set frequency FS and the order SCL from the storage circuit 110 in response to the start bit BS. Next, the arithmetic circuit 120 generates the unit count value CNT based on the set frequency FS, the order SCL, and the arithmetic frequency FC.

[0040] In this embodiment, when the arithmetic circuit 120 is instructed to generate a control signal SC, the arithmetic circuit 120 reads the unit count value CNT from the storage circuit 110 and provides the unit count value CNT to the timer 130. In some embodiments, the timer 130 directly receives the unit count value CNT stored in the storage circuit 110.

[0041] In this embodiment, the light-emitting element LD may include a light-emitting unit (not shown) and a driving circuit (not shown) for driving the light-emitting unit. The driving circuit can drive the light-emitting unit according to the control signal SC. The light-emitting unit may be an LED or other element that can provide output light.

[0042] In this embodiment, the storage circuit 110 may be a storage medium capable of storing data. In this embodiment, the arithmetic circuit 120 may be, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device.

[0043] Please refer to Figure 1 as well as Figure 2 , Figure 2 This is an operation flowchart of a control circuit according to an embodiment of the present invention. In this embodiment, operation flow S100 includes steps S110 to S140. In step S110, the arithmetic circuit 120 obtains the arithmetic frequency FC, the set frequency FS, and the order SCL. Further, in this embodiment, the arithmetic frequency FC can be the frequency of the arithmetic circuit 120 itself. Therefore, the arithmetic circuit 120 itself can know the arithmetic frequency FC. Furthermore, when the arithmetic circuit 120 receives the start bit BS, the arithmetic circuit 120 receives the set frequency FS and the order SCL from the storage circuit 110 in response to the start bit BS.

[0044] In step S120, the arithmetic circuit 120 calculates the product of the set frequency FS and the order SCL, and takes the reciprocal of the product as the unit period PUNIT. Specifically, the arithmetic circuit 120 can obtain the unit period PUNIT according to formula (1).

[0045] Formula (1)

[0046] For example, the frequency FS is set to 30 kHz (but this invention is not limited thereto). The order SCL is equal to "255". Therefore, the unit period PUNIT is equal to 130.7 nanoseconds (ns).

[0047] In step S130, the arithmetic circuit 120 divides the unit period PUNIT by the reciprocal of the arithmetic frequency FC to obtain the unit count value CNT.

[0048] Formula (2)

[0049] In other words, the arithmetic circuit 120 multiplies the unit period PUNIT by the arithmetic frequency FC to obtain the unit count value CNT. Specifically, the arithmetic circuit 120 can obtain the unit count value CNT according to formula (2).

[0050] For example, the operating frequency FC is equal to 60 MHz (however, this invention is not limited thereto). The unit period PUNIT is equal to 130.7 ns. Therefore, the unit count value CNT is equal to "7.84". The unit count value CNT can be approximated as an integer value. Therefore, the unit count value CNT is approximated as "8".

[0051] In step S130, the arithmetic circuit 120 stores the unit count value CNT into the storage circuit 110.

[0052] In step S140, when the arithmetic circuit 120 is instructed to generate a control signal SC, the arithmetic circuit 120 reads the unit count value CNT from the storage circuit 110 and provides the unit count value CNT to the timer 130. Furthermore, the timer 130 controls the arithmetic circuit 120 to generate the control signal SC based on the unit count value CNT.

[0053] For example, the control signal SC is a pulse-width modulation (PWM) signal. The unit count value CNT corresponds to the pulse width difference between two adjacent gray levels of the control signal SC. The timer 130 can trigger the arithmetic circuit 120 based on the unit count value CNT, causing the arithmetic circuit 120 to provide a high voltage value based on a first cycle of at least one unit count value CNT to generate a high voltage value portion of the control signal SC, and to provide a low voltage value based on a second cycle of at least one unit count value CNT to generate a low voltage value portion of the control signal SC.

[0054] For example, the higher the multiples of the unit count value CNT corresponding to high voltage values ​​and low voltage values, the lower the frequency of the control signal SC. Conversely, the lower the multiples of the unit count value CNT corresponding to high voltage values ​​and low voltage values, the higher the frequency of the control signal SC.

[0055] For example, the unit count value CNT equals "8". The operation frequency FC can be the frequency of the operation circuit 120. Therefore, the pulse width difference between two adjacent gray levels of the control signal SC is equal to 8 times the corresponding period of the frequency of the operation circuit 120. In other words, when the gray level corresponding to the control signal SC increases by "1", the width of the positive pulse of the control signal SC increases by 8 times the corresponding period of the frequency of the operation circuit 120. When the gray level corresponding to the control signal SC increases by "2", the width of the positive pulse of the control signal SC increases by 16 times the corresponding period of the frequency of the operation circuit 120.

[0056] It should be noted that the control circuit 200 can use the operating frequency FC and the unit count value CNT to implement the control signal SC with a set frequency FS. Once the set frequency FS of the control signal SC is changed and / or by the working cycle, the control circuit 200 can correspondingly change the unit count value CNT to implement the control signal SC with the set frequency FS.

[0057] Please refer to Figure 1 as well as Figure 3 , Figure 3 This is a waveform diagram of the control signal according to an embodiment of the present invention. In this embodiment, Figure 3Control signals SC1 to SC4 are shown. Control signal SC1 has a fixed operating period and frequency. The arithmetic circuit 120 changes the operating period of control signal SC1 by fixing a first multiple K1 of the unit count value CNT and changing a second multiple K2 of the unit count value CNT, thereby determining the grayscale of the light-emitting element LD. The first multiple K1 is greater than the second multiple K2. The second multiple K2 is associated with the duration of the high voltage level of control signal SC1. For example, the set frequency FS is equal to 30 kHz. The operating frequency FC is equal to 60 MHz. The order SCL is equal to "255". Therefore, the initial first multiple K1 is, for example, equal to "2000". The second multiple K2 is, for example, equal to one of "1" to "255". Therefore, based on the unit count value CNT, the arithmetic circuit 120 can flexibly adjust the waveform of control signal SC1 to generate control signals SC2 to SC4. In this embodiment, at least one of the first multiple K1 and the second multiple K2 of control signal SC1 can be adjusted over time to generate a new control signal.

[0058] For example, the arithmetic circuit 120 changes the unit count value CNT by a first multiple K1 to change the period of the control signal SC1, thereby generating the control signal SC2. Alternatively, the arithmetic circuit 120 increases the unit count value CNT by a first multiple K1 to generate the control signal SC2. Therefore, the period of the control signal SC2 is longer than the period of the control signal SC1.

[0059] For example, the operational circuit 120 changes the unit count value CNT by a first multiple K1 and a second multiple K2 to generate a control signal SC3. The period of the control signal SC3 changes from period T3 to period T2, and then from period T2 to period T1. Next, after several periods T1, the period of the control signal SC3 changes from period T1 to period T2, and then from period T2 to period T3. Period T3 is shorter than period T2. Period T2 is shorter than period T1. Furthermore, the working period corresponding to period T3 is longer than the working period corresponding to period T2. The working period corresponding to period T2 is longer than the working period corresponding to period T1. Therefore, the control signal SC3 provides three stages of grayscale and period, thus presenting a three-stage breathing light effect.

[0060] The operational circuit 120 changes the first multiple K1 and the second multiple K2 of the unit count value CNT to generate a control signal SC4. The period of the control signal SC4 changes from period T1 to period T2, and then changes back to period T1 after several periods T2. Next, the period of the control signal SC4 changes back to period T2 after several periods T1. Therefore, the control signal SC3 provides two stages of grayscale and period, thus presenting a two-stage breathing light effect.

[0061] Please refer to Figure 4, Figure 4 This is a schematic diagram of a control circuit according to an embodiment of the present invention. In this embodiment, the control circuit 200 includes a storage circuit 110, an arithmetic circuit 220, and a timer 130. The arithmetic circuit 220 includes a decoder 221 and a calculation circuit 222. The decoder 221 is coupled to the storage circuit 110. When a start bit BS is received, the decoder 221 receives a set frequency FS and an order SCL from the storage circuit 110. The calculation circuit 222 is coupled to the decoder 221 and the timer 130. The calculation circuit 222 calculates the unit period PUNIT and generates a unit count value CNT based on the arithmetic frequency FC and the unit period PUNIT.

[0062] Upon receiving the start bit BS, decoder 221 provides the set frequency FS and order SCL to calculation circuit 222. Calculation circuit 222 generates a unit count value CNT and stores it in storage circuit 110. When arithmetic circuit 220 is instructed to generate a control signal SC, calculation circuit 222 reads the unit count value CNT from storage circuit 110 and provides it to timer 130. Therefore, timer 130 controls calculation circuit 222 to generate control signal SC based on the triggering of the unit count value CNT. Calculation circuit 222 provides control signal SC to light-emitting element LD.

[0063] In summary, the control circuit calculates the unit period based on the set frequency and order, and generates a unit count value based on the operating frequency and unit period. The timer then uses the unit count value to control the operating circuit to generate control signals. In this way, the control circuit can generate a variety of control signals.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A control circuit for controlling a light-emitting element, characterized in that, The control circuit includes: Storage circuit; An arithmetic circuit, coupled to the storage circuit and configured to receive a set frequency and the order of the operating cycle, calculate a unit cycle based on the set frequency and the order, generate a unit count value based on the arithmetic frequency and the unit cycle, and store the unit count value in the storage circuit; and A timer, coupled to the arithmetic circuit and configured to control the arithmetic circuit to generate control signals based on the unit count value stored in the storage circuit. The operational circuit uses the control signal to control the light-emitting element, and The operating frequency is higher than the set frequency.

2. The control circuit according to claim 1, characterized in that, The set frequency is the frequency applicable to the light-emitting element.

3. The control circuit according to claim 1, characterized in that, The order is equal to the grayscale level applicable to the light-emitting element.

4. The control circuit according to claim 1, characterized in that, The set frequency and the order are stored in the storage circuit.

5. The control circuit according to claim 4, characterized in that: The storage circuit provides a start bit in response to an operation command, and The arithmetic circuit responds to the start bit by receiving the set frequency and the order from the storage circuit.

6. The control circuit according to claim 5, characterized in that, The arithmetic circuit includes: A decoder, coupled to the storage circuit, is configured to receive the set frequency and the order from the storage circuit when the start bit is received.

7. The control circuit according to claim 6, characterized in that, The arithmetic circuit also includes: A computing circuit, coupled to the decoder and the timer, is configured to calculate the unit period and generate the unit count value based on the operation frequency and the unit period. The timer controls the computing circuit to generate the control signal based on the triggering of the unit count value.

8. The control circuit according to claim 1, characterized in that, When the arithmetic circuit is instructed to generate the control signal, the arithmetic circuit reads the unit count value from the storage circuit and provides the unit count value to the timer.

9. The control circuit according to claim 1, characterized in that, The arithmetic circuit calculates the product of the set frequency and the order, and uses the reciprocal of the product as the unit period.

10. The control circuit according to claim 9, characterized in that, The arithmetic circuit multiplies the unit cycle by the arithmetic frequency to obtain the unit count value.

11. The control circuit according to claim 1, characterized in that, The arithmetic circuit changes the first multiple of the unit count value to change the period of the control signal.

12. The control circuit according to claim 11, characterized in that: The arithmetic circuit fixes a first multiple of the unit count value and changes a second multiple of the unit count value to change the working cycle of the control signal, thereby determining the grayscale of the light-emitting element. The first multiple is greater than the second multiple, and The second multiple is associated with the duration of the high voltage level of the control signal.

Images