Light-emitting driving device, light-emitting device and light-emitting system
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-05
- Publication Date
- 2026-08-14
Smart Images
Figure CN122579387A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a light-emitting driving device, a light-emitting device, and a light-emitting system. Background Technology
[0002] Typically, a light-emitting drive device has been provided that can control the light emission of multiple light-emitting elements to be turned on / off (illuminate / extinguish). Summary of the Invention
[0003] The light-emitting driving device according to this disclosure includes a bypass circuit and a bypass control circuit. The bypass circuit is configured to switch between a current-inflow state and a current-outflow state. In the current-inflow state, a driving current flows into each of a plurality of light-emitting elements connected in series. In the current-outflow state, the driving current does not flow but is instead withdrawn. The bypass control circuit is configured to control the bypass circuit in such a way that when an externally input enable signal is at a first logic level, the driving current flows into or withdraws from each light-emitting element, and when the enable signal is at a second logic level, the driving current does not flow into any light-emitting element but is withdrawn from all light-emitting elements until the driving current becomes less than a specified current value.
[0004] The light-emitting device according to this disclosure includes a plurality of light-emitting devices and a light-emitting driving device configured as described above.
[0005] The light-emitting system according to this disclosure includes a light-emitting device configured as described above, and a power supply device configured to generate a drive current based on an enable signal and provide the drive current to the light-emitting device. Attached Figure Description
[0006] Figure 1 This is a diagram showing the configuration of the light-emitting system.
[0007] Figure 2 This is a diagram showing the internal configuration of the light-emitting device.
[0008] Figure 3 This is a timing diagram showing the timing of the light emission control on the light-emitting element array.
[0009] Figure 4 It is a timing diagram showing the time lag between the enable signal input to the power supply unit and the enable signal input to the light-emitting device.
[0010] Figure 5 This is a timing diagram showing the enable signal input to the power supply unit and the enable signal input to the light-emitting device.
[0011] Figure 6 This is a diagram showing the configuration of the light-emitting device in the first embodiment.
[0012] Figure 7This is a timing diagram showing the delays for charging enable and power enable.
[0013] Figure 8 This is a diagram illustrating an example of the internal configuration of the delay control circuit.
[0014] Figure 9 This is a diagram showing the internal configuration of a delay control circuit as another example.
[0015] Figure 10 This is a timing diagram illustrating the internal controls in a configuration example.
[0016] Figure 11 This is a diagram showing the configuration of the gate driver.
[0017] Figure 12 This is a diagram showing a light-emitting device according to a second embodiment.
[0018] Figure 13 This is a diagram showing a light-emitting device according to a third embodiment.
[0019] Figure 14 This is a diagram showing a light-emitting system equipped with multiple light-emitting devices. Detailed Implementation
[0020] <Basic Configuration of Lighting System 100>
[0021] First, the basic configuration of the light-emitting system 100 will be described. Figure 1 This is a diagram showing the configuration of the light-emitting system 100. (As shown) Figure 1 As shown, the lighting system 100 receives an enable signal E from the ECU (Electronic Control Unit) 200. The ECU 200 is a central processing circuit, such as a microcomputer that centrally controls the lighting system 100. The enable signal E is a digital signal that switches between binary logic levels (high and low).
[0022] In response to the enable signal E, the light-emitting system 100 performs or stops driving control on the light-emitting elements (light-emitting elements D1 to D4, described later in this figure) included in the system itself. For example, when the enable signal E is high, the light-emitting system 100 drives and controls the individual light-emitting elements. Conversely, when the enable signal E is low, the light-emitting system 100 turns off the individual light-emitting elements, thereby causing the system to be in a stopped state.
[0023] The light-emitting system 100 includes a power supply unit 1 and a light-emitting device 2. The power supply unit 1 receives an enable signal E as input. Furthermore, the power supply unit 1 operates by receiving a battery voltage Vb. The power supply unit 1 generates a drive current I1 and supplies this current to the light-emitting device 2. This will be explained in detail below.
[0024] The power supply unit 1 includes a boost converter circuit 3 and a drive current generation circuit 4. The boost converter circuit 3 receives an enable signal E as input. Furthermore, the boost converter circuit 3 operates in response to a battery voltage Vb. In response to the enable signal E, the boost converter circuit 3 generates a boost voltage Vo derived from the battery voltage Vb. The boost converter circuit 3 then provides the boost voltage Vo to the drive current generation circuit 4.
[0025] The drive current generation circuit 4 receives an enable signal E and a boost voltage Vo as input. Furthermore, the drive current generation circuit 4 operates based on a battery voltage Vb. The drive current generation circuit 4 generates a drive current I1 based on the enable signal E, the battery voltage Vb, and the boost voltage Vo. The drive current generation circuit 4 provides the drive current I1 to the light-emitting device 2 (more specifically, the light-emitting element array 5, described later).
[0026] Figure 2 This is a diagram showing the internal structure of the light-emitting device 2. (For example...) Figure 1 and Figure 2 As shown, the light-emitting device 2 receives an enable signal E as input. Furthermore, the light-emitting device 2 operates by receiving a battery voltage Vb. The light-emitting device 2 also causes the light-emitting elements D1 to D4 to emit light based on the enable signal E and the drive current I1. This will be explained in detail below.
[0027] The light-emitting device 2 includes a light-emitting element array 5 and a light-emitting driving device 6. The light-emitting element array 5 includes multiple light-emitting elements (D1 to D4 in this case). Light-emitting elements D1 to D4 are connected in series with each other. More specifically, the anode of light-emitting element D4 is connected to the driving current generating circuit 4. The cathode of light-emitting element D4 is connected to the anode of light-emitting element D3. The cathode of light-emitting element D3 is connected to the anode of light-emitting element D2. The cathode of light-emitting element D2 is connected to the anode of light-emitting element D1. The cathode of light-emitting element D1 is connected to node n1.
[0028] Furthermore, in this case, node n1 is connected to the ground terminal GND. Alternatively, node n1 can be connected to a designated circuit other than the ground terminal GND.
[0029] The light-emitting driving device 6 includes a battery terminal Tb and an enable terminal Te. The light-emitting driving device 6 receives an enable signal E via the enable terminal Te. Furthermore, the light-emitting driving device 6 operates by receiving a battery voltage Vb via the battery terminal Tb. The light-emitting driving device 6 controls the light-emitting element array 5 to emit light in response to the enable signal E. The specific structure of the light-emitting driving device 6 is as follows.
[0030] The light-emitting driving device 6 includes a bypass circuit 7 and a bypass control circuit 8. The light-emitting driving device 6 is a semiconductor integrated circuit (IC), in which the bypass circuit 7 and the bypass control circuit 8 are integrated together.
[0031] The bypass circuit 7 is configured to switch to a current-flow state that allows the drive current I1 to flow into each of the light-emitting elements D1 to D4, or to switch to a current-avoidance state that prevents the drive current I1 from flowing into the light-emitting elements D1 to D4 and avoids it.
[0032] The bypass circuit 7 is equipped with multiple switching elements (SW1 to SW4 in this case). Switching elements SW1 to SW4 are N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Switching elements SW1 to SW4 are connected in parallel with light-emitting elements D1 to D4, respectively. This will be explained in detail below.
[0033] The source of switching element SW1 is connected to the cathode of light-emitting element D1 via terminal T1. The drain of switching element SW1, together with the source of switching element SW2, is connected to the anode of light-emitting element D1 and the cathode of light-emitting element D2 via terminal T2.
[0034] The drain of switching element SW2, together with the source of switching element SW3, is connected to the anode of light-emitting element D2 and the cathode of light-emitting element D3 via terminal T3. The drain of switching element SW3, together with the source of switching element SW4, is connected to the anode of light-emitting element D3 and the cathode of light-emitting element D4 via terminal T4. The drain of switching element SW4 is connected to the anode of light-emitting element D4 via terminal T5.
[0035] The gates of each of the switching elements SW1 to SW4 are given inputs of drive signals G1 to G4 from the bypass control circuit 8 (more specifically, gate drivers 9 to 12, described later). The switching elements SW1 to SW4 are turned on / off respectively in response to the drive signals G1 to G4 input to the gates of the switching elements themselves.
[0036] For example, when the switching element SW4 is in the ON state, the drive current I1 does not flow into the light-emitting element D4, but instead flows into the switching element SW4. In this case, the light-emitting element D4 enters a current avoidance state, in which the lamp is off. Conversely, when the switching element SW4 is in the OFF state, the drive current I1 flows into the light-emitting element D4. In this case, the light-emitting element D4 enters a current inflow state, in which the lamp is on.
[0037] Similarly, light-emitting element D3 switches to either a current-avoidance state or a current-inflow state in response to the on / off state of switching element SW3. Furthermore, light-emitting element D2 switches to either a current-avoidance state or a current-inflow state in response to the on / off state of switching element SW2. Light-emitting element D1 switches to either a current-avoidance state or a current-inflow state in response to the on / off state of switching element SW1.
[0038] The bypass control circuit 8 generates drive signals G1 to G4 in response to the enable signal E. This will be explained in detail below. The bypass control circuit 8 includes an internal power supply circuit 15, gate drivers 9 to 12, a main control circuit 13, and a charge pump 14.
[0039] The internal power supply circuit 15 generates an internal power supply voltage Vreg when it receives a supply of battery voltage Vb. The internal power supply circuit 15 supplies the internal power supply voltage Vreg to the gate drivers 9 to 12, the main control circuit 13, and the charge pump 14.
[0040] The main control circuit 13 operates by receiving an internal power supply voltage Vreg. The main control circuit 13 receives an enable signal E as input. Based on the enable signal E, the main control circuit 13 generates control signals S1 to S4. The main control circuit 13 inputs the control signals S1 to S4 to the gate drivers 9 to 12, respectively.
[0041] Charge pump 14 receives an enable signal E as input. Furthermore, charge pump 14 is supplied with an internal power supply voltage Vreg. In response to the enable signal E, charge pump 14 increases the internal power supply voltage Vreg to generate a charging voltage Vcp. Charge pump 14 provides the charging voltage Vcp to gate drivers 9 to 12.
[0042] Gate drivers 9 to 12 generate drive signals G1 to G4 based on the charging voltage Vcp in response to control signals S1 to S4 respectively input to the gate drivers themselves.
[0043] The voltage generated to terminal T1 is assumed to be voltage V1, and similarly, the voltage generated to terminal T2 is assumed to be voltage V2, the voltage generated to terminal T3 is assumed to be voltage V3, the voltage generated to terminal T4 is assumed to be voltage V4, and the voltage generated to terminal T5 is assumed to be voltage V5.
[0044] The voltage value of the high-level drive signal G1 is set to exceed the sum of voltage V1 and the turn-on threshold voltage of switching element SW1. Due to this setting, switching element SW1 is safely turned on when drive signal G1 is high. Furthermore, switching element SW1 is turned off when drive signal G1 is low.
[0045] The voltage value of the high-level drive signal G2 is set to exceed the sum of voltage V2 and the turn-on threshold voltage of switching element SW2. Due to this setting, switching element SW2 is safely turned on when drive signal G2 is high. Furthermore, switching element SW2 is turned off when drive signal G2 is low.
[0046] The voltage value of the high-level drive signal G3 is set to exceed the sum of voltage V3 and the turn-on threshold voltage of switching element SW3. Due to this setting, switching element SW3 is safely turned on when drive signal G3 is high. Furthermore, switching element SW3 is turned off when drive signal G3 is low.
[0047] The voltage value of the high-level drive signal G4 is set to exceed the sum of the voltage V4 and the turn-on threshold voltage of the switching element SW4. Due to this setting, when the drive signal G4 is high, the switching element SW4 is safely turned on. Furthermore, when the drive signal G4 is low, the switching element SW4 is turned off.
[0048] Furthermore, the relationship expression maintains that drive signal G4 > drive signal G3 > drive signal G2 > drive signal G1. That is, the drains of their adjacent switching elements SW1 to SW3 are connected to the sources of switching elements SW2 to SW4, respectively. Therefore, the gate-source voltage of switching elements SW2 to SW4 increases equal to the increment of the drain voltage of their adjacent switching elements SW1 to SW3. This is why the above relationship holds true.
[0049] Charge pump 14 generates a charging voltage Vcp that allows all switching elements SW1 to SW4 to be turned on / off. More specifically, charge pump 14 sets the charging voltage Vcp to a level higher than the high-level drive signal G4.
[0050] When the enable signal E rises to a high level, the light emission control of the light-emitting element array 5 is activated. This will be explained in detail below.
[0051] <Control Example of Light-Emitting System 100>
[0052] Figure 3 This is a timing diagram showing the timing of the light emission control on the light-emitting element array 5. Figure 3 The drive current I1, boost voltage Vo, and enable signal E are shown in order from top to bottom.
[0053] like Figure 3 As shown, when time t1 arrives, the enable signal E rises to a high level. The boost circuit 3 receives the high-level enable signal E as input and begins boost operation based on the battery voltage Vb. Subsequently, when time t2 arrives, the boost voltage Vo begins to increase. After the boost voltage Vo increases to a specified value, when time t3 arrives, the drive current generation circuit 4 generates a drive current I1 based on the boost voltage Vo. The drive current I1 flows into the light-emitting device 2.
[0054] When time t4 arrives, the enable signal E drops to a low level. The boost circuit 3 receives the low-level enable signal E as input, ending the boost operation. Therefore, the boost voltage Vo decreases at and after time t4. Furthermore, the drive current generation circuit 4 receives the low-level enable signal E as input, ending the generation of drive current I1. Therefore, drive current I1 no longer flows to the light-emitting device 2.
[0055] Therefore, the light-emitting driving device 6 controls the light-emitting elements D1 to D4 to emit light during the time period from time t3 to time t4. When time t4 arrives, the light-emitting driving device 6 stops driving the light-emitting elements D1 to D4 and extinguishes the light.
[0056] <Discussion on the flashing of light-emitting elements>
[0057] As described above, the light-emitting system 100 drives and controls its own light-emitting elements (light-emitting elements D1 to D4) in response to the enable signal E. In this case, the enable signal E is input to the power supply unit 1 and the light-emitting device 2 in the light-emitting system 100. Therefore, each of the power supply unit 1 and the light-emitting device 2 switches between starting and stopping its own operation in response to the logic level of the enable signal E input to it.
[0058] In this regard, when the light-emitting device 2 stops operating under the condition that the driving current I1 flows to the light-emitting device 2, there is a concern that the light-emitting elements D1 to D4 may flash. The term flash refers to the instantaneous emission of light. When the light-emitting elements D1 to D4, which are in an off state, flash at the stopping timing of the light-emitting system 100, it can be said that the light-emitting elements D1 to D4 emit light at the moment when they should properly keep the light off. This behavior may undesirably deviate considerably from the correct operation of the light-emitting system 100.
[0059] One possible cause of the flashing is as follows. In one case, a slight time lag occurs in the input enable signal E between the power supply unit 1 side and the light-emitting device 2 side. This time lag may occur due to differences in the wiring length of the enable signal E (more specifically, the difference between the wiring length from ECU 200 to power supply unit 1 and the wiring length from ECU 200 to light-emitting device 2), differences in wiring resistance, noise, etc.
[0060] When this lag occurs, in some cases, the start / stop timing of the operation of the power supply unit 1 does not coincide with the start / stop timing of the operation of the light-emitting device 2.
[0061] Figure 4 This is a timing diagram showing the time lag between the enable signal E (here referred to as enable signal E1) input to the power supply unit 1 and the enable signal E (here referred to as enable signal E2) input to the light-emitting device 2.
[0062] like Figure 4 As shown, assume that enable signal E1 lags behind enable signal E2. Also assume that ECU 200 has already lowered enable signal E2 to a low level. At the immediately following time t4', enable signal E2 drops to a low level. Simultaneously, enable signal E1 remains high at time t4'. At a slightly elapsed time t5 after time t4', enable signal E1 drops to a low level. Then, at a slightly elapsed time t6 after time t5, the drive current I1 stops flowing.
[0063] In the scenario described above, at time t4', the light-emitting device 2 stops operating before the power supply unit 1. More specifically, the operation of the charge pump 14 is stopped while the drive current I1 is flowing. Therefore, the supply of the charging voltage Vcp to the gate drivers 9 to 12 is stopped. Then, although the drive current I1 is flowing, the gates of the switching elements SW1 to SW4 enter a high-impedance state. In this case, the switching elements SW1 to SW4, which had been conducting until time t4', no longer remain conducting at time t4' and thereafter. However, during the period from time t4' to time t6, the drive current I1 flows into the light-emitting device 2. Therefore, the light-emitting elements D1 to D4, which were in a current-avoidance state, are switched to a current-flowing state, allowing the drive current I1 to flow into them, resulting in a flash. Since the drive current I1 stops flowing at the rising moment of time t6, the light-emitting elements D1 to D4 are turned off; however, a flash may still occur during the period from time t4' to time t6.
[0064] Another reason for the flash is as follows. For example... Figure 5 As shown, as an example, it is assumed that there is almost no time delay between the enable signal E1 and the enable signal E2. In this case, when the ECU 200 has already lowered the enable signal E to a low level, the power supply unit 1 and the light-emitting device 2 typically stop operating simultaneously at time t7. However, when the individual operations are delayed within the light-emitting device 2, or when the drive current I1 flows to the light-emitting elements D1 to D4 due to residual charge, there is a possibility that the charge pump 14 may stop operating when the drive current I1 is supplied to the light-emitting device 2. In this case, flashing of the light-emitting elements D1 to D4 may occur during the period from time t7, which is the falling edge timing of the enable signal E2, to time t8, which is the end time of supplying the drive current I1 to the light-emitting device 2.
[0065] In view of the above problems, the light-emitting device 2 of this disclosure is able to suppress the flashing of each light-emitting device (light-emitting elements D1 to D4) when the light-emitting system 100 is stopped. The light-emitting system 100 according to various embodiments of this disclosure will be described in detail below.
[0066] <Light-emitting device 2 according to the first embodiment of this disclosure>
[0067] Figure 6 This is a diagram showing the structure of the light-emitting device 2 in the first embodiment. (See diagram for example.) Figure 6 As shown, in addition to the aforementioned configuration components, the bypass control circuit 8 of this disclosure is also equipped with an OR gate OG. The main control circuit 13 of this disclosure can suppress the aforementioned problems through its internal configuration. This is described in detail below.
[0068] The main control circuit 13 includes a delay control circuit 16 and a driver control circuit 17. The delay control circuit 16 generates a power enable RE, a charging enable CE, and a switch drive enable SE in response to the enable signal E1.
[0069] The delay control circuit 16 generates the charge enable CE in a manner that delays the power enable CE relative to the power enable RE. The delay control circuit 16 also generates the switch drive enable SE in a manner that delays the switch drive enable SE relative to the charge enable CE. Details of the delay control circuit 16 will be described later.
[0070] The first input terminal of the OR gate OG is connected to the enable terminal Te. The second input terminal of the OR gate OG is connected to the main control circuit 13. The output terminal of the OR gate OG is input to the internal power supply circuit 15.
[0071] The OR gate OG receives an enable signal E1 at its first input terminal. The OR gate OG also receives a power enable signal RE at its second input terminal. When at least one of the enable signal E1 and the power enable signal RE is high, the OR gate OG sets the battery enable signal BE to high. Furthermore, when both the enable signal E1 and the power enable signal RE are low, the OR gate OG sets the battery enable signal BE to low.
[0072] The internal power supply circuit 15 receives a high-level battery enable input (BE) and generates the internal power supply voltage Vreg. Conversely, when the internal power supply circuit 15 receives a low-level battery enable input (BE), it stops generating the internal power supply voltage Vreg.
[0073] Charge pump 14 receives a high-level charge enable input CE and generates a charging voltage Vcp. Conversely, charge pump 14 receives a low-level charge enable input CE and stops generating the charging voltage Vcp.
[0074] The driver control circuit 17 receives a high-level switch drive enable input SE and sets control signals S1 to S4 to arbitrary logic levels to arbitrarily control gate drivers 9 to 12 respectively. That is, in this respect, light-emitting elements D1 to D4 are each controlled by the driver control circuit 17 to an arbitrary light-emitting state. At the same time, the driver control circuit 17 receives a low-level switch drive enable input SE and sets control signals S1 to S4 to high levels to control gate drivers 9 to 12, causing light-emitting elements D1 to D4 to turn off to the off state.
[0075] <Control Example of Main Control Circuit 13>
[0076] Figure 7 This is a timing diagram showing the delays of the charge enable (CE) and power enable (RE). For example... Figure 7 As shown, at time t10, the enable signal E1 drops to a low level. In response to the falling edge of the enable signal E1, the main control circuit 13 sets the switch drive enable SE to a low level without any intentional delay. At this level, the gate drivers 9 to 12 set the switching elements SW1 to SW4 to the ON state. Therefore, the light-emitting elements D1 to D4 are placed in a current-avoiding state (=off state) at time t10.
[0077] After a delay of d1 followed by a time delay of t10, at time t11, the delay control circuit 16 lowers the charge enable CE to a low level. In response to the falling edge of the charge enable CE, the charge pump 14 stops generating the charging voltage Vcp. As a result, gate drivers 9 to 12 stop generating drive signals G1 to G4. Therefore, at time t11, the gates of switching elements SW1 to SW4 are placed in a high-impedance state.
[0078] Then, at time t12, a delay time d2 after time t11, the delay control circuit 16 lowers the power enable RE to a low level. Subsequently, the OR gate OG, receiving the low-level enable signal E1 and the low-level power enable RE, lowers the battery enable BE to a low level. The internal power supply circuit 15 stops generating the internal power supply voltage Vreg in response to the falling edge of the power enable RE. Therefore, at time t13, a relatively short time elapsed after time t12, the internal power supply voltage Vreg becomes 0V. Therefore, at time t13, the gate drivers 9 to 12, the main control circuit 13, and the charge pump 14 each enter a stop state. Thus, the power consumption of the light-emitting device 2 during the stop of the light-emitting system 100 is suppressed.
[0079] Therefore, the delay time d1 can be appropriately set so that the supply of drive current I1 to the light-emitting device 2 ends during the period from the moment the enable signal E of ECU 200 drops to a low level until time t11. By doing so, it is evident that at the point in time when the supply of drive current I1 to the light-emitting device 2 ends, the charging enable CE remains at a high level, allowing the charge pump 14 to continue generating the charging voltage Vcp. Therefore, when drive current I1 is supplied to the light-emitting device 2 as described above, the gates of switching elements SW1 to SW4 can be prevented from entering a high-impedance state. Furthermore, flashing of light-emitting elements D1 to D4 can be suppressed.
[0080] <Configuration Example 1 of Delay Control Circuit 16>
[0081] Next, an example of the internal configuration of the delay control circuit 16 will be described. Figure 8 This is a diagram illustrating an example of the internal configuration of the delay control circuit 16. (See diagram for example.) Figure 8 As shown, the delay control circuit 16 in this configuration example includes a signal generator 18 and a counter 19.
[0082] Signal generator 18 receives an input of enable signal E1 and generates charging enable CE, power enable RE, and switch drive enable SE. Counter 19 receives an input of charging enable CE and outputs charging enable CE with a delay time given as delay time d1. Furthermore, counter 19 receives an input of power enable RE and outputs power enable RE with a delay time equal to the total delay time of delay time d1 and delay time d2.
[0083] <Configuration Example 2 of Delay Control Circuit 16>
[0084] The delay control circuit 16 allows the following internal configuration to be used instead of the internal configuration example described above. Figure 9 This is a diagram showing the internal configuration of the delay control circuit 16 as another example. (See diagram for example.) Figure 9 As shown, the delay control circuit 16 of this configuration example includes a constant current source 20, a comparator 21, a threshold voltage generation circuit 22, a switch SWn, and a capacitor C1.
[0085] A constant current source 20 is connected to the internal power supply circuit 15 and node n2. The non-inverting input terminal (+) of comparator 21 is connected to node n2. The inverting input terminal (-) of comparator 21 is connected to the threshold voltage generation circuit 22. The first terminal of switch SWn is connected to node n2. The second terminal of switch SWn is connected to the ground terminal GND. Capacitor C1 is externally connected to the light-emitting driver 6 via terminal Tn between terminal Tn and ground terminal GND. Terminal Tn is connected to node n2 and capacitor C1.
[0086] The constant current source 20 generates a constant current I2 when it receives a supply of battery voltage Vb. The switch SWn turns on when it receives a high-level enable signal E1. Furthermore, the switch SWn turns off when it receives a low-level enable signal E1. The threshold voltage generation circuit 22 generates a threshold voltage Vth1 as a specified constant voltage. The comparator 21 outputs a charging enable CE in response to the comparison result between the voltage at node n2 and the threshold voltage Vth1.
[0087] Figure 10 This is a timing diagram illustrating the internal controls in this configuration example. (Example:) Figure 10 As shown, when the enable signal E1 is high (in Figure 10 Before time t20, switch SWn is turned on as described above. Therefore, a constant current I2 flows to the ground terminal GND, preventing capacitor C1 from charging. Consequently, the voltage at node n2 is lower than the threshold voltage Vth1. Therefore, in this situation, comparator 21 keeps the charging enable CE at a high level.
[0088] When the enable signal E1 drops to a low level, switch SWn is turned off as described above. Then, a constant current I2 flows into capacitor C1, charging it. Consequently, the voltage at node n2 increases. After a delay time d1 followed by time t21, the voltage at node n2 exceeds the threshold voltage Vth1. Therefore, as time t21 arrives, comparator 21 lowers the charging enable CE to a low level.
[0089] The delay time d1 is determined based on the capacitance of capacitor C1. Capacitor C1 is externally connected to the light-emitting drive device 6. Therefore, capacitor C1 of arbitrary capacitance is connected to terminal Tn, and this capacitor C1 is selected to obtain the desired delay time d1.
[0090] <Configuration examples of gate drivers 9 to 12>
[0091] This section describes configuration examples for gate drivers 9 through 12. Figure 11 This is a diagram showing the configuration of gate driver 9. Since gate drivers 9 to 12 are substantially the same in configuration, gate driver 9 will be described, and gate drivers 10 to 12 are omitted in the description.
[0092] like Figure 11 As shown, the gate driver 9 includes a regulator 30 and a drive circuit 31. When the regulator 30 receives a charging voltage Vcp, it reduces the charging voltage Vcp to generate a high-side voltage Vh and a low-side voltage Vl.
[0093] The input terminal of the drive circuit 31 receives the control signal S1. The high-side power supply terminal of the drive circuit 31 receives the high-side voltage Vh. The low-side power supply terminal of the drive circuit 31 receives the low-side voltage V1. The drive circuit 31 outputs a drive signal G1 upon receiving both the high-side voltage Vh and the low-side voltage V1. More specifically, to set the drive signal G1 to a high level, the drive circuit 31 sets the drive signal G1 to a value equivalent to the high-side voltage Vh. Conversely, to set the drive signal G1 to a low level, the drive circuit 31 sets the drive signal G1 to a value equivalent to the low-side voltage V1.
[0094] As described above, the high-level voltage values of drive signals G1 to G4 increase sequentially from G1 to G4. Therefore, the regulator 30 of gate drivers 9 to 12 generates a high-side voltage Vh that increases sequentially from gate drivers 9 to 12. This will be explained in detail below.
[0095] The regulator 30 of gate driver 9 generates a high-side voltage Vh equivalent to a high-level drive signal G1. The regulator 30 of gate driver 10 generates a high-side voltage Vh equivalent to a high-level drive signal G2. The regulator 30 of gate driver 11 generates a high-side voltage Vh equivalent to a high-level drive signal G3. The regulator 30 of gate driver 12 generates a high-side voltage Vh equivalent to a high-level drive signal G4.
[0096] <Light-emitting device 2 according to the second embodiment>
[0097] Next, the light-emitting device 2 according to the second embodiment will be described in detail. The light-emitting device 2 of this embodiment has a substantially the same structure as the light-emitting device 2 of the first embodiment. Therefore, components common to the first embodiment are indicated by the same reference numerals, which are omitted from their description; the configurations that differ from those of the first embodiment will be explained mainly.
[0098] Figure 12 This is a diagram illustrating the light-emitting device 2 in the second embodiment. (See diagram for example.) Figure 12 As shown, the main control circuit 13 of this embodiment includes a driver control circuit 23 and a current sensing circuit 24. Furthermore, the sensing resistor R1 is externally connected to the light-emitting device 2 of this embodiment via terminals T6 and T7.
[0099] The first terminal of the sensing resistor R1 is connected to terminal T6 and the cathode of the light-emitting element D1. Furthermore, the second terminal of the sensing resistor R1 is connected to terminal T7 and node n1.
[0100] When a drive current I1 is provided to the light-emitting device 2, the current flows from the cathode or terminal T1 of the light-emitting device D1 to the sensing resistor R1. Then, a voltage V6 is generated across the sensing resistor R1 in response to the resistance value of the sensing resistor R1.
[0101] The driver control circuit 23 receives an enable signal E1 as input. Upon receiving a high-level enable signal E1, the driver control circuit 23 generates control signals S1 to S4 of arbitrary logic levels to control gate drivers 9 to 12, causing any one of the light-emitting elements D1 to D4 to enter an arbitrary light-emitting state. Furthermore, upon receiving a low-level enable signal E1, the driver control circuit 23 generates low-level control signals S1 to S4 to control gate drivers 9 to 12, causing light-emitting elements D1 to D4 to turn off.
[0102] The current sensing circuit 24 is configured to detect whether current flows in the sensing resistor R1 and generate a current sensing signal Vse in response to the detection result. The current sensing signal Vse is a digital signal that can be changed between binary logic levels, i.e., high or low. The current sensing circuit 24 inputs the current sensing signal Vse to the charge pump 14.
[0103] In this embodiment, the charge pump 14 receives a high-level current sensing signal Vse as input and generates a charging voltage Vcp based on the battery voltage Vb. Furthermore, in this embodiment, the charge pump 14 receives a low-level current sensing signal Vse as input and terminates the generation of the charging voltage Vcp.
[0104] The specific configuration of the current sensing circuit 24 is as follows. The current sensing circuit 24 includes a threshold voltage generation circuit 25 and a comparator 26. The threshold voltage generation circuit 25 generates a threshold voltage Vth2, which is a specified constant voltage.
[0105] The non-inverting input terminal (+) of comparator 26 is connected to terminal T6. The inverting input terminal (-) of comparator 26 is connected to threshold voltage generation circuit 25.
[0106] A voltage V6 is applied to the non-inverting input terminal (+) of comparator 26 via terminal T6. A threshold voltage Vth2 is applied to the inverting input terminal (-) of comparator 26. Comparator 26 generates a current sensing signal Vse in response to the comparison result between voltage V6 and threshold voltage Vth2, thereby inputting the signal to charge pump 14.
[0107] For example, when voltage V6 exceeds threshold voltage Vth2 (i.e., when drive current I1 exceeds a specified current value), comparator 26 sets the current sensing signal Vse to a high level. In this state, assume that enable signal E1 has already dropped from a high level to a low level. Then, as described above, driver control circuit 23 sets control signals S1 to S4 to a high level to turn on switching elements SW1 to SW4. Therefore, light-emitting elements D1 to D4 enter a current avoidance state, causing light-emitting elements D1 to D4 to turn off. In this case, drive current I1 flows into sensing resistor R1 via terminal T1.
[0108] Assume a hysteresis occurs between the enable signals E1 and E2 as described above. Furthermore, assume that the enable signal E1 has already dropped to a low level while the drive current I1 is supplied to the light-emitting device 2. In this case, as long as the drive current I1 exceeds a specified amount supplied to the light-emitting device 2, the current sensing signal Vse remains at a high level as described above. Therefore, even when the enable signal E1 has dropped to a low level, the charge pump 14 continues to generate the charging voltage Vcp until the current value of the drive current I1 becomes lower than a specified value (i.e., the voltage V6 becomes lower than the threshold voltage Vth2), causing the threshold voltage generation circuit 25 to stop detecting the drive current I1. Therefore, when the drive current I1 is supplied to the light-emitting device 2, the switching elements SW1 to SW4 can remain in the on state. Thus, it is possible to prevent the light-emitting elements D1 to D4 from flickering during the stop timing of the light-emitting system 100.
[0109] <Light-emitting device 2 according to the third embodiment>
[0110] Next, the light-emitting device 2 according to the third embodiment will be described in detail. The light-emitting device 2 of this embodiment has a substantially the same structure as that of the first embodiment. Therefore, components common to the first embodiment are indicated by the same reference numerals, which are omitted from their description; the configurations that differ from those of the first embodiment will be explained mainly.
[0111] Figure 13 This is a diagram showing the light-emitting device 2 in the third embodiment. (See diagram for example.) Figure 13 As shown, in addition to bypass circuit 7, the light-emitting driving device 6 according to this embodiment also includes another bypass circuit 27, different from bypass circuit 7. Bypass circuit 27 detects that the falling edge of the enable signal E1 is low, causing the drive current I1 to flow through bypass circuit 27 itself to the ground terminal, resulting in the light-emitting elements D1 to D4 entering a current-avoidance state. This will be explained in detail below.
[0112] The bypass circuit 27 includes a switching element SW5 and a driver control circuit 28. The switching element SW5 is an N-channel MOSFET. The source of the switching element SW5 is connected to terminal T1 together with the source of the switching element SW1. The drain of the switching element SW5 is connected to terminal T5 together with the drain of the switching element SW4. The gate of the switching element SW5 receives the input of the drive signal G5.
[0113] Switching element SW5 is turned on when it receives a high-level drive signal G5 to its own gate input. Conversely, switching element SW5 is turned off when it receives a low-level drive signal G5 to its own gate input.
[0114] The driver control circuit 28 operates by receiving a battery voltage Vb. Additionally, the driver control circuit 28 receives an enable signal E1 as input. Upon receiving a high-level enable signal E1, the driver control circuit 28 sets the drive signal G5 to a low level. Furthermore, when the driver control circuit 28 detects a low falling edge on the enable signal E1, it raises the drive signal G5 to a high level.
[0115] In this embodiment, the charge pump 14 generates a charging voltage Vcp when a high-level enable signal E1 is input. Furthermore, the charge pump 14 stops generating the charging voltage Vcp when a low-level enable signal E1 is input.
[0116] The main control circuit 13 of this embodiment includes a driver control circuit 29. The driver control circuit 29 receives a high-level enable signal E1 as input and generates control signals S1 to S4 of arbitrary logic levels to control gate drivers 9 to 12 respectively, causing any one or more of the light-emitting elements D1 to D4 to enter an arbitrary light-emitting state. Furthermore, the driver control circuit 29 receives a low-level enable signal E1 as input and generates low-level control signals S1 to S4 to control gate drivers 9 to 12, causing light-emitting elements D1 to D4 to turn off.
[0117] Assume that ECU 200 has already lowered the enable signal E to a low level. In this case, charge pump 14, driver control circuit 28, and driver control circuit 29 receive the low-level enable signal E1 as input. Then, as described above, charge pump 14 stops generating the charging voltage Vcp.
[0118] In this situation, the driver control circuit 28 also sets the drive signal G5 to a high level. Then, as described above, the switching element SW5 is turned on. Therefore, even when the charge pump 14 has stopped charging the voltage Vcp so that the switching elements SW1 to SW4 can no longer remain in the on state due to the drive current I1 being supplied to the light-emitting device 2, the drive current I1 is withdrawn from the light-emitting elements D1 to D4 and flows through the switching element SW5 and terminal T1 to node n1. Therefore, the flashing of the light-emitting elements D1 to D4 can be suppressed.
[0119] <Light-emitting system 100 equipped with multiple light-emitting devices 2>
[0120] The light-emitting system 100 in each of the above embodiments can be configured to be equipped with a plurality of light-emitting devices 2. For example, the light-emitting system 100 equipped with a plurality of light-emitting devices 2 according to the first embodiment is configured as follows.
[0121] Figure 14 A light-emitting system 100 equipped with multiple light-emitting devices 2 is shown. For example... Figure 14 As shown, the light-emitting system 100 of this construction example includes a first light-emitting device 2a and a second light-emitting device 2b. Each of the first light-emitting device 2a and the second light-emitting device 2b is equivalent to the aforementioned light-emitting device 2. The aforementioned node n1 serves as a connection node between terminal T1 of light-emitting device 2a and terminal T5 of light-emitting device 2b. Terminal T1 of light-emitting device 2b is connected to a ground terminal together with the cathode of light-emitting device D1.
[0122] The enable signal E1 is input to the enable terminal Te of the light-emitting device 2a and the enable terminal Te of the light-emitting device 2b.
[0123] The light-emitting system 100, as shown in this configuration example, is equipped with multiple light-emitting devices 2 (in... Figure 14 In the case of a configuration of light-emitting devices 2a and 2b), the aforementioned flashing can be suppressed in the light-emitting system 100 equipped with multiple light-emitting devices. Furthermore, the light-emitting device 2 in this embodiment is not limited to the light-emitting device 2 of the first embodiment, but may also be the light-emitting device 2 of the second embodiment or the light-emitting device 2 of the third embodiment.
[0124] <Variation>
[0125] Furthermore, this disclosure is not limited to the above-described embodiments and can be changed or modified in various ways without departing from the spirit of this disclosure. For example, although in the above description the enable signal E is input to switch SWn (see... Figure 9 However, the switch driver enable SE can replace the enable signal E.
[0126] Furthermore, for example, although the light-emitting element array 5 in the above embodiment includes light-emitting elements D1 to D4, as an example, the light-emitting element array 5 may include two light-emitting elements, or may include five or more light-emitting elements.
[0127] The light-emitting driving device (6) disclosed herein is configured to include: a bypass circuit (7) configured to switch between an inflow state and a backoff state, wherein in the inflow state, a driving current (I1) flows into each of a plurality of light-emitting elements (D1 to D4) connected in series, and in the backoff state, the driving current (I1) does not flow but is backoffed; and a bypass control circuit (8) configured to control the bypass circuit (7) such that when an externally input enable signal (E, E1, E2) is at a first logic level, the driving current (I1) flows into or is backoffed from each light-emitting element (D1 to D4), and when the enable signal (E, E1, E2) is at a second logic level, the driving current (I1) does not flow into all light-emitting elements (D1 to D4) but is backoffed from all light-emitting elements (D1 to D4) until the driving current (I1) becomes less than a specified current value (first configuration).
[0128] According to the first configuration, the light-emitting driving device (6) can be suitably configured such that the bypass circuit (7) includes a plurality of switching elements (SW1 to SW4) respectively connected in parallel with the light-emitting elements (D1 to D4), such that in the on state, the driving current (I1) is deflected from the light-emitting elements (D1 to D4) to the bypass circuit itself so as to be prevented from flowing to the light-emitting elements (D1 to D4), and in the off state, the driving current (I1) is allowed to flow to the light-emitting elements (D1 to D4) (second configuration).
[0129] According to the first or second configuration, the light-emitting driving device (6) can be suitably configured as a bypass control circuit (8) comprising: a delay control circuit (16) configured to generate a first control signal (SE) and a second control signal (CE) obtained by adding a specified delay time (d1) to the first control signal (SE) based on at least one of the logic level of the enable signal (E, E1, E2) and the drive current (I1); an operating voltage generation circuit (14) configured to generate a first operating voltage (Vcp) in response to the second control signal (CE); and a drive control circuit (17) configured to drive the bypass circuit (7) such that, upon receiving the supply of the first operating voltage (Vcp), the bypass circuit switches between an inflow state and a backoff state of the light-emitting elements (D1 to D4) based on the first control signal (SE) (third configuration).
[0130] According to the third configuration, the light-emitting driving device (6) can be suitably configured such that the delay control circuit (16) operates to: set the first control signal (SE) to the third logic level when receiving an input of an enable signal (E, E1, E2) having a first logic level; set the first control signal (SE) to the fourth logic level when receiving an input of an enable signal (E, E1, E2) having a second logic level; and switch the second control signal (CE) from the third logic level to the fourth logic level when a delay time (d1) has elapsed since the enable signal (E, E1, E2) switched from the first logic level to the second logic level, and the operating voltage generation circuit (14) operates to: generate a first operating voltage (Vcp) when receiving an input of a first control signal (SE) having a third logic level, and stop generating the first operating voltage (Vcp) when receiving an input of a first control signal (SE) having a fourth logic level (fourth configuration).
[0131] According to the first configuration, the light-emitting driving device (6) can be suitably configured such that the bypass control circuit (8) includes: a current sensing circuit (24) configured to sense the driving current (I1) and generate a sensing signal in response to the sensing result; and a driving control circuit (17) configured to drive the bypass circuit (7) such that when a first operating voltage (Vcp) is received, the bypass circuit switches between the inflow state and the outflow state of the light-emitting elements (D1 to D4) based on the enable signal (E, E1, E2) (fifth configuration).
[0132] The light-emitting driving device (6) according to the first configuration can be suitably configured such that the bypass circuit (7) includes: a second bypass circuit (27) connected in parallel to the light-emitting element array (5) consisting of light-emitting elements (D1 to D4), and configured to allow the driving current (I1) to flow into the light-emitting element array (5), or to allow the driving current (I1) to retreat from the light-emitting element array (5) so that the driving current (I1) does not flow to any of the light-emitting elements (D1 to D4); and the first bypass circuit (7) connected in parallel to the light-emitting elements (D1 to D4) and configured such that when the driving current (I1) flows into the light-emitting element array (5), the flow state of each of the light-emitting elements (D1 to D4) and The bypass control circuit (8) includes: a working voltage generation circuit (14) configured to generate a first working voltage (Vcp) in response to the enable signal (E, E1, E2); a first bypass drive control circuit (29) configured to drive the first bypass circuit (7) upon receiving the first working voltage (Vcp) to switch between the inflow state and the backoff state of the light-emitting elements (D1 to D4); and a second bypass drive control circuit (28) configured to operate based on a second working voltage (Vcp) provided from the outside and to drive the second bypass circuit (27) in response to the enable signal (E, E1, E2) (sixth configuration).
[0133] The light-emitting drive (6) according to any of the first to sixth configurations can be suitably configured such that the bypass circuit (7) and the bypass control circuit (8) are integrated together (seventh configuration).
[0134] The light-emitting device (2) disclosed herein may be suitably configured to include a plurality of light-emitting devices (D1 to D4) and a light-emitting driving device (6) according to any one of the first to seventh configurations (eighth configuration).
[0135] According to the eighth configuration, the light-emitting device (2) can be appropriately configured to have multiple light-emitting driving devices (6) (ninth configuration).
[0136] The light-emitting system (100) disclosed herein is configured to include a light-emitting device (2) according to an eighth or ninth configuration, and a power supply device (1) configured to generate a drive current (I1) based on an enable signal (E, E1, E2) and provide the drive current (I1) to the light-emitting device (2) (tenth configuration).
[0137] According to the tenth configuration, the light-emitting system (100) can be suitably configured such that the power supply device (1) includes: a boost circuit (3) configured to generate a boost voltage (Vo) obtained by boosting an externally supplied power supply voltage (Vb) based on an enable signal (E, E1, E2); and a drive current generation circuit (4) configured to generate a drive current (I1) by current-to-voltage conversion of the boost voltage (Vo) (eleventh configuration).
Claims
1. A light-emitting driving device, comprising: A bypass circuit is configured to switch between an inflow state and a backoff state, wherein in the inflow state, a drive current flows into each of a plurality of light-emitting elements connected in series, and in the backoff state, the drive current does not flow but is backed off. as well as The bypass control circuit is configured to control the bypass circuit in such a way that when an externally input enable signal is at a first logic level, the drive current flows into or flows away from each of the light-emitting elements, and when the enable signal is at a second logic level, the drive current does not flow into any of the light-emitting elements, but flows away from all of the light-emitting elements, until the drive current becomes less than a specified current value.
2. The light-emitting driving device according to claim 1, wherein, The bypass circuit includes a plurality of switching elements connected in parallel with the light-emitting element, such that, in the on state, the drive current is diverted from the light-emitting element to the bypass circuit itself so as to be prevented from flowing to the light-emitting element, and in the off state, the drive current is allowed to flow to the light-emitting element.
3. The light-emitting driving device according to claim 1, wherein, The bypass control circuit includes: A delay control circuit is configured to generate a first control signal and a second control signal by adding a specified delay time to the first control signal based on at least one of the logic level of the enable signal and the drive current. The operating voltage generation circuit is configured to generate a first operating voltage based on the second control signal; and A drive control circuit is configured to drive the bypass circuit such that, upon receiving a supply of the first operating voltage, the bypass circuit switches between the inflow state and the backoff state of the light-emitting element based on the first control signal.
4. The light-emitting driving device according to claim 3, wherein, The delay control circuit operates to: When an input with the first logic level is received, the first control signal is set to the third logic level; When an input with an enable signal having the second logic level is received, the first control signal is set to the fourth logic level; as well as When the delay time has elapsed since the enable signal switched from the first logic level to the second logic level, the second control signal is switched from the third logic level to the fourth logic level, and The operating voltage generation circuit operates to: Upon receiving an input of a first control signal having the third logic level, the first operating voltage is generated, and Upon receiving an input of a first control signal having the fourth logic level, the generation of the first operating voltage is stopped.
5. The light-emitting driving device according to claim 1, wherein, The bypass control circuit includes: A current sensing circuit, the current sensing circuit being configured to sense the drive current and generate a sensing signal in response to the sensing result; An operating voltage generation circuit, configured to generate a first operating voltage based on the sensing signal, at least after the drive current has been sensed; and A drive control circuit is configured to drive the bypass circuit such that, upon receiving a supply of the first operating voltage, the bypass circuit switches between the inflow state and the backoff state of the light-emitting element based on the enable signal.
6. The light-emitting driving device according to claim 1, wherein, The bypass circuit includes: A second bypass circuit, connected in parallel to the array of light-emitting elements comprising the light-emitting elements, is configured to either allow the driving current to flow into the array of light-emitting elements or to deflect the driving current away from the array of light-emitting elements so that the driving current does not flow into any of the light-emitting elements; and A first bypass circuit is connected in parallel with the light-emitting elements, and the first bypass circuit is configured such that the driving current switches between an inflow state and a retraction state in each of the light-emitting elements when it flows into the array of light-emitting elements. The bypass control circuit includes: A working voltage generation circuit is configured to generate a first working voltage in response to the enable signal; A first bypass drive control circuit is configured to drive the first bypass circuit upon receiving a supply of the first operating voltage, so as to switch the light-emitting element between the inflow state and the outflow state; and The second bypass drive control circuit is configured to operate based on a second operating voltage provided from an external source and to drive the second bypass circuit in response to the enable signal.
7. The light-emitting driving device according to any one of claims 1 to 6, wherein, The bypass circuit and the bypass control circuit are integrated together.
8. A light-emitting device, comprising: Multiple light-emitting elements; as well as The light-emitting driving device according to any one of claims 1 to 6.
9. The light-emitting device according to claim 8, wherein a plurality of the light-emitting driving devices are provided.
10. A light-emitting system, comprising: The light-emitting device according to claim 9; as well as A power supply device is configured to generate the drive current based on the enable signal and to provide the drive current to the light-emitting device.
11. The light-emitting system according to claim 10, wherein, The power supply device includes: A boost converter circuit is configured to generate a boost voltage obtained by boosting an externally supplied power supply voltage based on the enable signal; and The drive current generation circuit is configured to generate the drive current through current-to-voltage conversion of the boost voltage.