Circuit boards and electronic equipment

Abstract

This application provides a circuit board and an electronic device, relating to the field of circuit board technology. The circuit board includes: a signal layer with at least one pair of differential transmission lines; a first reference conductor layer and a second reference conductor layer disposed on opposite sides of the signal layer; wherein the first reference conductor layer has a first deconductor region, and the second reference conductor layer has a second deconductor region; the first and second deconductor regions are symmetrically arranged with respect to the normal direction of the plane containing the signal layer; the first deconductor region is located on both sides of the at least one pair of differential transmission lines on the plane projection of the signal layer and extends along the extension direction of the at least one pair of differential transmission lines; the first and second deconductor regions are used to suppress the common-mode component of the differential signal transmitted by the differential transmission lines.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and more particularly to a circuit board and electronic device. Background Technology

[0002] With the rapid development of high-speed serial bus technology, high-speed SerDes buses (such as MIPI DPHY, USB3, etc.) have been widely used in high-speed signal interconnection scenarios. These buses generally adopt differential signal transmission to improve signal anti-interference capability and transmission rate.

[0003] However, in practical engineering applications, due to limitations in PCB manufacturing precision, wiring constraints, and device characteristics, differential pairs are difficult to achieve perfectly equal-length matching. Signal amplitudes cannot remain completely equal, and there are deviations in the rise and fall times, resulting in a non-negligible common-mode component in the ideal differential signal. This common-mode component not only degrades signal integrity but also triggers strong EMI (electromagnetic interference), affecting system stability and electromagnetic compatibility performance. Summary of the Invention

[0004] The purpose of this application is to provide a circuit board and electronic device, mainly providing the following technical solutions:

[0005] The first aspect of this application provides a circuit board, the circuit board including: a signal layer, the signal layer being provided with at least one pair of differential transmission lines;

[0006] The first reference conductor layer and the second reference conductor layer are respectively disposed on both sides of the signal layer;

[0007] Wherein, a first deconducting region is provided on the first reference conductor layer, and a second deconducting region is provided on the second reference conductor layer;

[0008] The first deconductor region and the second deconductor region are symmetrically arranged with respect to the normal direction of the plane in which the signal layer is located;

[0009] The first deconductor region is located on both sides of the at least one pair of differential transmission lines on the plane projection of the signal layer and extends along the extension direction of the at least one pair of differential transmission lines. The first deconductor region and the second deconductor region are used to suppress the common-mode component of the differential signal transmitted by the differential transmission lines.

[0010] In some modified embodiments of the first aspect of this application, the deconductor region on each of the reference conductor layers includes a plurality of deconductor units arranged sequentially along the extension direction.

[0011] In some modified embodiments of the first aspect of this application, the plurality of deconductor units have at least partially different dimensions in the extension direction to increase the common-mode rejection bandwidth.

[0012] In some modified embodiments of the first aspect of this application, the conductor removal unit includes two first conductor removal segments arranged along the extension direction and parallel to each other, and a second conductor removal segment arranged perpendicular to the extension direction, wherein the second conductor removal segment connects the two first conductor removal segments.

[0013] In some modified embodiments of the first aspect of this application, the spacing w1 between the two first conductor segments satisfies the following relationship:

[0014] ;

[0015] in, The linewidth of the differential transmission line is... The line spacing between the pair of differential transmission lines is... This represents the absolute value of the layer deviation tolerance of the circuit board. This is the absolute value of the linewidth tolerance of the circuit board.

[0016] In some modified embodiments of the first aspect of this application, the width of the second deconductor segment in the extending direction... The following relationship must be satisfied:

[0017] ;

[0018] in, This is the minimum linewidth of the circuit board.

[0019] In some modified embodiments of the first aspect of this application, the signal layer is provided with at least two pairs of differential transmission lines arranged side by side;

[0020] A plurality of ground vias are evenly arranged between two adjacent pairs of differential transmission lines along the extension direction, and each ground via is opened along the normal direction of the plane where the signal layer is located.

[0021] Some modified embodiments of the first aspect of this application also include:

[0022] An isolation layer is disposed on the side of the first reference conductor layer and / or the second reference conductor layer opposite to the signal layer.

[0023] In some modified embodiments of the first aspect of this application, a first insulating dielectric layer is respectively filled between the signal layer and the adjacent first reference conductor layer or second reference conductor layer;

[0024] The isolation layer and the adjacent first reference conductor layer or second reference conductor layer are respectively filled with a second insulating dielectric layer;

[0025] The thickness of the second insulating dielectric layer is not less than twice the minimum thickness of the first insulating dielectric layer.

[0026] A second aspect of this application provides an electronic device, the electronic device comprising: a body;

[0027] Circuit board, comprising:

[0028] A signal layer, wherein at least one pair of differential transmission lines are provided;

[0029] The first reference conductor layer and the second reference conductor layer are respectively disposed on both sides of the signal layer;

[0030] Wherein, a first deconducting region is provided on the first reference conductor layer, and a second deconducting region is provided on the second reference conductor layer;

[0031] The first deconductor region and the second deconductor region are symmetrically arranged with respect to the normal direction of the plane in which the signal layer is located;

[0032] The first deconductor region is located on both sides of the at least one pair of differential transmission lines on the plane projection of the signal layer and extends along the extension direction of the at least one pair of differential transmission lines. The first deconductor region and the second deconductor region are used to suppress the common-mode component of the differential signal transmitted by the differential transmission lines. Attached Figure Description

[0033] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein:

[0034] Figure 1 A schematic diagram of the structure of a circuit board provided in an embodiment of this application is shown.

[0035] Figure 2 schematically shown Figure 1 A schematic diagram of a cross-sectional structure of section AA in the middle section;

[0036] Figure 3 The tolerance analysis curves of the common-mode suppression performance of this scheme are shown;

[0037] Figure 4 The common-mode rejection performance comparison curves of this solution and traditional common-mode inductors are shown;

[0038] Figure 5 The differential-mode insertion loss comparison curves of this scheme, conventional differential transmission lines, and traditional common-mode inductors are shown.

[0039] Figure 6 The differential-mode impedance test curve of this scheme is shown;

[0040] Figure 7 The differential-mode impedance test curve of a conventional 90Ω differential transmission line is shown.

[0041] Figure 8 A schematic diagram of another circuit board structure provided in an embodiment of this application is shown.

[0042] Figure 9 schematically shown Figure 8 A schematic diagram of a cross-sectional structure of section BB in the middle section;

[0043] Figure 10 A schematic diagram of another circuit board structure provided in an embodiment of this application is shown.

[0044] Explanation of icon numbers:

[0045] 1. Circuit board;

[0046] 2. Signal layer; 201. Differential transmission line;

[0047] 31. First reference conductor layer; 3101. First deconductor region; 32. Second reference conductor layer; 3201. Second deconductor region; 301. Deconductor unit; 3011. First deconductor segment; 3012. Second deconductor segment; 302. Retained copper strip;

[0048] 4. Grounding via;

[0049] 5. Isolation layer;

[0050] 6. First insulating dielectric layer;

[0051] 7. Second insulating dielectric layer;

[0052] X, direction of extension. Detailed Implementation

[0053] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0054] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.

[0055] In PCB interconnect designs for high-speed serial buses (such as MIPI DPHY, USB 3.0, etc.), differential signal transmission is the mainstream method. However, due to limitations in actual manufacturing and routing processes, it is difficult to achieve ideal perfect length, perfect amplitude, and perfect rise / fall time between differential pairs, inevitably resulting in a non-negligible common-mode component in the differential signal. This common-mode component can cause signal integrity degradation and lead to severe electromagnetic interference (EMI), especially significantly affecting radio frequency (RF) sensitive circuits.

[0056] To suppress common-mode noise, current technologies generally employ the method of connecting a common-mode inductor in series in the differential link. For example, in tablet products, high-speed interfaces such as DSI, CSI, and USB 3.0 typically require the addition of a common-mode inductor. However, as a discrete component, the common-mode inductor not only increases material and surface mount costs but also occupies valuable PCB layout area and introduces differential-mode insertion loss, affecting signal quality.

[0057] Therefore, how to effectively suppress the common-mode component of high-speed differential signals without increasing discrete components or significantly sacrificing the quality of differential signals has become a technical challenge in current PCB design.

[0058] Reference Appendix Figure 1 and attached Figure 2 This application provides a circuit board 1, which includes: a signal layer 2, on which at least one pair of differential transmission lines 201 are arranged; and a first reference conductor layer 31 and a second reference conductor layer 32 disposed on both sides of the signal layer 2; wherein, a first deconductor region 3101 is disposed on the first reference conductor layer 31, and a second deconductor region 3201 is disposed on the second reference conductor layer 32; the first deconductor region 3101 and the second deconductor region 3201 are symmetrically arranged with respect to the normal direction of the plane on which the signal layer 2 is located; the first deconductor region 3101 is located on both sides of the at least one pair of differential transmission lines 201 on the plane projection of the plane on which the signal layer 2 is located, and extends along the extension direction X of the at least one pair of differential transmission lines 201; the first deconductor region 3101 and the second deconductor region 3201 are used to suppress the common-mode component of the differential signal transmitted by the differential transmission lines 201.

[0059] The circuit board 1 provided in this embodiment can be applied, but is not limited to, to high-speed digital communication systems, especially electronic devices with high-speed serial buses (such as USB 3.0, MIPI DPHY, PCIe, HDMI, etc.), such as tablet computers, smartphones, laptops, servers, etc. In these application scenarios, the differential transmission line 201 will generate non-negligible common-mode noise due to physical asymmetry (such as length, line width, spacing, rise / fall time differences, etc.), which will lead to signal integrity deterioration and electromagnetic interference problems, especially in radio frequency sensitive frequency bands.

[0060] As attached Figure 2 As shown, the structure of circuit board 1 mainly includes three functional layers: signal layer 2, first reference conductor layer 31, and second reference conductor layer 32. Signal layer 2 is located in the middle and is used to lay at least one pair of differential transmission lines 201, which together form a differential pair. The first reference conductor layer 31 and the second reference conductor layer 32 are located above and below signal layer 2, respectively, serving as the reference return plane for the signal. There is no direct electrical connection between signal layer 2 and the first reference conductor layer 31 and the second reference conductor layer 32; signal return is achieved through electromagnetic field coupling.

[0061] The first reference conductor layer 31 has a first deconductor region 3101, and the second reference conductor layer 32 has a second deconductor region 3201. The first deconductor region 3101 and the second deconductor region 3201 are hollow areas without conductive copper layers. The projection of the first deconductor region 3101 on the signal layer 2 covers the areas on both sides of a pair of differential transmission lines 201, maintains a fixed gap with the differential transmission lines 201, and extends along the extension direction X of the differential transmission lines 201, with a copper strip 302 in the middle facing the differential transmission lines 201.

[0062] The first deconductor region 3101 and the second deconductor region 3201 are symmetrical about the normal of signal layer 2, meaning they have the same shape and size, and deviations within the PCB manufacturing tolerance range are allowed. (See attached...) Figure 3 As shown in the figure, this graph represents multiple curves illustrating the common-mode rejection performance (Scc21) of this solution as a function of frequency, based on Ansys HFSS simulations and taking into account typical PCB manufacturing factors such as linewidth tolerance, layer offset tolerance, layer thickness fluctuation tolerance, and dielectric constant fluctuation tolerance. The horizontal axis represents frequency (GHz), and the vertical axis represents the common-mode rejection performance Scc21 (dB). (See attached figure...) Figure 3The data shows that within the target frequency band of 5.1GHz-7.1GHz, the common-mode rejection ratio (CMRR) for all tolerance combinations is below -25dB, specifically: -29.01dB at 5.1GHz, -25.30dB at 5.8GHz, -26.53dB at 6.2GHz, -30.42dB at 6.8GHz, and -34.07dB at 7.1GHz, fully meeting the design specifications. Although the rejection depth slightly increases to -22dB to -23dB in some high-frequency bands (such as 8.8GHz and 9.2GHz), this band is not the primary focus for Wi-Fi or USB3. Overall, [the data is missing from the original text]. Figure 3 The results fully demonstrate that the proposed solution exhibits good process robustness and mass production consistency under typical PCB manufacturing tolerance fluctuations, and can stably achieve the expected common-mode suppression effect.

[0063] The formation process of the first conductor removal region 3101 and the second conductor removal region 3201 can be as follows: In the copper foil fabrication process of the first reference conductor layer 31 and the second reference conductor layer 32, the copper foil conductor in the corresponding area can be completely removed using the standard PCB subtractive process of photolithography, development, and etching, according to the preset cutout pattern and size parameters, so that the area forms a conductor-free cutout area, namely the first conductor removal region 3101 and the second conductor removal region 3201. This formation process does not require any additional process steps, laser or special processing, and is fully compatible with the mass production process of conventional circuit board 1.

[0064] The return path of differential-mode signals mainly relies on line-to-line coupling and is not sensitive to the integrity of the upper and lower reference conductor layers; while the electric field of common-mode signals is mainly concentrated in the space between each differential transmission line 201 and the adjacent reference conductor layer (the area that has not been hollowed out), and its return path depends on the reference plane. By setting symmetrical deconducting regions in the reference conductor layers, the low-impedance return path of common-mode signals is artificially disrupted, causing them to be reflected, scattered, or dissipated, thereby suppressing common-mode components.

[0065] Reference Appendix Figure 4 This demonstrates the difference in common-mode rejection performance between the proposed solution (proposal_SCC12, curve e) and the traditional common-mode inductor (choke_SCC12, curve f). The proposed solution involves setting symmetrical deconducting regions on the upper and lower reference conductor layers of the differential pair. (See attached image.) Figure 4 The horizontal axis represents frequency (GHz), and the vertical axis represents common-mode rejection performance (Scc21) (dB). A more negative value indicates stronger rejection capability. (See attached image.) Figure 4As shown, within the Wi-Fi operating frequency band of 5.1 GHz–7.1 GHz, the common-mode rejection of a traditional common-mode inductor is approximately -23 dB (e.g., -23.41 dB at 5.1 GHz), while the common-mode rejection of this solution reaches below -30 dB (e.g., -36.54 dB to -37.25 dB at 5.1 GHz). The comparison demonstrates that the common-mode rejection performance of this solution is significantly better than that of a traditional common-mode inductor, with a difference of 7 dB–13 dB, verifying that this solution can achieve superior electromagnetic interference suppression within the target frequency band.

[0066] Reference Appendix Figure 5 The figure shows a comparison of the differential-mode insertion loss (SDD21) of three devices: a conventional differential transmission line 201 (with a complete reference plane, curve g), this design (differential transmission line 201 with a length of 25mm, and symmetrically arranged deconducting regions on the upper and lower reference conductor layers, curve i), and a traditional common-mode inductor (curve h). The horizontal axis represents frequency (GHz), and the vertical axis represents insertion loss (dB). See attached figure. Figure 5 As shown in the figure, the trend of the three curves reveals that the differential-mode insertion loss of the conventional differential transmission line 201 gradually increases with increasing frequency. The differential-mode insertion loss curve of this scheme almost coincides with that of the conventional differential transmission line 201, while the differential-mode insertion loss of the traditional common-mode inductor is significantly greater. This comparison result indicates that, although a deconducting region is set in the reference conductor layer to suppress common-mode noise in the technical solution adopted in this application, almost no additional insertion loss is introduced into the differential-mode signal.

[0067] Reference Appendix Figure 6 and attached Figure 7 , attached Figure 6 The differential-mode impedance test results of this scheme (with symmetrical deconducting regions set in the upper and lower reference conductor layers of the differential pair) are shown, along with... Figure 7 The differential-mode impedance test results of a conventional 90Ω differential transmission line 201 without this scheme are shown, with appended... Figure 6 and attached Figure 7 The horizontal axis in the graph represents Time [ns], indicating the round-trip time of the TDR (Time Domain Reflectometer) test pulse as it travels from the test point along the differential transmission line 201 and back. This time axis indirectly reflects the distance along the transmission line; a longer time indicates a greater distance from the test starting point. (See attached graph.) Figure 6 and attached Figure 7 The vertical axis represents impedance values ​​in ohms (Ω), indicating the instantaneous differential-mode impedance at various locations along the differential transmission line 201. This impedance is used to evaluate the impedance continuity and consistency of the transmission line. (See attached diagram.) Figure 6 Curves a and b in the figure represent the differential-mode impedance test results of the same pair of differential transmission lines 201 under two different test channels (or two different probe connection methods) after adopting this scheme; Appendix Figure 6 Curves c and d in the figure represent the differential-mode impedance test results of a conventional 90Ω differential transmission line 201 without this scheme under two different test channels.

[0068] As attached Figure 6 As shown, curves a and b almost completely overlap throughout the measurement time range, with the impedance value remaining stable between 90.31Ω and 90.36Ω, and the fluctuation range being only 0.05Ω. This indicates that no significant impedance discontinuity was introduced in the conductor removal region; as shown in the attached figure. Figure 6 As shown, the impedance value fluctuates between 89.663Ω and 89.956Ω, with a fluctuation amplitude of approximately 0.293Ω, which is within the normal fluctuation range due to conventional PCB manufacturing processes. (Attached...) Figure 6 and attached Figure 7 As can be seen from the comparison, the technical solution adopted in this application causes the center value of the differential mode impedance to be offset by about 0.3Ω-0.5Ω relative to the conventional differential transmission line 201. This offset is on the same order of magnitude as the manufacturing fluctuation of the conventional differential transmission line 201 itself. Therefore, the impact of this solution on the differential mode impedance can be ignored and has no substantial impact on signal integrity.

[0069] Based on the above, this application proposes a circuit board 1 that, by setting symmetrical deconducting regions in the reference conductor layers above and below the differential transmission line 201, effectively suppresses common-mode signals without adding any discrete components or changing the existing PCB manufacturing process. Simultaneously, it introduces almost no additional differential-mode insertion loss and has a negligible impact on differential-mode impedance. Compared to existing series common-mode inductor solutions, this solution eliminates the need for additional surface-mount components, significantly reducing material and surface-mount processing costs. Furthermore, it does not occupy surface area on the circuit board 1, facilitating high-density and miniaturized designs. Moreover, by achieving common-mode suppression through the PCB structure itself, it offers stronger performance consistency, more stable impedance control, and superior common-mode suppression performance.

[0070] In some embodiments, to avoid a direct short circuit between signal layer 2 and reference conductor layer, and to ensure that the signal is transmitted only on differential transmission line 201, the reference conductor layer is used. Figure 2 and attached Figure 9 The first insulating dielectric layer 6 can be filled between the signal layer 2 and the first reference conductor layer 31 and the second reference conductor layer 32 respectively. The first insulating dielectric layer 6 isolates the signal layer 2 from the reference conductor layers on both sides, providing a stable and controllable interlayer spacing and dielectric environment for the differential transmission line 201, realizing precise control of the characteristic impedance of the differential transmission line 201, and ensuring stable and complete transmission of differential mode signals. The thickness h1 and h2 of the first insulating dielectric layer 6 on both sides of the signal layer 2 can be flexibly set according to the actual processing technology of the circuit board 1 to adapt to different impedance design requirements.

[0071] In some embodiments, the first deconducting region 3101 of the first reference conductor layer 31 and the second deconducting region 3201 of the second reference conductor layer 32 may be a single hollow structure, or a reference to an attached structure. Figure 8 The deconductor region can also be composed of multiple deconductor units 301 arranged sequentially and independently along the extension direction X of the differential transmission line 201. A preset interval is maintained between adjacent deconductor units 301 and they are separated from each other. Each deconductor unit 301 of the first reference conductor layer 31 and the corresponding deconductor unit 301 on the second reference conductor layer 32 are symmetrical about the normal of the signal layer 2.

[0072] By dividing the overall deconductor region into multiple independent deconductor units 301, a segmented symmetrical cutout structure is used along the extension direction X of the differential transmission line 201 to create multiple local discontinuities in the return path of the common-mode signal. This causes the common-mode signal to be reflected multiple times and gradually dissipated during transmission, thereby enhancing the overall common-mode rejection effect. The segmented structure effectively avoids the degradation of common-mode rejection performance caused by excessively long single segments. Furthermore, the number and spacing of the deconductor units 301 can be flexibly configured according to the PCB trace length, achieving a balance between common-mode rejection performance and layout area. Each deconductor unit 301 has virtually no impact on the return path of the differential-mode signal; therefore, the differential-mode transmission characteristics remain unchanged.

[0073] To ensure that the common-mode suppression performance of each deconductor unit 301 is not affected by mutual interference between edge fields, a preset interval can be maintained between adjacent deconductor units 301 based on simulation optimization of the edge field attenuation distance. Values This value ensures that the strong edge field generated at the end of the previous deconductor unit 301 has been sufficiently attenuated to a negligible level before reaching the next deconductor unit 301, thereby ensuring that each deconductor unit 301 independently and stably performs common-mode reflection and dissipation functions.

[0074] The common-mode suppression structure is essentially an electromagnetic bandgap structure based on a periodic or quasi-periodic impedance discontinuous distribution. Its suppression effect on common-mode signals of different frequencies is closely related to the length of the deconductor unit 301 in the extension direction X.

[0075] In some embodiments, the dimensions of each deconductor unit 301 in the extension direction X can be the same, or in order to expand the common-mode suppression bandwidth, the technical solution adopted in this application refers to the appendix. Figure 8The lengths of each deconductor unit 301 along the extension direction X can be designed to be at least partially different, which is equivalent to introducing multiple suppression units with different resonance characteristics, each corresponding to a different characteristic frequency. These deconductor units 301 with different sizes are arranged in series along the extension direction X of the differential transmission line 201, and each generates a strong reflection and dissipation effect on the common-mode frequency component that matches its size. This allows the overall structure to maintain effective common-mode rejection capability over a wider frequency range, thus achieving an extension of the common-mode rejection bandwidth.

[0076] By setting the dimensions of multiple deconductor units 301 to be at least partially different in the extension direction X of the differential transmission line 201, the effective suppression frequency range of common-mode noise can be significantly widened without significantly affecting the differential-mode signal. This design effectively improves the suppression capability of the circuit board 1 for common-mode noise in different frequency bands without adding additional components or changing the existing PCB manufacturing process. It exhibits stronger anti-interference capability in scenarios where multiple frequency bands operate simultaneously, while reducing the possibility of a decrease in suppression effect due to processing deviations or frequency changes, thus improving the overall operational stability.

[0077] In some embodiments, refer to the appendix Figure 2 The deconductor unit 301 can be composed of two first deconductor segments 3011 and one second deconductor segment 3012. The two first deconductor segments 3011 are arranged parallel to the extension direction X (i.e., the signal transmission direction) of the differential transmission line 201, and respectively correspond to both sides of a pair of differential transmission lines 201. The second deconductor segment 3012 is arranged perpendicular to the extension direction X, connecting the ends of the two first deconductor segments 3011 to form a continuous "U"-shaped cutout area. The area enclosed by the three segments is the retained copper strip 302, which is also the copper strip area directly opposite the differential transmission line 201. This design ensures that the retained copper strip 302 is surrounded by deconductor segments in three directions, thereby forming a well-defined, geometrically regular common-mode suppression unit on the reference conductor layer.

[0078] It should be noted that the appendix Figure 1 The dashed frame surrounding copper strip 302 is only used to indicate the boundary and coverage area of ​​the copper strip; this area is actually a continuous copper foil. Figure 1 Appendix Figure 8 and attached Figure 10 The dashed box within the conductor removal unit 301 is used to indicate that this area is a cutout area for removing copper foil.

[0079] When a common-mode signal propagates along the differential transmission line 201, its electric field is mainly distributed between the differential transmission line 201 and the reference conductor layer. Two parallel first deconductor segments 3011 interrupt the continuity of the reference layers on both sides of the differential transmission line 201, forcing the common-mode current to bypass it, thereby increasing the impedance of the common-mode loop. Meanwhile, the vertically positioned second deconductor segment 3012 further disrupts the return path of the common-mode signal at its end, causing the common-mode signal to encounter impedance discontinuities at the unit end and generate reflection. This "U"-shaped structure design retains a copper strip of a certain width directly above the differential transmission line 201. This copper strip forms an edge field at the boundary between the deconductor regions on both sides. By appropriately designing the gap width, the binding and dissipation effect on the common-mode signal can be enhanced. The electric field of the differential-mode signal is mainly concentrated between the pairs of differential transmission lines 201, and its return path almost does not pass through the hollowed-out area; therefore, differential-mode transmission is almost unaffected.

[0080] The "U"-shaped deconductor unit 301 design achieves efficient common-mode rejection within a limited PCB area. Two parallel first deconductor segments 3011 provide continuous common-mode rejection along the differential transmission line 201, while the second deconductor segment 3012 forms an additional impedance discontinuity at the unit end, further enhancing the reflection and attenuation of common-mode signals and improving rejection efficiency per unit length. Simultaneously, this structure retains the continuous copper strip directly above the differential transmission line 201, ensuring precise control of the differential-mode impedance, making differential-mode signal transmission virtually unaffected and guaranteeing signal integrity.

[0081] The length of the copper strip 302 retained in conductor unit 301 along the extension direction X of differential transmission line 201 can be set to the same or different values ​​according to actual design specifications. In a specific embodiment, with the common-mode rejection performance benchmarked against USB3 common-mode inductors as the design target, and combined with the dielectric constant (dk) and loss factor (df) parameters of the specific PCB board material, a set of differentiated length configurations were determined through simulation and optimization. Specifically: using FR4 board material (dk... 4.3, df (0.02) The lengths of the retained copper strips 302 in the three conductor removal units 301 are l1=5.5mm, l2=6.2mm, and l3=6.8mm, respectively. This length configuration introduces multiple suppression units with different resonance characteristics, enabling each unit to generate strong reflection and dissipation effects on common-mode components in different frequency bands. This achieves a common-mode rejection depth of over 30dB in the 5.1GHz~7.1GHz Wi-Fi band, while the differential-mode insertion loss is almost unaffected. It should be noted that the above length values ​​are only examples; in actual designs, adjustments can be made according to specific stack-up parameters, target suppression frequency bands, and performance requirements.

[0082] The reserved copper strip 302 should be positioned directly above / below the pair of differential transmission lines 201 (differential pair), ensuring that the return path for the differential-mode signal is completed through the low-impedance reserved copper strip 302, while the common-mode signal encounters high impedance due to the presence of deconductor regions on both sides. If the differential transmission line 201 is horizontally offset relative to the reserved copper strip 302 due to layer offset, or if the actual width of the differential transmission line 201 varies due to linewidth tolerances, the differential transmission line 201 may partially or even completely deviate to be directly above / below the deconductor region. If this occurs, the return path for the differential-mode signal is disrupted, introducing unacceptable differential-mode insertion loss and impedance abrupt changes.

[0083] In some embodiments, to ensure that the differential transmission line 201 always falls directly above / below the reserved copper strip 302 under PCB manufacturing tolerance fluctuations, the technical solution adopted in this application can achieve process tolerance compensation by designing the width of the reserved copper strip 302. Specifically, the width of the reserved copper strip 302 is limited, that is, the spacing w1 between the two first conductor segments 3011 satisfies the following relationship:

[0084]

[0085] in, The linewidth of the differential transmission line 201 is... The line spacing between the two differential transmission lines 201 within a differential pair. This represents the total width occupied by a single difference pair. This represents the absolute value of the lamination alignment deviation (lamination offset tolerance) during the manufacturing process of circuit board 1. This represents the absolute value of the linewidth machining tolerance for circuit board 1. This represents the process redundancy reserved on both sides of the differential transmission line 201. In other words, the width of the copper strip 302 is equal to the total width occupied by a pair of differential pairs plus one layer offset tolerance compensation and one line width tolerance compensation on each side.

[0086] By Designed for This is equivalent to the width of each component on the left and right sides of the difference pair being [missing information]. The process tolerance buffer ensures that the projection of the differential transmission line 201 onto the plane of the signal layer 2 in the normal direction is always completely covered by the copper strip 302, regardless of how the layer offset and line width fluctuate within the tolerance range. This ensures that the integrity of the differential signal is not degraded due to manufacturing fluctuations, while also ensuring that the common-mode rejection function functions properly. At the same time, this design ensures that different batches of circuit boards 1 have suppressed signal transmission characteristics, reducing quality control costs.

[0087] In the deconductor unit 301 structure, the second deconductor segment 3012 is a deconductor isolation gap that retains the end of the copper strip 302 and the adjacent reference plane, eliminating the direct conductor connection between them. In other words, the second deconductor segment 3012 is a critical discontinuity in the common-mode signal return path. When the common-mode signal propagates along the differential transmission line 201 to this location, due to the presence of the deconductor region, the common-mode current cannot pass directly and is forced to diffract or couple at the gap formed by the second deconductor segment 3012. According to electromagnetic field theory, the smaller the gap width, the stronger the edge field coupling between the conductors on both sides of the gap, and the greater the impedance change encountered by the common-mode signal at this location, resulting in stronger reflection and dissipation effects.

[0088] In some embodiments, in order to minimize the area occupied by the circuit board 1 while maximizing the common-mode rejection effect, the width of the second deconductor segment 3012 in the deconductor unit 301 can be limited. The specific values ​​for (i.e., the dimensions of the second conductor segment 3012 in the extension direction X) are as follows:

[0089]

[0090] in, The minimum line width of circuit board 1, namely the width of the second conductor segment 3012, is set to the minimum value allowed by the process of circuit board 1, which can be set between 0.075mm and 0.1mm, depending on the process capability of circuit board 1.

[0091] Setting the width of the second deconductor segment 3012 to the minimum linewidth of circuit board 1 utilizes the strongest edge field coupling achievable with current process capabilities, maximizing the suppression of common-mode signals at the ends of each deconductor unit 301. Simultaneously, the electric field of the differential-mode signal is primarily concentrated between the differential pairs, and its return path essentially does not pass through the area where the second deconductor segment 3012 is located. Therefore, this narrow-gap design has almost no impact on differential-mode transmission.

[0092] In the deconductor unit 301 structure, the retained copper strip 302 not only forms edge field coupling with the reference plane on the other side of the second deconductor segment 3012, but also has electromagnetic coupling with the outer reference plane through the first deconductor segment 3011. If the width of the first deconductor segment 3011 (the dimension in the lateral direction of the differential transmission line 201) is too small, the distance between the retained copper strip 302 and the outer reference plane will be too close, resulting in strong edge coupling between them. This coupling provides an additional, relatively low-impedance parasitic path for the common-mode signal, allowing the common-mode current to couple directly to the outer reference plane without passing through the intended high-impedance region (such as the second deconductor segment 3012), thereby weakening the common-mode rejection effect of the deconductor unit 301. Conversely, increasing the width of the first deconductor segment 3011 can effectively weaken this unfavorable coupling, forcing the common-mode signal to propagate along the designed path (across the second deconductor segment 3012), thereby maintaining the expected reflection and dissipation effects. However, increasing the width of the first conductor removal segment 3011 will directly increase the width of each conductor removal unit 301 in the lateral direction of the differential transmission line 201, which will significantly occupy the PCB wiring area after accumulation.

[0093] In some embodiments, the width of the first conductor segment 3011 can be... The value can be:

[0094] This defines the width of the first conductor segment 3011. The lower limit is intended to ensure that the coupling between the copper strip 302 and the outer reference plane is weak enough to prevent common-mode signals from bypassing the high-impedance region through parasitic paths, while keeping the area of ​​the circuit board 1 occupied by each deconductor unit 301 within an acceptable range, thereby balancing common-mode rejection performance and the feasibility of product layout.

[0095] In some embodiments, the signal layer 2 may have at least two pairs of differential transmission lines 201 arranged side by side. In the high-speed digital circuit board 1, multiple pairs of differential transmission lines 201 arranged side by side will couple with each other through electromagnetic fields, mainly manifested as near-end crosstalk and far-end crosstalk. When the coupling strength exceeds a certain threshold, it will cause the bit error rate at the receiving end to increase, or even the system to fail.

[0096] To suppress electromagnetic coupling interference between differential pairs and ensure that far-end crosstalk and near-end crosstalk meet high-speed signal design constraints, the technical solution adopted in this application refers to the appendix. Figure 10Several grounding vias 4 need to be provided between two adjacent pairs of differential transmission lines 201. These grounding vias 4 are arranged at approximately uniform intervals along the extension direction X of the differential transmission lines 201. Each grounding via 4 penetrates the circuit board 1 from the plane where the signal layer 2 is located along the normal direction and is electrically connected to each reference conductor layer (such as the first reference conductor layer 31, the second reference conductor layer 32, or other possible ground layers). The function of the grounding vias 4 is to build a low-impedance electrical isolation wall between adjacent differential pairs, reducing the intrusion of the electromagnetic field generated by a pair of differential transmission lines 201 into the adjacent differential transmission lines 201.

[0097] By placing several grounding vias 4 between adjacent pairs of differential transmission lines 201, the circuit board 1 can support high-density side-by-side routing of multiple pairs of differential transmission lines 201, significantly improving the routing density and system integration of the circuit board 1, and preventing signal integrity degradation due to excessive crosstalk between lines. At the same time, this design is fully compatible with standard circuit board 1 manufacturing processes; the vias require no additional steps or special materials, thus not increasing manufacturing costs.

[0098] In some embodiments, refer to the appendix Figure 9 The circuit board 1 provided in this embodiment further includes an isolation layer 5, which is an additional conductor layer disposed on the side of the first reference conductor layer 31 and / or the second reference conductor layer 32 away from the signal layer 2. The isolation layer 5 can be selectively added according to the actual product design needs. For example, in a high-density double-sided layout circuit board 1, multiple layers of traces are required on both sides of the signal layer 2. At this time, there may be other signal layers 2 or reference layers outside the layer where the conductor area is located, and these layers constitute the isolation layer 5.

[0099] In some embodiments, in order to suppress parasitic coupling between the isolation layer 5 and the deconductor region and ensure that the presence of the isolation layer 5 does not cause unacceptable degradation to the common-mode rejection performance, as shown in the appendix... Figure 9 As shown, a second insulating dielectric layer 7 with a thickness of h3 can be filled between the side of the first reference conductor layer 31 facing away from the signal layer 2 and the isolation layer 5, and a second insulating dielectric layer 7 with a thickness of h4 can be filled between the side of the second reference conductor layer 32 facing away from the signal layer 2 and the isolation layer 5; in the technical solution adopted in this application, h3 is specified. Also limited to h4 ,in The thicknesses of the first insulating dielectric layer 6 between the signal layer 2 and the first reference conductor layer 31 and the second reference conductor layer 32 are respectively. Such thickness constraints can prevent the isolation layer 5 from generating excessive parasitic coupling due to excessive distance, so that the common-mode current bypassed by the isolation layer 5 is limited to an acceptable range, and the common-mode rejection performance can still be better than that of traditional common-mode inductors.

[0100] It should be noted that the appendix Figure 4The results were measured with both upper and lower isolation layers 5 retained on circuit board 1. With this stack-up configuration, this solution still achieves a common-mode rejection depth of over 30dB in the 5.1GHz~7.1GHz Wi-Fi operating frequency band, significantly outperforming traditional common-mode inductors (only about 23dB). This demonstrates that even with the potential parasitic coupling bypass effect from the two isolation layers 5, as long as the dielectric thickness constraint set by this solution is met, the common-mode rejection performance of this solution is still superior to the common-mode inductor solution, verifying its reliability and performance advantages under worst-case stack-up conditions.

[0101] This application provides an electronic device comprising: a body; a circuit board 1, which includes: a signal layer 2, wherein at least one pair of differential transmission lines 201 are arranged on the signal layer 2; a first reference conductor layer 31 and a second reference conductor layer 32 respectively disposed on both sides of the signal layer 2; wherein, a first deconducting region 3101 is disposed on the first reference conductor layer 31, and a second deconducting region 3201 is disposed on the second reference conductor layer 32; the first deconducting region 3101 and the second deconducting region 3201 are symmetrically arranged with respect to the normal direction of the plane on which the signal layer 2 is located; the first deconducting region 3101 is located on both sides of the at least one pair of differential transmission lines 201 on the plane projection of the plane on which the signal layer 2 is located, and extends along the extension direction X of the at least one pair of differential transmission lines 201; the first deconducting region 3101 and the second deconducting region 3201 are used to suppress the common-mode component of the differential signal transmitted by the differential transmission lines 201.

[0102] The electronic device provided in this embodiment can be widely used in various digital systems that include high-speed serial buses and are sensitive to electromagnetic interference, including but not limited to: tablet computers, smartphones, laptops, servers, communication base stations, and vehicle systems. In these electronic devices, high-speed differential buses generate common-mode noise during transmission due to physical asymmetry, which interferes with the internal radio frequency modules, leading to decreased wireless communication sensitivity or failure to pass electromagnetic compatibility certification.

[0103] By integrating the circuit board 1 with common-mode suppression function into the electronic device body, the common-mode noise and electromagnetic interference problems caused by high-speed differential signals can be solved in a low-cost and highly integrated manner. This eliminates the need for discrete components such as common-mode inductors, saving material and surface-mount costs, and freeing up internal layout space, thus facilitating the thinner and lighter design and high-density integration of the device. Simultaneously, this structure effectively suppresses common-mode noise while barely affecting the normal transmission of differential-mode signals, ensuring high-speed signal integrity and link stability, improving wireless communication quality and system reliability, and making it easier for electronic devices to meet electromagnetic compatibility standards.

[0104] It should be noted that in the description of this specification, the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application; the terms "connection," "installation," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0105] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0106] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, include: A signal layer, wherein at least one pair of differential transmission lines are provided; The first reference conductor layer and the second reference conductor layer are respectively disposed on both sides of the signal layer; Wherein, a first deconducting region is provided on the first reference conductor layer, and a second deconducting region is provided on the second reference conductor layer; The first deconductor region and the second deconductor region are symmetrically arranged with respect to the normal direction of the plane in which the signal layer is located; The first deconductor region is located on both sides of the at least one pair of differential transmission lines on the plane projection of the signal layer and extends along the extension direction of the at least one pair of differential transmission lines. The first deconductor region and the second deconductor region are used to suppress the common-mode component of the differential signal transmitted by the differential transmission lines.

2. The circuit board according to claim 1, characterized in that, The deconductor region on each of the reference conductor layers includes a plurality of deconductor units arranged sequentially along the extension direction.

3. The circuit board according to claim 2, characterized in that, The plurality of deconductor units have at least partially different dimensions in the extension direction to increase the common-mode rejection bandwidth.

4. The circuit board according to claim 2, characterized in that, The conductor removal unit includes two first conductor removal segments arranged parallel to each other along the extension direction and a second conductor removal segment arranged perpendicular to the extension direction, wherein the second conductor removal segment connects the two first conductor removal segments.

5. The circuit board according to claim 4, characterized in that, The spacing w1 between the two first conductor segments satisfies the following relationship: ； in, The linewidth of the differential transmission line is... The line spacing between the pair of differential transmission lines is... This represents the absolute value of the layer deviation tolerance of the circuit board. This is the absolute value of the linewidth tolerance of the circuit board.

6. The circuit board according to claim 5, characterized in that, The width of the second conductor segment in the extension direction The following relationship must be satisfied: ； in, This is the minimum linewidth of the circuit board.

7. The circuit board according to claim 1, characterized in that, The signal layer is provided with at least two pairs of differential transmission lines arranged side by side; A plurality of ground vias are evenly arranged between two adjacent pairs of differential transmission lines along the extension direction, and each ground via is opened along the normal direction of the plane where the signal layer is located.

8. The circuit board according to claim 1, characterized in that, Also includes: An isolation layer is disposed on the side of the first reference conductor layer and / or the second reference conductor layer opposite to the signal layer.

9. The circuit board according to claim 8, characterized in that, The signal layer and the adjacent first reference conductor layer or second reference conductor layer are respectively filled with a first insulating dielectric layer; The isolation layer and the adjacent first reference conductor layer or second reference conductor layer are respectively filled with a second insulating dielectric layer; The thickness of the second insulating dielectric layer is not less than twice the minimum thickness of the first insulating dielectric layer.

10. An electronic device, characterized in that, include: ontology; Circuit board, comprising: A signal layer, wherein at least one pair of differential transmission lines are provided; The first reference conductor layer and the second reference conductor layer are respectively disposed on both sides of the signal layer; Wherein, a first deconducting region is provided on the first reference conductor layer, and a second deconducting region is provided on the second reference conductor layer; The first deconductor region and the second deconductor region are symmetrically arranged with respect to the normal direction of the plane in which the signal layer is located; The first deconductor region is located on both sides of the at least one pair of differential transmission lines on the plane projection of the signal layer and extends along the extension direction of the at least one pair of differential transmission lines. The first deconductor region and the second deconductor region are used to suppress the common-mode component of the differential signal transmitted by the differential transmission lines.

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