High-density interconnect printed circuit boards and their manufacturing methods

Abstract

This application provides a high-density interconnect printed circuit board and its manufacturing method, relating to the field of electronic manufacturing technology. The high-density interconnect printed circuit board includes: a core layer; a first lamination outer layer laminated to at least one side of the core layer, wherein the core layer and the first lamination outer layer have through-holes; and a second lamination outer layer laminated to the side of the first lamination outer layer opposite to the core layer. Both the first and second lamination outer layers have cross-layer vias, which are electrically connected to the through-holes. The core layer and the first lamination outer layer are laminated together in a first lamination process, and the second lamination outer layer is laminated onto the first lamination outer layer in a second lamination process. This high-density interconnect printed circuit board and its manufacturing method reduce lamination steps and simplify the process flow.

Description

Technical Field

[0001] This application relates to the field of electronic manufacturing technology, and in particular to a high-density interconnect printed circuit board and a method for manufacturing the same. Background Technology

[0002] In high-density, high-speed electronic devices, such as servers or high-end communication equipment, high-order, high-density interconnect printed circuit boards (PCBs) are key components that carry core circuit functions. These PCBs typically require multi-layer electrical interconnects, fine circuit structures, and numerous microvias.

[0003] In related technologies, taking the conventional 22-layer four-stage high-density interconnect structure as an example, the process of laminating and mating layers to process blind or buried vias is usually adopted. Specifically, each lamination process involves independent dielectric layer bonding and micro-via processing steps, resulting in a large number of lamination processes and a complex overall process flow. Summary of the Invention

[0004] This application provides a high-density interconnect printed circuit board and its manufacturing method, which reduces the lamination process and simplifies the process flow.

[0005] In a first aspect, embodiments of this application provide a high-density interconnect printed circuit board, comprising: a core layer having a first buried via; a first laminated outer layer laminated to at least one side of the core layer, wherein the core layer and the first laminated outer layer have through-holes; a second laminated outer layer laminated to the side of the first laminated outer layer opposite to the core layer; both the first laminated outer layer and the second laminated outer layer have cross-layer vias, wherein the cross-layer vias are electrically connected to the through-holes; the core layer and the first laminated outer layer are laminated together by a first lamination process, and the second laminated outer layer is laminated onto the first laminated outer layer by a second lamination process.

[0006] In one possible implementation, the high-density interconnect printed circuit board includes unit layers, wherein the core layer, the first lamination outer layer, and the second lamination outer layer are all formed by stacking multiple unit layers, and each unit layer includes a dielectric layer and a conductive layer; the through-hole and the cross-layer via penetrate the unit layer.

[0007] In one possible implementation, the first lamination outer layer has two layers respectively located on both sides of the core layer, and the second lamination outer layer has two layers corresponding to the first lamination outer layer; the plurality of unit layers constituting the first lamination outer layer are provided with first deep micropores, and the plurality of first deep micropores are interconnected and constitute cross-layer conductive holes on the first lamination outer layer.

[0008] The multiple unit layers constituting the second lamination outer layer are provided with second deep micropores, and the multiple second deep micropores are interconnected to form cross-layer conductive holes on the second lamination outer layer.

[0009] In one possible implementation, conductive materials are formed on the inner walls of the through hole and the interlayer through hole, suitable for electrical connection.

[0010] In one possible implementation, both the first and second laminated outer layers have at least two unit layers, and the depth of the cross-layer via spans at least two of the conductive layers.

[0011] In one possible implementation, the plurality of unit layers are stacked sequentially to form 22 layers, the printed circuit board including layers 1 to 22; the core layer including layers 5 to 18; the first lamination outer layer including layers 3 and 4, and layers 19 and 20; and the second lamination outer layer including layers 1 and 2, and layers 21 and 22.

[0012] In one possible implementation, the second deep micropore is formed in layers 1 and 2, and layers 21 and 22, and the first deep micropore is formed in layers 3 and 4, and layers 19 and 20, and the first deep micropore and the second deep micropore are in communication.

[0013] In one possible implementation, the third and fifth layers are high-speed signal layers, interconnected across layers through cross-layer vias in the first and second laminated outer layers;

[0014] Layers 18 and 20 are high-speed signal layers, interconnected across layers through cross-layer vias in the first and second laminated outer layers.

[0015] In one possible implementation, the through hole extends through layers 3 to 20.

[0016] In one possible implementation, the diameter of the first and second deep micropores is 6mil-10mil, and / or the depth of the first and second deep micropores is 7mil-11mil.

[0017] In one possible implementation, the dielectric layer comprises a prepreg, and / or the conductive layer comprises copper foil.

[0018] Secondly, embodiments of this application also provide a method for manufacturing a high-density interconnect printed circuit board, used to fabricate the aforementioned high-density interconnect printed circuit board, the manufacturing method comprising the following steps:

[0019] S1: Provides multiple stacked cell layers;

[0020] S2: Divide multiple unit layers into a stack including a core layer, a first pressing outer layer and a second pressing outer layer, and complete the overall stacking through two independent pressing processes;

[0021] S3: After each pressing, through holes and cross-layer through holes are machined at preset positions to achieve electrical interconnection between non-adjacent unit layers.

[0022] In one possible implementation, the overall lamination is completed through two independent pressing processes, including:

[0023] The first pressing involves stacking the two first pressing outer layers onto both sides of the core layer and pressing them together as a whole.

[0024] The second pressing involves stacking the two second pressing outer layers onto the outside of the two first pressing outer layers and pressing them together as a whole.

[0025] In one possible implementation, after the first pressing, a first deep micropore is processed on the first pressing outer layer, and through holes are processed on the first pressing outer layer and the core layer.

[0026] After the second pressing, a second deep micropore is processed on the second pressing outer layer, with the first deep micropore and the second deep micropore facing each other.

[0027] The high-density interconnect printed circuit board and its manufacturing method provided in this application embodiment are formed by setting a core layer and cooperating with a first and second lamination outer layer with cross-layer vias, and forming the circuit through a two-lamination manufacturing method. Compared with the traditional step-by-step lamination method that requires at least five laminations, this method reduces the lamination process, reduces the cumulative error of alignment misalignment between conductive layers, and is beneficial to improving the characteristic impedance consistency of high-speed signal transmission lines. In addition, reducing the number of laminations also reduces the number of electroplating and via filling processes associated with each lamination, reducing material consumption and processing time. Furthermore, the simplification of the overall process flow shortens the production cycle and reduces manufacturing costs. Moreover, the cross-layer vias formed by direct processing penetrate the first and second lamination outer layers, or cooperate with deep buried vias in the core layer, enabling direct electrical interconnection across multiple layers. The cross-layer vias replace the traditional dense step-by-step blind vias, freeing up more interlayer space and providing greater flexibility for wiring design. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0029] Figure 1 Schematic diagram of the structure of the high-density interconnect printed circuit board provided in this application Figure 1 ;

[0030] Figure 2 Schematic diagram of the structure of the high-density interconnect printed circuit board provided in this application Figure 2 ;

[0031] Figure 3 This is a schematic diagram illustrating a method for manufacturing a high-density interconnect printed circuit board provided in this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100 - Core Layer;

[0034] 200 - First lamination outer layer; 201 - First deep micropore;

[0035] 300 - Second lamination outer layer; 301 - Second deep micropore;

[0036] 400-Interlayer via;

[0037] 500 - Unit layer; 510 - Dielectric layer; 520 - Conductive layer;

[0038] 600 - Through hole.

[0039] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0041] In high-density, high-speed electronic devices, such as servers or high-end communication equipment, high-order, high-density interconnect printed circuit boards (PCBs) are key components that carry core circuit functions. These PCBs typically require multi-layer electrical interconnects, fine circuit structures, and numerous microvias.

[0042] In related technologies, taking the conventional 22-layer four-stage high-density interconnect structure as an example, the process of laminating and mating layers to process blind or buried vias is usually adopted. Specifically, each lamination process involves independent dielectric layer bonding and micro-via processing steps, resulting in a large number of lamination processes and a complex overall process flow.

[0043] As the total number of layers on a circuit board increases, conventional stacking and processing methods introduce other technical challenges. Firstly, fourth-order microvias, such as blind vias connecting the first and second layers, or the second and third layers, require multiple lamination processes and electroplating filling steps. Furthermore, controlling the alignment accuracy during via stacking is difficult, leading to a longer process time and significantly increased processing costs. Secondly, multiple lamination operations can cause cumulative thickness deviations in the dielectric layers, resulting in increased alignment misalignment between conductive layers. This deviation directly affects the characteristic impedance control accuracy of signal transmission lines on the printed circuit board, impacting the overall electrical performance of the board.

[0044] To address the aforementioned issues, this application provides a high-density interconnect printed circuit board and its manufacturing method. A core layer is configured, along with a first and second lamination outer layer having cross-layer vias. The board is formed through a two-stage lamination process. Compared to the traditional step-by-step lamination method requiring at least five laminations, this reduces the number of lamination steps, lowers the cumulative error of alignment misalignment between conductive layers, and improves the characteristic impedance consistency of high-speed signal transmission lines. Furthermore, reducing the number of laminations also reduces the number of electroplating and via-filling processes associated with each lamination, reducing material consumption and processing time. The simplified overall process shortens the production cycle and lowers manufacturing costs. Additionally, the cross-layer vias, formed directly through the first and second lamination outer layers or in conjunction with buried vias in the core layer, enable direct electrical interconnection across multiple layers. These cross-layer vias replace the traditional dense, step-by-step blind vias, freeing up more interlayer space and providing greater flexibility for wiring design.

[0045] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0046] The embodiments of this application will now be described with reference to the accompanying drawings.

[0047] Reference Figure 1 and Figure 2 As shown in the embodiment of this application, a high-density interconnect printed circuit board includes a core layer 100, a first laminated outer layer 200, and a second laminated outer layer 300. The first laminated outer layer 200 is laminated to at least one side of the core layer 100, and the core layer 100 and the first laminated outer layer 200 have through holes 600.

[0048] The second laminated outer layer 300 is laminated onto the side of the first laminated outer layer 200 opposite to the core layer 100. Both the first laminated outer layer 200 and the second laminated outer layer 300 are provided with interlayer through holes 400, and the interlayer through holes 400 and the through holes 600 are electrically connected.

[0049] The core layer 100 and the first outer layer 200 are pressed together through a first pressing process, and the second outer layer 300 is pressed onto the first outer layer 200 through a second pressing process.

[0050] Optionally, the core layer 100, the first laminated outer layer 200, and the second laminated outer layer 300 can all be formed by stacking multiple unit layers 500, and each unit layer 500 may include a dielectric layer 510 and a conductive layer 520. For example, the core layer 100 may include unit layers 500 from the fifth to the eighteenth layer.

[0051] Optionally, the through hole 600 can be formed after the first lamination process. The first buried hole 101 penetrates multiple internal conductive layers 520 of the core layer 100 and the first lamination outer layer 200, enabling electrical interconnection.

[0052] The core layer 100 and the first outer layer 200 are bonded together as a single unit through a first bonding process. Optionally, there are two first outer layers 200, which are bonded to both sides of the core layer 100. The second outer layer 300 is laminated onto the surface of the first outer layer 200 facing away from the core layer 100 through a second independent bonding process.

[0053] Optionally, the first laminated outer layer 200 includes a third and fourth layer above the core layer 100, and a nineteenth and twentieth layer below the core layer 100. The first lamination process involves pressing all the materials, including the core layers (e.g., the fifth to eighteenth layers) and the third, fourth, nineteenth, and twentieth layers of the first laminated outer layer 200, into a single unit, forming the first laminated plate from the third to the twentieth layers. After this lamination, through holes 600 can be formed, as well as cross-layer through holes 400 connecting the third and fifth layers of the first laminated outer layer 200, and cross-layer through holes 400 connecting the twentieth to the eighteenth layers of the first laminated outer layer 200.

[0054] The second laminated outer layer 300 is laminated onto the surface of the first laminated outer layer 200 facing away from the core layer 100 through a second independent lamination process. Optionally, the second laminated outer layer 300 may include an uppermost first layer, a second layer, and a lowermost twenty-first and twenty-second layer. The second lamination process involves laminating the materials of the first and second layers onto the plate that has completed the first lamination, and laminating the materials of the twenty-first and twenty-second layers onto the bottom of the plate, ultimately forming a complete twenty-two-layer laminated structure.

[0055] Both the first lamination outer layer 200 and the second lamination outer layer 300 are provided with interlayer through-holes 400. Optionally, the interlayer through-holes 400 include a first deep micro-hole 201 and a second deep micro-hole 301. The first lamination outer layer 200 has the first deep micro-hole 201, and the second lamination outer layer 300 has the second deep micro-hole 301. The interlayer through-holes 400 and through-holes 600 in the first lamination outer layer 200 are formed after the first lamination process, and the interlayer through-holes 400 in the second lamination outer layer 300 are formed after the second lamination process. The combination of interlayer through-holes and deep-buried holes can replace the traditional method of fabricating multiple blind holes layer by layer.

[0056] In one example, taking the formation of a 22-layer laminate as an example, when manufacturing the high-density interconnect printed circuit board of this embodiment, firstly, multiple unit layers 500 corresponding to the fifth to eighteenth layers constituting the core layer 100, and multiple unit layers 500 corresponding to the third, fourth, nineteenth, and twentieth layers constituting the first lamination outer layer 200 are prepared respectively. Then, a first lamination process is performed to symmetrically laminate the material of the core layer 100 and the material of the first lamination outer layer 200 together to form the first lamination board from the third to the twentieth layer.

[0057] After this pressing, a through hole 600 that penetrates the core layer 100 and the first pressing outer layer 200 can be formed in the first pressing plate, and a first deep micro-hole 201 connecting the third layer and the fifth layer, namely a cross-layer through hole 400 on the first pressing outer layer 200, can be formed.

[0058] Next, a second lamination process is performed, where the dielectric and conductive materials constituting the second lamination outer layer 300—that is, the materials corresponding to the first, second, twenty-first, and twenty-second layers—are laminated onto the outside of the first lamination plate, forming a twenty-two-layer stacked blank. After the second lamination, through-hole machining is performed to form cross-layer conductive holes 400 that extend from the surface of the first layer to the surface of the third layer. Finally, an electroplating process can be used to form a conductive material, such as a conductive film, on the inner walls of all the conductive holes, achieving interlayer electrical connection.

[0059] The high-density interconnect printed circuit board provided in this application embodiment has a core layer 100 and a first lamination outer layer 200 and a second lamination outer layer 300 having cross-layer vias 400. The core layer 100 and the first lamination outer layer 200 are laminated through a first lamination process, and then the second lamination outer layer 300 is laminated onto the first lamination outer layer 200 through a second lamination process.

[0060] Compared to the traditional step-by-step lamination method that requires at least five laminations, this method reduces the number of lamination steps, lowers the cumulative error of alignment misalignment between each conductive layer 520, and helps improve the characteristic impedance consistency of high-speed signal transmission lines. Furthermore, reducing the number of laminations also reduces the number of electroplating and via filling processes associated with each lamination, reducing material consumption and processing time. The simplified overall process shortens the production cycle and reduces manufacturing costs. In addition, the cross-layer vias 400 formed through direct machining penetrate the first lamination outer layer 200 and the second lamination outer layer 300, and cooperate with the through-holes 600 penetrating the core layer 100 and the first lamination outer layer 200, enabling direct electrical interconnection across multiple layers. The cross-layer vias 400 replace the traditional dense step-by-step blind vias, freeing up more interlayer space and providing greater flexibility for wiring design.

[0061] In some embodiments, combined with Figure 1 and Figure 2 The high-density interconnect printed circuit board includes a unit layer 500, a core layer 100, a first laminated outer layer 200, and a second laminated outer layer 300, all of which are stacked from multiple unit layers 500. Each unit layer 500 includes a dielectric layer 510 and a conductive layer 520. Through-holes 600 and interlayer vias 400 penetrate the unit layer 500.

[0062] By using the same unit layer 500 as the basic structural unit for stacking, the basic materials of the core layer 100, the first lamination outer layer 200 and the second lamination outer layer 300 can be unified, simplifying the types of materials used in the production of the circuit board.

[0063] After the first lamination process is completed, drilling is performed on the stacked unit layers 500 so that the through holes 600 and the cross-layer through holes 400 located in the first lamination outer layer 200 simultaneously penetrate the dielectric layer 510 and the conductive layer 520 of the corresponding unit layer 500. Subsequently, conductive layers are formed on the inner walls of the through holes 600 and the cross-layer through holes 400 through conductive treatments such as electroplating, thereby achieving electrical interconnection between the conductive layers 520 in different unit layers 500.

[0064] Similarly, after the second lamination process is completed, by processing the cross-layer through hole 400 on the second lamination outer layer 300, it penetrates the dielectric layer 510 of the unit layer 500 corresponding to the second lamination outer layer 300 and exposes the conductive layer 520. After conductive treatment, interlayer conduction can be achieved inside the second lamination outer layer 300 and between it and the first lamination outer layer 200.

[0065] In some embodiments, combined with Figure 1 and Figure 2 The first lamination outer layer 200 has two layers located on both sides of the core layer 100, and the second lamination outer layer 300 has two layers corresponding to the first lamination outer layer 200.

[0066] First deep micropores 201 are formed on the multiple unit layers 500 constituting the first lamination outer layer 200. The multiple first deep micropores 201 are interconnected and form cross-layer conductive holes 400 on the first lamination outer layer 200. Second deep micropores 301 are formed on the multiple unit layers 500 constituting the second lamination outer layer 300. The multiple second deep micropores 301 are interconnected and form cross-layer conductive holes 400 on the second lamination outer layer 300.

[0067] Specifically, after the core layer 100 and the first pressed outer layer 200 are pressed together in the first pressing process, first deep micropores 201 are formed on multiple unit layers 500 of the first pressed outer layer 200, and after electroplating and other conductive treatments, the multiple first deep micropores 201 are interconnected, thereby forming a cross-layer conductive hole 400 on the first pressed outer layer 200 to realize cross-layer conductivity between the first pressed outer layer 200 and the core layer 100.

[0068] Subsequently, after the second lamination outer layer 300 is laminated onto the first lamination outer layer 200 through a second lamination process, second deep micropores 301 are formed on multiple unit layers 500 of the second lamination outer layer 300. Similarly, after conductive treatment, the multiple second deep micropores 301 are interconnected to form cross-layer conductive holes 400 located on the second lamination outer layer 300, so as to realize cross-layer conductivity between the second lamination outer layer 300 and the lower first lamination outer layer 200 and the core layer 100.

[0069] The first deep micro-hole 201 and the second deep micro-hole 301 are processed after the corresponding pressing process, which avoids structural deformation or misalignment caused by pre-opening holes before pressing, and ensures the processing accuracy of the cross-layer through hole 400 and the reliability of electrical connection.

[0070] In some embodiments, combined with Figure 1 and Figure 2 Conductors are formed on the inner walls of the through hole 600 and the cross-layer through hole 400, which are suitable for electrical connection.

[0071] Specifically, after the first pressing process is completed, the through hole 600 and the cross-layer through hole 400 on the first pressing outer layer 200 are drilled; after the second pressing process is completed, the cross-layer through hole 400 on the second pressing outer layer 300 is drilled.

[0072] A continuous conductive metal film can be deposited on the inner wall surface of the through-hole 600 and the cross-layer via 400 using electroless copper plating and copper plating processes. This conductive metal film constitutes a conductor. The conductor is attached to the hole wall, electrically connecting the various conductive layers 520 through which the hole passes. This makes the through-hole 600 suitable for realizing the electrical interconnection between multiple conductive layers 520 between the core layer 100 and the first laminated outer layer 200, and makes the cross-layer via 400 suitable for realizing the electrical interconnection between conductive layers 520 at different positions in the first laminated outer layer 200 and the second laminated outer layer 300, as well as realizing the electrical connection between the cross-layer via 400 and the through-hole 600.

[0073] In some embodiments, combined with Figure 1 and Figure 2 The first lamination outer layer 200 and the second lamination outer layer 300 each have at least two unit layers 500, and the depth of the cross-layer through hole 400 spans at least two conductive layers 520.

[0074] Specifically, the cross-layer via 400 intersects at least three conductive layers 520 at different depths along its extension path. By forming a conductor on the inner wall of the cross-layer via 400, the conductor makes electrical contact with each conductive layer 520 through which the via passes, thereby achieving an electrical connection point that simultaneously forms an electrical interconnection with at least two conductive layers 520 at different depths.

[0075] This design replaces the traditional method of creating vias for every two adjacent conductive layers 520 and connecting them layer by layer. This reduces the number of holes required for drilling and the number of electroplating filling processes, lowering the complexity of the process and processing time, and shortening the production cycle. Furthermore, by reducing the number of traditionally independent and precisely aligned stacked blind vias, it reduces the risk of interlayer connection reliability issues caused by accumulated alignment deviations, expands the wiring space, and facilitates higher-density circuit designs.

[0076] In some embodiments, combined with Figure 1 and Figure 2 Multiple unit layers 500 are stacked sequentially to form 22 layers, and the printed circuit board includes layers 1 to 22 counting from the top layer. The core layer 100 includes layers 5 to 18. The first lamination outer layer 200 includes layers 3, 4, 19, and 20. The second lamination outer layer 300 includes layers 1, 2, 21, and 22.

[0077] During manufacturing, the unit layers 500 that constitute the core layer 100 and the 3rd, 4th, 19th and 20th layers of the first pressing outer layer 200 are first aligned and pressed together to form a pressing body containing layers 3 to 20.

[0078] Then, the unit layers 500 corresponding to the first, second, 21st and 22nd layers of the second outer lamination layer 300 are aligned and laminated to the outside of the lamination body after the first lamination, thus completing the stacking construction of the entire 22-layer circuit board.

[0079] After the first pressing, a through hole 600 and a cross-layer through hole 400 on the first pressing outer layer 200 can be formed. After the second pressing, a cross-layer through hole 400, i.e., a second deep micro-hole 301, can be formed from the surface of the first layer to the direction of the third layer, penetrating the first and second layers and terminating in the third layer. The cross-layer through hole 400 is electrically connected to the through hole 600.

[0080] By dividing the 22-layer structure into a core layer 100, a first lamination outer layer 200, and a second lamination outer layer 300, and defining the specific design of each layer, the total number of lamination steps required to manufacture the printed circuit board is reduced to two. Compared to the at least five independent lamination steps required to build a traditional 22-layer four-level high-density interconnect board, this design reduces the lamination process, which helps to reduce the processing cost and processing time caused by multiple lamination steps, and solves the problems of complex process flow and high cost in the background technology.

[0081] In some embodiments, combined with Figure 1 and Figure 2 The second deep micropore 301 is formed in the first and second layers, as well as the 21st and 22nd layers, and the first deep micropore 201 is formed in the third and fourth layers, as well as the 19th and 20th layers.

[0082] Between adjacent first laminated outer layer 200 and second laminated outer layer 300, the second deep micropore 301 of the second laminated outer layer 300 and the first deep micropore 201 of the first laminated outer layer 200 are connected. The second deep micropore 301 and the first deep micropore 201 are aligned in the stacking direction and electrically connected.

[0083] After the first pressing process is completed, the core layer 100 and the first pressed outer layer 200 are integrated. At this time, the first deep micro-holes 201 are processed in the 3rd and 4th layers and the 19th and 20th layers. This can effectively avoid problems such as hole wall deviation and resin drilling contamination that may be caused by directly drilling deep holes on the thin or unpressed independent unit layer 500, thus ensuring hole position accuracy and hole wall quality.

[0084] Subsequently, after the second bonding outer layer 300 is bonded onto the first bonding outer layer 200 in the second bonding process, the second deep microvia 301 is then processed in layers 1 and 2, as well as layers 21 and 22. Since the first deep microvia 201 has been pre-processed and conductive, the second deep microvia 301 can be directly connected to the already conductive first deep microvia 201 during processing.

[0085] This segmented processing method reduces the depth of a single drilling operation, reduces the risk of breakage of slender drill bits, and allows drilling stress to be released in stages at different pressing stages, reducing the risk of interlayer delamination.

[0086] Ultimately, the first deep microvia 201 and the second deep microvia 301 are aligned and electrically connected in the stacking direction, together forming a complete cross-layer via 400 spanning the first and second lamination layers 200 and 300. This achieves electrical interconnection across four conductive layers 520, improves the processing yield of deep microvias and the reliability of interlayer connections, and effectively frees up wiring space, which is beneficial for the refined circuit design of high-density interconnect printed circuit boards.

[0087] In some embodiments, combined with Figure 1 and Figure 2 Layers 3 and 5 are high-speed signal layers, interconnected across layers via through-holes 400 in the first and second laminated outer layers 200 and 300. Layers 18 and 20 are also high-speed signal layers, interconnected across layers via through-holes 400 in the first and second laminated outer layers 200 and 300.

[0088] Since the third layer is located in the first pressing outer layer 200 and the fifth layer is located in the core layer 100, in order to achieve cross-layer interconnection between the third layer and the fifth layer, after the first pressing process is completed, that is, after the core layer 100 and the first pressing outer layer 200 are pressed together, a cross-layer through hole 400, such as the first deep microhole 201, can be formed through the first pressing outer layer 200 and extend into the core layer 100.

[0089] After the second outer layer 300 is pressed, the corresponding cross-layer via 400, such as the second deep micro-hole 301, in the second outer layer 300 can be connected with the cross-layer via 400 in the first outer layer 200, thereby forming a complete conductive path across the first outer layer 200 and the second outer layer 300, realizing reliable transmission of high-speed signals between the 3rd and 5th layers.

[0090] Layer 3 and Layer 5 can serve as high-speed signal layers. They are connected to Layer 3 by the first to third deep microvias (i.e., the second deep microvia 301) created after the second lamination, and then connected to Layer 5 by the first to fifth deep microvias (i.e., the first deep microvia 201) created after the first lamination, thus forming a cross-layer interconnect.

[0091] Conversely, layers 18 and 20 can serve as high-speed signal layers. They are connected to layer 20 through deep microvias (layers 22-20, i.e., the second deep microvia 301) created after the second lamination, and then connected to layer 18 through deep microvias (layers 20-18, i.e., the first deep microvia 201) created after the first lamination, thus forming a cross-layer interconnect.

[0092] In addition, layers 3 to 20 in the core layer region can be connected by through holes 600 between layers 3 and 20, and together with the first deep micro-hole 201 and the second deep micro-hole 301, they form a cross-layer interconnection between layers 1 to 22.

[0093] This design enables high-speed signals to be directly interconnected across multiple layers between the core layer 100 and the first laminated outer layer 200, avoiding the cumbersome path of step-by-step interconnection via multiple short blind vias required in traditional processes. This direct interconnection across multiple layers shortens the signal transmission path in the vertical direction, effectively reducing signal transmission delay.

[0094] Furthermore, by reducing the number of intermediate conducting nodes, the impedance change nodes encountered by high-speed signals when traversing different dielectric layers 510 are reduced, improving the impedance continuity of the signal path and reducing signal reflection and attenuation caused by impedance mismatch, thereby enhancing the quality and integrity of high-speed signal transmission.

[0095] In some embodiments, combined with Figure 1 and Figure 2 The 600mm through hole penetrates from the 3rd to the 20th layer.

[0096] Specifically, in the first pressing process, the unit layer 500 constituting the core layer 100 is pressed together with the unit layer 500 constituting the first pressing outer layer 200 to form an integral pressed body containing layers 3 to 20. After the first pressing is completed, drilling is performed directly on the integral pressed body to form through holes 600 penetrating layers 3 to 20 in one step. Subsequently, through conductive treatments such as electroplating, a continuous conductor is formed on the inner wall of the through hole 600, realizing the electrical connection of the corresponding conductive layers 520 between layers 3 to 20.

[0097] This method of machining a 600mm through hole in one go after overall pressing avoids the cumbersome steps of drilling holes in the core layer and outer layer separately and then aligning and connecting them in the traditional process. It eliminates the risk of accumulated alignment deviation caused by segmented drilling and multiple pressing, simplifies the manufacturing process, and improves the hole position accuracy and electrical connection reliability of long-distance vertical interconnection.

[0098] Optionally, the aperture of the first deep microvia 201 and the second deep microvia 301 is 6-10 mil. For example, the aperture of the first deep microvia 201 and the second deep microvia 301 is 8 mil. The aperture range of 6 to 10 mil can save wiring space to the maximum extent while ensuring machinability and electroplating quality.

[0099] Optionally, the depth of the first deep microvia 201 and the second deep microvia 301 is 7-11 mil. For example, the depth of the first deep microvia 201 and the second deep microvia 301 is 9.2 mil. Controlling the depth within the range of 7 to 11 mil and the aperture range of 6 to 10 mil can maintain the aspect ratio at a reasonable level that is conducive to process control.

[0100] Optionally, the dielectric layer 510 includes a prepreg, and the conductive layer 520 includes a copper foil.

[0101] Prepregs have a certain degree of flexibility before lamination, which facilitates interlayer alignment and stacking operations. During lamination, their fluidity can fill the gaps between circuit patterns, ensuring tight interlayer bonding without air bubbles and providing a stable dielectric constant.

[0102] Copper foil possesses excellent electrical and thermal conductivity, enabling efficient transmission of current and signals while dissipating heat generated during circuit operation. The treated bonding surface between the copper foil and the prepreg provides superior peel strength, ensuring the reliability of the circuit board under thermal or mechanical stress.

[0103] In addition, combined Figure 3 This application also provides a method for manufacturing a high-density interconnect printed circuit board, which is used to manufacture the high-density interconnect printed circuit board described above. The manufacturing method includes the following steps.

[0104] S1: Provides multiple stacked cell layers 500.

[0105] Specifically, prepare multiple copper-clad laminates and prepregs. Determine the total number of conductive layers 520 and dielectric layers 510 required, and cut the materials to the appropriate dimensions. The unit layer 500 includes a conductive layer 520 for forming circuit patterns and a dielectric layer 510 as an insulating and adhesive material.

[0106] S2: Divide the multiple unit layers 500 into a stack including a core layer 100, a first pressing outer layer 200 and a second pressing outer layer 300, and complete the overall stacking through two independent pressing processes.

[0107] Specifically, the unit layer 500 constituting the core layer 100 and the unit layer 500 constituting the first pressing outer layer 200 are first aligned and stacked in the design order to perform the first pressing process, so that the materials of each layer are solidified into a whole to form the first pressing plate containing the core layer 100 and the first pressing outer layer 200.

[0108] Subsequently, the unit layer 500 constituting the second lamination outer layer 300 is aligned and laminated with the first lamination board to perform the second lamination process, thereby completing the overall lamination of the entire high-density interconnect printed circuit board.

[0109] S3: After each pressing, through holes 600 and cross-layer through holes 400 spanning multiple unit layers 500 are machined at preset positions to achieve electrical interconnection between non-adjacent unit layers 500.

[0110] Specifically, after the first pressing process is completed, through holes 600 are formed at the preset position of the first pressing plate by mechanical drilling or laser drilling, for example, through the 3rd to 20th layers of the core layer 100 and the first pressing outer layer 200, and cross-layer through holes 400, i.e., the first deep micropores 201, are located on the first pressing outer layer 200.

[0111] After the second pressing process is completed, a cross-layer through hole 400, namely the second deep micro hole 301, is formed on the outermost second pressing outer layer 300. The second deep micro hole 301 is aligned and connected with the first deep micro hole 201 on the first pressing outer layer 200.

[0112] After the through-hole 600 or the cross-layer through-hole 400 is processed, it needs to be metallized. A continuous conductor is formed on the inner wall of the hole through chemical copper plating and electroplating, so that non-adjacent unit layers 500 can be directly electrically interconnected through these conductors.

[0113] By dividing the multi-layer stacked structure into a core layer 100, a first pressing outer layer 200, and a second pressing outer layer 300, and using two independent pressing processes to achieve overall pressing, the pressing process is simplified. The reduction in pressing processes directly shortens the number of hot pressing cycles, improves the uniformity of the final plate thickness and the alignment accuracy between layers.

[0114] Furthermore, by performing drilling after each pressing, the machining accuracy and hole wall quality of the through holes 600 and the cross-layer through holes 400 are ensured. The use of through holes 600 directly penetrating multiple layers and the step-by-step machining of the cross-layer through holes 400 reduces the number of independent blind holes and the number of electroplating filling processes, thereby reducing drilling time and cost, shortening the production cycle, and optimizing the process flow.

[0115] In some embodiments, the overall lamination is completed by two independent lamination processes, including a first lamination and a second lamination. The first lamination stacks two first lamination outer layers 200 to both sides of the core layer 100 and laminations them together. The second lamination stacks two second lamination outer layers 300 to the outside of the two first lamination outer layers 200 and laminations them together.

[0116] In the first pressing, the two first pressing outer layers 200 are stacked on both sides of the core layer 100 and pressed together as a whole. After pressing, the core layer 100 and the two first pressing outer layers 200 are combined into a multi-layer plate that extends from the outer surface of the first pressing outer layer 200 on one side of the core layer 100 to the outer surface of the first pressing outer layer 200 on the other side.

[0117] In the second lamination, two second lamination outer layers 300 are stacked on the outside of the two first lamination outer layers 200 and then laminated together. During the second lamination process, the prepreg dielectric layer 510 in the second lamination outer layer 300 melts, flows and solidifies, firmly bonding the conductive layer 520 of the second lamination outer layer 300 to the underlying first lamination outer layer 200, thus completing the lamination of the entire high-density interconnect printed circuit board.

[0118] In this way, the first lamination solidifies the core layer 100 with the two outermost layers 200 in one step. The second lamination then symmetrically adds the outermost layer 300, reducing the total number of laminations required to construct a 22-layer or similar multi-layer structure to just two. Compared to the multiple laminations required in traditional processes where outer layers are added pair by pair from the inside out, this reduces the time spent on the lamination machine and energy consumption. Furthermore, the symmetrical operation of both laminations helps maintain stress balance in the thickness direction of the sheet, improving the dimensional stability and mechanical reliability of the product.

[0119] In some embodiments, after the first lamination, a first deep micropore 201 is processed on the first lamination outer layer 200, and a through hole 600 is processed on the first lamination outer layer 200 and the core layer 100. After the second lamination, a second deep micropore 301 is processed on the second lamination outer layer 300, with the first deep micropore 201 and the second deep micropore 301 facing each other.

[0120] After the first lamination process is completed, processing is performed on the first lamination plate, which includes the core layer 100 and the first lamination outer layer 200. Specifically, a first deep microhole 201 is machined at a predetermined position on the first lamination outer layer 200 using mechanical drilling or laser drilling. Its depth is designed to connect at least two non-adjacent conductive layers 520 in the first lamination outer layer 200.

[0121] At another predetermined location, a through hole 600 is machined. The through hole 600 starts from the outer surface of the first lamination plate, extends inward, and penetrates the entire first lamination outer layer 200 and the core layer 100, achieving electrical conductivity from the 3rd to the 20th layer. After machining, the first deep micro-hole 201 and the through hole 600 are subjected to hole metallization treatment to form a conductor on their inner walls.

[0122] After the second lamination process is completed, processing is performed on the final integrated circuit board. Specifically, a second deep microvia 301 is machined at a predetermined location on the second lamination outer layer 300 using mechanical drilling or laser drilling. Its depth is designed to connect at least two non-adjacent conductive layers 520 in the second lamination outer layer 300. When machining the second deep microvia 301, its position is opposite to the first deep microvia 201 on the first lamination outer layer 200 after the first lamination in the stacking direction. Subsequently, the second deep microvia 301 undergoes a hole metallization process to form a conductor on the inner wall of the hole.

[0123] The first deep microvia 201 and the second deep microvia 301 are electrically connected, forming a cross-layer through-hole 400 that extends from the outermost layer to the designated conductive layer 520 inside the first laminated outer layer 200. In addition, the through-hole 600 enables long-distance direct interconnection between the core layer 100 and the multiple conductive layers 520 inside the first laminated outer layer 200.

[0124] Finally, it should be noted that other embodiments of this application will readily conceive of by those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and alterations may be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A high-density interconnect printed circuit board, characterized in that, include: Core layer (100); The first press-fit outer layer (200) is pressed onto at least one side of the core layer (100), and the core layer (100) and the first press-fit outer layer (200) are provided with through holes (600). The second laminated outer layer (300) is laminated to the side of the first laminated outer layer (200) opposite to the core layer (100); Both the first laminated outer layer (200) and the second laminated outer layer (300) are provided with cross-layer through holes (400), and the cross-layer through holes (400) are electrically connected to the through holes (600); The core layer (100) and the first pressed outer layer (200) are pressed together by a first pressing process, and the second pressed outer layer (300) is pressed onto the first pressed outer layer (200) by a second pressing process.

2. The high-density interconnect printed circuit board according to claim 1, characterized in that, It includes a unit layer (500), wherein the core layer (100), the first lamination outer layer (200) and the second lamination outer layer (300) are all stacked from multiple unit layers (500), and each unit layer (500) includes a dielectric layer (510) and a conductive layer (520). The through hole (600) and the cross-layer through hole (400) penetrate the unit layer (500).

3. The high-density interconnect printed circuit board according to claim 2, characterized in that, The first laminated outer layer (200) has two layers respectively located on both sides of the core layer (100), and the second laminated outer layer (300) has two layers corresponding to the first laminated outer layer (200); First deep micropores (201) are formed on the multiple unit layers (500) constituting the first press-fit outer layer (200). The multiple first deep micropores (201) are interconnected and form cross-layer through holes (400) on the first press-fit outer layer (200). The multiple unit layers (500) constituting the second press-fit outer layer (300) are provided with second deep micropores (301), and the multiple second deep micropores (301) are interconnected and constitute cross-layer through holes (400) on the second press-fit outer layer (300).

4. The high-density interconnect printed circuit board according to claim 1, characterized in that, Conductors are formed on the inner walls of the through hole (600) and the cross-layer through hole (400) to facilitate electrical connection.

5. The high-density interconnect printed circuit board according to claim 2, characterized in that, The first laminated outer layer (200) and the second laminated outer layer (300) each have at least two unit layers (500), and the depth of the cross-layer via (400) spans at least two of the conductive layers (520).

6. The high-density interconnect printed circuit board according to claim 3, characterized in that, The multiple unit layers (500) are stacked sequentially to form 22 layers, and the printed circuit board includes layers 1 to 22; The core layer (100) includes layers 5 to 18; The first laminated outer layer (200) includes a third layer and a fourth layer, as well as a 19th layer and a 20th layer; The second laminated outer layer (300) includes a first layer and a second layer, as well as a 21st layer and a 22nd layer.

7. The high-density interconnect printed circuit board according to claim 6, characterized in that, The second deep micropore (301) is formed in the first and second layers, as well as the 21st and 22nd layers, and the first deep micropore (201) is formed in the third and fourth layers, as well as the 19th and 20th layers. The first deep micropore (201) and the second deep micropore (301) are connected.

8. The high-density interconnect printed circuit board according to claim 6, characterized in that, The third and fifth layers are high-speed signal layers, interconnected across layers through the cross-layer vias (400) of the first laminated outer layer (200) and the second laminated outer layer (300); Layer 18 and Layer 20 are high-speed signal layers, interconnected across layers through the cross-layer vias (400) of the first laminated outer layer (200) and the second laminated outer layer (300).

9. The high-density interconnect printed circuit board according to claim 6, characterized in that, The through hole (600) extends through layers 3 to 20.

10. The high-density interconnect printed circuit board according to claim 3, characterized in that, The diameter of the first deep micropore (201) and the second deep micropore (301) is 6mil-10mil, and / or the depth of the first deep micropore (201) and the second deep micropore (301) is 7mil-11mil.

11. The high-density interconnect printed circuit board according to claim 2, characterized in that, The dielectric layer (510) includes a prepreg, and / or the conductive layer (520) includes a copper foil.

12. A method for manufacturing a high-density interconnect printed circuit board, characterized in that, The manufacturing method for producing a high-density interconnect printed circuit board according to any one of claims 1-11 includes the following steps: S1: Provides multiple stacked cell layers (500). S2: Divide multiple unit layers (500) into a stack including a core layer (100), a first pressing outer layer (200) and a second pressing outer layer (300), and complete the overall stacking through two independent pressing processes; S3: After each pressing, through holes (600) and cross-layer through holes (400) spanning multiple unit layers (500) are machined at preset positions to achieve electrical interconnection between non-adjacent unit layers (500).

13. The manufacturing method according to claim 12, characterized in that, The overall lamination is completed through two independent pressing processes, including: In the first pressing, the two first pressing outer layers (200) are stacked on both sides of the core layer (100) and pressed together as a whole; In the second pressing, the two second pressing outer layers (300) are stacked on the outside of the two first pressing outer layers (200) and pressed together as a whole.

14. The manufacturing method according to claim 13, characterized in that, After the first pressing, a first deep micropore (201) is processed on the first pressing outer layer (200), and a through hole (600) is processed on the first pressing outer layer (200) and the core layer (100). After the second pressing, a second deep micropore (301) is processed on the second pressing outer layer (300), with the first deep micropore (201) and the second deep micropore (301) facing each other.

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