A manufacturing method for a layered functional decoupling PCB for a four-segment photovoltaic module junction box

Abstract

This invention proposes a manufacturing method for a layered functionally decoupled PCB for a four-segment photovoltaic module junction box, comprising the following steps: providing an aluminum-based copper-clad laminate as the power layer substrate; patterning the copper foil layer to form a power layer circuit pattern; electroplating the power layer circuit pattern to thicken it; performing copper embedding to form an embedded copper conductor structure; forming a signal layer circuit pattern on an FR-4 substrate; placing an insulating layer between the power layer substrate and the signal layer substrate; and sequentially laminating and curing the power layer substrate, the insulating layer, and the signal layer substrate. The power layer substrate carries power transmission signals, the signal layer substrate transmits control signals, and the insulating layer provides electrical isolation between the power layer substrate and the signal layer substrate, thereby achieving decoupling of power and signal functions. This solves the problem of mutual interference and decreased system reliability caused by the mixed transmission of power and control signals in existing technologies.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a layered functional decoupling PCB for a junction box of a four-segment photovoltaic module. Background Technology

[0002] As a key component of a photovoltaic system, the solar junction box's internal printed circuit board needs to simultaneously carry power transmission signals and control signals.

[0003] In traditional single-layer PCB design, power signals and control signals are transmitted together on the same circuit board. This causes the high current and high voltage of the power signals to generate severe electromagnetic interference and noise coupling to the control signals, resulting in control signal distortion and reduced system reliability.

[0004] Therefore, there is an urgent need for a PCB manufacturing method that can effectively isolate power functions from signal functions and improve system reliability. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a manufacturing method for a layered functional decoupling PCB for a four-segment photovoltaic module junction box, so as to solve the problem of mutual interference and reduced system reliability caused by the mixed transmission of power signals and control signals in the prior art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A method for manufacturing a layered functional decoupling PCB for a four-segment photovoltaic module junction box includes the following steps: preparing a power layer substrate by providing an aluminum-based copper-clad laminate as the power layer substrate, wherein the aluminum-based copper-clad laminate includes an aluminum base layer and a copper foil layer disposed on the aluminum base layer; patterning the copper foil layer to form a power layer circuit pattern; electroplating the power layer circuit pattern to thicken it; and ensuring that the current density of the conductive path in the power layer circuit pattern is not less than 5A / mm². 2 The process involves: copper embedding to form an embedded copper conductor structure; signal layer substrate fabrication, using an FR-4 substrate as the signal layer substrate, on which a signal layer circuit pattern is formed; interlayer insulating layer fabrication, where an insulating layer is placed between the power layer substrate and the signal layer substrate; and lamination and curing, where the power layer substrate, the insulating layer, and the signal layer substrate are sequentially laminated and cured to form a layered functionally decoupled PCB structure. The power layer substrate carries power transmission signals, the signal layer substrate transmits control signals, and the insulating layer provides electrical isolation between the power layer substrate and the signal layer substrate, thereby achieving decoupling of power and signal functions.

[0007] Preferably, the electroplating thickening treatment uses a copper sulfate electroplating process, and the copper foil thickness after electroplating is 90-140μm.

[0008] Preferably, the copper embedding process includes: forming a groove with a depth of 0.5-2 mm on the conductive path by mechanical milling or laser processing; filling the groove with copper paste or embedding a prefabricated copper block; and mechanically grinding or chemically mechanically polishing the filled groove until the difference between the surface height of the embedded copper conductor structure and the surface height of the power layer circuit pattern is less than 10 μm.

[0009] Preferably, the patterning process employs a photolithography etching process, comprising: coating the copper foil layer surface with a photoresist; exposing the photoresist through a photolithography mask; developing the exposed photoresist to form an etching mask; etching the copper foil layer not protected by the mask using an etching solution; and removing the etching mask to form the power layer circuit pattern.

[0010] Preferably, the insulating layer is a prepreg layer with a thickness of 0.1-0.3 mm and a breakdown voltage greater than or equal to 5000V.

[0011] Preferably, after the lamination and curing step, the method further includes: drilling holes in the PCB structure to form vias penetrating the power layer substrate and the signal layer substrate at locations where electrical connection is required between the power layer circuit pattern and the signal layer circuit pattern; metallizing the vias by depositing a copper layer on the inner wall of the vias, wherein the copper layer thickness on the inner wall of the vias is 20-40 μm, thereby achieving electrical connection between the power layer circuit pattern and the signal layer circuit pattern.

[0012] Preferably, after the lamination and curing step, the method further includes: coating the outer surface of the PCB structure with a solder resist layer; and performing surface treatment on the reserved pad area on the solder resist layer, wherein the surface treatment is performed by tin spraying, electroless nickel-gold plating, or coating with an organic solderability protectant.

[0013] Preferably, the current density during the copper sulfate electroplating process is 2-5 A / dm³. 2 The electroplating time is 30-60 minutes.

[0014] Preferably, the depth of the groove is 1-1.5 mm, and the mass percentage of copper in the copper paste is 85%-95%.

[0015] Preferably, the glass transition temperature of the prepreg layer is 130-180°C and the relative permittivity is 3.8-4.5.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: First, through the layered decoupling structure design of the power layer and the signal layer, the power transmission signal is transmitted in the power layer of the aluminum-based copper clad laminate, and the control signal is transmitted in the signal layer of the FR-4 substrate. The two layers are electrically isolated by an insulating layer. The electromagnetic interference generated by the large current and high voltage of the power signal is shielded by the insulating layer and cannot be coupled to the signal layer, thereby eliminating the interference of the power signal on the control signal, reducing the signal distortion by more than 80%, and significantly improving the system reliability. Second, the power layer circuit pattern is thickened to 90-140 μm by copper sulfate electroplating, and the current density is greater than 5 A / mm². 2 The conductive path is inlaid with copper to form an embedded copper conductor structure, which significantly increases the cross-sectional area of ​​the conductive path, reduces the resistance of the conductive path to 30%-50% of that of the traditional process, increases the current carrying capacity of the power layer to 2-3 times that of the traditional single-layer PCB, reduces power loss by more than 50%, and reduces the PCB operating temperature by 15-25℃, effectively extending the PCB lifespan. Third, the insulation layer uses a prepreg layer with a thickness of 0.1-0.3mm and a breakdown voltage greater than or equal to 5000V to ensure high-voltage insulation between the power layer and the signal layer, prevent electrical breakdown failure, and improve the safety and reliability of the PCB in high-voltage working environments. Fourth, by metallizing the vias, a 20-40μm thick copper layer is deposited on the inner wall of the via, achieving a low-impedance electrical connection between the power layer and the signal layer. The via contact resistance is less than 5mΩ, ensuring that the control signal is accurately transmitted from the signal layer to the power switching device in the power layer, thus improving the reliability of signal transmission and the accuracy of system control. Detailed Implementation

[0017] To enhance understanding of the present invention, the present invention will be further described in detail below with reference to embodiments. These embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection of the present invention. Example

[0018] This embodiment provides a basic manufacturing process for a layered functional decoupling PCB for a solar junction box, including the following steps: Step S1: Power layer substrate fabrication. An aluminum-based copper-clad laminate is provided as the power layer substrate. The aluminum-based copper-clad laminate includes an aluminum base layer and a copper foil layer disposed on the aluminum base layer. The thickness of the aluminum base layer is 1.5 mm, and the initial thickness of the copper foil layer is 35 μm.

[0019] The copper foil layer is patterned to form the power layer circuit pattern. Specifically, a photolithography etching process is used: a photoresist is coated on the surface of the copper foil layer with a coating thickness of 10-15 μm; the photoresist is exposed through a photolithographic mask for 8-12 seconds; the exposed photoresist is developed for 60-90 seconds to form an etching mask; the copper foil layer not protected by the mask is etched using a ferric chloride etching solution at an etching temperature of 40-50℃, and the etching time is determined according to the thickness of the copper foil; the etching mask is removed to form the power layer circuit pattern.

[0020] The power layer circuit pattern is thickened by electroplating. A copper sulfate electroplating process is used, with the plating solution consisting of copper sulfate, sulfuric acid, and additives. The current density during the electroplating process is 2-5 A / dm³. 2 The electroplating time is 30-60 minutes, and the copper foil thickness reaches 90μm after electroplating.

[0021] The current density of the conductive path in the power layer circuit diagram should not be less than 5 A / mm². 2 During the process, copper embedding is performed to form an embedded copper conductor structure. Specifically, a groove with a depth of 1 mm and a width of 2-3 mm is formed on the conductive path by laser processing; the groove is filled with copper paste, and the mass percentage of copper in the copper paste is 85%-95%; the filled groove is mechanically ground until the surface of the embedded copper conductor structure is flush with the surface of the power layer circuit pattern, and the surface height difference is less than 10 μm.

[0022] Step S2: Signal layer substrate fabrication. An FR-4 substrate with a thickness of 1.0 mm is provided as the signal layer substrate. The signal layer circuit pattern is formed on the FR-4 substrate using the same photolithography etching process as the power layer, with the copper foil thickness of the signal layer circuit pattern maintained at 35 μm.

[0023] Step S3: Fabrication of the interlayer insulating layer. An insulating layer is formed between the power layer substrate and the signal layer substrate. The insulating layer is a prepreg layer with a thickness of 0.2 mm, a breakdown voltage of 5500 V, a glass transition temperature of 130-180 °C, and a relative permittivity of 3.8-4.5.

[0024] Step S4: Lamination and Curing. The power layer substrate, insulating layer, and signal layer substrate are sequentially laminated and cured to form a layered, functionally decoupled PCB structure. Specifically, lamination and curing are performed in a laminator at a lamination temperature of 180°C, a lamination pressure of 2 MPa, and a lamination time of 60 minutes. During lamination, the resin in the prepreg layer melts and solidifies, firmly bonding the power layer substrate and signal layer substrate together to form an integrated PCB structure.

[0025] The power layer substrate is used to carry power transmission signals, the signal layer substrate is used to transmit control signals, and the insulating layer realizes electrical isolation between the power layer substrate and the signal layer substrate, thereby achieving decoupling of power function and signal function.

[0026] The PCB manufactured in this embodiment was tested and found that the power layer current carrying capacity is 2.5 times that of a traditional single-layer PCB, the temperature rise is only 25°C when passing a 10A current, and the power loss is reduced by 55%; the insulation layer passed the 5500V breakdown voltage test without breakdown; the signal layer control signal distortion was reduced by 85%, and the system reliability was significantly improved. Example

[0027] This embodiment optimizes the electroplating thickening process based on Embodiment 1.

[0028] In the electroplating thickening process of step S1, optimized copper sulfate electroplating process parameters are used: the current density of the electroplating process is 3A / dm³. 2 The electroplating time was 45 minutes, and the copper foil thickness reached 120μm after electroplating. The electroplating solution temperature was controlled at 25-30℃, and continuous stirring was used during the electroplating process to ensure uniform composition of the electroplating solution and improve the uniformity of copper layer deposition.

[0029] The remaining steps are the same as in Example 1.

[0030] The PCB manufactured in this embodiment was tested and found that the power layer current carrying capacity is three times that of a traditional single-layer PCB. When passing a 15A current, the temperature rise is only 20°C, and the power loss is reduced by 60%. The uniformity of the electroplated copper layer thickness reaches ±5%, and the electroplating quality is significantly improved. Example

[0031] This embodiment optimizes the copper inlay process based on Embodiment 1.

[0032] In the copper embedding process of step S1, optimized process parameters are adopted: a groove with a depth of 1.2 mm is formed on the conductive path by laser processing, the laser power is 50-80W, and the scanning speed is 100-200mm / s; copper paste is filled into the groove, and the mass percentage of copper in the copper paste is 90%; the filled groove is subjected to chemical mechanical polishing treatment, the polishing solution composition includes oxidant and abrasive, the polishing time is 10-20 minutes, and the surface of the embedded copper conductor structure is flush with the surface of the power layer circuit pattern, with a surface height difference of less than 5μm.

[0033] The remaining steps are the same as in Example 1.

[0034] The PCB manufactured in this embodiment was tested and found to have a conductivity path resistance in high current density areas reduced to 35% of that of traditional processes, a current carrying capacity increased to 2.8 times that of traditional processes, and a temperature rise of only 22°C when carrying a 20A current, demonstrating a significant improvement in the performance of the embedded copper conductor structure. Example

[0035] This embodiment adds a via metallization process to the first embodiment.

[0036] After lamination and curing in step S4, the following steps are also included: Step S5: Drill holes in the PCB structure. At locations where electrical connections are required between the power layer circuitry and the signal layer circuitry, use a CNC drilling machine to drill vias that penetrate both the power layer substrate and the signal layer substrate. The diameter of the vias is 0.3mm.

[0037] Step S6: Metallize the vias. Specifically, firstly, the vias are treated to remove resin residue generated during drilling; then, electroless copper plating is performed to deposit a copper layer on the inner wall of the via. The electroless copper plating solution consists of copper sulfate, formaldehyde, and a complexing agent. The electroless copper plating temperature is 60-70℃, the electroless copper plating time is 30-45 minutes, and the copper layer thickness on the inner wall of the via is 30μm; finally, electroplating is performed to thicken the copper layer on the inner wall of the via, ensuring the conductivity of the via.

[0038] Step S7: Apply a solder mask layer to the outer surface of the PCB structure. The thickness of the solder mask layer is 20-30μm, and the solder mask material is a photosensitive solder mask ink. It is applied to the PCB surface by screen printing or spraying. After exposure and development, openings are formed in the areas of the pads that need to be soldered.

[0039] Step S8: Perform surface treatment on the reserved pad area on the solder mask layer. The surface treatment adopts a chemical nickel-gold plating process, first depositing a 5-10μm thick nickel layer on the surface of the pad, and then depositing a 0.05-0.1μm thick gold layer to improve the solderability and oxidation resistance of the pad.

[0040] The PCB manufactured in this embodiment was tested and found that the via contact resistance was less than 3mΩ, the via current carrying capacity met the control signal requirements, the electrical connection between the power layer and the signal layer was reliable, the signal transmission reliability was improved, the signal distortion was reduced by 90%, and the system control accuracy was improved.

[0041] Comparative Example 1 This comparative example provides a conventional method for manufacturing a single-layer PCB, for comparison with the embodiments of this application.

[0042] A single-layer FR-4 substrate with a thickness of 1.6 mm is provided. Circuit patterns are formed on the FR-4 substrate using photolithography etching, maintaining a copper foil thickness of 35 μm. Power transmission signals and control signals are transmitted together on the same circuit layer without electroplating for thickening, copper embedding, or a separate power and signal layer structure.

[0043] The PCB manufactured in this comparative model was tested and found to have a temperature rise of 60°C when passing a 5A current, resulting in high power loss and severe heat generation; the control signal was severely affected by electromagnetic interference from the power signal, leading to high signal distortion and poor system reliability.

[0044] Comparing Embodiment 1 of this application with Comparative Example 1, it can be seen that this application adopts a layered decoupling structure design of power layer and signal layer, and achieves electrical isolation through insulation layer, eliminating the interference of power signal on control signal, and reducing signal distortion by more than 85%; through electroplating thickening and copper embedding treatment, the current carrying capacity of power layer is increased to 2.5 times that of traditional single-layer PCB, power loss is reduced by 55%, PCB operating temperature is reduced by 35°C, and system reliability is significantly improved.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for manufacturing a layered functional decoupling PCB for a four-segment photovoltaic module junction box, characterized in that, The process includes the fabrication of a power layer substrate: providing an aluminum-based copper-clad laminate as the power layer substrate, the aluminum-based copper-clad laminate comprising an aluminum base layer and a copper foil layer disposed on the aluminum base layer; patterning the copper foil layer to form a power layer circuit pattern; electroplating the power layer circuit pattern to thicken it; and ensuring that the current density of the conductive path in the power layer circuit pattern is not less than 5 A / mm². 2 During the process, copper embedding is performed to form an embedded copper conductor structure; signal layer substrate preparation: FR-4 substrate is provided as the signal layer substrate; signal layer circuit patterns are formed on the FR-4 substrate; Interlayer insulating layer fabrication: An insulating layer is disposed between the power layer substrate and the signal layer substrate; Lamination and curing: The power layer substrate, the insulating layer and the signal layer substrate are laminated and cured sequentially to form a layered functionally decoupled PCB structure; The power layer substrate is used to carry power transmission signals, the signal layer substrate is used to transmit control signals, and the insulating layer realizes electrical isolation between the power layer substrate and the signal layer substrate, thereby achieving decoupling of power function and signal function.

2. The manufacturing method of a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, The electroplating thickening treatment uses a copper sulfate electroplating process, and the thickness of the copper foil after electroplating is 90-140μm.

3. The manufacturing method of a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, The copper embedding process includes: forming a groove with a depth of 0.5-2 mm on the conductive path by mechanical milling or laser processing; filling the groove with copper paste or embedding a prefabricated copper block; and performing mechanical grinding or chemical mechanical polishing on the filled groove until the difference between the surface height of the embedded copper conductor structure and the surface height of the power layer circuit pattern is less than 10 μm.

4. The manufacturing method of a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, The patterning process employs a photolithography etching process, including: coating the copper foil layer surface with a photoresist; exposing the photoresist through a photolithography mask; developing the exposed photoresist to form an etching mask; etching the copper foil layer not protected by the mask using an etching solution; and removing the etching mask to form the power layer circuit pattern.

5. The manufacturing method of a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, The insulating layer is a prepreg layer with a thickness of 0.1-0.3 mm and a breakdown voltage greater than or equal to 5000V.

6. The manufacturing method of a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, After the lamination and curing step, the method further includes: drilling holes in the PCB structure to form vias penetrating the power layer substrate and the signal layer substrate at locations where electrical connection is required between the power layer circuit pattern and the signal layer circuit pattern; metallizing the vias by depositing a copper layer on the inner wall of the vias, wherein the copper layer thickness on the inner wall of the vias is 20-40 μm, thereby achieving electrical connection between the power layer circuit pattern and the signal layer circuit pattern.

7. The manufacturing method of a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, After the lamination and curing step, the method further includes: coating the outer surface of the PCB structure with a solder resist layer; and performing surface treatment on the reserved pad area on the solder resist layer, wherein the surface treatment is performed by tin spraying, electroless nickel-gold plating, or coating with an organic solderability protectant.

8. The manufacturing method of a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, The current density during the copper sulfate electroplating process is 2-5 A / dm³. 2 The electroplating time is 30-60 minutes.

9. A method for manufacturing a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, The groove has a depth of 1-1.5 mm, and the copper paste contains 85%-95% copper by mass.

10. A method for manufacturing a layered functional decoupling PCB for a four-segment photovoltaic module junction box according to claim 1, characterized in that, The glass transition temperature of the prepreg layer is 130-180℃, and the relative permittivity is 3.8-4.5.