Printed circuit board manufacturing methods and printed circuit boards

Abstract

This invention discloses a method for manufacturing a printed circuit board (PCB) and a PCB. The method includes the following steps: setting a first circuit pattern and ball grid array (BGA) pads in a first region; electroplating a gold layer on the exposed BGA pad area; removing the dry film mask and etching away the base copper and copper layer not covered by the gold layer to expose the substrate surface between the BGA pads; and fabricating a second circuit pattern. Thus, by first pre-fabricating the first circuit pattern and BGA pads in a first region of the substrate and electroplating a gold layer on the BGA pad surface, and then fabricating the second circuit pattern in a second region of the substrate, a complete circuit pattern is formed on the substrate. This not only improves the oxidation resistance and soldering reliability of the BGA pads and achieves electrical isolation between adjacent BGA pads, but also maintains good compatibility with traditional PCB manufacturing processes, thereby reducing the production cost of PCBs.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board technology, and in particular to a method for manufacturing a printed circuit board and a printed circuit board. Background Technology

[0002] With the rapid development of semiconductor technology, printed circuit boards are rapidly iterating towards higher density and smaller size. Therefore, the requirements for the packaging density and interconnect reliability of printed circuit boards are becoming more stringent.

[0003] In related technologies, electrical short circuits often occur between adjacent ball grid array pads, which seriously reduces the reliability of high-density interconnects on printed circuit boards and their production yield. To avoid this risk, additional processing steps are often required, which in turn makes the printed circuit board process more complex and the production cost higher. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a method for manufacturing a printed circuit board that is more reliable, effectively preventing electrical short circuits between adjacent ball grid array pads, and reducing the production cost of the printed circuit board.

[0005] The present invention further proposes a printed circuit board.

[0006] The method for manufacturing a printed circuit board according to the present invention includes the following steps: setting a first circuit pattern corresponding to ball grid array pads in a first region of a substrate and setting ball grid array pads according to the first circuit pattern; depositing a base copper layer on the surface of the substrate and electroplating a copper layer on the base copper layer; laminating a dry film on the surface of the copper layer in the first region, and after exposure and development, exposing the ball grid array pad area to be gold plated; using the dry film as a mask, electroplating a gold layer on the surface of the exposed ball grid array pad area; removing the dry film mask, etching away the base copper and the copper layer not covered by the gold layer, so that the substrate surface between the ball grid array pads is exposed; performing a dry film lamination, exposure and development process on a second region of the substrate to form a second circuit pattern in the second region; etching away the base copper and the copper layer not covered by the second circuit pattern in the second region, and removing the dry film in the second region to form the final circuit pattern.

[0007] Therefore, a first circuit pattern and ball grid array pads are prefabricated in the first region of the substrate, and a gold layer is electroplated on the surface of the ball grid array pads. Then, a second circuit pattern is fabricated in the second region of the substrate, thereby forming a complete circuit pattern on the substrate. This not only improves the oxidation resistance and soldering reliability of the ball grid array pads, but also achieves electrical isolation between adjacent ball grid array pads, avoiding short circuits between adjacent ball grid array pads. At the same time, it can maintain good compatibility with traditional printed circuit board manufacturing processes, thereby reducing the production cost of printed circuit boards and improving the production efficiency of printed circuit boards.

[0008] In some examples of the present invention, the step of depositing a base copper layer on the substrate surface and electroplating a copper layer on the base copper surface further includes cleaning, micro-etching and activation treatment of the substrate surface.

[0009] In some examples of the present invention, the step of laminating a dry film onto the copper layer surface in the first region, and exposing the ball grid array pad area to be gold-plated after exposure and development, further includes: laminating the dry film using a vacuum laminator.

[0010] In some examples of the present invention, the step of laminating a dry film onto the copper layer surface in the first region, and exposing the ball grid array pad area to be gold-plated after exposure and development, further includes: the size of the graphic window formed in the ball grid array pad area after exposure and development is larger than the preset final formed ball grid array pad size.

[0011] In some examples of the present invention, the step of electroplating a gold layer on the exposed surface of the ball grid array pad area using the dry film as a mask further includes: setting the time interval from after the dry film is pressed onto the copper layer surface in the first region to before the gold layer is electroplated on the exposed surface of the ball grid array pad area as t, then t satisfies the relationship: t≤8h.

[0012] In some examples of the present invention, after the step of removing the dry film mask, etching away the base copper and the copper layer not covered by the gold layer, and exposing the substrate surface between the ball grid array pads, the method further includes: inspecting whether the base copper and / or the copper layer remain on the surface of the first region of the substrate.

[0013] In some examples of the present invention, the step of performing dry film lamination, exposure and development processes on the second region of the substrate to form a second circuit pattern in the second region further includes: dividing the second region into two or more sub-regions, and sequentially exposing each sub-region; after completing the exposure of all sub-regions, developing them uniformly to form a complete second circuit pattern.

[0014] In some examples of the present invention, after the steps of removing the dry film in the second region, etching away the base copper and the copper layer in the second region that are not covered by the circuit pattern, and forming the final circuit pattern, the method further includes: performing solder resist printing on the non-soldering areas on the substrate surface; and performing electroless nickel-palladium-gold or electroless nickel-gold treatment on the surface of the non-ball grid array pads in the second region.

[0015] The printed circuit board according to the embodiments of the present invention is applicable to the above-described method for manufacturing printed circuit boards.

[0016] In some examples of the present invention, the printed circuit board includes: a substrate, the substrate including a first region and a second region; a circuit pattern formed on the substrate, the circuit pattern including a first circuit pattern and a second circuit pattern, the first circuit pattern being disposed in the first region and the second circuit pattern being disposed in the second region, and the first circuit pattern and the second circuit pattern being electrically connected; a plurality of ball grid array pads, the plurality of ball grid array pads being disposed in the first region and electrically connected to the first circuit pattern; and other pads outside the ball grid array pad region, the other pads outside the ball grid array pad region being disposed in the second region and electrically connected to the second circuit pattern.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart of a method for manufacturing a printed circuit board according to an embodiment of the present invention; Figure 2 This is a flowchart of a method for manufacturing a printed circuit board according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the first region of a printed circuit board according to an embodiment of the present invention; Figure 4 This is a cross-sectional view of the first region of the printed circuit board after the dry film has been applied according to an embodiment of the present invention; Figure 5 This is a cross-sectional view of the first region of a printed circuit board after exposure and development according to an embodiment of the present invention; Figure 6 This is a cross-sectional view of the first region of the printed circuit board after the dry film has been removed and the bottom copper has been etched, according to an embodiment of the present invention.

[0019] Figure label: 100. Printed circuit boards; 10. Substrate; 101. First region; 20. Ball grid array pads; 30. Copper layer; 40. Dry film. Detailed Implementation

[0020] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0021] The following is for reference. Figures 1-6 A method for manufacturing a printed circuit board 100 according to an embodiment of the present invention is described. The method for manufacturing the printed circuit board 100 can be applied to the manufacturing of the printed circuit board 100.

[0022] Combination Figures 1-6 As shown, the manufacturing method of the printed circuit board 100 according to the present invention mainly includes the following steps: setting a first circuit pattern corresponding to the ball grid array pads 20 in a first region 101 of the substrate 10 and setting the ball grid array pads 20 according to the first circuit pattern; depositing a base copper layer on the surface of the substrate 10 and electroplating a copper layer 30 on the surface of the base copper; pressing a dry film 40 onto the surface of the copper layer 30 in the first region 101, and after exposure and development, exposing the area of ​​the ball grid array pads 20 that needs to be gold plated; using the dry film 40 as a mask, electroplating a gold layer on the surface of the exposed area of ​​the ball grid array pads 20; removing the dry film 40 mask, etching away the base copper and copper layer 30 not covered by the gold layer, so that the surface of the substrate 10 between the ball grid array pads 20 is exposed; performing the pressing, exposure and development process of dry film 40 on a second region of the substrate 10 to form a second circuit pattern in the second region; etching away the base copper and copper layer 30 not covered by the second circuit pattern in the second region, and removing the dry film 40 in the second region to form the final circuit pattern.

[0023] First, the diameter, shape and spacing of the ball grid array pad 20, which serves as the starting or ending point of the first circuit pattern, must be compatible with the line width and wiring density of the first circuit pattern. In terms of pattern design, the path of the first circuit pattern determines the relative layout position of the ball grid array pad 20.

[0024] In some embodiments of the present invention, the ball grid array pad 20 and the first circuit pattern are formed synchronously in the same exposure, development and etching process, which can ensure the alignment accuracy between the ball grid array pad 20 and the first circuit pattern.

[0025] In other embodiments of the present invention, a first circuit pattern may be fabricated first, and then the ball grid array pads 20 may be fabricated by electroplating or ball-planting processes, using the first circuit pattern as a conductive substrate or the alignment marks generated during its fabrication as a reference.

[0026] Among them, such as Figure 3As shown, the ball grid array pads 20 can be exposed on the surface of the substrate 10 through etching and other processes, while the first circuit pattern is hidden in the inner layer of the substrate 10.

[0027] Furthermore, a base copper layer is formed on the surface of the substrate 10 by chemical deposition. Then, using this base copper as a seed layer, a flash-plated copper layer 30 is electroplated on its surface by controlling the electroplating parameters. This not only achieves the transformation of the substrate 10 surface from insulating to conductive, but also enables the ball grid array pads 20 on the surface of the substrate 10 to be interconnected through the base copper and the copper layer 30, facilitating the subsequent gold plating process. The thickness of the base copper is preferably in the range of 0.1 to 0.7 μm, and the total thickness of the base copper and the flash-plated copper layer 30 is preferably in the range of 3 to 5 μm.

[0028] Furthermore, a dry film 40 is laminated onto the surface of the copper layer 30 in the first region 101, and a high-precision exposure machine is used for alignment exposure. After development, the dry film 40 corresponding to the area of ​​the ball grid array pad 20 is selectively removed, so that the ball grid array pad 20 and the copper layer 30 corresponding to that area are exposed. The remaining copper layer 30 on the surface of the substrate 10 is still tightly covered by the dry film 40, thus preparing for the subsequent gold plating process.

[0029] Among them, the dry film 40 can be a special dry film 40 for anti-electroplating such as Changxing HQ6320 dry film 40. Its thickness needs to be determined according to the design requirements of the gold plating layer. It should generally be greater than or equal to the total thickness of the ball grid array pads 20 and the gold plating layer to ensure that the dry film 40 forms an effective lateral barrier around the ball grid array pads 20, preventing lateral climbing or bridging short circuits between adjacent pads caused by the gold plating layer exceeding the surface of the dry film 40, thereby ensuring the edge clarity and structural reliability of the gold plating layer.

[0030] Furthermore, using the dry film 40 retained after development as an electroplating mask, a gold layer is electroplated on the exposed surface of the ball grid array pads 20. Since the gold layer has high hardness and good wear resistance, this improves the oxidation resistance, friction resistance, and soldering reliability of the ball grid array pads 20, meeting the testing and reflow soldering requirements of the ball grid array chip. The preferred thickness range for the gold layer is 3–5 μm.

[0031] Furthermore, the dry film 40 mask is removed, and the gold layer is used as an etching barrier layer to etch the bottom copper and copper layer 30 that are not covered by the gold layer. This removes the excess bottom copper and copper layer 30 between the ball grid array pads 20, exposing the corresponding areas on the surface of the substrate 10. This achieves electrical isolation between adjacent ball grid array pads 20, prevents short circuits between adjacent ball grid array pads 20, ensures stable and reliable electrical performance of the printed circuit board 100 during packaging and use, and improves the yield of the printed circuit board 100.

[0032] Compared to the method of electroplating gold after the final circuit etching, electroplating gold first and then etching can prevent the risk of short circuit between adjacent pads due to a thicker gold layer. In addition, the manufacturing process is simple and the cost is lower.

[0033] Furthermore, a dry film 40 is laminated onto the surface of the copper layer 30 in the second region, and a high-precision exposure machine is used for alignment exposure. After development, the dry film 40 in the non-second circuit pattern area of ​​the second region is selectively removed, thereby retaining the dry film 40 covering the second circuit pattern as an anti-corrosion protective layer.

[0034] Further, the substrate 10 is etched to remove the bottom copper and copper layer 30 not covered by the dry film 40, that is, the bottom copper and copper layer 30 in the non-second circuit pattern area; after etching, the remaining dry film 40 is removed, leaving only the copper layer 30 corresponding to the second circuit pattern, thereby forming the final circuit pattern on the substrate 10.

[0035] The proposed solution employs a two-stage pattern transfer process. First, through a first pattern transfer, the area of ​​the ball grid array pads 20 on the substrate 10 is defined, and an electroplated gold layer is formed on the surface of the ball grid array pads 20. Second, through a second pattern transfer, the other circuit patterns of the printed circuit board 100, i.e., the second circuit patterns, are defined, thereby forming a complete circuit pattern on the substrate 10. This process is smooth and uninterrupted, and highly compatible with the traditional manufacturing process of the printed circuit board 100. It not only reduces the production cost of the printed circuit board 100 but also facilitates mass production.

[0036] Therefore, a first circuit pattern and ball grid array pads 20 are prefabricated in the first region 101 of the substrate 10, and a gold layer is electroplated on the surface of the ball grid array pads 20. Then, a second circuit pattern is fabricated in the second region of the substrate 10, thereby forming a complete circuit pattern on the substrate 10. This not only improves the oxidation resistance and soldering reliability of the ball grid array pads 20, but also achieves electrical isolation between adjacent ball grid array pads 20, avoiding short circuits between adjacent ball grid array pads 20. At the same time, it can maintain good compatibility with the traditional printed circuit board 100 manufacturing process, thereby reducing the production cost of the printed circuit board 100 and improving the production efficiency of the printed circuit board 100.

[0037] Combination Figure 1 and Figure 2As shown, before the steps of depositing a base copper layer on the surface of substrate 10 and electroplating a copper layer 30 on the base copper surface, the method further includes cleaning, micro-etching, and activation treatment of the surface of substrate 10. Specifically, before depositing the base copper on substrate 10, the surface of substrate 10 should be cleaned to remove oil, dust, and contaminants to ensure the cleanliness of the substrate 10 surface. Then, the surface of substrate 10 is micro-etched to roughen the surface of substrate 10 and increase the adhesion between the subsequent base copper deposition layer and substrate 10. Finally, the substrate 10 is activated to adsorb a layer of chemically plated palladium or colloidal palladium catalytic active centers on the surface of substrate 10, providing a uniform reaction starting point for the subsequent base copper deposition layer to ensure the uniformity and continuity of the base copper.

[0038] In some embodiments of the present invention, the substrate of the substrate 10 is an insulating substrate, and its surface is insulating.

[0039] Combination Figure 1 , Figure 2 , Figure 4 and Figure 5 As shown, the step of pressing a dry film 40 onto the surface of the copper layer 30 in the first region 101, and exposing the area of ​​the ball grid array pad 20 to be gold-plated after exposure and development, further includes: pressing the dry film 40 onto the surface of the copper layer 30 using a vacuum laminator. Specifically, the pre-treated substrate 10 is fed into the working chamber of the vacuum laminator, and the chamber is evacuated to completely remove the air between the surface of the substrate 10 and the dry film 40. Then, while maintaining the vacuum, the dry film 40 is pressed tightly onto the surface of the copper layer 30 at a preset temperature and pressure using heated rollers. This not only prevents air bubbles from forming between the dry film 40 and the copper layer 30, ensuring a tight fit between the dry film 40 and the copper layer 30, thus guaranteeing accurate development of the subsequent ball grid array pad 20 area, but also prevents the gold plating solution from eroding and seeping into non-preset areas during subsequent gold plating.

[0040] In some embodiments of the present invention, when using a vacuum laminator to laminate the dry film 40, the lamination pressure is preferably controlled within a range of 0.4–0.6 MPa, and the lamination temperature is preferably controlled within a range of 110–120°C. The pressure and temperature parameters of the vacuum laminator can be adaptively adjusted according to the specific model of the dry film 40 and the specific thickness of the copper layer 30 to ensure that the dry film 40 and the copper layer 30 are tightly bonded without the generation of air bubbles.

[0041] Combination Figure 1 , Figure 2 , Figure 4 and Figure 5As shown, the step of exposing the area of ​​the ball grid array pad 20 to be gold-plated after pressing a dry film 40 onto the surface of the copper layer 30 in the first region 101 and after exposure and development further includes: the size of the pattern window formed in the area of ​​the ball grid array pad 20 after exposure and development is larger than the preset final size of the ball grid array pad 20. Specifically, the pattern window corresponding to the ball grid array pad 20 is pre-compensated so that the size of the pattern window formed on the dry film 40 after exposure and development to expose the area of ​​the ball grid array pad 20 is designed to be larger than the preset target size of the final ball grid array pad 20. This allows a gap to be formed between the ball grid array pad 20 and the remaining dry film 40, that is, an additional edge area of ​​exposed copper layer 30 extends along the circumference of the ball grid array pad 20. Therefore, during the electroplating of the gold layer, the gold layer is deposited not only on the top surface of the target pad, but also covers the area of ​​the ball grid array pad 20. On the top surface of the ball grid array pad 20, a gold layer is also deposited on the circumferential edge region of the ball grid array pad 20, covering the circumferential sidewalls of the ball grid array pad 20. This can improve the overall oxidation resistance and soldering reliability of the ball grid array pad 20, meet the testing and reflow soldering requirements of the ball grid array chip. Moreover, the gold layer covering the surface of the ball grid array pad 20 can also act as a barrier during the etching process, effectively counteracting the erosion of the sidewalls of the ball grid array pad 20 by the side etching effect, ensuring the accuracy of the final dimensions of the ball grid array pad 20, and meeting the requirements of high-precision mounting.

[0042] In some embodiments of the present invention, the graphic window formed in the area of ​​the ball grid array pad 20 after exposure and development has a single-side size that is 15 to 25 μm larger than the single-side size of the preset final formed ball grid array pad 20, so as to ensure the reliability of the electroplated gold layer while preventing the electroplated gold layer from being too thick and causing bridging short circuits between adjacent ball grid array pads 20.

[0043] Combination Figure 1 and Figure 2 As shown, the step of electroplating a gold layer on the surface of the exposed ball grid array pad 20 region using the dry film 40 as a mask further includes: setting the time interval between pressing the dry film 40 onto the surface of the copper layer 30 in the first region 101 and before electroplating a gold layer on the surface of the exposed ball grid array pad 20 region as t, then t satisfies the relationship: t≤8h.

[0044] Specifically, if the interval between the two processes of laminating the dry film 40 onto the copper layer 30 surface in the first region 101 and electroplating the gold layer onto the ball grid array pad 20 surface exceeds 8 hours, not only may the dry film 40 shrink, become brittle, or have reduced adhesion, but an oxide layer may also form on the exposed copper layer 30 surface. Therefore, ensuring that the interval between these two processes does not exceed 8 hours can not only ensure that the copper surface is covered by the gold layer before a significant oxide layer forms, thereby improving the bonding force between the gold layer and the copper layer 30 and avoiding reliability risks caused by interface oxidation, but also ensure that the dry film 40 is still in its optimal performance state, effectively preventing the gold plating solution from eroding and seeping into non-preset areas and preventing short circuits between adjacent ball grid array pads 20.

[0045] In addition, it can reduce the possibility of environmental contamination on the surface of the ball grid array pad 20 and the exposed copper layer 30, providing a clean deposition substrate for the electroplated gold layer, thereby improving the density and purity of the gold layer, effectively reducing the quality risk caused by excessive waiting time, and improving the yield and consistency of the printed circuit board 100 during mass production.

[0046] In some embodiments of the present invention, the current density range used when electroplating a gold layer on the surface of the ball grid array pad 20 is preferably 2 to 5 ASD, and the temperature range is preferably 40 to 60°C.

[0047] Combination Figure 1 , Figure 2 and Figure 6 As shown, after the steps of removing the dry film 40 mask, etching away the bottom copper and copper layer 30 not covered by the gold layer to expose the surface of the substrate 10 between the ball grid array pads 20, the method further includes: inspecting whether there is any remaining bottom copper and / or copper layer 30 on the surface of the first region 101 of the substrate 10.

[0048] Specifically, a full inspection or random inspection is performed on the surface of the first region 101 of the substrate 10 to check for any residual copper and / or copper layer 30 residues that have not been completely etched away. If residual copper is found, the substrate 10 is marked as a defective product or enters the rework process. If the inspection is qualified, it enters the subsequent process. This not only effectively avoids the risk of micro-short circuits and leakage caused by conductive residues between the ball grid array pads 20, improves the insulation reliability between the ball grid array pads 20, and ensures the normal function of the printed circuit board 100, but also allows the inspection results to serve as a quantitative evaluation index of the effect of the previous etching process, providing data support for the optimization and adjustment of process parameters, forming a quality control closed loop. At the same time, timely rejection or rework of defective products can avoid ineffective cost investment in subsequent processes, thereby effectively improving the yield rate and overall cost-effectiveness of the mass production of the printed circuit board 100.

[0049] Combination Figure 1 and Figure 2 As shown, the process of laminating dry film 40, exposure and development is performed on the second region of substrate 10. The step of forming the second circuit pattern in the second region further includes: dividing the second region into two or more sub-regions, and exposing each sub-region in sequence. After the exposure of all sub-regions is completed, development is performed uniformly to form a complete second circuit pattern.

[0050] This configuration, by dividing the second region into two or more sub-regions, not only allows for individual optimization of exposure parameters based on the graphic characteristics of each sub-region, ensuring optimal exposure for each region and thus improving the overall resolution and dimensional accuracy of the second circuit pattern, but also breaks down what would otherwise be a single large-area exposure into multiple smaller-area exposures. This reduces the area required for a single exposure, improves compatibility with different exposure equipment specifications, and enhances production flexibility and yield. Furthermore, unified development ensures consistent development conditions across all sub-regions, preventing defects such as residual or overdeveloped development at sub-region boundaries, thereby guaranteeing the consistency and electrical reliability of the second circuit pattern.

[0051] Combination Figure 1 , Figure 2 and Figure 6 As shown, after the steps of removing the dry film 40 in the second region, etching away the base copper and copper layer 30 not covered by the circuit pattern in the second region, and forming the final circuit pattern, the process further includes: Solder resist printing is performed on the non-soldering areas of the substrate 10 surface; The surface of the non-ball grid array pad 20 in the second region is treated with chemical nickel-palladium-gold or chemical nickel-gold.

[0052] Specifically, after the final circuit pattern is formed, solder resist ink is printed on the non-soldering area on the surface of the substrate 10. After exposure, development and curing, a solder resist layer is formed. This allows for precise windowing at the pad positions in the second region, exposing the surface to be processed while protecting the remaining circuit areas in the second region.

[0053] Furthermore, the surface of the non-ball grid array pads 20 in the second region is treated with electroless nickel-palladium-gold or electroless nickel-gold to form a protective layer, which can improve the solderability and oxidation resistance of the pads in the second region.

[0054] The printed circuit board 100 according to the present invention is manufactured using the above-described method.

[0055] Combination Figures 3-6 As shown, the printed circuit board 100 according to the present invention may mainly include: a substrate 10, a circuit pattern formed on the substrate 10, a plurality of ball grid array pads 20 and other pads in the non-ball grid array pad 20 area.

[0056] The substrate 10 includes a first region 101 and a second region; the circuit pattern includes a first circuit pattern and a second circuit pattern, with the first circuit pattern disposed in the first region 101 and the second circuit pattern disposed in the second region, and the first circuit pattern and the second circuit pattern being electrically connected. This arrangement enables the interconnection of the first circuit pattern and the second circuit pattern, achieving signal transmission between them and ensuring the integrity and reliability of the overall circuitry of the printed circuit board.

[0057] Furthermore, multiple ball grid array pads 20 are disposed in the first region 101 and electrically connected to the first circuit pattern, thus forming a ball grid array package interface. This provides precise electrical connection points for the ball grid array chip or external chips through the ball grid array pads 20, meeting chip mounting or interconnection requirements. The top surface and sidewalls of the ball grid array pads 20 are covered with a gold layer, and there is no residual bottom copper or copper layer 30 on the surface of the substrate 10 surrounding the ball grid array pads 20. Adjacent ball grid array pads 20 are electrically isolated from each other.

[0058] Furthermore, other pads in the non-ball grid array pad 20 area are located in the second area and electrically connected to the second circuit pattern for mounting electronic components or as external connection interfaces.

[0059] In this way, by dividing the high-density ball grid array pads 20 and ordinary pads into different areas through partitioned layout, the layout architecture and space utilization of the printed circuit board 100 can be optimized. Moreover, forming a gold layer mainly on the ball grid array pads 20 can not only improve the oxidation resistance and soldering reliability of the ball grid array pads 20 and ensure the stability and reliability of the printed circuit board 100 structure, but also avoid the ineffective deposition of gold layer material on non-soldering areas such as circuit traces, thereby reducing the production cost of the printed circuit board 100.

[0060] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0061] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0062] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a printed circuit board, characterized in that, Includes the following steps: A first circuit pattern corresponding to the ball grid array pad (20) is provided in a first region (101) of the substrate (10), and the ball grid array pad (20) is provided according to the first circuit pattern. A base copper layer is deposited on the surface of the substrate (10) and a copper layer (30) is electroplated on the surface of the base copper. A dry film (40) is laminated onto the surface of the copper layer (30) in the first region (101). After exposure and development, the area of ​​the ball grid array pad (20) that needs to be gold-plated is exposed. Using the dry film (40) as a mask, a gold layer is electroplated on the surface of the exposed ball grid array pad (20) area; Remove the dry film (40) mask, etch away the bottom copper and the copper layer (30) not covered by the gold layer, and expose the surface of the substrate (10) between the ball grid array pads (20); A dry film (40), exposure and development process are performed on the second region of the substrate (10) to form a second circuit pattern in the second region; The bottom copper and the copper layer (30) not covered by the second circuit pattern in the second region are etched away, and the dry film (40) in the second region is removed to form the final circuit pattern.

2. The method for manufacturing a printed circuit board according to claim 1, characterized in that, Before the step of depositing a base copper layer on the surface of the substrate (10) and electroplating a copper layer (30) on the base copper surface, the method further includes cleaning, micro-etching and activation treatment of the surface of the substrate (10).

3. The method for manufacturing a printed circuit board according to claim 1, characterized in that, The step of laminating a dry film (40) onto the surface of the copper layer (30) in the first region (101), and exposing the area of ​​the ball grid array pad (20) to be gold-plated after exposure and development, further includes: laminating the dry film (40) using a vacuum laminator.

4. The method for manufacturing a printed circuit board according to claim 1, characterized in that, The step of pressing a dry film (40) onto the surface of the copper layer (30) in the first region (101), and exposing the area of ​​the ball grid array pad (20) to be gold-plated after exposure and development, further includes: the size of the graphic window formed in the area of ​​the ball grid array pad (20) after exposure and development is larger than the preset size of the final formed ball grid array pad (20).

5. The method for manufacturing a printed circuit board according to claim 1, characterized in that, The step of electroplating a gold layer on the exposed surface of the ball grid array pad (20) area using the dry film (40) as a mask further includes: setting the time interval from after the dry film (40) is pressed onto the surface of the copper layer (30) in the first region (101) to before electroplating a gold layer on the exposed surface of the ball grid array pad (20) area as t, then t satisfies the relationship: t≤8h.

6. The method for manufacturing a printed circuit board according to claim 1, characterized in that, The step of removing the dry film (40) mask, etching away the base copper and the copper layer (30) not covered by the gold layer, and exposing the surface of the substrate (10) between the ball grid array pads (20) further includes: inspecting whether the base copper and / or the copper layer (30) remain on the surface of the first region (101) of the substrate (10).

7. The method for manufacturing a printed circuit board according to claim 1, characterized in that, The step of performing the lamination of dry film (40), exposure and development processes on the second region of the substrate (10) to form a second circuit pattern in the second region further includes: dividing the second region into two or more sub-regions, and sequentially exposing each sub-region. After the exposure of all sub-regions is completed, development is performed uniformly to form a complete second circuit pattern.

8. The method for manufacturing a printed circuit board according to claim 1, characterized in that, The steps of removing the dry film (40) in the second region, etching away the base copper and copper layer (30) not covered by the circuit pattern in the second region, and forming the final circuit pattern further include: Solder resist printing is performed on the non-soldering areas of the substrate (10); The surface of the non-ball grid array pads (20) in the second region is treated with chemical nickel-palladium-gold or chemical nickel-gold.

9. A printed circuit board, characterized in that, The method of manufacturing a printed circuit board applicable to any one of claims 1-8.

10. The printed circuit board according to claim 9, characterized in that, include: A substrate (10) comprising a first region (101) and a second region; A circuit pattern formed on the substrate (10), the circuit pattern including a first circuit pattern and a second circuit pattern, the first circuit pattern being disposed in the first region (101), the second circuit pattern being disposed in the second region, and the first circuit pattern and the second circuit pattern being electrically connected. Multiple ball grid array pads (20) are disposed in a first region (101) and electrically connected to the first circuit pattern; other pads in the non-ball grid array pad (20) region are disposed in a second region and electrically connected to the second circuit pattern.

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