A method for fabricating a high-precision PCB pad structure

Abstract

This invention discloses a method for fabricating a high-precision PCB pad structure, relating to the field of pad fabrication technology. The method includes a circuit layer pad with a graphic size larger than the design size of the target finished pad; a solder mask layer covers the circuit layer, and a solder mask window is formed at the corresponding position of the circuit layer pad. The size of the solder mask window is equal to the design size of the target finished pad, and the solder mask window is completely located within the circuit layer pad area. The portion of the circuit layer pad exposed by the solder mask window forms the final finished pad. This invention intentionally makes the graphic size of the circuit layer pad larger than the design size of the target finished pad during the circuit layer design stage, so that the size of the final finished pad is determined by the size of the solder mask window rather than by the size of the etched circuit pad. The dispersion of size data distribution is significantly reduced, and etching process fluctuations are isolated from the size determination chain of the final finished pad by the solder mask layer, achieving high-precision control of the pad size.

Description

Technical Field

[0001] This invention relates to the field of pad fabrication technology, and in particular to a method for fabricating a high-precision PCB pad structure. Background Technology

[0002] The pads on a printed circuit board (PCB) are the key structures for the electrical connection and mechanical fixation of electronic components and circuits. As electronic components develop towards miniaturization, high density, and precision, increasingly stringent requirements are being placed on the dimensional accuracy and consistency of PCB pads. Even slight deviations in pad dimensions can lead to serious quality problems such as component misalignment, directly affecting product yield and long-term reliability.

[0003] Currently, PCB pad structures are typically fabricated using the following method: A pad pattern with a size essentially identical to the target finished pad is created on the circuit layer; then, solder mask windows corresponding to the pad pattern are opened on the solder mask layer to expose the pad for soldering. In this process, photoresist is first coated onto a copper-clad substrate. After exposure and development, a pad pattern is formed on the photoresist layer. Then, chemical etching is used to remove the copper layer not protected by the photoresist, ultimately obtaining the circuit pad.

[0004] However, etching is essentially a chemical dissolution process, which is affected by various factors such as etching solution concentration, temperature, spray pressure, substrate wiring density, and local load effects. The etching rate and etching factor inevitably fluctuate. This fluctuation leads to a deviation between the actual formed pad size and the designed size, and the deviation is randomly distributed across different locations and batches within the board. This inconsistency in pad size caused by etching fluctuations affects the integrity of the pad dimensions. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a high-precision PCB pad structure to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for manufacturing a high-precision PCB pad structure, comprising:

[0007] The pattern size of the circuit layer pads is larger than the design size of the target finished pads;

[0008] A solder mask layer is applied over the circuit layer, and a solder mask window is provided at the position corresponding to the pad of the circuit layer. The size of the solder mask window is equal to the design size of the target finished pad, and the solder mask window is completely located within the area of ​​the circuit layer pad. The portion of the circuit layer pad exposed by the solder mask window forms the final finished pad.

[0009] Preferably, the outline of the circuit layer pad is the same as the outline of the target finished pad, and the dimensions of each side of the circuit layer pad are 0.1mm to 0.3mm larger than the design dimensions of the target finished pad on each side.

[0010] Preferably, the offset between the geometric center of the solder mask window and the geometric center of the circuit layer pad is less than or equal to the remaining value after subtracting the alignment error of the solder mask manufacturing process from the single-sided compensation amount of the circuit layer pad, so as to ensure that a non-negative width solder mask overlap area is maintained between the boundary of the solder mask window and the boundary of the circuit layer pad.

[0011] Preferably, the size difference between the circuit layer pad and the solder mask window forms an annular solder mask covering band. The width of the annular solder mask covering band is uniformly or non-uniformly distributed around the circuit layer pad. The actual width of the annular solder mask covering band is determined by the solder mask exposure alignment deviation.

[0012] Preferably, the actual exposed area of ​​the final finished pad is equal to the difference between the designed area of ​​the target finished pad and the area loss caused by the misalignment of the solder mask window, wherein the area loss is zero or positive, and the actual area of ​​the final finished pad is not less than 90% of the designed area of ​​the target finished pad.

[0013] A method for fabricating a high-precision PCB pad structure, comprising the high-precision PCB pad structure as described above, specifically including the following steps:

[0014] Step S1, graphic design: Based on the design size of the target finished pad, determine the compensation amount of the circuit layer pad and design the enlarged circuit layer pad graphic; at the same time, copy the design size of the target finished pad at a 1:1 scale as the window pattern of the solder mask layer.

[0015] Step S2, Circuit fabrication: Enlarged circuit layer pads are formed on the substrate through pattern transfer and etching processes;

[0016] Step S3, Solder mask fabrication: Solder mask ink is coated on the board surface where the circuit layer pads are formed, and then exposed and developed using film or direct imaging data with the window pattern to form a solder mask window on the solder mask layer that is the same size as the target finished pad, exposing part of the circuit layer pad area. This exposed part is the final finished pad.

[0017] Step S4, Post-processing: Perform subsequent surface treatment processes.

[0018] Preferably, in step S3, an automatic alignment exposure machine is used for exposure. The automatic alignment exposure machine uses the alignment marks on the circuit layer pads or substrate as a reference for alignment, so that the alignment accuracy of the solder mask window relative to the circuit layer pads is controlled within ±0.05mm, and the single-sided compensation of each side of the circuit layer pads is greater than the sum of the maximum alignment deviation of the automatic alignment exposure machine and the etching process fluctuation.

[0019] Preferably, in step S3, the solder mask window is positioned in the center area of ​​the circuit layer pad after automatic alignment and exposure, and an annular solder mask coverage area is formed between the boundary of the solder mask window and the boundary of the circuit layer pad.

[0020] Preferably, in step S3, for a plurality of adjacent circuit layer pads, solder mask windows with the same size as their respective target finished pads are opened on the solder mask layer, and the solder mask material between adjacent solder mask windows is retained and forms a solder mask bridge.

[0021] Preferably, in step S3, the width of the solder mask bridge is determined by the spacing between adjacent target finished pads and the compensation amount of the circuit layer pads, and the enlarged design of the circuit layer pads reduces the gap between adjacent circuit layer pads accordingly. The width of the solder mask bridge is less than the nominal spacing value calculated based on the design size of the target finished pads.

[0022] The technical effects and advantages of this invention are as follows:

[0023] (1) This invention intentionally makes the size of the circuit layer pad pattern larger than the design size of the target finished pad during the circuit layer design stage, and opens a window on the solder mask layer that is strictly equal to the size of the target finished pad, so that the size of the final finished pad is determined by the size of the solder mask window rather than by the size of the etched circuit pad. Since the solder mask window is formed by photolithography exposure and development process, its dimensional accuracy is much higher than that of the etching process, and the fluctuation factor of chemical dissolution is not involved in the ultraviolet imaging process. Therefore, the size consistency and repeatability of the final finished pad are fundamentally improved, the process capability index is improved, the dispersion of size data distribution is greatly reduced, and the fluctuation of the etching process is isolated from the size determination chain of the final finished pad by the solder mask layer, thus realizing high-precision control of the pad size;

[0024] (2) In this invention, because the design size of the circuit layer pads is larger than that of the final finished pads, although etching process fluctuations will still affect the actual boundary position of the circuit layer pads, since the solder mask window is completely located within the circuit layer pad area, the actual boundary of the circuit layer pad is always outside the boundary of the solder mask window. Therefore, etching fluctuations will not change the effective pad area exposed by the solder mask window. The single-sided compensation amount of the circuit layer pads comprehensively considers the average etching factor, maximum etching fluctuation amount, and solder mask exposure alignment error of the etching process. This compensation amount provides sufficient margin for solder mask alignment. Even if there is a slight alignment deviation in solder mask exposure, the solder mask window can still fall completely within the enlarged circuit layer pad area, ensuring that a non-negative width solder mask overlap area is always maintained between the boundary of the solder mask window and the boundary of the circuit layer pad. This design simultaneously offsets the effects of two error sources: etching fluctuations and alignment deviations, enhances the process window, and improves product yield. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0026] Figure 1 This is a diagram illustrating the manufacturing steps of the present invention;

[0027] Figure 2 This is a schematic diagram illustrating the process capability of the 0.2mm pad before optimization according to the present invention.

[0028] Figure 3 This is a schematic diagram illustrating the process capability of the optimized 0.2mm pad specification according to the present invention.

[0029] Figure 4 This is a schematic diagram illustrating the process capability of the 0.5mm pad before optimization according to the present invention.

[0030] Figure 5 This is a schematic diagram illustrating the process capability of the optimized 0.5mm pad specification according to the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] This invention provides, for example Figures 1-5 The diagram shows a high-precision PCB pad structure.

[0033] Example 1: Includes circuit layer pads and solder mask layer, the pattern size of the circuit layer pads is larger than the design size of the target finished pads;

[0034] The solder mask layer covers the circuit layer pads. The solder mask layer has a solder mask window at the position of the corresponding circuit layer pad. The size of the solder mask window is equal to the design size of the target finished pad, and the solder mask window is completely located within the circuit layer pad area. The part of the circuit layer pad exposed by the solder mask window forms the final finished pad.

[0035] The outline of the circuit layer pad is the same as that of the target finished pad, and the dimensions of each side of the circuit layer pad are 0.1mm to 0.3mm larger than the design dimensions of the target finished pad on each side. The specific dimensions can be adjusted according to the manufacturing capabilities, for example, the overall dimensions can be increased by 0.2mm.

[0036] The offset between the geometric center of the solder mask window and the geometric center of the circuit layer pad is less than or equal to the remaining value after subtracting the alignment error of the solder mask manufacturing process from the single-sided compensation amount of the circuit layer pad, so as to ensure that a non-negative width solder mask overlap area is maintained between the boundary of the solder mask window and the boundary of the circuit layer pad.

[0037] The size difference between the circuit layer pads and the solder mask window forms an annular solder mask coverage band. The width of the annular solder mask coverage band is uniformly or non-uniformly distributed around the circuit layer pads. The actual width of the annular solder mask coverage band is determined by the solder mask exposure alignment deviation.

[0038] The actual exposed area of ​​the final finished pad is equal to the difference between the designed area of ​​the target finished pad and the area loss caused by the misalignment of the solder mask window. The area loss is zero or a positive value, and the actual area of ​​the final finished pad is not less than 90% of the designed area of ​​the target finished pad. Among them, the circuit layer pad is a rectangular pad, a circular pad, an elliptical pad, or an irregularly shaped pad, and the corresponding solder mask window is a rectangular window, a circular window, an elliptical window, or an irregularly shaped window of the same shape, and the shape of the solder mask window is consistent with the shape of the circuit layer pad.

[0039] Example 2: Based on Example 1, a method for manufacturing a high-precision PCB pad structure specifically includes the following steps:

[0040] Step S1, Graphic Design: Based on the design dimensions of the target finished pads, determine the compensation amount for the circuit layer pads and design an enlarged circuit layer pad graphic. Simultaneously, replicate the design dimensions of the target finished pads at a 1:1 scale as the opening pattern for the solder mask layer. The compensation amount is calculated based on the average etching factor and maximum etching fluctuation of the etching process; typically, the single-sided compensation amount is 0.05-0.2mm. Use professional PCB design software for graphic design. The design process includes importing the target finished pad dimensions, setting compensation parameters, and generating the circuit layer pad graphic and the solder mask layer opening pattern.

[0041] Step S2, Circuit Fabrication: Enlarged circuit layer pads are formed on the substrate through pattern transfer and etching processes. The pattern transfer process includes steps such as photoresist coating, exposure, and development. The photoresist thickness is controlled at 10-20μm, the exposure energy is controlled at 50-100mJ / cm², and the development time is controlled at 30-60 seconds. The etching process uses an acidic etching solution, with the etching rate controlled at 1-2μm / min and the etching factor controlled between 3 and 5. After etching, the quality is inspected by AOI equipment to ensure the dimensional accuracy and appearance quality of the circuit layer pads.

[0042] Step S3, Solder Mask Fabrication: Solder mask ink is applied to the board surface with circuit layer pads. Then, film with a windowed pattern or direct imaging data is used for exposure and development to form a solder mask window on the solder mask layer, which is consistent with the size of the target finished pad. This exposed part is the final finished pad, and the final pad size is determined by the solder mask window. The solder mask window is formed by optical alignment imaging, and its dimensional accuracy is much higher than that of the etching process, effectively avoiding the influence of circuit etching fluctuations. The solder mask ink is selected as a high-temperature resistant, chemical corrosion resistant, and insulating epoxy resin ink. The coating process adopts screen printing or roller coating, and the ink thickness is controlled at 15-25μm. The exposure process uses ultraviolet exposure, and the exposure energy is controlled at 80-120mJ / cm². The development process uses alkaline developer, and the development time is controlled at 60-120 seconds. After development, the quality is inspected by visual inspection and AOI inspection equipment to ensure the dimensional accuracy and appearance quality of the solder mask window.

[0043] The solder mask fabrication process utilizes an automatic alignment exposure machine. This machine uses alignment marks on the circuit layer pads or substrate as a reference for alignment, ensuring the alignment accuracy of the solder mask window relative to the circuit layer pads is controlled within ±0.05mm. Furthermore, the single-sided compensation of each side of the circuit layer pads is greater than the sum of the maximum alignment deviation of the automatic alignment exposure machine and the etching process fluctuations, guaranteeing precise positioning of the solder mask window and the circuit layer pads. The automatic alignment exposure machine employs machine vision technology, using a CCD camera to capture alignment marks on the circuit layer pads or substrate and comparing them with a preset reference image to achieve automatic alignment. Alignment marks are typically designed as circular or square, 1-2mm in size, and located at the corners of the substrate. Alignment accuracy is detected using a laser interferometer, ensuring the alignment deviation is controlled within ±0.05mm.

[0044] Furthermore, after automatic alignment and exposure, the solder mask window is positioned in the center of the circuit layer pad. A ring-shaped solder mask coverage area is formed between the boundary of the solder mask window and the boundary of the circuit layer pad. Because the solder mask window size is strictly equal to the design value and the alignment is precise, the centrality of the produced pad size data is significantly improved, the standard deviation is greatly reduced, and the process capability index (Cpk) is significantly improved. The function of the ring-shaped solder mask coverage area is to protect the edges of the circuit layer pads, preventing bridging, short circuits, and other problems during subsequent soldering. The width of the ring-shaped solder mask coverage area is typically controlled between 0.05-0.1 mm, and is controlled by adjusting the size and alignment accuracy of the solder mask window. The presence of the ring-shaped solder mask coverage area can improve the mechanical strength and corrosion resistance of the pads, extending their service life.

[0045] Furthermore, for multiple adjacent circuit layer pads, solder mask windows with the same size as their respective target finished pads are opened on the solder mask layer, so that the solder mask material between adjacent solder mask windows can be retained and form solder mask bridges.

[0046] The width of the solder mask bridge is determined by the spacing between adjacent target finished pads and the compensation amount of the circuit layer pads. The enlarged design of the circuit layer pads reduces the gap between adjacent circuit layer pads. The width of the solder mask bridge is less than the nominal spacing value calculated based on the design size of the target finished pads. The enlarged circuit pads provide sufficient margin for solder mask alignment. Even with slight alignment deviations, the solder mask window can still fall completely within the circuit pads, ensuring the integrity of the final pad size. Consistent pad sizes facilitate accurate placement and consistent soldering of subsequent components, improving the reliability of the final product. The function of solder mask bridges is to separate adjacent pads and prevent bridging, short circuits, and other problems during subsequent soldering. The width of solder mask bridges is usually controlled between 0.05-0.2mm, and is designed based on the spacing between adjacent target finished pads and the compensation amount of circuit layer pads. If the width of the solder mask bridge is too small, it will cause the solder mask bridge to break, affecting the reliability of the pads. If the width of the solder mask bridge is too large, the spacing between the pads will be too small, affecting the placement and soldering of components. Therefore, the width design of solder mask bridges needs to comprehensively consider the reliability and manufacturability of the pads.

[0047] Step S4, Post-processing: Perform subsequent surface treatment processes. Surface treatment processes include immersion gold, immersion silver, immersion tin, OSP, etc. For immersion gold, the gold layer thickness is controlled at 0.05-0.1μm, and the nickel layer thickness is controlled at 2-5μm; for immersion silver, the silver layer thickness is controlled at 0.1-0.2μm; for immersion tin, the tin layer thickness is controlled at 1-3μm; for OSP, the organic protective film thickness is controlled at 0.1-0.5μm. After surface treatment, reliability tests such as salt spray test and thermal shock test are conducted to ensure the solderability and corrosion resistance of the pads.

[0048] Example 3: Based on Example 2, a method for manufacturing PCB pads with a finished pad size of 0.2mm x 0.5mm is provided, specifically including the following steps:

[0049] Step S1: Based on the design dimensions of the target finished pad, design an enlarged circuit layer pad pattern, and design a solder mask opening pattern with a size equal to the design dimensions of the target finished pad;

[0050] In the circuit layer design, the overall pad pattern size is increased by 0.2mm, resulting in a design size of 0.4mm × 0.7mm. This means each side is expanded outward by 0.1mm, for a total increase of 0.2mm. The pad pattern size can be adjusted according to actual process capabilities. In the solder mask layer design, the original design requirement of 0.2mm × 0.5mm pad size is directly used as the solder mask window pattern. Therefore, the enlarged circuit layer pad design size is 0.4mm × 0.7mm, the target finished pad design size is 0.2mm × 0.5mm, and the single-sided compensation is 0.1mm. The solder mask window size is 0.2mm × 0.5mm.

[0051] Step S2: Enlarged circuit layer pads are formed on the substrate using an etching process;

[0052] The circuit fabrication process utilizes conventional pattern transfer and etching techniques to create circuit pads measuring 0.4mm × 0.7mm on the substrate. Despite fluctuations in the etching process, the enlarged design ensured that the final residual pad area was sufficiently large.

[0053] Step S3: Apply solder resist ink to the board surface with the circuit layer pads, and expose and develop the solder resist window pattern designed in step S1 to form solder resist windows, so that part of the circuit layer pads are exposed as the final finished pads.

[0054] After coating the board surface with solder resist ink, a film or direct imaging data with a 0.2mm × 0.5mm window pattern is used to precisely locate the window in the center area of ​​the circuit pad using an automatic alignment exposure machine. After development, a 0.2mm × 0.5mm window is formed on the solder resist layer, exposing the corresponding part of the circuit pad below. This exposed part is the final finished pad.

[0055] The dimensions of the fabricated pads were measured, and the results showed that all pad dimensions were stable within the range of 0.2mm × 0.5mm ± 0.015mm, with a concentrated data distribution and no out-of-tolerance phenomena. In contrast, the control group produced using traditional methods had a size distribution range of 0.2mm × 0.5mm ± 0.05mm and contained outliers. By increasing the pad compensation and defining the final pads by the solder mask layer, the consistency of pad dimensions and process stability were improved.

[0056] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-precision PCB pad structure, characterized in that, include: The pattern size of the circuit layer pads is larger than the design size of the target finished pads; A solder mask layer is applied over the circuit layer, and a solder mask window is provided at the position corresponding to the pad of the circuit layer. The size of the solder mask window is equal to the design size of the target finished pad, and the solder mask window is completely located within the area of ​​the circuit layer pad. The portion of the circuit layer pad exposed by the solder mask window forms the final finished pad.

2. The high-precision PCB pad structure according to claim 1, characterized in that, The outline of the circuit layer pad is the same as that of the target finished pad, and the dimensions of each side of the circuit layer pad are 0.1mm to 0.3mm larger than the design dimensions of the target finished pad on each side.

3. The high-precision PCB pad structure according to claim 1, characterized in that, The offset between the geometric center of the solder mask window and the geometric center of the circuit layer pad is less than or equal to the remaining value after subtracting the alignment error of the solder mask manufacturing process from the single-sided compensation amount of the circuit layer pad, so as to ensure that a non-negative width solder mask overlap area is maintained between the boundary of the solder mask window and the boundary of the circuit layer pad.

4. The high-precision PCB pad structure according to claim 1, characterized in that, The size difference between the circuit layer pads and the solder mask window forms an annular solder mask covering band. The width of the annular solder mask covering band is uniformly or non-uniformly distributed around the circuit layer pads. The actual width of the annular solder mask covering band is determined by the solder mask exposure alignment deviation.

5. The high-precision PCB pad structure according to claim 1, characterized in that, The actual exposed area of ​​the final finished pad is equal to the difference between the designed area of ​​the target finished pad and the area loss caused by the misalignment of the solder mask window. The area loss is zero or positive, and the actual area of ​​the final finished pad is not less than 90% of the designed area of ​​the target finished pad.

6. A method for fabricating a high-precision PCB pad structure, characterized in that, The method for manufacturing a high-precision PCB pad structure includes the high-precision PCB pad structure as described in any one of claims 1-5, specifically comprising the following steps: Step S1, graphic design: Based on the design size of the target finished pad, determine the compensation amount of the circuit layer pad and design the enlarged circuit layer pad graphic; at the same time, copy the design size of the target finished pad at a 1:1 scale as the window pattern of the solder mask layer. Step S2, Circuit fabrication: Enlarged circuit layer pads are formed on the substrate through pattern transfer and etching processes; Step S3, Solder mask fabrication: Solder mask ink is coated on the board surface where the circuit layer pads are formed, and then exposed and developed using film or direct imaging data with the window pattern to form a solder mask window on the solder mask layer that is the same size as the target finished pad, exposing part of the circuit layer pad area. This exposed part is the final finished pad. Step S4, Post-processing: Perform subsequent surface treatment processes.

7. The method for manufacturing a high-precision PCB pad structure according to claim 6, characterized in that, In step S3, an automatic alignment exposure machine is used for exposure. The automatic alignment exposure machine uses the alignment marks on the circuit layer pads or substrate as a reference for alignment, so that the alignment accuracy of the solder mask window relative to the circuit layer pads is controlled within ±0.05mm, and the single-sided compensation of each side of the circuit layer pads is greater than the sum of the maximum alignment deviation of the automatic alignment exposure machine and the etching process fluctuation.

8. The method for manufacturing a high-precision PCB pad structure according to claim 6, characterized in that, In step S3, the solder mask window is positioned in the center area of ​​the circuit layer pad after automatic alignment and exposure, and an annular solder mask coverage area is formed between the boundary of the solder mask window and the boundary of the circuit layer pad.

9. The method for manufacturing a high-precision PCB pad structure according to claim 6, characterized in that, In step S3, for each of the adjacent circuit layer pads, a solder mask window with the same size as the target finished pad is opened on the solder mask layer, and the solder mask material between the adjacent solder mask windows is retained to form a solder mask bridge.

10. The method for manufacturing a high-precision PCB pad structure according to claim 9, characterized in that, In step S3, the width of the solder mask bridge is determined by the spacing between adjacent target finished pads and the compensation amount of the circuit layer pads. The enlarged design of the circuit layer pads reduces the gap between adjacent circuit layer pads accordingly. The width of the solder mask bridge is less than the nominal spacing value calculated based on the design size of the target finished pads.

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