A method for fabricating blind vias for high-end HDI boards

Abstract

This invention relates to a method for fabricating blind vias for high-end HDI boards, comprising the following steps: S1: performing copper plating on the circuit board to form a copper plating layer within the blind vias; S2: performing flash plating on the copper plating layer to form a flash plating layer; S3: performing a wet-out process on the circuit board to keep it moist; S4: performing a fill plating process on the blind vias while the circuit board is moist. This invention, by setting a flash plating layer, protects the copper plating layer from oxidation or excessive corrosion. Simultaneously, the wet-out process before fill plating avoids residual air within the blind vias, eliminating the drying step in traditional processes. This fundamentally solves the technical problem of voids and gaps between the copper plating layer and the plating layer, significantly improving the filling density and bonding reliability of the blind vias, effectively solving the RST failure problem, and improving product yield and quality. It is particularly suitable for the production of high-end AI computing card HDI boards.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, and more specifically, to a method for fabricating blind vias for high-end HDI boards. Background Technology

[0002] With the rapid development of artificial intelligence (AI) technology, the demand for high-performance AI computing cards is increasing daily. AI computing cards typically use HDI (High-Density Interconnect) boards as their core carrier, and their order has evolved from the early 2nd order to the current 14th order or even higher. The substrate materials used have also been upgraded from M4 level to M9, M10, and other levels. At the same time, the number of blind vias on HDI boards has increased dramatically, with the number of blind vias on a single board rising from around 200,000 to the level of millions of vias.

[0003] In the manufacturing process of high-end HDI boards, the reliability of blind vias is one of the key factors affecting product quality. The industry typically uses the RST (Thermal Stress Test) to evaluate the reliability of blind vias. However, with increasing board order, material upgrades, and blind via density, RST failure becomes increasingly prominent, becoming a major technical bottleneck restricting the mass production and customer certification of high-end AI computing cards. To address the aforementioned RST failure problem, existing technologies generally employ methods such as optimizing laser drilling parameters and adding plasma adhesive removal processes to improve blind via quality. However, actual failure analysis shows that the root cause of RST failure is not the traditionally attributed "bottom adhesive residue" problem, but rather a physical void or gap at the interface between the copper plating layer and the electroplated layer.

[0004] The main reason for the aforementioned voids and gaps is that the traditional blind via manufacturing process includes copper plating, drying, and via-filling electroplating. After horizontal copper plating, the board is typically dried before via-filling electroplating (i.e., dry board electroplating). During the drying process, air can easily remain inside the blind vias. When the dried board enters the electroplating solution, surface tension makes it difficult for the solution to completely expel the air from the blind vias, creating "bubble traps." This prevents the electroplating solution from effectively contacting the copper plating layer at the bottom of the blind via, resulting in voids between the copper plating layer and the electroplating layer. Furthermore, the drying process causes oxidation on the surface of the extremely thin and chemically active copper plating layer, reducing its adhesion to subsequent electroplating layers and further exacerbating the formation of voids and interface gaps, severely impacting product yield and quality. Summary of the Invention

[0005] In view of this, the present invention provides a method for fabricating blind vias for high-end HDI boards, which can effectively solve the problem of voids and gaps between the copper plating layer and the electroplating layer, thereby solving the problem of RST test failure and significantly improving the product qualification rate and quality.

[0006] This invention is achieved through the following technical solution: A method for fabricating blind vias for high-end HDI boards includes the following steps: S1: Perform copper plating on the circuit board to form a copper plating layer inside the blind holes on the circuit board; S2: Flash plating is performed on the copper plating layer to form a flash plating layer; S3: Perform a wet treatment on the circuit board to keep it moist. S4: When the circuit board is wet, perform a hole-filling electroplating process on the blind holes of the circuit board.

[0007] In the above scheme, firstly, a copper plating layer is deposited inside the blind vias and on the surface of the circuit board using a copper plating process, providing a conductive foundation for subsequent electroplating. After the copper plating is completed, a flash plating layer is formed on the copper plating layer. Because the copper plating layer is extremely thin and chemically active, it is easily oxidized to form an oxide layer, which reduces the adhesion to the subsequent electroplating layer. The flash plating layer can effectively isolate the air, protect the copper plating layer from oxidation, ensure the adhesion to the subsequent electroplating layer, and limit the formation of gaps. In addition, during the pretreatment (such as micro-etching and pickling) before the subsequent via-filling electroplating process, the flash plating layer can also protect the inner copper plating layer from excessive corrosion or damage, further avoiding voids or gaps and ensuring the integrity of the conductive path. After the flash plating is completed, the circuit board is not dried, but wet-out treatment is performed to keep the circuit board surface and inside the blind vias in a moist state at all times. That is, liquid is always present on the circuit board surface and inside the blind vias. Then, via-filling electroplating is performed on the circuit board in a moist state. The wet plate plating method of this application, compared with the traditional dry plate plating method of drying the circuit board before plating, eliminates the drying process, which can effectively avoid the presence of air inside the blind holes and prevent voids or gaps after the filling plated due to air bubbles, thereby effectively eliminating the problem of RST failure in subsequent tests.

[0008] Optionally, in one embodiment, in S3, the wet treatment includes immersing the circuit board in a treatment solution to keep the circuit board moist.

[0009] In the above solution, wet treatment is achieved by immersing the circuit board in liquid. Immersion allows the circuit board to be completely surrounded by liquid, ensuring that there is always liquid inside the blind holes of the circuit board to keep it moist.

[0010] Optionally, in one embodiment, in S3, the wet stripping process is implemented by a wet stripping device, which includes a soaking water tray and a curing water tank. The soaking water tray is used to place the circuit board, and the soaking water tray is immersed in the liquid in the curing water tank.

[0011] In the above scheme, the sample tank contains liquid for wet stripping the circuit board, the soaking water tray is submerged in the water in the sample tank, and the circuit board is submerged in the curing tank through the soaking water tray. The circuit board is always surrounded by liquid from all sides, ensuring that it is always in a moist and humid state.

[0012] Optionally, in one embodiment, the wet outlet device further includes a transmission mechanism that passes through the curing tank and is used to transport the circuit board into the curing tank.

[0013] In the above scheme, the transmission mechanism is used to transport the circuit board from the previous process to the soaking water tray in the curing water tank. After the circuit board is processed in the curing water tank, it is then transported to the next process through the transmission mechanism to achieve automated production and improve production efficiency.

[0014] Optionally, in one embodiment, the flash plating layer is made of one of nickel, copper, or gold.

[0015] In the above scheme, the preferred material for the flash plating layer is copper. Copper is the most commonly used conductive metal in PCB manufacturing. Since both the copper plating layer and the electroplated layer obtained by the through-hole plating are made of copper, when the flash plating layer is also made of copper, a homogeneous metal bonding interface can be formed between the three layers. This homogeneous bonding has a high degree of lattice matching, and the metal atoms can form continuous intercrystalline bonds with strong bonding force. There is no interfacial stress caused by the difference in thermal expansion coefficients of different metals.

[0016] Optionally, in one embodiment, the thickness of the flash coating is 4 to 6 μm.

[0017] Optionally, in one embodiment, in S1, the copper plating process includes: transporting the circuit board in a horizontal state through a copper plating solution tank.

[0018] In the above scheme, during the horizontal transmission process, the blind hole openings of the circuit board face upwards or downwards. When the circuit board passes through the chemical tank, the horizontal movement combined with the circulating flow of the chemical can generate a continuous flushing effect, which helps to effectively remove residual air bubbles or reaction byproducts in the blind holes and prevent them from being stuck at the bottom of the holes.

[0019] Optionally, in one embodiment, after the via-filling electroplating process, an electroplating layer is formed on the side of the flash plating layer away from the copper plating layer, and the electroplating layer fills the blind via.

[0020] In the above scheme, the electroplating layer formed by the hole-filling electroplating can completely fill the blind hole, realizing the full filling, surface smoothing and structural strengthening of the blind hole, thereby significantly improving the conductivity, thermal conductivity, mechanical strength and thermal stress resistance of the blind hole.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention eliminates the drying step in traditional blind via fabrication by combining flash plating in S2 and wet plating in S3, successfully solving the problem of voids and gaps between the copper plating layer and the electroplated layer. This solves the problem of RST test failure and significantly improves the product's pass rate and quality, making it particularly suitable for the fabrication of high-end HDI boards. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of the blind hole fabrication method of the present invention.

[0024] Figure 2 This is a schematic diagram of the structure of the blind hole obtained by the method of the present invention.

[0025] Figure 3 This is a schematic diagram of a blind hole obtained using existing processes.

[0026] Figure 4 This is a slice of the HDI test board in Comparative Example 1.

[0027] Figure 5 This is a slice of the HDI test board in Comparative Example 1.

[0028] Figure 6 This is a slice of the HDI test board in Comparative Example 1.

[0029] Figure 7 EDX spectrum of the HDI test plate in Comparative Example 1 Figure 1 .

[0030] Figure 8 EDX spectrum of the HDI test plate in Comparative Example 1 Figure 2 .

[0031] Figure 9 This is a slice image of the HDI test board obtained by the method of the present invention.

[0032] Explanation of the reference numerals in the figure: 1-Blind via; 2-Immersion copper layer; 3-Flash plating layer; 4-Electroplated layer. Detailed Implementation

[0033] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0034] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0035] Comparative Example 1 The blind via fabrication of existing high-end HDI boards typically employs dry plate plating. Dry plate plating mainly includes the following process: copper plating → drying → via filling plating. First, a copper plating layer 2 is formed inside the blind via through copper plating. Then, the circuit board is dried, and the dried circuit board is then filled with via plating layer 4 to fill the blind via. Figure 3 This is a schematic diagram of the internal structure of a blind hole when using the above-mentioned dry plate electroplating method.

[0036] in, Figure 3 It is mainly used to show the mating relationship between the layers. It only serves as a demonstration. The electroplating layer 4 in the figure does not fill the entire blind hole 1. In fact, after the hole filling electroplating is completed, the electroplating layer 4 will fill the entire blind hole 1.

[0037] When performing RST (thermal stress test) on HDI test boards manufactured using dry plate electroplating, it was found that RST failure often occurred, resulting in test failure, low product qualification rate, and inability to guarantee quality.

[0038] Please refer to Figures 4 to 8 ,in, Figures 4 to 6 To obtain cross-sectional images of the HDI test board after dry plated electroplating. Figure 7 and Figure 8 The EDX spectrum of the HDI test board was analyzed. After analyzing the cross-section image and EDX, it was found that the EDX spectrum did not show any extra elements. Combined with the cross-section image, this indicates that the root cause of the RST failure is that there are voids and gaps between the copper plating layer 2 in the blind via 1 and the electroplated layer 4 formed by filling the via, rather than the traditionally believed cause of the bottom residual adhesive.

[0039] Therefore, it is necessary to address the voids and gaps between the copper plating layer 2 and the electroplated layer 4 to prevent RST failure and ensure product quality. Example 1

[0040] Please refer to Figure 1 and Figure 2 To address the technical problems identified in Comparative Example 1, this embodiment provides a method for fabricating blind vias in a high-end HDI board, comprising the following steps: S1: Perform copper plating on the circuit board to form a copper plating layer 2 inside the blind via 1 on the circuit board; S2: Flash plating is performed on the copper plating layer 2 to form the flash plating layer 3; S3: Perform a wet treatment on the circuit board to keep it moist. S4: When the circuit board is wet, perform a hole-filling electroplating process on the blind holes 1 on the circuit board.

[0041] Specifically, firstly, a copper plating layer 2 is deposited inside the blind vias and on the surface of the circuit board using a copper plating process, providing a conductive foundation for subsequent electroplating. After the copper plating is completed, a flash plating layer 3 is formed on the copper plating layer 2 through flash plating. Because the copper plating layer 2 is extremely thin and chemically active, it is easily oxidized to form an oxide layer, which reduces the adhesion to the subsequent electroplating layer 4. The flash plating layer 3 can effectively isolate the air, protect the copper plating layer 2 from oxidation, ensure the adhesion to the subsequent electroplating layer 4, limit the formation of gaps, and facilitate subsequent via filling electroplating. During pretreatment processes (such as micro-etching and pickling), the flash plating layer 3 also protects the inner copper plating layer 2 from excessive corrosion or damage, further preventing voids or gaps and ensuring the integrity of the conductive path. After flash plating, the circuit board is not dried; instead, it undergoes a wet plating process. This process involves immersing the circuit board in liquid, keeping the board surface and blind vias constantly moist. Liquid is always present on the board surface and inside the blind vias. Then, in this moist state, the circuit board is subjected to via-filling electroplating. Compared to the traditional dry plating method where the circuit board is dried before plating, this wet plating method effectively avoids air inside the blind vias, preventing voids or gaps after via-filling electroplating due to air bubbles, thus effectively eliminating the problem of RST failure in subsequent tests.

[0042] In this specific embodiment, water is selected as the liquid for wet treatment of the circuit board.

[0043] It should be noted that for micro-blind vias with a high diameter, if the circuit board is dry, air will remain inside the via. When the dried circuit board is immersed in the electroplating solution for electroplating, due to surface tension, the electroplating solution cannot completely expel the air from the bottom of the via. The air remains inside the via, forming bubbles, preventing the electroplating solution from reaching the copper plating layer 2 and flash plating layer 3 at the bottom of the via. This results in voids or gaps after the via-filling electroplating. However, this application uses a wet-out process to ensure that the inside of the via is always filled with water. During subsequent via-filling electroplating, since the electroplating solution and water are miscible, the electroplating solution can replace the liquid inside the via without bubbles, ensuring that the inside of the via is completely covered by the electroplating solution, thus preventing the formation of voids or gaps after electroplating.

[0044] Since copper plating, flash plating, and via-filling plating all require the circuit board to be in a specific chemical solution, the circuit board only needs to be transferred between different liquids. This avoids the circuit board being exposed to air for too long, preventing air from entering the blind vias. Specifically, in this embodiment, after the circuit board is immersed in water for wet stripping in S3, chemical substances and additives (such as leveling agents and inhibitors) can be directly added to the water to prepare the chemical solution required for via-filling plating. Then, the circuit board is wired and the via-filling plating is performed.

[0045] It should be understood that hole-filling electroplating refers to thickening the copper layer inside the blind hole to form an electroplating layer 4 by applying an external current, and finally filling the blind hole. It belongs to the existing circuit board processing process and will not be described in detail here.

[0046] Preferably, the flash plating in this embodiment is PLB flash plating, which is a flash plating process in the prior art. The specific principle can be referred to the prior art, and will not be described in detail here.

[0047] In this embodiment, in S3, the wet stripping process is implemented by a wet stripping device (not specifically shown in the figure). The wet stripping device includes a soaking water tray, a curing water tank, and a transmission mechanism. The soaking water tray is used to place the circuit board and is immersed in the liquid in the curing water tank. The transmission mechanism passes through the curing water tank and is used to transport the circuit board into the curing water tank.

[0048] Specifically, the sample tank contains water, and the soaking water tray is submerged in the water of the sample tank. The transfer mechanism is used to transport the circuit board from the previous process to the soaking water tray in the curing tank for wet stripping treatment, ensuring that the circuit board is always surrounded by liquid and kept in a moist state. After the circuit board has been treated in the curing tank, it is transported to the next process via the transfer mechanism.

[0049] It is worth mentioning that flash plating can be achieved using existing PLB electroplating lines, and the sample water tank and conveying mechanism can be achieved using the water tank and conveyor on existing HDI production lines. Therefore, this embodiment only requires the addition of a dedicated immersion water tray for circuit boards, without the need for additional complex equipment, resulting in low modification costs and easy promotion and application on existing HDI production lines.

[0050] The flash plating layer 3 is made of one of nickel, copper, or gold. In this embodiment, copper is preferred. Copper is the most commonly used conductive metal in PCB manufacturing. The copper plating layer 2 is electroless copper plating, and the electroplating layer 4 formed by the through-hole electroplating is electroplated copper. When the flash plating layer 3 is also made of copper, a homogeneous metal interface is formed between the three layers. This homogeneous interface has a high degree of lattice matching, and the metal atoms can form continuous intercrystalline bonds with strong bonding force. There is no interface stress caused by the difference in thermal expansion coefficients of different metals. Moreover, in subsequent heat treatment (such as reflow soldering and thermal cycling test), the homogeneous interface will not produce microcracks or delamination due to thermal mismatch, thereby significantly improving the reliability of RST test and ensuring product qualification rate.

[0051] In this embodiment, the thickness of the flash coating 3 is 4 to 6 μm, preferably 5 μm.

[0052] In this embodiment, in step S1, the copper plating process includes: transporting the circuit board horizontally through a copper plating solution tank. This is the horizontal copper plating process in the art. During horizontal transport, the blind vias of the circuit board face upwards or downwards. As the circuit board passes through the solution tank, the horizontal movement combined with the circulating flow of the solution generates a continuous scouring effect, which helps to effectively remove residual air bubbles or reaction byproducts from the blind vias, preventing them from remaining at the bottom of the vias. The horizontal copper plating process is a commonly used process in the art, and its specific principles can be found in existing technologies, which will not be described in detail here.

[0053] In this embodiment, after the hole-filling electroplating process in S4, an electroplating layer 4 is formed on the side of the flash plating layer 3 away from the copper plating layer 2 (i.e., the flash plating layer 3 is located between the copper plating layer 2 and the electroplating layer 4), and the blind hole is filled through the electroplating layer 4.

[0054] Ordinary electroplating only forms a single plating layer 4 on the inner wall of blind vias, leaving depressions or gaps in the central area, preventing complete filling. These incompletely filled blind vias are prone to cracking due to thermal expansion and contraction or mechanical stress during subsequent processes (such as lamination and reflow soldering) or use, leading to electrical connection failure. Therefore, existing high-end HDI boards primarily employ through-hole plating. The plating layer 4 formed by through-hole plating completely fills the blind vias, achieving full filling, surface smoothing, and structural reinforcement, thereby significantly improving the conductivity, thermal conductivity, mechanical strength, and thermal stress resistance of the blind vias.

[0055] in, Figure 2 It is mainly used to show the mating relationship between the layers. It only serves as a demonstration. In the figure, the electroplating layer 4 does not fill the entire blind hole. In fact, after the hole filling electroplating is completed, the electroplating layer 4 will fill the entire blind hole.

[0056] This application, through a combination of flash plating in S2 and wet plating in S3, successfully solved the problem of voids and gaps between the copper plating layer 2 and the electroplated layer 4, thereby resolving the RST test failure issue and significantly improving product quality. Figure 9 As shown, the HDI board produced using the method of this invention, when cross-sectioned, shows that the copper plating layer 2, flash plating layer 3, and electroplating layer 4 are tightly bonded without any voids, and there are no failure issues in subsequent RST tests, effectively improving the product's pass rate and quality.

[0057] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0059] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0060] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating blind vias for high-end HDI boards, characterized in that, Includes the following steps: S1: Apply copper plating to the circuit board to form a copper plating layer inside the blind vias on the circuit board; S2: Flash plating is performed on the copper plating layer to form a flash plating layer; S3: Perform a wet treatment on the circuit board to keep it moist. S4: When the circuit board is wet, perform a hole-filling electroplating process on the blind holes of the circuit board.

2. The method for manufacturing a blind hole according to claim 1, characterized in that, In S3, the wet treatment includes immersing the circuit board in a treatment solution to keep the circuit board moist.

3. The method for manufacturing a blind hole according to claim 1, characterized in that, In S3, the wet-out process is achieved through a wet-out device, which includes a soaking water tray and a curing water tank. The soaking water tray is used to place the circuit board and is submerged in the liquid in the curing water tank.

4. The method for manufacturing a blind hole according to claim 3, characterized in that, The wet outlet device also includes a transmission mechanism that passes through the curing tank and is used to transport the circuit board into the curing tank.

5. The method for manufacturing a blind hole according to claim 1, characterized in that, The flash plating layer is made of one of nickel, copper, or gold.

6. The method for manufacturing a blind hole according to claim 1, characterized in that, The thickness of the flash coating is 4–6 μm.

7. The method for manufacturing a blind hole according to claim 1, characterized in that, In S1, the copper plating process includes: transporting the circuit board in a horizontal position through a copper plating solution tank.

8. The method for manufacturing a blind hole according to claim 1, characterized in that, After the via-filling electroplating process, an electroplating layer is formed on the side of the flash plating layer away from the copper plating layer, and the electroplating layer fills the blind via.

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