A method and apparatus for embedding circuit board stacking

Abstract

This invention relates to a method and apparatus for embedded circuit board stacking. By manufacturing embedded grooves in stages, precisely controlling multi-stage lamination and baking parameters, and optimizing blind via fabrication and circuit connection processes, this invention effectively solves the problems of insufficient processing accuracy of embedded grooves, poor interlayer bonding, unreliable electrical connections, and low alignment accuracy of multi-layer structures. It not only achieves high processing accuracy of embedded grooves and precise control of multi-layer lamination parameters, but also ensures reliable electrical connections of blind vias and high alignment accuracy of multi-layer structures.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, specifically to a method and apparatus for embedded circuit board stacking. Background Technology

[0002] Green development has become a core direction for the economic and social transformation of countries around the world. The new energy vehicle industry, as an important vehicle for achieving low-carbon transportation, has shown rapid development in recent years. However, range anxiety and insufficient charging efficiency remain key bottlenecks restricting its large-scale adoption. To improve user experience, OEMs are deploying 800V high-voltage platform architectures, aiming to reduce current loss, shorten charging time, and improve system efficiency by increasing voltage levels. However, existing power devices, especially traditional silicon-based insulated-gate bipolar transistors (IGBTs), experience significantly increased on-resistance and switching losses under high-voltage, high-frequency operating conditions, leading to severe system heating and decreased efficiency, making it difficult to meet the stringent requirements of next-generation high-performance electric drive systems for high power density and low loss. Silicon carbide, as a typical representative of third-generation wide-bandgap semiconductor materials, with its excellent material properties—high breakdown field strength, high thermal conductivity, low on-resistance, and high switching frequency—can operate stably under high-temperature and high-voltage conditions, significantly reducing the energy loss of power devices themselves, thereby significantly improving the overall efficiency of electric drive systems. Applying silicon carbide power devices to core components such as main drive inverters, on-board chargers, and DC-DC converters for new energy vehicles is expected to break through the performance limits of existing silicon-based devices, providing a feasible technical path to alleviate range anxiety and achieve fast charging.

[0003] Therefore, developing high-performance power devices and their application solutions based on silicon carbide materials is of great practical significance for promoting the new energy vehicle industry towards high efficiency and high voltage development. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention provide a method and apparatus for embedded circuit board stacking to solve the problem that the on-resistance and switching loss of traditional silicon-based insulated gate bipolar transistors (IGBTs) increase significantly under high voltage and high frequency operating conditions, resulting in severe system heat generation and reduced efficiency, making it difficult to meet the stringent requirements of next-generation high-performance electric drive systems for high power density and low loss.

[0005] According to one aspect of the present invention, an embedded circuit board stacking method is provided, the method comprising: S1, fabricate the core board and create embedded grooves in the core board shown; S2, Electrical components are embedded in the embedded groove, and a first outer layer plate is pressed onto the first surface of the core plate to form a first multilayer plate, and a first outer layer circuit is fabricated on the first multilayer plate. S3, A second outer layer plate is pressed onto the second surface of the core plate to form a second multilayer plate, a first blind hole is made in the first multilayer plate and the second multilayer plate, and a first connection line electrically connected to the electrical device is made in the first blind hole. S4, at least one third outer layer is laminated on the first and / or second surfaces of the second multilayer board to form a target PCB board, a second blind via is formed on the target PCB board, and a second connection line electrically connected to the first blind via is formed on the second blind via.

[0006] In some embodiments, step S1 involves fabricating a core board, specifically including: S11, the raw material board is split into core boards by a splitting equipment; S12, perform the first inner layer circuit processing on the first inner layer board of the core board to create the first inner layer circuit; S13, the core board is subjected to the first cutting and grinding process; S14, perform a second inner layer circuit processing on the core board to fabricate the second inner layer circuit; S15, perform inner layer AOI inspection on the first inner layer circuit and the second inner layer circuit, and transfer the core board that passes the inspection to the next process.

[0007] In some embodiments, in step S1, an embedded groove is formed in the core plate, comprising: S16, The core board is first grooved along the first inner layer board using a roughing method. S17, A second groove is made along the position of the first groove using a precision milling method to create an embedded groove, and the single-sided dimension of the embedded groove is larger than the electrical component by a first preset value. S18, check whether the embedded groove is white or has burrs. If so, perform a third groove processing on the embedded groove; otherwise, transfer the core board to the next process.

[0008] In some embodiments, in step S2, an electrical component is embedded in the embedding groove, and a first outer layer plate is pressed onto the first surface of the core board to form a first multilayer board. A first outer layer circuit is fabricated on the first multilayer board, specifically including: S21, the embedding groove of the core board is cleaned and pre-treated, a fixing film is attached to the second surface of the core board, and the electrical components are placed in the embedding groove along the first surface of the core board, wherein the connection terminals of the electrical components are arranged along the first surface of the chip. S22, after peeling off the fixing film on the second surface of the core board, the first outer layer board is pressed onto the first surface of the core board by a preset multi-segment pressing method to form a first multi-layer board, and the first multi-layer board is baked and fixed by a preset multi-segment baking method. S23, after the first multilayer board is subjected to a second cutting and grinding process, the first outer layer circuit is fabricated on the first outer layer board using an auxiliary film method to create the first outer layer circuit, and the first outer layer circuit is subjected to AOI detection processing.

[0009] In some embodiments, in step S22, the first outer layer plate is pressed onto the first surface of the core plate using a preset multi-segment pressing method, specifically including: S221, press the first outer layer plate and the core plate together for 8 minutes under a vacuum environment with a pressure value of 100 PSI; S222, press the first outer layer plate and the core plate together for 7 minutes under a vacuum environment with a pressure value of 200 PSI; S223, press the first outer layer plate and the core plate together for 3 minutes under vacuum with a pressure of 350 PSI. S224, the first outer layer plate and the core plate are pressed together in a vacuum environment for 2 hours and 23 minutes using a pressure value of 400 PSI. S225, press the first outer layer plate and the core plate together for 10 minutes in a vacuum environment using a pressure value of 300 PSI; S226, using a pressure of 100 PSI, the first outer layer plate and the core plate are pressed together for 5 minutes in a non-vacuum environment to produce the first multilayer board.

[0010] In some embodiments, in step S22, the first multilayer board is baked and fixed using a preset multi-segment baking method, specifically including: S227, the first multilayer board is pressed and baked for 5 minutes in a vacuum environment at a baking temperature of 160 degrees Celsius; S228, the first multilayer board is pressed and baked for 5 minutes in a vacuum environment at a baking temperature of 190 degrees Celsius; S229, the first multilayer board is baked at a baking temperature of 220 degrees Celsius in a vacuum environment for 1 hour; S230, the first multilayer board is pressed and baked in a vacuum environment at a baking temperature of 205 degrees Celsius for 10 minutes; S231, the first multi-layer board is baked at 165 degrees Celsius for 5 minutes in a non-vacuum environment.

[0011] In some embodiments, in step S3, a second outer layer is pressed onto the second surface of the core board to form a second multilayer board, a first blind via is formed in the first multilayer board and the second multilayer board, and a first connection line electrically connected to the electrical device is formed in the first blind via, specifically including: S31, a second outer layer is pressed onto the second surface of the core board to form a second multilayer board, and the second multilayer board is subjected to a third cutting and grinding process; S32, perform a second outer layer circuit fabrication on the first multilayer board and the second multilayer board to etch the copper layer at the first blind via location and perform AOI inspection processing; S33, laser drilling is performed on the first multilayer board and the second multilayer board to create the first blind hole, and plasma desmearing and AOI inspection are performed on the second multilayer board. S34, perform hole filling and board electrical treatment on the first blind hole to create a first copper plating layer on the first multilayer board, the second multilayer board and the first blind hole; S35, perform a third outer layer circuit fabrication on the first multilayer board and the second multilayer board to create the first connection line, and perform AOI detection processing on the first connection line.

[0012] In some embodiments, in step S4, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form a target PCB board, a second blind via is formed on the target PCB board, and a second connection line electrically connected to the first blind via is formed on the second blind via, specifically including: S41, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form the target PCB board, and the second multilayer board is subjected to a third cutting and grinding process. S42, a fourth outer layer circuit fabrication is performed on the third outer layer board to etch the copper layer at the second blind via location and perform AOI inspection. S43, the third outer layer board is laser drilled to create a second blind hole, and the target PCB board is subjected to plasma de-adhesive treatment and AOI inspection. S44, fill the second blind hole and perform board electrical treatment to create a second copper plating layer on the third outer layer board and the second blind hole; S45, perform the fifth outer layer circuit fabrication on the third multilayer board to create the second connection line, and perform AOI detection processing on the second connection line.

[0013] In some implementations, after step S4, the following steps are also included: S5, the target PCB board is sequentially subjected to solder resist treatment, text processing, forming treatment, testing treatment, FQC treatment, tin melting treatment and surface cleaning treatment.

[0014] According to another aspect of the present invention, an embedded circuit board stacking apparatus is provided, the apparatus being used to perform the above-described embedded circuit board stacking method.

[0015] The embedded circuit board stacking method and apparatus of the present invention have the following advantages: The present invention effectively solves the problems of insufficient processing accuracy of embedded grooves, poor interlayer bonding, unreliable electrical connection and low alignment accuracy of multi-layer structures by step-by-step manufacturing of embedded grooves, precise control of multi-stage pressing and baking parameters, and optimization of blind hole manufacturing and circuit connection processes. It not only achieves high processing accuracy of embedded grooves and precise control of multi-layer pressing parameters, but also reliable electrical connection of blind holes and high alignment accuracy of multi-layer structures.

[0016] The above description is merely an overview of the technical solutions of the embodiments of the present invention. In order to better understand the technical means of the embodiments of the present invention and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0017] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart illustrating an embodiment of the embedded circuit board stacking method provided by the present invention is shown. Figure 2 A flowchart illustrating step S3 of an embodiment provided by the present invention is shown; Figure 3 A schematic diagram of the structure of the target PCB board according to an embodiment of the present invention is shown.

[0018] Figure label: L1 / L6, third outer layer plate; L2, second outer layer plate; L3, second surface of core plate; L4, first surface of core plate; L5, first outer layer plate; 10, electrical components; 11, first connecting line; 12, second connecting line. Detailed Implementation

[0019] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0020] Example 1: Figures 1-3 This illustration shows a first embodiment of an embedded circuit board stacking method provided by the present invention, which addresses the problem that traditional silicon-based insulated-gate bipolar transistors (IGBTs) experience significantly increased on-resistance and switching losses under high-voltage, high-frequency operating conditions, leading to severe system overheating and decreased efficiency, making it difficult to meet the stringent requirements of next-generation high-performance electric drive systems for high power density and low loss. This method includes: S1, fabricate the core board and create embedding grooves in the core board; in step S1, the core board is fabricated and the embedding grooves are formed. The core board can be fabricated in various ways, for example, by directly selecting a prefabricated substrate that meets specifications as the core board; or by cutting and edge-processing a large-size raw material board to obtain a core board of the required size. When creating the embedding grooves on the core board, mechanical processing methods can be used, such as milling or drilling to form grooves at predetermined positions on the core board; or, laser technology can be used to precisely control the laser beam to ablate the core board material, thereby forming embedding grooves of precise size and shape.

[0021] S2, Electrical components are embedded in the embedding groove, and a first outer layer plate is pressed onto the first surface of the core board to form a first multilayer board. A first outer layer circuit is then fabricated on the first multilayer board. In step S2, electrical components are embedded in the embedding groove, and a first outer layer plate is pressed onto the first surface of the core board to form a first multilayer board. Subsequently, a first outer layer circuit is fabricated on the first multilayer board. The embedding of electrical components can be done manually, placing the components in the embedding groove and initially fixing them; or, automated equipment can be used, employing machine vision and a precision robotic arm to accurately place the components into the embedding groove. The pressing of the first outer layer plate can be done using a one-time lamination process, covering the first outer layer plate material (e.g., prepreg and copper foil) onto the first surface of the core board and curing and bonding it under a set temperature and pressure to form the first multilayer board; or, a multi-stage pressing method can be used, applying different pressures and temperatures in stages to optimize the lamination effect. The fabrication of the first outer layer circuit can be carried out using traditional photolithography, development, and etching processes to transfer the circuit pattern onto the copper layer of the first outer layer board, and remove unwanted copper through chemical etching to form conductive circuits; alternatively, direct imaging technology can be used to directly expose the circuit pattern onto a photosensitive material, followed by subsequent etching.

[0022] S3, a second outer layer is laminated onto the second surface of the core board to form a second multilayer board. A first blind hole is formed on the first and second multilayer boards, and a first connection line electrically connected to an electrical component is formed within the first blind hole. In step S3, the second outer layer is laminated onto the second surface of the core board to form a second multilayer board, and a first blind hole is formed on the first and second multilayer boards, with a first connection line electrically connected to an electrical component formed within the first blind hole. The lamination of the second outer layer can employ a lamination process similar to that of the first outer layer, covering the second outer layer material onto the second surface of the core board, and forming the second multilayer board by heating and pressurizing. The first blind hole can be formed by mechanical drilling, drilling incompletely penetrating holes at designated locations on the first and second multilayer boards; or, laser drilling technology can be used to precisely form blind holes between layers using a laser beam. The fabrication of the first connection line involves depositing a copper layer on the inner wall and surface of the blind hole using chemical copper plating and electroplating processes after the first blind hole is formed. This enables the blind hole to conduct and establishes an electrical connection between the electrical components and the external circuitry.

[0023] S4, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form a target PCB board. A second blind via is fabricated on the target PCB board, and a second connection line electrically connected to the first blind via is fabricated within the second blind via. In step S4, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form the target PCB board, and a second blind via is fabricated on the target PCB board. A second connection line electrically connected to the first blind via is fabricated within the second blind via. The lamination of the third outer layer can be performed according to design requirements, adding one or more outer layers on one or two surfaces of the second multilayer board through a lamination process to ultimately form a complete PCB board structure. The second blind via can be fabricated using mechanical drilling or laser drilling technology, creating blind vias between corresponding layers of the target PCB board. The second connection line is fabricated after the second blind via is formed, by using a copper plating process to form a conductive layer on the inner wall of the second blind via and the board surface, thereby enabling the second blind via to conduct and establishing an electrical connection with the first blind via, completing the interlayer interconnection of the entire circuit board.

[0024] This embodiment of the embedded circuit board stacking method achieves high-density integration and interlayer interconnection of electrical components by embedding electrical components in the core board and laminating outer layers layer by layer, fabricating multi-layer circuitry and blind vias. This method helps to construct a compact and efficient circuit board structure, thereby reducing energy loss of power devices under high-voltage and high-frequency operating conditions and improving overall system efficiency. This plays a positive role in meeting the requirements of high power density and low loss for electric drive systems in new energy vehicles, alleviating range anxiety, and improving charging efficiency.

[0025] Example 2: Based on Embodiment 1, the present invention provides a second embodiment of the embedded circuit board stacking method to further describe the embedded circuit board stacking method.

[0026] In some embodiments, step S1 involves fabricating a core board, specifically including: S11, the raw material board is split into core boards by a splitting equipment; S12, perform the first inner layer circuit processing on the first inner layer board of the core board to create the first inner layer circuit; S13, the core board undergoes its first cutting and grinding process; S14, perform a second inner layer circuit processing on the core board to fabricate the second inner layer circuit; S15, perform inner layer AOI inspection on the first inner layer circuit and the second inner layer circuit, and transfer the core board that passes the inspection to the next process.

[0027] In steps S11-S15, through the above technical solution, the core board manufacturing process in the embedded circuit board stacking method is controlled with precision and standardization. First, the raw material board is precisely separated using a board separation device to ensure that the initial size and shape of the core board meet the requirements. Subsequently, the first and second inner layer boards of the core board are processed step by step for inner layer circuitry, supplemented by intermediate grinding, so that the conductive patterns inside the core board can be accurately formed and the geometric accuracy of the core board can be guaranteed. More importantly, after the inner layer circuitry is manufactured, an inner layer AOI inspection step is introduced, which can promptly detect and remove defective core boards, thereby avoiding the use of unqualified semi-finished products in subsequent high-cost processes such as embedding electrical components and laminating outer layer boards. This not only significantly improves the quality and reliability of the inner layer circuitry of the core board and reduces the scrap rate in the production process, but also provides a high-quality foundation for the precise embedding of subsequent electrical components and the stable stacking of multilayer boards, ultimately effectively ensuring the overall performance and production efficiency of the embedded circuit board.

[0028] In some embodiments, in step S1, an embedded groove is formed in the core plate, comprising: S16, The core board is first grooved along the first inner layer board using a roughing method. S17, A second groove is made along the position of the first groove by precision milling to create an embedded groove, and the single-sided dimension of the embedded groove is larger than the first preset value of the electrical component. S18, check if there is whitening or burrs in the embedded groove. If so, perform a third groove treatment on the embedded groove; otherwise, transfer the core board to the next process.

[0029] In steps S16-S18, specifically, the core board is first grooved along the first inner layer plate using a rough milling method. This step aims to perform preliminary material removal from the core board to form a rough outline of the embedded groove. Using a rough milling method, i.e., machining with a larger diameter milling cutter or at a higher feed rate, allows for the rapid and efficient removal of most of the material, laying the foundation for subsequent fine machining. Grooving along the first inner layer plate ensures that the position of the embedded groove matches the internal structure of the core board.

[0030] Based on this, a second milling is performed along the position of the first milling groove using a precision milling method to create an embedding groove. The single-sided dimension of the embedding groove is larger than the electrical component by a first preset value. This step, based on the initial milling, performs a secondary machining of the embedding groove using a precision milling method to achieve high-precision dimensions and excellent surface quality. The milling cutter diameter for precision milling is smaller than that for rough milling, the feed rate is lower than that for rough milling, and the spindle speed is higher than that for rough milling; this results in a smooth and flat groove wall, ensuring that the geometry of the embedding groove meets design requirements. Furthermore, the single-sided dimension of the embedding groove is designed to be larger than the corresponding dimension of the electrical component by a first preset value. This preset value provides the necessary clearance to accommodate the dimensional tolerances of the electrical component, adhesive materials, or encapsulating resin, ensuring that the electrical component can be smoothly and accurately embedded, and providing space for subsequent curing and connection. The first preset value can be 1-3 mil.

[0031] Subsequently, the embedded groove is inspected for whitening or burrs. If any are found, the embedded groove undergoes a third milling process; otherwise, the core board is moved to the next process. The third milling process, a targeted rework measure, eliminates defects through further fine machining, ensuring the embedded groove meets quality standards. If no defects are found, the core board can smoothly proceed to subsequent processes, guaranteeing a smooth production flow and stable product quality.

[0032] Through the above technical solution, when fabricating the embedded slots on the core board, a preliminary roughing process is first used to quickly remove most of the material, improving processing efficiency. Subsequently, a secondary fine-milling process significantly improves the dimensional accuracy and surface finish of the embedded slots, ensuring that the geometry of the slots meets design requirements. In particular, by setting the single-sided dimension of the embedded slot to be larger than the electrical component by a first preset value, necessary clearance is reserved for the precise embedding of the electrical component, effectively avoiding problems such as improper installation or inaccurate positioning due to excessively tight or loose dimensions. Based on this, a detection and correction mechanism for defects such as whitening and burrs in the embedded slots, along with a third milling process, is introduced. This allows for the timely detection and elimination of quality problems arising during processing, thereby ensuring the overall quality and reliability of the embedded slots. This phased, refined processing flow with quality feedback greatly improves the manufacturing accuracy and pass rate of the embedded slots, providing a solid guarantee for the stable embedding of subsequent electrical components and the overall performance of the circuit board, effectively solving the problem of difficult quality control of embedded slots under a single processing method.

[0033] In some embodiments, in step S2, electrical components are embedded in the embedding groove, and a first outer layer plate is pressed onto the first surface of the core board to form a first multilayer board. The first outer layer circuitry is fabricated on the first multilayer board, specifically including: S21, the embedding groove of the core board is cleaned and pre-treated, a fixing film is attached to the second surface of the core board, and the electrical components are placed in the embedding groove along the first surface of the core board, wherein the connection terminals of the electrical components are arranged along the first surface of the chip. S22, after peeling off the fixing film on the second surface of the core board, the first outer layer board is pressed onto the first surface of the core board by a preset multi-segment pressing method to form the first multi-layer board, and the first multi-layer board is baked and fixed by a preset multi-segment baking method. S23, after the second cutting and grinding process of the first multilayer board, the first outer layer circuit is fabricated on the first outer layer board by means of the auxiliary film method, so as to fabricate the first outer layer circuit and perform AOI inspection on the first outer layer circuit.

[0034] In steps S21-S23, specifically, during the pre-treatment cleaning of the embedding groove of the core board, physical or chemical methods are typically used to remove dust, debris, oxides, or other contaminants from the embedding groove to ensure a clean surface. This provides a foundation for good contact between the electrical components and the core board, and for effective resin filling subsequently. A fixing adhesive film is applied to the second surface of the core board. Its function is to provide temporary support and protection during the placement and initial fixing of the electrical components, preventing accidental displacement or detachment during operation or handling. The electrical components are placed in the embedding groove along the first surface of the core board, ensuring that the connection terminals of the electrical components are also aligned with the first surface of the core board. This is crucial for subsequent electrical connections to external circuits, guaranteeing the correct functional implementation of the electrical components and the overall electrical performance of the circuit board.

[0035] After peeling off the adhesive film from the second surface of the core board, a first outer layer is pressed onto the first surface of the core board using a pre-defined multi-stage pressing method to form a first multilayer board. The peeling process is necessary to prevent the adhesive film from being pressed into the multilayer board structure, which could affect product quality and reliability. The pre-defined multi-stage pressing method refers to applying different pressures, temperatures, and / or vacuum levels in stages during the pressing process to achieve precise and uniform pressing of the first outer layer and the core board. For example, pre-pressing can be performed at a lower pressure to allow the resin to initially flow and expel gas. Subsequently, the pressure and temperature are gradually increased to ensure that the resin fully fills the gaps around the embedding groove and bonds tightly to the surface of the electrical components, while avoiding excessive stress damage to the electrical components. This multi-stage control helps prevent bubble formation, reduce lamination stress, and ensure uniform resin curing around the electrical components. Meanwhile, the first multilayer board is baked and fixed by a pre-set multi-stage baking method. After the pressing is completed, the first multilayer board is heated in stages to further promote the complete curing of the resin, stabilize the laminated structure, and release internal stress, thereby improving the mechanical strength and reliability of the multilayer board.

[0036] After the second trimming and grinding process on the first multilayer board, the first outer layer circuitry is fabricated on the first outer layer board using an auxiliary film method. This first outer layer circuitry is then subjected to AOI (Automated Optical Inspection) inspection. The second trimming and grinding process precisely corrects the dimensions and shape of the laminated first multilayer board, providing a standardized substrate for subsequent circuit fabrication. The auxiliary film method is a technique that uses photoresist and a mask (film) to precisely transfer circuit patterns onto the copper foil of the first outer layer board. This method ensures the accuracy and consistency of the circuit patterns, especially in complex structures with embedded electronic components, effectively avoiding potential impacts on the embedded components. This step only fabricates the first outer layer circuitry, meaning that the current stage of circuit fabrication focuses on the first outer layer board, simplifying the process complexity. The subsequent AOI inspection process automatically identifies defects such as short circuits, open circuits, uneven line widths, and residual copper on the first outer layer circuitry through high-speed, high-precision optical scanning, ensuring that the circuit quality meets design requirements and providing qualified semi-finished products for subsequent processes.

[0037] Through the above technical solution, in the embedded circuit board stacking process, the embedding groove of the core board is first cleaned and pre-treated. A fixing film is then used to assist in the precise placement and temporary fixation of electrical components, ensuring that the connection terminals of the components are correctly positioned along the first surface of the core board. This effectively solves the problems of inaccurate positioning and displacement of electrical components during the embedding process. Subsequently, the fixing film is removed through a peeling process, and a pre-set multi-stage pressing and baking method is used to perform staged and refined pressing and curing of the core board and the first outer layer board. This multi-stage control strategy can effectively manage the pressure and temperature during the pressing process, avoiding excessive stress on the embedded electrical components, while ensuring uniform resin filling and full curing. This significantly reduces the risk of lamination delamination, bubble formation, and damage to electrical components, greatly improving the structural integrity and reliability of the first multilayer board. Finally, a precise second grinding process and an auxiliary film method are used to fabricate the first outer layer circuitry, supplemented by AOI inspection, ensuring the accuracy and quality of the circuit fabrication and avoiding performance problems caused by circuit defects. Overall, this solution provides a highly controllable and reliable process for embedding electrical components and forming the first multilayer board, which significantly improves the manufacturing yield and product performance of embedded circuit boards.

[0038] In some embodiments, in step S22, the first outer layer plate is pressed onto the first surface of the core plate using a preset multi-segment pressing method, specifically including: S221, the first outer layer plate and the core plate are pressed together under vacuum for 8 minutes at a pressure of 100 PSI. This initial stage uses a lower pressure to gently establish initial contact and positioning between the first outer layer plate and the core plate. The vacuum environment helps to effectively expel air from the interface during the initial pressing process, avoiding air bubble residue and laying the foundation for a tighter bond later. The shorter pressing time ensures a gentle transition, avoiding impact on the embedded electrical components.

[0039] S222: The first outer layer and core board are pressed together under vacuum for 7 minutes at a pressure of 200 PSI. During this stage, the pressure is moderately increased to further promote a tighter bond between the first outer layer and the core board. The continuous vacuum environment further eliminates any potential micro-air bubbles, ensuring a uniform distribution of the resin material before subsequent curing.

[0040] S223: The first outer layer and core board are pressed together under vacuum for 3 minutes at a pressure of 350 PSI. The pressure is increased again to enhance the interlayer bonding, allowing the resin material to flow fully and fill microscopic voids. This stage of pressing is relatively short, primarily to quickly achieve the desired bonding state, preparing for the main curing stage.

[0041] S224, the first outer layer and core board are pressed together under vacuum at a pressure of 400 PSI for 2 hours and 23 minutes. This is the main pressing stage in the entire process, employing the highest pressure and longest pressing time. High pressure ensures sufficient flow, penetration, and curing of the resin material between the first outer layer and core board, as well as around the embedded electrical components, forming a strong physical and chemical bond. The long pressing time ensures the resin material has enough time to complete the curing reaction, resulting in optimal interlayer bond strength and dimensional stability. The vacuum environment is crucial at this stage, minimizing the risk of voids or delamination during curing.

[0042] S225, the first outer layer board and the core board are pressed together under vacuum for 10 minutes at a pressure of 300 PSI. After the main pressing stage, the pressure is gradually reduced. This stage aims to stabilize the cured first multilayer board and avoid internal stress concentration or structural deformation caused by a sudden drop in pressure. Performing this under vacuum helps maintain the flatness of the board during the cooling process.

[0043] S226, the first outer layer board and the core board are pressed together for 5 minutes under a pressure of 100 PSI in a non-vacuum environment to produce the first multilayer board. This is the final stage of the pressing process, where the pressure is reduced to its minimum and the environment is switched to non-vacuum. This stage is mainly used for the final cooling and stress release of the first multilayer board, allowing it to reach a stable state before demolding. Performing this in a non-vacuum environment allows for a smooth release of the pressed state, preventing damage to the board due to excessive internal and external pressure differences, and ensuring the integrity and flatness of the first multilayer board.

[0044] By employing the above technical solution and using phased, gradient-varying pressing parameters, the problems of weak bonding, voids, delamination, and damage to embedded electrical components that may occur in traditional pressing methods can be effectively solved. Specifically, the initial low-pressure vacuum pressing gently removes air and provides preliminary positioning, avoiding impact on the electrical components. Subsequently, the pressure is gradually increased to ensure the resin material flows fully and fills all voids, forming a dense interlayer structure. The high-pressure, long-duration vacuum treatment in the main pressing stage ensures complete resin curing and interlayer bonding strength, significantly improving the overall reliability and mechanical properties of the first multilayer board. Finally, the phased pressure reduction and stabilization treatment in a non-vacuum environment effectively releases internal stress, preventing board warping or delamination, thereby ensuring the flatness and dimensional stability of the first multilayer board, maximizing the protection of the integrity of the embedded electrical components, and improving product yield.

[0045] In some embodiments, in step S22, the first multilayer board is baked and fixed using a preset multi-segment baking method, specifically including: S227, the first multilayer board is pressed and baked for 5 minutes in a vacuum environment at a baking temperature of 160 degrees Celsius; S228, the first multilayer board is pressed and baked for 5 minutes in a vacuum environment at a baking temperature of 190 degrees Celsius; S229, the first multilayer board is baked at a baking temperature of 220 degrees Celsius in a vacuum environment for 1 hour; S230, the first multilayer board is pressed and baked in a vacuum environment at a baking temperature of 205 degrees Celsius for 10 minutes; S231, the first multi-layer board is baked at 165 degrees Celsius for 5 minutes in a non-vacuum environment.

[0046] In steps S227-S231, the first multilayer board is baked and fixed using a pre-set multi-stage baking method, which effectively solves problems such as uneven curing, high internal stress, delamination, or voids that may occur with traditional baking methods. Specifically, the staged temperature control, gradually increasing from 160 degrees Celsius to 220 degrees Celsius and then gradually decreasing to 165 degrees Celsius, precisely matches the curing curve of the resin material, ensuring sufficient polymerization and cross-linking of the resin. Maintaining a vacuum environment during most of the baking process efficiently removes volatiles and trapped air from the resin, significantly reducing the generation of bubbles and voids, and improving the interlayer bonding strength and board density. In particular, the long-term (1 hour) primary curing at 220 degrees Celsius ensures the complete curing of the resin around the embedded electrical components, enhancing the encapsulation and fixation effect of the electrical components. Finally, cooling in a non-vacuum environment helps to uniformly release the stress of the board and avoids board deformation or warping caused by rapid cooling or excessive internal and external pressure differences. Therefore, this multi-stage baking method significantly improves the structural integrity, electrical performance stability and reliability of the first multilayer board, laying a solid foundation for subsequent circuit fabrication and the overall performance of the PCB board.

[0047] In some embodiments, in step S3, a second outer layer is pressed onto the second surface of the core board to form a second multilayer board, a first blind via is formed in the first multilayer board and the second multilayer board, and a first connection line electrically connected to the electrical device is formed in the first blind via, specifically including: S31, a second outer layer is laminated onto the second surface of the core board to form a second multilayer board, and the second multilayer board undergoes a third trimming process. By laminating materials such as prepreg and copper foil onto the second surface of the core board, a composite structure comprising a core board, a first outer layer, and a second outer layer is formed, i.e., the second multilayer board. The lamination process is typically carried out under high temperature and high pressure to ensure sufficient adhesion between the layers, eliminate air bubbles, and form a stable laminated structure. The subsequent third trimming process aims to precisely control the external dimensions and edge quality of the second multilayer board, providing a standardized substrate for subsequent circuit fabrication and drilling processes, ensuring the accuracy and yield of subsequent processing.

[0048] S32, a second outer layer circuit fabrication is performed on the first and second multilayer boards to etch the copper layer at the location of the first blind via and then perform AOI (Automated Optical Inspection) processing. The second outer layer circuit fabrication typically employs photolithography and etching processes. Through a series of chemical treatments including exposure, development, and etching, a predetermined circuit pattern is formed on the surface copper layer of the first and second multilayer boards. During this process, the copper layer at the predetermined location of the first blind via is precisely controlled using the etching process to remove the copper layer in that area, creating an opening so that subsequent laser drilling can accurately locate and penetrate to the target layer. After the circuit fabrication is completed, AOI processing is performed to detect defects such as short circuits, open circuits, uneven line width, and residual copper, ensuring the quality of the circuit fabrication.

[0049] S33, laser drilling is performed on the first and second multilayer boards to create the first blind via. The second multilayer board undergoes plasma desmearing and AOI inspection. Laser drilling technology is used here to precisely create the first blind via. Compared to mechanical drilling, laser drilling can achieve smaller hole diameters and higher positioning accuracy, and is particularly suitable for creating blind vias, i.e., holes that do not completely penetrate the entire board thickness. The laser beam forms the hole by ablating or vaporizing the material, and its depth can be precisely controlled to ensure that the blind via can accurately connect to the connection terminals of embedded electrical components or to a predetermined layer inside the core board. After drilling, plasma desmearing is performed to remove resin residue from the inner wall of the blind via caused by laser drilling, ensuring a clean hole wall and providing a good adhesion surface for subsequent copper plating, preventing poor copper plating or open circuits. Finally, AOI inspection is performed again to verify that the position, size, and hole wall quality of the first blind via meet the design requirements.

[0050] S34, a via filling process and board electroplating are performed on the first blind via to create a first copper plating layer on the first multilayer board, the second multilayer board, and the first blind via. The via filling process aims to fill the first blind via, typically using conductive or non-conductive resin materials. If conductive via filling is used, a conductive path is directly formed; if non-conductive via filling is used, it mainly provides mechanical support and surface flatness, providing a flat substrate for subsequent copper plating. Board electroplating is a key conductive layer formation step, which includes chemical copper plating and electroplating. First, a thin conductive copper layer is formed on the inner wall of the blind via and the board surface by chemical copper plating, and then the copper layer is further thickened by electroplating to achieve the required conductivity and mechanical strength. Through this step, the inner wall of the first blind via is completely plated, forming a continuous and reliable electrical connection with the surface copper layers of the first and second multilayer boards, thereby creating the first copper plating layer.

[0051] S35, a third outer layer circuit fabrication is performed on the first and second multilayer boards to create the first connection lines, and AOI inspection is conducted on these first connection lines. After the first copper plating layer is formed, photolithography and etching processes are performed again, i.e., the third outer layer circuit fabrication. The goal of this circuit fabrication is to precisely define the first connection lines, which electrically connect the first blind vias to other circuit nodes. Through meticulous circuit fabrication, high-density wiring can be achieved to meet the needs of complex circuit functions. After the circuit fabrication is completed, AOI inspection is performed again to ensure the integrity and accuracy of the first connection lines and to eliminate any manufacturing defects, thereby ensuring the electrical functionality of the entire circuit board.

[0052] In steps S31-S35, using the above technical solution, after the second outer layer board is laminated onto the second surface of the core board, a series of meticulous process steps, including pre-etching, high-precision laser drilling, thorough plasma desmearing, reliable via filling and board electrical processing, and precise circuit fabrication, ensure the formation quality of the first blind via and the reliability of its electrical connection with the embedded electrical components. This step-by-step and meticulous processing method effectively solves the technical challenge of accurately connecting embedded electrical components from the non-embedded side in a multilayer board structure, avoiding connection failures caused by unclean hole walls, poor copper plating, or circuit defects. Simultaneously, the introduction of multiple AOI inspections allows for timely detection and correction of defects after critical processes, significantly improving the manufacturing yield and product reliability of embedded circuit boards. This enables embedded electrical components to be stably integrated into more complex circuit systems, thereby achieving circuit board products with higher integration, smaller size, and superior performance.

[0053] In some embodiments, in step S4, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form a target PCB board, a second blind via is formed on the target PCB board, and a second connection line electrically connected to the first blind via is formed in the second blind via, specifically including: S41, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form the target PCB board, and the second multilayer board is subjected to a third trimming process. S42, the fourth outer layer circuit fabrication is performed on the third outer layer board to etch the copper layer at the second blind via location and perform AOI inspection. S43, laser drilling is performed on the third outer layer board to create the second blind via, and plasma de-adhesive removal and AOI inspection are performed on the target PCB board. S44, fill the second blind hole and perform board electrical treatment to create a second copper plating layer on the third outer layer board and the second blind hole; S45, perform the fifth outer layer circuit fabrication on the third multilayer board to create the second connection circuit, and perform AOI inspection on the second connection circuit.

[0054] In steps S41-S45, through the aforementioned technical solution, based on the existing multilayer board structure, a series of steps including precisely controlled lamination, circuit fabrication, laser drilling, plasma adhesive removal, via filling, and board electrical treatment effectively increase the number of PCB layers, enabling more complex circuit layouts. In particular, the fourth and fifth outer layer circuit fabrication, laser drilling to create the second blind via, and via filling and board electrical treatment to form the second copper plating layer ensure precise and reliable electrical connections between the third outer layer and the underlying structure. Plasma adhesive removal and multiple AOI inspections are integrated throughout the key steps, significantly improving the fabrication quality of blind vias and circuits, effectively preventing electrical performance degradation or failure caused by residual adhesive, short circuits, open circuits, etc., thereby guaranteeing the high integration, high reliability, and excellent electrical performance of the target PCB, meeting the demands of modern electronic products for complex multilayer boards.

[0055] In some implementations, after step S4, the following steps are also included: S5 sequentially performs solder mask treatment, text processing, molding treatment, testing treatment, FQC treatment, tinning treatment, and surface cleaning treatment on the target PCB board.

[0056] Through the aforementioned series of post-processing steps, the embedded circuit board prepared in this application achieves significant improvements in reliability, functionality, manufacturability, and final product quality. Solder resist treatment effectively protects internal circuitry, preventing short circuits and environmental corrosion, thus extending the circuit board's lifespan. Text processing provides clear guidance for subsequent component assembly, debugging, and maintenance, improving production efficiency and traceability. Forming processing ensures the precise dimensions and structure of the circuit board, enabling its smooth integration into the final product. Testing processing comprehensively verifies the electrical integrity and functionality of the circuit board before shipment, effectively preventing defective products from entering the market. Final quality control (FQC) processing, as the final quality check, ensures that the product's appearance and overall quality meet standards. Soldering provides excellent solderability and oxidation resistance to the pads, ensuring the reliability of subsequent component soldering. Finally, surface cleaning thoroughly removes contaminants generated during manufacturing, further improving the circuit board's electrical performance and long-term stability. These processes collectively ensure that the embedded circuit board not only possesses complex internal structures and functions but also meets high standards in physical morphology, electrical performance, and environmental adaptability, thereby meeting the application requirements of high-performance electronic products.

[0057] Example 3: Based on Embodiment 1 or Embodiment 2, the present invention provides an embodiment of an embedded circuit board stacking device, which is used to perform the embedded circuit board stacking method of Embodiment 1 or Embodiment 2.

[0058] exist Figure 3 In the example shown, the core board and PP of layers L2 to L6 all use Teng Hui VT-464L core board and PP, which have the following characteristics: a. Compatible with lead-free processes, suitable for modern high-reliability PCB manufacturing; b. Low Dk (dielectric constant) and extremely low loss (Df), suitable for high-speed, high-frequency signal transmission; c. High Tg (glass transition temperature), ensuring structural stability at high temperatures; d. Low Z-axis coefficient of thermal expansion (CTE) and resistance to CAF (resistance to conductive anode filament growth, reducing microshortage caused by interlayer ion migration), improving the reliability of multilayer boards; e. Halogen-free environmentally friendly formula: compliant with RoHS and other environmental regulations. The L1-L2 layers of PP use Tenghui thermally conductive adhesive film, model VT-4B7H. Its main characteristics are: a. High thermal conductivity: 2.2 W / m·K, which can conduct heat generated by electronic components from the inside to the heat dissipation layer or outer casing; b. Electrical insulation: Prevents interlayer short circuits and withstands high voltages (e.g., ≥500V); c. Structural bonding: Achieves strong adhesion between copper foil layers of the PCB during high-temperature and high-pressure lamination; d. Low dielectric constant (Dk) and loss (Df): Suitable for high-speed signal transmission scenarios, reducing signal distortion. It is mainly used for heat conduction and bonding between electronic devices and heat dissipation structures, combining thermal conductivity, insulation, and structural bonding functions.

[0059] L3 and L4 are the first and second surfaces of the core board, respectively. L3 and L4 are also the first and second inner layer boards within the core board. When fabricating the inner layer circuitry, LDI exposure is required. Only the L4 layer circuitry is fabricated; the L3 layer circuitry is fabricated using an auxiliary film unit. After circuitry fabrication, the core board is grooved to create embedded slots. The groove size is based on the median of the actual embedded chip size plus 3mil on one side. A roughing and finishing process is used, employing a 1.6mm ET milling cutter with a milling cutter life of 8m and a finishing cutter life of 4m. CP compensation is 1.56 (approximately 0.025mm above the median). A CCD milling machine is used for grooving, with the grooving dimensional tolerance controlled within + / -2mil. The first piece with the grooved dimensional tolerance is controlled slightly above the median, with the L4 side facing upwards. The first piece milled with the grooved dimensional tolerance must be checked for whitening and flash in the first, middle, and last groove holes.

[0060] When laminating the first outer layer board onto the core board, embed the chips in the L3-L4 layers before lamination. Clean the chip embedding board thoroughly to remove PP dust. Before pre-stacking, apply a fixing film to the L3 side of the core board, ensuring the chip terminals face L4. The chips must be placed flat and level, without any misalignment, reversal, tilting, or omissions. Use a small press for production. During lamination, kraft paper should be added at the top, bottom, and middle. Silicone pads should be added outside the top and bottom kraft paper to ensure overall flatness and uniform heating. Remove the chip fixing film before oven curing. LDI exposure is required for the circuitry; only L3 layer circuitry is fabricated, while L5 layer circuitry is fabricated using an auxiliary film unit.

[0061] During the lamination of the second outer layer board onto the core board, blind vias were designed for L2L3 and L4L5, as well as for the embedded chip terminals. This facilitates direct interconnection between the chip and the next outer layer. Because the chip terminal diameter is 6 mil, direct laser etching could not guarantee the roundness of the blind vias. Therefore, a circuit fabrication method was used to etch away the copper at the blind via locations before laser etching. The diameter tolerance of the blind vias was controlled at 6 mil ± 0.5 mil, and the plating depression for filling the vias was controlled within 0.6 mil. After plating, the L2L5 layer circuitry was fabricated normally.

[0062] When the second multilayer board is laminated with the third outer layer board, the blind vias L1L2 and L6L5 are made in the same way as the L2L5 layer. The blind vias are made to be filled without voids and with a depression of less than 1mil. The copper of the through-holes is controlled to a minimum of 70μm with a minimum surface copper of 1.4mil. The surface treatment is tinning to facilitate the mounting of high-density, fine-pitch components.

[0063] This invention combines the embedded circuit board stacking method with device functions in a systematic way, thereby achieving high-density integration of electrical components and optimization of interlayer interconnection, which reduces the energy loss of power devices and improves the overall efficiency of the electric drive system.

[0064] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A method for embedding circuit board stacking, characterized in that, The method includes: S1, fabricate the core board and create embedded grooves in the core board shown; S2, Electrical components are embedded in the embedded groove, and a first outer layer plate is pressed onto the first surface of the core plate to form a first multilayer plate, and a first outer layer circuit is fabricated on the first multilayer plate. S3, A second outer layer plate is pressed onto the second surface of the core plate to form a second multilayer plate, a first blind hole is made in the first multilayer plate and the second multilayer plate, and a first connection line electrically connected to the electrical device is made in the first blind hole. S4, at least one third outer layer is laminated on the first and / or second surfaces of the second multilayer board to form a target PCB board, a second blind via is formed on the target PCB board, and a second connection line electrically connected to the first blind via is formed on the second blind via.

2. The embedded circuit board stacking method according to claim 1, characterized in that, In step S1, the core board is fabricated, specifically including: S11, the raw material board is split into core boards by a splitting equipment; S12, perform the first inner layer circuit processing on the first inner layer board of the core board to create the first inner layer circuit; S13, the core board is subjected to the first cutting and grinding process; S14, perform a second inner layer circuit processing on the core board to fabricate the second inner layer circuit; S15, perform inner layer AOI inspection on the first inner layer circuit and the second inner layer circuit, and transfer the core board that passes the inspection to the next process.

3. The embedded circuit board stacking method according to claim 2, characterized in that, In step S1, an embedded groove is formed in the core board, comprising: S16, The core board is first grooved along the first inner layer board using a roughing method. S17, A second groove is made along the position of the first groove using a precision milling method to create an embedded groove, and the single-sided dimension of the embedded groove is larger than the electrical component by a first preset value. S18, check whether the embedded groove is white or has burrs. If so, perform a third groove processing on the embedded groove; otherwise, transfer the core board to the next process.

4. The embedded circuit board stacking method according to claim 1, characterized in that, In step S2, electrical components are embedded in the embedding groove, and a first outer layer plate is pressed onto the first surface of the core board to form a first multilayer board. A first outer layer circuit is fabricated on the first multilayer board, specifically including: S21, the embedding groove of the core board is cleaned and pre-treated, a fixing film is attached to the second surface of the core board, and the electrical components are placed in the embedding groove along the first surface of the core board, wherein the connection terminals of the electrical components are arranged along the first surface of the chip. S22, after peeling off the fixing film on the second surface of the core board, the first outer layer board is pressed onto the first surface of the core board by a preset multi-segment pressing method to form a first multi-layer board, and the first multi-layer board is baked and fixed by a preset multi-segment baking method. S23, after the first multilayer board is subjected to a second cutting and grinding process, the first outer layer circuit is fabricated on the first outer layer board using an auxiliary film method to create the first outer layer circuit, and the first outer layer circuit is subjected to AOI detection processing.

5. The embedded circuit board stacking method according to claim 4, characterized in that, In step S22, the first outer layer plate is pressed onto the first surface of the core plate using a preset multi-segment pressing method, specifically including: S221, press the first outer layer plate and the core plate together for 8 minutes under a vacuum environment with a pressure value of 100 PSI; S222, press the first outer layer plate and the core plate together for 7 minutes under a vacuum environment with a pressure value of 200 PSI; S223, press the first outer layer plate and the core plate together for 3 minutes under vacuum with a pressure of 350 PSI. S224, the first outer layer plate and the core plate are pressed together in a vacuum environment for 2 hours and 23 minutes using a pressure value of 400 PSI. S225, press the first outer layer plate and the core plate together for 10 minutes in a vacuum environment using a pressure value of 300 PSI; S226, using a pressure of 100 PSI, the first outer layer plate and the core plate are pressed together for 5 minutes in a non-vacuum environment to produce the first multilayer board.

6. The embedded circuit board stacking method according to claim 4, characterized in that, In step S22, the first multilayer board is baked and fixed using a preset multi-segment baking method, specifically including: S227, the first multilayer board is pressed and baked for 5 minutes in a vacuum environment at a baking temperature of 160 degrees Celsius; S228, the first multilayer board is pressed and baked for 5 minutes in a vacuum environment at a baking temperature of 190 degrees Celsius; S229, the first multilayer board is baked at a baking temperature of 220 degrees Celsius in a vacuum environment for 1 hour; S230, the first multilayer board is pressed and baked in a vacuum environment at a baking temperature of 205 degrees Celsius for 10 minutes; S231, the first multi-layer board is baked at 165 degrees Celsius for 5 minutes in a non-vacuum environment.

7. The embedded circuit board stacking method according to claim 1, characterized in that, In step S3, a second outer layer is pressed onto the second surface of the core board to form a second multilayer board. A first blind hole is formed in the first multilayer board and the second multilayer board, and a first connection line electrically connected to the electrical device is formed in the first blind hole. Specifically, this includes: S31, a second outer layer is pressed onto the second surface of the core board to form a second multilayer board, and the second multilayer board is subjected to a third cutting and grinding process; S32, perform a second outer layer circuit fabrication on the first multilayer board and the second multilayer board to etch the copper layer at the first blind via location and perform AOI inspection processing; S33, laser drilling is performed on the first multilayer board and the second multilayer board to create the first blind hole, and plasma desmearing and AOI inspection are performed on the second multilayer board. S34, perform hole filling and board electrical treatment on the first blind hole to create a first copper plating layer on the first multilayer board, the second multilayer board and the first blind hole; S35, perform a third outer layer circuit fabrication on the first multilayer board and the second multilayer board to create the first connection line, and perform AOI detection processing on the first connection line.

8. The embedded circuit board stacking method according to claim 1, characterized in that, In step S4, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form a target PCB board. A second blind via is fabricated on the target PCB board, and a second connection line electrically connected to the first blind via is fabricated on the second blind via. Specifically, this includes: S41, at least one third outer layer is laminated onto the first and / or second surfaces of the second multilayer board to form the target PCB board, and the second multilayer board is subjected to a third cutting and grinding process. S42, a fourth outer layer circuit fabrication is performed on the third outer layer board to etch the copper layer at the second blind via location and perform AOI inspection. S43, the third outer layer board is laser drilled to create a second blind hole, and the target PCB board is subjected to plasma de-adhesive treatment and AOI inspection. S44, fill the second blind hole and perform board electrical treatment to create a second copper plating layer on the third outer layer board and the second blind hole; S45, perform the fifth outer layer circuit fabrication on the third multilayer board to create the second connection line, and perform AOI detection processing on the second connection line.

9. The embedded circuit board stacking method according to claim 1, characterized in that, Following step S4, the following is also included: S5, the target PCB board is sequentially subjected to solder resist treatment, text processing, forming treatment, testing treatment, FQC treatment, tin melting treatment and surface cleaning treatment.

10. An embedded circuit board stacking device, characterized in that, The apparatus is used to perform the embedded circuit board stacking method according to any one of claims 1-9.

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