A method and system for signal noise reduction processing of a high-speed acquisition card

Abstract

This invention discloses a signal noise reduction method and system for high-speed data acquisition cards, belonging to the field of signal processing and data acquisition technology. The invention comprises two parts: a hardware system and a processing method. The hardware system uses a metal partition to completely isolate the analog chamber from the digital chamber. A labyrinthine connection structure is formed through protrusions and grooves, steps and sealing barriers. A conductive gasket ensures continuous electrical connection between the cover plate and the metal partition. An absorbing material layer and a T-shaped thermal pad are also provided to achieve fully enclosed electromagnetic shielding and heat dissipation without ventilation holes. The processing method, based on hardware isolation, sequentially performs three levels of processing on residual noise: adaptive filtering, variational mode decomposition, and lightweight deep learning residual learning. The hardware and algorithm work together to improve the signal-to-noise ratio by 30-40 dB, with a single-frame processing time of less than 2.5 ms. This invention addresses both electromagnetic shielding and heat dissipation requirements, significantly improving the signal acquisition quality of high-speed data acquisition cards through deep synergy between structure and algorithm.

Description

Technical Field

[0001] This invention relates to the field of information and communication equipment technology, and in particular to a signal noise reduction processing method and system for a high-speed acquisition card. Background Technology

[0002] The core function of a high-speed data acquisition card is to condition and convert external analog signals into digital signals for processing by a host computer. It is widely used in industrial testing, instrumentation, communication systems, and scientific experiments. The acquisition card typically contains both analog front-end circuitry and digital processing circuitry. The former is responsible for amplifying and filtering weak signals, while the latter handles high-speed analog-to-digital conversion and digital signal processing. Due to its wide operating bandwidth and small signal amplitude, the analog front-end is highly susceptible to external electromagnetic interference and high-frequency switching noise from the internal digital circuitry, leading to a reduced signal-to-noise ratio and, in severe cases, even obscuring the valid signal.

[0003] To suppress the aforementioned interference, existing data acquisition cards typically use metal casings for shielding. However, conventional casings are mostly single-cavity structures, with analog and digital circuits sharing the same space. High-frequency noise generated by the digital circuits can still be directly coupled to the analog front end through spatial radiation, resulting in limited shielding effectiveness. Furthermore, the joint between the casing cover and the housing is often a planar butt joint, with straight gaps at the seams. High-frequency electromagnetic waves can easily leak or intrude through these gaps, causing the overall shielding effectiveness to decrease significantly with increasing frequency. Some products also have ventilation holes in the casing to meet heat dissipation requirements; these holes further become channels for electromagnetic leakage. Moreover, the casing lacks effective absorption of reflected electromagnetic waves, and the cavity resonance effect exacerbates interference in specific frequency bands, affecting acquisition accuracy.

[0004] In signal processing noise reduction, existing methods based on digital filters for data acquisition cards are ineffective against noise overlapping with the signal spectrum, and the filtering process introduces phase delay. Meanwhile, wavelet transform-based noise reduction methods suffer from high algorithm complexity, making them difficult to meet real-time requirements. More importantly, existing signal processing noise reduction methods typically treat the data acquisition card as a "black box," failing to consider the contribution of the card's internal circuit layout and electromagnetic shielding structure to noise suppression, thus limiting the effectiveness of the algorithms when facing strong electromagnetic interference.

[0005] Therefore, it is necessary to provide a signal noise reduction method and system that can effectively isolate analog and digital circuits at the structural level, while combining adaptive signal processing algorithms to finely suppress residual noise. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to overcome the defects of existing high-speed acquisition cards in that the electromagnetic shielding structure and signal processing algorithm are independent and lack coordination, and to provide a signal noise reduction processing method and system that deeply couples the hardware structure and signal processing algorithm and simplifies each other.

[0007] To address the aforementioned technical problems, this invention provides a signal noise reduction processing system and method for high-speed data acquisition cards.

[0008] Hardware System The hardware structure remains unchanged from the original description, with slight modifications to reflect "spatial isolation" rather than "complete isolation". Signal noise reduction processing methods Based on the physical isolation and shielding of electromagnetic interference by the hardware system, the following steps are executed by an FPGA built into the digital chamber using a multi-stage pipelined parallel processing architecture.

[0009] Deep collaborative working mechanism between hardware and algorithms The core innovation of this invention lies in the following deep coupling and mutual simplification relationship between the hardware structure and the algorithm steps: Hardware's role in pruning and simplifying algorithms In traditional single-cavity structures, high-frequency switching noise (bandwidth 100MHz-1GHz) generated by digital circuits is directly coupled to the analog cavity through spatial radiation, forcing algorithms to employ complex filtering or multi-level decomposition to suppress interference in this frequency band. In this invention, the metal partition and conductive pad form a continuous shielding layer, achieving a measured suppression capability of over 35dB for digital noise in the 100MHz-1GHz band. Therefore, in the adaptive filtering step two, the algorithm can directly omit the filtering strategy for this high-frequency digital noise, eliminating the need for band search and notch filtering.

[0010] Meanwhile, the labyrinthine sealing structure, composed of protrusions, grooves, and absorbing material layers, reduces the coupling strength of external radio frequency interference (800MHz-6GHz) by more than 20dB. This allows the noise type identification in step one to use a lower energy threshold (e.g., from 0.1V² / Hz to 0.02V² / Hz), avoiding false triggering of filtering strategies due to environmental noise fluctuations.

[0011] Hardware improvements to algorithm real-time performance Since high-frequency and high-intensity interference has been significantly attenuated at the hardware level, the VMD decomposition in step three no longer requires excessively fine decomposition to separate weak signals from strong noise. The number of decomposition layers K can be reduced from the conventional 8-12 layers to 5-7 layers. Actual measurements show that for every two layers reduction in K, the VMD computation time is reduced by approximately 30%. When the overall algorithm is implemented on an FPGA, the processing time per frame (1024 points) can be reduced from over 4ms to less than 1.8ms, meeting the real-time processing requirements at a sampling rate of 2.5GSPS.

[0012] Algorithm feedback to hardware and closed-loop optimization The noise type and its dominant frequency band identified in Step 1 can be fed back to the hardware monitoring unit in real time. For example, when the algorithm continuously detects strong 600kHz-800kHz power frequency interference, it can determine that the external grounding is faulty or the shielding layer is aging, and the system will issue an alarm. Alternatively, the center frequency of the pre-filter in the analog cavity can be finely adjusted by a digital potentiometer to achieve algorithm-guided hardware adaptive adjustment.

[0013] Compared with the prior art, the present invention has at least the following beneficial effects: This invention employs deep coupling between hardware and algorithms, achieving a final output signal-to-noise ratio of 39.8dB under a 10dB input signal-to-noise ratio, with a total improvement of 29.8dB, which is superior to the combined improvement of 13.5dB from hardware alone and 18.1dB from the algorithm alone.

[0014] After pruning the algorithm using hardware, the number of VMD decomposition layers was reduced, the single-frame processing latency decreased from 3.2ms to 1.8ms, and the real-time performance was improved by 44%.

[0015] Using T-shaped thermal pads in conjunction with heat dissipation fins, a fully enclosed shield without ventilation holes is achieved, eliminating electromagnetic leakage and ensuring the stability of algorithm processing. Attached Figure Description

[0016] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to implement and use the present disclosure.

[0017] Figure 1 This is a schematic diagram of the overall structure of the present invention; Figure 2 This is a schematic diagram of the cover plate structure of the present invention; Figure 3 This is a schematic diagram of the conductive pad structure of the present invention; Figure 4 This is a schematic diagram of the thermal pad structure of the present invention.

[0018] [Figure Labels] 1-Enclosure; 2-Cover plate; 3-Metal partition; 4-Circuit board; 5-Wave absorption material layer; 6-Heat dissipation fins; 7-Signal input interface; 8-Conductive pad; 9-Thermal conductive pad; 101-Step; 102-Ribbon; 103-Analog chamber; 104-Digital chamber; 201-Groove; 202-Sealed enclosure; 801-Card slot.

[0019] As shown in the figure, specific structures and devices are labeled in the figure to clearly illustrate the structure of the embodiments of the present invention. However, this is only for illustrative purposes and is not intended to limit the present invention to the specific structure, device and environment. Those skilled in the art can adjust or modify these devices and environments according to specific needs, and such adjustments or modifications are still included in the scope of the appended claims. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Example 1:

[0022] Keep the original hardware description, change "complete isolation" to "isolation of the main parts of space and electromagnetic field", and specify the feedthrough capacitor as a filter feedthrough element. Example 2:

[0023] This embodiment demonstrates the synergistic effect of the hardware system and the noise reduction algorithm. The following control experiment is set up: Test conditions: The effective signal is a 10MHz sine wave superimposed with a 1MHz square wave. Added noise: 200MHz high-frequency noise (SNR = -5dB) simulating digital crosstalk, 50Hz-500Hz low-frequency noise (SNR = 10dB) simulating power frequency harmonics, and Gaussian white noise; overall input signal-to-noise ratio 10dB. Evaluation method: Output SNR and processing delay were measured using a spectrum analyzer and FPGA processing platform.

[0024] Results analysis: Signal-to-noise ratio improvement: Group D improved by 29.8dB compared to Group A, far exceeding the sum of the improvements of Groups B and C (31.6dB, non-linear superposition), demonstrating the synergistic effect of hardware and algorithm.

[0025] Real-time performance improvement: The processing latency of group D was 1.8ms, a 44% reduction compared to group C's 3.2ms. This is because after hardware shielding, the algorithm omitted the high-frequency interference filtering step, and the number of VMD decomposition layers was reduced from 10 to 6, resulting in a significant decrease in computational load.

[0026] The relationship between processing latency and frame shift: With a sampling rate of 2.5 GSPS, a subframe length of 1024 points, and a frame shift of 512 points, the frame shift time is approximately 204.8 ns, which is much smaller than the processing latency of 1.8 ms. This system utilizes an FPGA pipeline architecture to buffer large frame (8192 points) data and process it in a time-division multiplexing manner. A four-stage pipelined parallel computation is implemented in DSP Builder, ensuring continuous, uninterrupted data output, and achieving the actual throughput requirement of 2.5 GSPS in real-time processing. Example 3:

[0027] Step one, "identifying the main noise type of the current signal," is implemented through the following logic: Impulse noise detection: Calculate the ratio of signal peak-to-peak value to variance, P = x_pp / σ². If P > 15, impulse noise is determined to be present.

[0028] Power frequency interference detection: Perform peak search on the signal spectrum. If a spectral peak with an energy greater than 10dB above the average spectral energy appears at 50Hz / 60Hz and its harmonics (±1Hz), power frequency interference is determined to exist.

[0029] Clock jitter noise detection: Calculate the energy Ed2 of the second derivative of the signal. If Ed2 > 0.05 × E_base (baseband energy), clock jitter noise is determined to exist.

[0030] White noise detection: If none of the above criteria are met, and the power spectral density is flat and the autocorrelation function decays to less than 0.1 when τ>0, it is determined to be white noise. Example 4:

[0031] Variational mode decomposition was employed, and the K value was determined through center frequency observation: K was initialized to 3, and gradually increased until redundancy appeared at the center frequency of a certain component (frequency difference less than a preset threshold), with the final K value set to 6. The correlation coefficient ρ_i and energy entropy E_i of each IMF component were calculated, and the comprehensive evaluation index S_i = w1·ρ_i + w2·(1 - E_i / E_max), where w1=0.6 and w2=0.4. Components with S_i ≥ 0.7 were completely retained, components with S_i < 0.3 were discarded, and the remaining components were processed using a soft thresholding function. Example 5:

[0032] The FPGA employs a four-stage pipeline architecture: the first stage is FIFO buffering and frame capture, the second stage is adaptive filtering, the third stage is VMD decomposition, and the fourth stage is CNN inference. Each stage is connected via an AXI-Stream interface, with data flowing between processing stages at a granularity of 1024 points. Through time-division multiplexing and parallel computing, the single-subframe processing latency is stabilized at 1.8ms ± 0.1ms, meeting real-time requirements.

[0033] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0034] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A signal noise reduction processing method and system for a high-speed data acquisition card, characterized in that, It includes a housing (1) and a cover plate (2) that is removably fitted onto the housing (1); The box (1) is provided with at least one metal partition (3), which divides the internal space of the box (1) into at least two independent chambers; The box (1) has a step (101) on the open end face, and a raised ridge (102) is provided around the upper part of the outer periphery of the step (101). The mating surface of the cover plate (2) is provided with a groove (201) that matches the shape of the protrusion (102) at the corresponding position. The mating surface of the cover plate (2) is integrally formed with a sealing barrier (202) that matches the shape of the step (101). The cover plate (2) is provided with a conductive pad (8) on the inner side of the sealing enclosure (202). The conductive pad (8) is long and narrow, and the inner side of the conductive pad (8) is provided with a "concave" shaped groove (801). When the cover plate (2) is closed on the box (1), the conductive pad (8) is locked on the outer end of the metal partition (3) through the groove (801). The cover plate (2) is provided with several sets of thermally conductive pads (9) on the side of the conductive pad (8). The inner wall of the box (1) and / or the inner wall of the cover plate (2) is provided with a wave-absorbing material layer (5); Furthermore, based on the physical isolation and shielding of electromagnetic interference by the hardware system, the acquired signal is processed by a field-programmable gate array (FPGA) built into the enclosure (1) using a multi-stage pipelined parallel processing architecture, as follows: Step 1: Acquire the original digital signal sequence and extract and identify the main noise type of the current signal through time domain features, frequency domain features, and statistical features; Step 2: Based on the noise type identified in Step 1, adaptively select the corresponding filtering strategy to perform noise reduction processing on the original signal; Step 3: Perform variational mode decomposition on the primary denoising signal obtained in Step 2, classify, filter and reconstruct the intrinsic mode function components to obtain the secondary denoising signal; Step 4: The residual between the secondary denoised signal and the original signal is used to predict the residual noise component through a lightweight one-dimensional convolutional neural network, and then subtracted from the secondary denoised signal to obtain the final denoised signal.

2. The signal noise reduction processing system for the high-speed acquisition card according to claim 1, characterized in that: The at least two chambers include an analog chamber (103) for accommodating analog front-end circuitry and a digital chamber (104) for accommodating digital processing circuitry. The analog chamber (103) and the digital chamber (104) are spatially and electromagnetically isolated by a metal partition (3). The circuit boards in the two chambers are electrically connected by filter feedthrough elements installed in through holes in the metal partition.

3. The signal noise reduction processing system for the high-speed acquisition card according to claim 1, characterized in that: The protruding ridge (102) is embedded in the groove (201), and the sealing barrier (202) is embedded in the step (101), together forming multiple tortuous sealing paths; the wave-absorbing material layer (5) is a wave-absorbing coating used to absorb reflected electromagnetic waves in the cavity.

4. The signal noise reduction processing system for the high-speed acquisition card according to claim 1, characterized in that: The thermal pad (9) is a T-shaped strip, with its vertical part connected to the cover plate (2) and its horizontal part used to contact the heat-generating device on the internal circuit board (4); the outer surface of the box (1) is provided with multiple heat dissipation fins (6) to form a fully enclosed heat dissipation structure without ventilation holes.

5. The signal noise reduction processing system for the high-speed acquisition card according to claim 1, characterized in that: The contact surface inside the slot (801) of the conductive pad (8) is a gradually expanding slope; when the cover plate (2) is pressed, the conductive pad (8) is tightly fitted with the metal partition (3), and a continuous and reliable electrical connection is established between the metal partition (3) and the cover plate (2).

6. A method for noise reduction processing of high-speed acquisition card signals based on the system described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step 1: Signal preprocessing and noise feature extraction - Acquire the original digital signal sequence x(n), perform frame processing on the signal, calculate the time domain features, frequency domain features and statistical features of each frame, and identify the main noise type of the current signal based on the preset judgment logic; Step 2: Adaptive Filtering – Based on the identified noise type, adaptively select the corresponding filtering strategy or combination of filtering strategies to perform a noise reduction process, and obtain a noise-reduced signal x1(n). Step 3: Variational Mode Decomposition and Fine Denoising – Perform variational mode decomposition on x1(n) to obtain K intrinsic mode function components. Calculate the comprehensive evaluation index of each component. Based on the index value, classify the components into three categories: signal-dominant components, mixed components, and noise-dominant components. Perform complete retention, soft threshold correction, or direct removal on each category. Reconstruct the processed components to obtain the secondary denoised signal x2(n). Step 4: Residual noise prediction based on deep learning - Calculate the residual signal r(n) = x(n) - x2(n), take x2(n) as input, predict the residual noise component n̂(n) through a lightweight one-dimensional convolutional neural network, so that n̂(n) approximates r(n), and then subtract the predicted noise from the secondary denoised signal to obtain the final denoised signal y(n) = x2(n) - λ·n̂(n); Step 5: Signal Reconstruction and Output – The final denoised signals are superimposed and added together to restore the continuous signal output.

7. The signal noise reduction processing method for a high-speed acquisition card according to claim 6, characterized in that, The identification of the main noise type of the current signal in step one is specifically achieved through the following sub-steps: Impulse noise detection: Calculate the ratio of peak-to-peak value to variance of the signal. If it exceeds a preset threshold, it is determined that impulse noise exists. Power frequency interference detection: Peak search is performed on the signal spectrum. If a spectral peak with significantly higher energy than the average spectrum appears at 50Hz / 60Hz and its harmonics, power frequency interference is determined to exist. Clock jitter noise detection: Calculate the higher-order derivative energy of the signal. If the energy exceeds a preset proportion of the baseband energy of the signal, clock jitter noise is determined to exist. White noise detection: If none of the above tests are successful, and the signal power spectral density is flat and the autocorrelation function decays rapidly, then the noise type is determined to be mainly white noise.

8. The signal noise reduction processing method for a high-speed acquisition card according to claim 6, characterized in that: In step three, the number of decomposition layers K of the variational mode decomposition is adaptively determined using the center frequency observation method; the comprehensive evaluation index considers both the correlation coefficient and energy entropy; the total number of parameters in the lightweight one-dimensional convolutional neural network does not exceed 5 × 10⁻⁶. 4 It is deployed within an FPGA to enable real-time inference.

9. The signal noise reduction processing method for a high-speed acquisition card according to claim 6, characterized in that: The relaxation factor λ in step four has a value range of 0.5 ≤ λ ≤ 0.9, which is used to prevent noise overestimation.

10. The signal noise reduction processing method for a high-speed acquisition card according to claim 6, characterized in that: The method is implemented using a pipelined parallel processing architecture on an FPGA. The acquired signal is stored in a FIFO buffer at a sampling rate of 2.5 GSPS to form a large frame of data. Subframes are extracted and analyzed from the data for processing. The processing delay is greater than the frame shift time. The pipeline enables continuous and uninterrupted data processing.

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