A method for forming a semiconductor structure and the semiconductor structure thereof

Abstract

This disclosure relates to the semiconductor field, providing a method for manufacturing a semiconductor structure and the semiconductor structure thereof, comprising at least: providing a substrate and forming a stacked structure on the substrate; etching the stacked structure to form a first capacitor hole; sequentially forming a first initial electrode layer, a second electrode layer, and a third electrode layer in the first capacitor hole, wherein the second electrode layer has greater oxidation resistance than the first initial electrode layer and the third electrode layer; removing a portion of the stacked structure and a portion of the first initial electrode layer to form a second capacitor hole, wherein the remaining first initial electrode layer serves as the first electrode layer; the first electrode layer, the second electrode layer, and the third electrode layer constitute a lower electrode; and forming a dielectric layer and an upper electrode in the second capacitor hole, wherein the dielectric layer covers the lower electrode and the upper electrode fills the second capacitor hole.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a method for forming a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] As DRAM technology advances and chip sizes continue to shrink, the radius of capacitors needs to be gradually reduced. However, how to reduce the radius of capacitors, and how to solve the capacitor bending and tilting phenomenon that occurs during the process of reducing the capacitor radius, are urgent technical problems that need to be solved in the semiconductor field. Summary of the Invention

[0003] This disclosure provides a method for forming a semiconductor structure and the semiconductor structure thereof, which at least helps to solve the problem of capacitor bending and tilting that occurs during the process of reducing the radius of the capacitor.

[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, including:

[0005] Provide a substrate, and form a laminated structure on the substrate;

[0006] Etch the stacked structure to form the first capacitor hole;

[0007] A first initial electrode layer, a second electrode layer, and a third electrode layer are sequentially formed in the first capacitor hole. The oxidation resistance of the second electrode layer is greater than that of the first initial electrode layer and the third electrode layer.

[0008] Part of the stacked structure and part of the first initial electrode layer are removed to form a second capacitor hole, and the remaining first initial electrode layer serves as the first electrode layer; the first electrode layer, the second electrode layer, and the third electrode layer constitute the lower electrode.

[0009] A dielectric layer and an upper electrode are formed in the second capacitor hole, the dielectric layer covers the lower electrode, and the upper electrode fills the second capacitor hole.

[0010] In some embodiments, the resistivity of the first electrode layer and the third electrode layer is less than that of the second electrode layer; the elastic modulus of the second electrode layer is greater than that of the first electrode layer and the third electrode layer.

[0011] In some embodiments, a first initial electrode layer covers a first capacitor hole, a second electrode layer covers the first initial electrode layer, and a third electrode layer fills the remaining first capacitor hole.

[0012] In some embodiments, the substrate further includes an isolation layer, the landing pad is located within the isolation layer, and the landing pad is electrically connected to the lower electrode.

[0013] In some embodiments, the first electrode layer and the third electrode layer may be titanium nitride, and the second electrode layer may be titanium silicon nitride.

[0014] In some embodiments, the stacked structure includes, from bottom to top, at least: a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer, wherein the intermediate support layer is located between the first sacrificial layer and the second sacrificial layer, and the bottom support layer, the intermediate support layer, and the top support layer together constitute a support layer.

[0015] In some embodiments, removing a portion of the stacked structure and a portion of the first initial electrode layer to form a second capacitor via, with the remaining first initial electrode layer serving as the first electrode layer, includes at least: removing a portion of the top support layer to form an initial top opening, the initial top opening exposing a portion of the side surface of the first initial electrode layer and a portion of the top surface of the second sacrificial layer; removing the exposed first initial electrode layer through the initial top opening to form a top opening; removing at least the first and second sacrificial layers through the top opening, and removing the first initial electrode layer corresponding to the first and second sacrificial layers, with the remaining first initial electrode layer serving as the first electrode layer; the first electrode layer is located at least between the support layer and the second electrode layer.

[0016] In some embodiments, the first electrode layer includes a top first electrode layer, a middle first electrode layer, and a bottom first electrode layer; the top first electrode layer corresponds to the top support layer and is located only between the top support layer and the second electrode layer; the middle first electrode layer corresponds to the middle support layer and is located only between the middle support layer and the second electrode layer; the bottom first electrode layer corresponds to the bottom support layer and is located between the bottom support layer and the second electrode layer and at the bottom of the first capacitor hole.

[0017] Another aspect of this disclosure provides a semiconductor structure, including:

[0018] A substrate having a stacked structure, the stacked structure having a first capacitor hole;

[0019] The lower electrode is located in the first capacitor hole. The lower electrode includes at least a first electrode layer, a second electrode layer and a third electrode layer. The oxidation resistance of the second electrode layer is greater than that of the first electrode layer and the third electrode layer.

[0020] The second capacitor hole is formed by removing at least a portion of the stacked structure;

[0021] The dielectric layer and the upper electrode are located in the second capacitor hole, the dielectric layer covers the lower electrode, and the upper electrode fills the second capacitor hole.

[0022] In some embodiments, the resistivity of the first electrode layer and the third electrode layer is less than that of the second electrode layer; the elastic modulus of the second electrode layer is greater than that of the first electrode layer and the third electrode layer.

[0023] In some embodiments, the substrate has an isolation layer, the landing pad is located within the isolation layer, and the landing pad is electrically connected to the lower electrode.

[0024] In some embodiments, the first electrode layer and the third electrode layer may be titanium nitride, and the second electrode layer may be titanium silicon nitride.

[0025] In some embodiments, the stacked structure includes, from bottom to top, at least: a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer, wherein the intermediate support layer is located between the first sacrificial layer and the second sacrificial layer, and the bottom support layer, the intermediate support layer, and the top support layer together constitute a support layer.

[0026] In some embodiments, the first electrode layer is located at least between the support layer and the second electrode layer.

[0027] In some embodiments, the first electrode layer includes a top first electrode layer, a middle first electrode layer, and a bottom first electrode layer; the top first electrode layer corresponds to the top support layer and is located only between the top support layer and the second electrode layer; the middle first electrode layer corresponds to the middle support layer and is located only between the middle support layer and the second electrode layer; the bottom first electrode layer corresponds to the bottom support layer and is located between the bottom support layer and the second electrode layer and at the bottom of the first capacitor hole.

[0028] The technical solution provided in this disclosure sequentially forms a first initial electrode layer, a second electrode layer, and a third electrode layer in a first capacitor hole, removes a portion of the first initial electrode layer to form the first electrode layer, and the second electrode layer has greater oxidation resistance than the first and third electrode layers. Because a portion of the first initial electrode layer is removed to form the first electrode layer, the radius of the lower electrode of the capacitor becomes smaller, and the second electrode layer has greater oxidation resistance than the first and third electrode layers. This prevents deformation and bending caused by oxidation of the lower electrode during subsequent deposition of the dielectric layer, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0029] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1This is a flowchart of a semiconductor structure fabrication method;

[0031] Figures 2A to 2M This is a process flow diagram of a semiconductor structure fabrication method provided in an embodiment of the present disclosure; wherein Figure 2A To form a schematic diagram of the stacked structure, Figure 2B A schematic diagram for forming the first capacitor hole. Figure 2C A schematic diagram for forming the first initial electrode layer. Figure 2D A schematic diagram for forming the second electrode layer. Figure 2E A schematic diagram of the formation of the third electrode layer. Figure 2F A schematic diagram showing the removal of the first initial electrode layer, the second electrode layer, and the third electrode layer above the top support layer. Figure 2G To form an initial top opening diagram, Figure 2H A schematic diagram showing the formation of the top opening and the first sacrificial opening. Figure 2I To illustrate the formation of the central opening. Figure 2J A schematic diagram for forming the second capacitor hole. Figure 2K To form a schematic diagram of the dielectric layer, Figure 2L A schematic diagram of the formation of the first upper electrode layer. Figure 2M A schematic diagram for forming the second upper electrode layer.

[0032] Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0033] Figure 4 for Figure 3 Enlarged view of point A in the middle;

[0034] Figure 5 for Figure 3 Enlarged view of point B in the middle;

[0035] Figure 6 for Figure 3 Enlarged diagram of point C in the middle. Detailed Implementation

[0036] As the background technology shows, with the advancement of DRAM technology nodes, chip sizes are continuously shrinking, requiring a gradual reduction in the radius of capacitors. However, how to reduce the radius of capacitors, and how to solve the capacitor bending and tilting phenomenon that occurs during the process of reducing the capacitor radius, are urgent technical problems that need to be solved in the semiconductor field.

[0037] This disclosure provides a method for forming a semiconductor structure and a semiconductor structure. By sequentially forming a first initial electrode layer, a second electrode layer, and a third electrode layer in a first capacitor hole, and removing a portion of the first initial electrode layer to form a first electrode layer, the oxidation resistance of the second electrode layer is greater than that of the first and third electrode layers. Since the removal of a portion of the first initial electrode layer to form the first electrode layer reduces the radius of the lower electrode of the capacitor, and the oxidation resistance of the second electrode layer is greater than that of the first and third electrode layers, deformation and bending phenomena caused by oxidation of the lower electrode are prevented during subsequent deposition of the dielectric layer, thereby improving the performance of the semiconductor structure.

[0038] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0039] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0040] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0041] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0042] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0043] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0044] Figure 1 This is a flowchart of a semiconductor structure fabrication method. Figures 2A to 2M This is a process flow diagram of a semiconductor structure fabrication method provided in an embodiment of the present disclosure; wherein Figure 2A To form a schematic diagram of the stacked structure, Figure 2B A schematic diagram for forming the first capacitor hole. Figure 2C A schematic diagram for forming the first initial electrode layer. Figure 2D A schematic diagram for forming the second electrode layer. Figure 2E A schematic diagram of the formation of the third electrode layer. Figure 2F A schematic diagram showing the removal of the first initial electrode layer, the second electrode layer, and the third electrode layer above the top support layer. Figure 2G To form an initial top opening diagram, Figure 2H A schematic diagram showing the formation of the top opening and the first sacrificial opening. Figure 2I To illustrate the formation of the central opening. Figure 2J A schematic diagram for forming the second capacitor hole. Figure 2K To form a schematic diagram of the dielectric layer, Figure 2L A schematic diagram of the formation of the first upper electrode layer. Figure 2M A schematic diagram for forming the second upper electrode layer. Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 4 for Figure 3 Enlarged diagram of point A in the middle. Figure 5 for Figure 3 Enlarged diagram at point B in the middle. Figure 6 for Figure 3 Enlarged diagram of point C in the middle.

[0045] like Figure 1 As shown, the preparation method includes at least the following steps: S10 providing a substrate and forming a stacked structure on the substrate; S20 etching the stacked structure to form a first capacitor hole; S30 sequentially forming a first initial electrode layer, a second electrode layer, and a third electrode layer in the first capacitor hole, wherein the oxidation resistance of the second electrode layer is greater than that of the first initial electrode layer and the third electrode layer; S40 removing part of the stacked structure and part of the first initial electrode layer to form a second capacitor hole, wherein the remaining first initial electrode layer serves as the first electrode layer; the first electrode layer, the second electrode layer, and the third electrode layer constitute the lower electrode; S50 forming a dielectric layer and an upper electrode in the second capacitor hole, wherein the dielectric layer covers the lower electrode, and the upper electrode fills the second capacitor hole.

[0046] The semiconductor structure formation method proposed in this application will be described in detail below with reference to the accompanying drawings.

[0047] Please see Figure 1 and Figure 2AA substrate 10 is provided, and a stacked structure 20 is formed on the substrate 10. The substrate 10 includes a substrate 101 and an isolation layer 102 located on the substrate 101. The isolation layer 102 has landing pads 103 spaced apart within it. The stacked structure 20 includes, from bottom to top, at least: a bottom support layer 2011, a first sacrificial layer 2021, an intermediate support layer 2012, a second sacrificial layer 2022, and a top support layer 2013. The intermediate support layer 2012 is located between the first sacrificial layer 2021 and the second sacrificial layer 2022. The bottom support layer 2011, the intermediate support layer 2012, and the top support layer 2013 together constitute the support layer 201. Specifically, the material of the substrate 101 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the material of the substrate 101 is silicon. The material of the isolation layer 102 can be one or more of silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), and oxynitride materials (e.g., silicon oxynitride). The material of the landing pad 103 can be a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, or a metal-containing material (e.g., metal nitride, metal silicide, metal carbide, metal oxide), etc. In this embodiment, the landing pad 103 can be tungsten, and the capacitor structure is connected to the transistor in the substrate through the landing pad. The material of the support layer 201 can be one or more of nitride materials (e.g., silicon nitride (Si3N4)), oxynitride materials (e.g., silicon oxynitride), carbon nitride materials (e.g., silicon carbon nitride (SiCN)), or carbon oxynitride materials (e.g., silicon oxynitride (SiOCN)). The materials of the first sacrificial layer 2021 and the second sacrificial layer 2022 can be one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), and fluorosilicate glass. It should be noted that the doping concentrations of the first sacrificial layer 2021 and the second sacrificial layer 2022 can be different. For example, if both the first sacrificial layer 2021 and the second sacrificial layer 2022 are borophosphosilicate glass (BPSG), the doping concentration of boron and phosphorus in the first sacrificial layer 2021 can be greater than that in the second sacrificial layer 2022. This is because the first sacrificial layer 2021 is located lower, and the higher the doping concentration of the first sacrificial layer 2021, the easier it is to remove it in the subsequent removal process, thereby simplifying the manufacturing process.

[0048] Please refer to the following: Figure 1 and Figure 2B The stacked structure 20 is etched to form the first capacitor hole 401. Dry etching can be used to form the first capacitor hole 401.

[0049] Please refer to the following: Figure 1 and Figure 2C-2E A first initial electrode layer 501', a second electrode layer 502, and a third electrode layer 503 are sequentially formed in the first capacitor hole 401. The first initial electrode layer 501' covers the sidewalls and bottom of the first capacitor hole 401, the second electrode layer 502 covers the first initial electrode layer 501', and the third electrode layer 503 fills the remaining portion of the first capacitor hole 401. The oxidation resistance of the second electrode layer 502 is greater than that of the first initial electrode layer 501' and the third electrode layer 503.

[0050] Then as Figure 2F As shown, the first initial electrode layer 501', the second electrode layer 502 and the third electrode layer 503 above the top support layer 2013 are removed, so that the top surface of the top support layer 2013 is exposed.

[0051] Please refer to the following: Figure 1 and Figure 2G-2J A portion of the stacked structure 20 and a portion of the first initial electrode layer 501' are removed to form the second capacitor hole 60, and the remaining first initial electrode layer 501' serves as the first electrode layer 501; the first electrode layer 501, the second electrode layer 502, and the third electrode layer 503 constitute the lower electrode 50.

[0052] Specific examples Figure 2G As shown, a portion of the top support layer 2013 is removed to form an initial top opening 6011', which exposes a portion of the side surface of the first initial electrode layer 501' and a portion of the top surface of the second sacrificial layer 2022; specifically as follows... Figure 2G As shown, in the direction parallel to the base 10, the initial top openings 6011' can be spaced apart, that is, there is a top support layer 2013 between every two initial top openings 6011'.

[0053] Then as Figure 2H As shown, the exposed first initial electrode layer 501' is removed through the initial top opening 6011' to form the top opening 6011, and the second sacrificial layer 2022 and the first initial electrode layer 501' corresponding to the second sacrificial layer 2022 are removed through the top opening 6011 to form the first sacrificial opening 6021; that is, as Figure 2H As shown, the second sacrificial layer 2022 and the first initial electrode layer 501' corresponding to the second sacrificial layer 2022 are completely removed. Specifically, a mixture of ammonia, hydrogen peroxide and water can be used to remove the first initial electrode layer 501'.

[0054] Then as Figure 2IAs shown, a portion of the intermediate support layer 2012 and the first initial electrode layer 501' corresponding to the intermediate support layer 2012 are further removed through the first sacrificial opening 6021 to form the intermediate opening 6012; the projection of the intermediate opening 6012 on the substrate 10 overlaps with the projection of the top opening 6011 on the substrate 10, and the intermediate openings 6012 are spaced apart, that is, there is an intermediate support layer 2012 between every two intermediate openings 6012.

[0055] Then as Figure 2J As shown, the etching continues to remove the first sacrificial layer 2021 and the first initial electrode layer 501' corresponding to the first sacrificial layer 2021 to form the second sacrificial opening 6022. The remaining first initial electrode layer 501' serves as the first electrode layer 501. The first electrode layer 501 is located at least between the support layer 201 and the second electrode layer 502, i.e., as shown. Figure 2J As shown, the first sacrificial layer 2021 and the first initial electrode layer 501' corresponding to the first sacrificial layer 2021 are completely removed; the top opening 6011, the first sacrificial opening 6021, the middle opening 6012, and the second sacrificial opening 6022 together constitute the second capacitor hole 60. Further as... Figure 2J As shown, the first electrode layer 501 includes a top first electrode layer 5011, a middle first electrode layer 5012, and a bottom first electrode layer 5013; the top first electrode layer 5011 corresponds to the top support layer 2013, and the top first electrode layer 5011 is located only between the top support layer 2013 and the second electrode layer 502; the middle first electrode layer 5012 corresponds to the middle support layer 2012, and the middle first electrode layer 5012 is located only between the middle support layer 2012 and the second electrode layer 502; the bottom first electrode layer 5013 corresponds to the bottom support layer 2011, and the bottom first electrode layer 5013 is located between the bottom support layer 2011 and the second electrode layer 502 and is located at the bottom of the first capacitor hole 401. Between adjacent second capacitor holes 60, there are a top support layer 2013, a middle support layer 2012 and a bottom support layer 2011. The remaining bottom support layer 2011, middle support layer 2012 and top support layer 2013, as well as the first electrode layer 501, the second electrode layer 502 and the third electrode layer 503, together provide support for the capacitor.

[0056] The first electrode layer 501, the second electrode layer 502, and the third electrode layer 503 together constitute the lower electrode 50. The landing pad 103 is electrically connected to the lower electrode 50. The first electrode layer 501 and the third electrode layer 503 can be titanium nitride, and the second electrode layer 502 can be titanium silicon nitride. The oxidation resistance of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503; the resistivity of the first electrode layer 501 and the third electrode layer 503 is less than that of the second electrode layer 502; and the elastic modulus of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503. In this embodiment, a first initial electrode layer 501', a second electrode layer 502, and a third electrode layer 503 are sequentially formed in the first capacitor hole 401. A portion of the first initial electrode layer 501' is removed to form the first electrode layer 501. Because a portion of the first initial electrode layer 501' is removed to form the first electrode layer 501, the radius of the lower electrode 50 of the capacitor becomes smaller, further enabling the miniaturization of the semiconductor structure. It should be noted that because a portion of the first initial electrode layer 501' is removed, the radius of the lower electrode 50 in the removed portion becomes smaller. That is, the radius of the lower electrode 50 varies in different cross-sections of the capacitor structure. The portion of the first initial electrode layer 501' corresponding to the support layer 201 is not removed, so the radius of the lower electrode 50 does not change. However, the portion of the first initial electrode layer 501' not corresponding to the support layer 201 is removed, so the radius of the lower electrode 50 becomes smaller, enabling the miniaturization of the capacitor. Moreover, the space left by removing the first initial electrode layer 501' provides more reserved space for the subsequent deposition of the dielectric layer 701. Furthermore, improving capacitor bending and tilting is a key aspect of enhancing capacitor performance and reliability in integrated circuits (ICs). Capacitor tilting typically occurs in high aspect ratio structures, especially in deep submicron technology nodes. As capacitor size decreases while height increases, structural stability is affected, leading to capacitor tilting or collapse, which in turn impacts capacitor performance and IC yield.In this embodiment, a first electrode layer 501, a second electrode layer 502, and a third electrode layer 503 with different elastic moduli are provided. Specifically, the elastic modulus of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503. In a specific embodiment, the first electrode layer 501 and the third electrode layer 503 can be titanium nitride (TiN), and the second electrode layer 502 can be titanium silicon nitride (TSN). The elastic moduli of TIN and TiSiN are 220.433 GPa and 329.03 GPa, respectively. That is, the second electrode layer 502 has a higher elastic modulus, which means that it can resist deformation and maintain the stability of the structure, so that the lower electrode 50 can maintain the verticality of the capacitor even under high stress conditions. The high elastic modulus of the lower electrode 50 helps to enhance the mechanical strength of the capacitor and reduce the risk of tipping over during deposition, etching, or subsequent processing.

[0057] Please refer to the following: Figure 1 and Figure 2K-2M A dielectric layer 701 and an upper electrode 80 are formed in the second capacitor hole 60. The dielectric layer 701 covers the lower electrode 50, and the upper electrode 80 fills the second capacitor hole 60.

[0058] Specific examples Figure 2KAs shown, a dielectric layer 701 is formed in the second capacitor hole 60. The dielectric layer 701 covers the sidewalls and bottom of the second capacitor hole and the inner walls of the first sacrificial opening 6021 and the second sacrificial opening 6022 between adjacent second capacitor holes 60. The dielectric layer 701 also covers the top of the top support layer 2013, the top first electrode layer 5011, the second electrode layer 502, and the third electrode layer 503. In a specific embodiment, the dielectric layer 701 can be one or more high dielectric constant materials selected from zirconium oxide, hafnium oxide, or tantalum oxide. The first electrode layer 501 and the third electrode layer 503 can be titanium nitride (TiN), and the second electrode layer 502 can be titanium silicon nitride (TiSiN, also abbreviated as TSN). When forming the dielectric layer 701, a hafnium source, a zirconium source, or a tantalum source is required to form hafnium oxide, zirconium oxide, or tantalum oxide through ozone oxidation. When forming the dielectric layer 701, TiN is more easily oxidized to TiON, while TSN is less easily oxidized, so TSN has stronger oxidation resistance. Furthermore, high dielectric constant materials may generate internal stress during deposition, especially in processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). This stress can be due to a mismatch between the thermal expansion coefficients of the dielectric layer 701 and the material of the lower electrode 50 (such as TiN, TSN, etc.), or it may be caused by chemical reactions during the deposition process. The accumulation of stress can lead to bending or warping of the lower electrode 50. Since the oxidation resistance of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503, deformation and bending of the lower electrode 50 caused by oxidation can be prevented during the deposition of the dielectric layer 701, thus improving the performance of the semiconductor structure. Specifically, applying TSN (TiSiN) material with stronger oxidation resistance to the lower electrode 50 can reduce the deformation of the lower electrode 50 during the deposition of the dielectric layer 701, while also reducing the deformation of the TSN material during the thinning process of the lower electrode, ultimately preventing the lower electrode 50 of the capacitor from tipping over.

[0059] Then as Figure 2L-2MAs shown, a first upper electrode layer 801 is first formed on the dielectric layer 701, the first upper electrode layer 801 covers the dielectric layer 701, and then a second upper electrode layer 802 is formed. The second upper electrode layer 802 fills the remaining second capacitor hole 60. The first upper electrode layer 801 and the second upper electrode layer 802 together constitute the upper electrode 80. Specifically, the first upper electrode layer 801 can be titanium nitride, and the second upper electrode layer 802 can be polycrystalline silicon. Since the first electrode layer 501, the second electrode layer 502, and the third electrode layer 503 together constitute the lower electrode 50, and the resistivity of the first electrode layer 501 and the third electrode layer 503 is less than the resistivity of the second electrode layer 502; in this embodiment, by removing part of the first initial electrode layer 501' to form the first electrode layer 501, the radius of the lower electrode 50 of the capacitor is reduced, further miniaturizing the size of the semiconductor structure. Furthermore, the elastic modulus of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503, and the oxidation resistance of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503, thus maintaining the stability of the capacitor during etching and deposition processes. Here, the resistivity of the first electrode layer 501 and the third electrode layer 503 is less than that of the second electrode layer 502, allowing the capacitor structure to remain stable without increasing the resistivity of the capacitor. Figure 2J As shown, the third electrode layer 503 fills the first capacitor hole 401, meaning the thickness of the third electrode layer 503 along the direction parallel to the substrate 10 is much greater than the thickness of the second electrode layer 502 along the direction parallel to the substrate 10. In a specific embodiment, the first electrode layer 501 and the third electrode layer 503 can be titanium nitride (TiN), and the second electrode layer 502 can be titanium silicon nitride (TSN). The resistivity of titanium nitride (TIN) is typically 50-150 μΩ·cm, and the resistivity of titanium silicon nitride (TiSiN) is typically 100-300 μΩ·cm. The resistivity of the first electrode layer 501 and the third electrode layer 503 is less than the resistivity of the second electrode layer 502, and the thickness of the third electrode layer 503 along the direction parallel to the substrate 10 is much greater than the thickness of the second electrode layer 502 along the direction parallel to the substrate 10, thereby reducing the resistivity of the entire lower electrode 50 and improving the performance of the capacitor structure.

[0060] In this application, by using the first initial electrode layer 501' as a sacrificial layer and removing a portion of the first initial electrode layer 501' to form the first electrode layer 501, the radius of the lower electrode 50 of the capacitor is reduced, further enabling the miniaturization of the semiconductor structure. Furthermore, the second electrode layer 502 has greater oxidation resistance than the first electrode layer 501 and the third electrode layer 503, and its elastic modulus is greater than that of the first electrode layer 501 and the third electrode layer 503, thus maintaining the stability of the capacitor structure during etching and deposition and preventing capacitor tilting. Additionally, the resistivity of the first electrode layer 501 and the third electrode layer 503 is less than that of the second electrode layer 502, reducing the overall resistivity of the lower electrode 50. By configuring the various film layers of the lower and lower electrodes 50, not only can the capacitor radius be reduced, enabling the miniaturization of the semiconductor device, but also capacitor bending and tilting phenomena can be prevented, and the performance of the capacitor structure can be improved.

[0061] Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 4 for Figure 3 Enlarged view of point A in the middle; Figure 5 for Figure 3 Enlarged view of point B in the middle; Figure 6 for Figure 3 A magnified view of point C. These will be explained in detail below.

[0062] Please refer to the details. Figure 2B , 2J as well as Figure 3A semiconductor structure includes: a substrate 10 having a stacked structure 20 thereon, the stacked structure 20 having a first capacitor hole 401; a lower electrode 50 located in the first capacitor hole 401, the lower electrode 50 including at least a first electrode layer 501, a second electrode layer 502 and a third electrode layer 503, the second electrode layer 502 having greater oxidation resistance than the first electrode layer 501 and the third electrode layer 503; a second capacitor hole 60 formed by removing at least a portion of the stacked structure 20; a dielectric layer 701 and an upper electrode 80 located in the second capacitor hole 60, the dielectric layer 701 covering the lower electrode 50, and the upper electrode 80 filling the second capacitor hole 60. The substrate 10 includes a substrate 101 and an isolation layer 102 located on the substrate 101, the isolation layer 102 having spaced-apart landing pads 103. The resistivity of the first electrode layer 501 and the third electrode layer 503 is less than that of the second electrode layer 502, and the elastic modulus of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503. The laminated structure 20 includes, from bottom to top, at least: a bottom support layer 2011, a first sacrificial layer 2021, an intermediate support layer 2012, a second sacrificial layer 2022, and a top support layer 2013. The intermediate support layer 2012 is located between the first sacrificial layer 2021 and the second sacrificial layer 2022. The bottom support layer 2011, the intermediate support layer 2012, and the top support layer 2013 together constitute the support layer 201. The first electrode layer 501 is located at least between the support layer 201 and the second electrode layer 502. The first electrode layer 501 includes a top first electrode layer 5011, a middle first electrode layer 5012, and a bottom first electrode layer 5013. The top first electrode layer 5011 corresponds to the top support layer 2013 and is located only between the top support layer 2013 and the second electrode layer 502. The middle first electrode layer 5012 corresponds to the middle support layer 2012 and is located only between the middle support layer 2012 and the second electrode layer 502. The bottom first electrode layer 5013 corresponds to the bottom support layer 2011 and is located between the bottom support layer 2011 and the second electrode layer 502 and at the bottom of the first capacitor hole 401. The first electrode layer 501 and the third electrode layer 503 can be titanium nitride, and the second electrode layer 502 can be titanium silicon nitride. The resistivity of titanium nitride (TIN) is usually 50-150 μΩ·cm, and the resistivity of titanium silicon nitride (TiSiN) is usually 100-300 μΩ·cm. The elastic moduli of TIN and TiSiN are 220.433 GPa and 329.03 GPa, respectively. When forming the dielectric layer 701, a hafnium source, a zirconium source or a tantalum source is required to form hafnium oxide, zirconium oxide or tantalum oxide after ozone oxidation. When forming the dielectric layer 701, TiN is more easily oxidized to TiON, while TSN is less easily oxidized. Therefore, TiSiN has stronger oxidation resistance.

[0063] In this application, by using the first initial electrode layer 501' as a sacrificial layer and removing a portion of the first initial electrode layer 501' to form the first electrode layer 501, the radius of the lower electrode 50 of the capacitor is reduced, further enabling the miniaturization of the semiconductor structure. Furthermore, the second electrode layer 502 has greater oxidation resistance than the first electrode layer 501 and the third electrode layer 503, and its elastic modulus is greater than that of the first electrode layer 501 and the third electrode layer 503, thus maintaining the stability of the capacitor structure during etching and deposition and preventing capacitor tilting. Additionally, the resistivity of the first electrode layer 501 and the third electrode layer 503 is less than that of the second electrode layer 502, reducing the overall resistivity of the lower electrode 50. By configuring the various film layers of the lower and lower electrodes 50, not only can the capacitor radius be reduced, enabling the miniaturization of the semiconductor device, but also capacitor bending and tilting phenomena can be prevented, and the performance of the capacitor structure can be improved.

[0064] Figure 4 for Figure 3 Enlarged diagram at point A in the middle, from Figure 4 It can be seen that the top first electrode layer 5011 is located on both sides of the top support layer 2013, the thickness of the second electrode layer 502 along the direction parallel to the substrate 10 is greater than the thickness of the top first electrode layer 5011 along the direction parallel to the substrate 10, and the upper and lower surfaces of the top support layer 2013 are covered by the dielectric layer 701. Figure 5 for Figure 3 Enlarged diagram at point B, from Figure 5 It can be seen that the first electrode layer 5012 is located on both sides of the intermediate support layer 2012. The thickness of the second electrode layer 502 along the direction parallel to the substrate 10 is greater than the thickness of the first electrode layer 5011 along the direction parallel to the substrate 10. The upper and lower surfaces of the intermediate support layer 2012 are covered by the dielectric layer 701. Figure 6 for Figure 3 Enlarged diagram at point C, from Figure 6It can be seen that the bottom first electrode layer 5013 is located on both sides of the bottom support layer 2011, and the bottom first electrode layer 5013 is also located at the bottom of the first capacitor hole 401. The thickness of the second electrode layer 502 along the direction parallel to the substrate 10 is greater than the thickness of the bottom first electrode layer 5013 along the direction parallel to the substrate 10. The bottom first electrode layer 5013 is electrically connected to the landing pad 103, and the orthographic projection of the landing pad 103 on the substrate 10 is located within the orthographic projection of the bottom first electrode layer 5013 on the substrate 10. The bottom first electrode layer 5013 is groove-shaped and has a bottom and sidewalls. The second electrode layer 502 covers the bottom of the bottom first electrode layer 5013, and the dielectric layer 701 covers the top surface of the sidewalls of the bottom first electrode layer 5013. In this application, the thickness of the second electrode layer 502 along the direction parallel to the substrate 10 is greater than the thickness of the first electrode layer 501 along the direction parallel to the substrate 10. Since the oxidation resistance of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503, the elastic modulus of the second electrode layer 502 is greater than that of the first electrode layer 501 and the third electrode layer 503, which makes the capacitor structure more stable and prevents the capacitor structure from tipping over or short-circuiting.

[0065] In the capacitor structure, the lower electrode using the first electrode layer 501, the second electrode layer 502, and the third electrode layer 503 of this scheme has superior performance compared to using only one layer for the lower electrode. In a specific embodiment, the lower electrode of the X capacitor uses a composite layer of TiN, TiSiN, and TiN, while the lower electrode of the Y capacitor uses only one layer of TiN. The critical dimension CD (Critical Dimension) of the X capacitor and the Y capacitor are the same. The porosity of the X capacitor is 0.02%-0.06%, the porosity of the Y capacitor is 5%-7%, the bending rate of the X capacitor is 0%, and the bending rate of the Y capacitor is 10%-14%. It should be noted that porosity here refers to the ratio of the number of capacitors containing pores to the total number of capacitors. The reasons for the formation of pores in capacitors are roughly as follows: When the lower electrode is only TiN, TiN will crystallize to form larger grains when deposited to a certain thickness. The presence of larger grains will cause the top of the capacitor holes to be sealed first, forming pores (void). However, in this application, the lower electrode is set as at least three film layers: the first electrode layer 501, the second electrode layer 502, and the third electrode layer 503. That is to say, the original thickness of the TiN layer was D1, but now the sum of the thicknesses of the three layers is D1, which is equivalent to a reduction in the thickness of TiN. This makes it impossible for TiN to meet the conditions for forming large grains. In addition, in this application, the first electrode layer 501 and the third electrode layer 503 are titanium nitride (TiN), and the second electrode layer 502 is titanium silicon nitride (TiSiN). The thickness of the second electrode layer TiSiN is much greater than the thickness of the first electrode layer. Therefore, the capacitor holes using the technical solution of this application are not easy to seal and generate pores, and its porosity is lower. The lower porosity results in better electrical performance and stability of the capacitor. Furthermore, the bending rate of a capacitor refers to the ratio of the number of bent capacitors to the total number of capacitors. The capacitor X manufactured using the technical solution of this application has a bending rate of 0, while the bending rate of capacitor Y, whose lower electrode uses only one TiN layer, is 10%-14%. Capacitor bending will cause the originally independent capacitors to tilt and connect together, resulting in a short circuit and forming a fail bit. This will seriously affect the performance of the capacitor. The solution of this application can improve the stability of the capacitor, prevent the capacitor from bending, and improve the performance of the capacitor.

[0066] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a substrate on which a laminated structure is formed; The stacked structure is etched to form a first capacitor hole; A first initial electrode layer, a second electrode layer, and a third electrode layer are sequentially formed in the first capacitor hole, wherein the oxidation resistance of the second electrode layer is greater than that of the first initial electrode layer and the third electrode layer; A portion of the stacked structure and a portion of the first initial electrode layer are removed to form a second capacitor hole, and the remaining first initial electrode layer serves as the first electrode layer; the first electrode layer, the second electrode layer, and the third electrode layer constitute the lower electrode; A dielectric layer and an upper electrode are formed in the second capacitor hole, the dielectric layer covering the lower electrode, and the upper electrode filling the second capacitor hole.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The resistivity of the first electrode layer and the third electrode layer is less than that of the second electrode layer; the elastic modulus of the second electrode layer is greater than that of the first electrode layer and the third electrode layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first initial electrode layer covers the first capacitor hole, the second electrode layer covers the first initial electrode layer, and the third electrode layer fills the remaining first capacitor hole.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate also has an isolation layer, and the landing pad is located within the isolation layer. The landing pad is electrically connected to the lower electrode.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first electrode layer and the third electrode layer can be titanium nitride, and the second electrode layer can be titanium silicon nitride.

6. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The stacked structure comprises, from bottom to top, at least: a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer. The intermediate support layer is located between the first sacrificial layer and the second sacrificial layer. The bottom support layer, the intermediate support layer, and the top support layer together constitute a support layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, Removing a portion of the stacked structure and a portion of the first initial electrode layer to form a second capacitor via, with the remaining first initial electrode layer serving as the first electrode layer, includes at least: removing a portion of the top support layer to form an initial top opening, the initial top opening exposing a portion of the side surface of the first initial electrode layer and a portion of the top surface of the second sacrificial layer; removing the exposed first initial electrode layer through the initial top opening to form a top opening; removing at least the first sacrificial layer and the second sacrificial layer through the top opening, and removing the first initial electrode layer corresponding to the first sacrificial layer and the second sacrificial layer, with the remaining first initial electrode layer serving as the first electrode layer; the first electrode layer is located at least between the support layer and the second electrode layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The first electrode layer includes a top first electrode layer, a middle first electrode layer, and a bottom first electrode layer; the top first electrode layer corresponds to the top support layer and is located only between the top support layer and the second electrode layer; the middle first electrode layer corresponds to the middle support layer and is located only between the middle support layer and the second electrode layer; the bottom first electrode layer corresponds to the bottom support layer and is located between the bottom support layer and the second electrode layer and at the bottom of the first capacitor hole.

9. A semiconductor structure, characterized in that, include: A substrate having a stacked structure having a first capacitor hole; The lower electrode is located in the first capacitor hole. The lower electrode includes at least a first electrode layer, a second electrode layer and a third electrode layer. The oxidation resistance of the second electrode layer is greater than that of the first electrode layer and the third electrode layer. The second capacitor hole is formed by removing at least a portion of the stacked structure; The dielectric layer and the upper electrode are located in the second capacitor hole, the dielectric layer covers the lower electrode, and the upper electrode fills the second capacitor hole.

10. The semiconductor structure according to claim 9, characterized in that, The resistivity of the first electrode layer and the third electrode layer is less than that of the second electrode layer; the elastic modulus of the second electrode layer is greater than that of the first electrode layer and the third electrode layer.

11. The semiconductor structure according to claim 9, characterized in that, The substrate has an isolation layer, the landing pad is located within the isolation layer, and the landing pad is electrically connected to the lower electrode.

12. The semiconductor structure according to claim 9, characterized in that, The first electrode layer and the third electrode layer can be titanium nitride, and the second electrode layer can be titanium silicon nitride.

13. The semiconductor structure according to any one of claims 9-12, characterized in that, The stacked structure comprises, from bottom to top, at least: a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer. The intermediate support layer is located between the first sacrificial layer and the second sacrificial layer. The bottom support layer, the intermediate support layer, and the top support layer together constitute a support layer.

14. The semiconductor structure according to claim 13, characterized in that, The first electrode layer is located at least between the support layer and the second electrode layer.

15. The semiconductor structure according to claim 14, characterized in that, The first electrode layer includes a top first electrode layer, a middle first electrode layer, and a bottom first electrode layer; the top first electrode layer corresponds to the top support layer and is located only between the top support layer and the second electrode layer; the middle first electrode layer corresponds to the middle support layer and is located only between the middle support layer and the second electrode layer; the bottom first electrode layer corresponds to the bottom support layer and is located between the bottom support layer and the second electrode layer and at the bottom of the first capacitor hole.

Images